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sayantnsayantn
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Correct allowed IMM values for cvtps_ph 
1 parent 6461d24 commit fe7c079

4 files changed

Lines changed: 77 additions & 70 deletions

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‎crates/core_arch/src/x86/avx512f.rs‎

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -15529,25 +15529,25 @@ pub fn _mm512_maskz_cvt_roundps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512)
1552915529

1553015530
/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).\
1553115531
/// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:
15532-
/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15533-
/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15534-
/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15535-
/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15532+
/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
15533+
/// * [`_MM_FROUND_TO_NEG_INF`] : round down
15534+
/// * [`_MM_FROUND_TO_POS_INF`] : round up
15535+
/// * [`_MM_FROUND_TO_ZERO`] : truncate
1553615536
/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1553715537
///
1553815538
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvt_roundps_ph&expand=1352)
1553915539
#[inline]
1554015540
#[target_feature(enable = "avx512f,avx512vl")]
1554115541
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15542-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15542+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1554315543
#[rustc_legacy_const_generics(3)]
1554415544
pub fn _mm256_mask_cvt_roundps_ph<const IMM8: i32>(
1554515545
src: __m128i,
1554615546
k: __mmask8,
1554715547
a: __m256,
1554815548
) -> __m128i {
1554915549
unsafe {
15550-
static_assert_uimm_bits!(IMM8, 8);
15550+
static_assert_round_mode!(IMM8);
1555115551
let a = a.as_f32x8();
1555215552
let src = src.as_i16x8();
1555315553
let r = vcvtps2ph256(a, IMM8, src, k);
@@ -15557,21 +15557,21 @@ pub fn _mm256_mask_cvt_roundps_ph<const IMM8: i32>(
1555715557

1555815558
/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).\
1555915559
/// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:\
15560-
/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15561-
/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15562-
/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15563-
/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15560+
/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
15561+
/// * [`_MM_FROUND_TO_NEG_INF`] : round down
15562+
/// * [`_MM_FROUND_TO_POS_INF`] : round up
15563+
/// * [`_MM_FROUND_TO_ZERO`] : truncate
1556415564
/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1556515565
///
1556615566
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvt_roundps_ph&expand=1353)
1556715567
#[inline]
1556815568
#[target_feature(enable = "avx512f,avx512vl")]
1556915569
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15570-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15570+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1557115571
#[rustc_legacy_const_generics(2)]
1557215572
pub fn _mm256_maskz_cvt_roundps_ph<const IMM8: i32>(k: __mmask8, a: __m256) -> __m128i {
1557315573
unsafe {
15574-
static_assert_uimm_bits!(IMM8, 8);
15574+
static_assert_round_mode!(IMM8);
1557515575
let a = a.as_f32x8();
1557615576
let r = vcvtps2ph256(a, IMM8, i16x8::ZERO, k);
1557715577
transmute(r)
@@ -15580,21 +15580,21 @@ pub fn _mm256_maskz_cvt_roundps_ph<const IMM8: i32>(k: __mmask8, a: __m256) -> _
1558015580

1558115581
/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).\
1558215582
/// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:\
15583-
/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15584-
/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15585-
/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15586-
/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15583+
/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
15584+
/// * [`_MM_FROUND_TO_NEG_INF`] : round down
15585+
/// * [`_MM_FROUND_TO_POS_INF`] : round up
15586+
/// * [`_MM_FROUND_TO_ZERO`] : truncate
1558715587
/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1558815588
///
1558915589
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvt_roundps_ph&expand=1350)
1559015590
#[inline]
1559115591
#[target_feature(enable = "avx512f,avx512vl")]
1559215592
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15593-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15593+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1559415594
#[rustc_legacy_const_generics(3)]
1559515595
pub fn _mm_mask_cvt_roundps_ph<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128) -> __m128i {
1559615596
unsafe {
15597-
static_assert_uimm_bits!(IMM8, 8);
15597+
static_assert_round_mode!(IMM8);
1559815598
let a = a.as_f32x4();
1559915599
let src = src.as_i16x8();
1560015600
let r = vcvtps2ph128(a, IMM8, src, k);
@@ -15604,21 +15604,21 @@ pub fn _mm_mask_cvt_roundps_ph<const IMM8: i32>(src: __m128i, k: __mmask8, a: __
1560415604

1560515605
/// Convert packed single-precision (32-bit) floating-point elements in a to packed half-precision (16-bit) floating-point elements, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).\
1560615606
/// Rounding is done according to the imm8\[2:0\] parameter, which can be one of:\
15607-
/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
15608-
/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
15609-
/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
15610-
/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
15607+
/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
15608+
/// * [`_MM_FROUND_TO_NEG_INF`] : round down
15609+
/// * [`_MM_FROUND_TO_POS_INF`] : round up
15610+
/// * [`_MM_FROUND_TO_ZERO`] : truncate
1561115611
/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
1561215612
///
1561315613
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvt_roundps_ph&expand=1351)
1561415614
#[inline]
1561515615
#[target_feature(enable = "avx512f,avx512vl")]
1561615616
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15617-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15617+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1561815618
#[rustc_legacy_const_generics(2)]
1561915619
pub fn _mm_maskz_cvt_roundps_ph<const IMM8: i32>(k: __mmask8, a: __m128) -> __m128i {
1562015620
unsafe {
15621-
static_assert_uimm_bits!(IMM8, 8);
15621+
static_assert_round_mode!(IMM8);
1562215622
let a = a.as_f32x4();
1562315623
let r = vcvtps2ph128(a, IMM8, i16x8::ZERO, k);
1562415624
transmute(r)
@@ -15722,11 +15722,11 @@ pub fn _mm512_maskz_cvtps_ph<const ROUNDING: i32>(k: __mmask16, a: __m512) -> __
1572215722
#[inline]
1572315723
#[target_feature(enable = "avx512f,avx512vl")]
1572415724
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15725-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15725+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1572615726
#[rustc_legacy_const_generics(3)]
1572715727
pub fn _mm256_mask_cvtps_ph<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m256) -> __m128i {
1572815728
unsafe {
15729-
static_assert_uimm_bits!(IMM8, 8);
15729+
static_assert_round_mode!(IMM8);
1573015730
let a = a.as_f32x8();
1573115731
let src = src.as_i16x8();
1573215732
let r = vcvtps2ph256(a, IMM8, src, k);
@@ -15746,11 +15746,11 @@ pub fn _mm256_mask_cvtps_ph<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m25
1574615746
#[inline]
1574715747
#[target_feature(enable = "avx512f,avx512vl")]
1574815748
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15749-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15749+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1575015750
#[rustc_legacy_const_generics(2)]
1575115751
pub fn _mm256_maskz_cvtps_ph<const IMM8: i32>(k: __mmask8, a: __m256) -> __m128i {
1575215752
unsafe {
15753-
static_assert_uimm_bits!(IMM8, 8);
15753+
static_assert_round_mode!(IMM8);
1575415754
let a = a.as_f32x8();
1575515755
let r = vcvtps2ph256(a, IMM8, i16x8::ZERO, k);
1575615756
transmute(r)
@@ -15769,11 +15769,11 @@ pub fn _mm256_maskz_cvtps_ph<const IMM8: i32>(k: __mmask8, a: __m256) -> __m128i
1576915769
#[inline]
1577015770
#[target_feature(enable = "avx512f,avx512vl")]
1577115771
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15772-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15772+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1577315773
#[rustc_legacy_const_generics(3)]
1577415774
pub fn _mm_mask_cvtps_ph<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128) -> __m128i {
1577515775
unsafe {
15776-
static_assert_uimm_bits!(IMM8, 8);
15776+
static_assert_round_mode!(IMM8);
1577715777
let a = a.as_f32x4();
1577815778
let src = src.as_i16x8();
1577915779
let r = vcvtps2ph128(a, IMM8, src, k);
@@ -15793,11 +15793,11 @@ pub fn _mm_mask_cvtps_ph<const IMM8: i32>(src: __m128i, k: __mmask8, a: __m128)
1579315793
#[inline]
1579415794
#[target_feature(enable = "avx512f,avx512vl")]
1579515795
#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15796-
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))]
15796+
#[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 0))]
1579715797
#[rustc_legacy_const_generics(2)]
1579815798
pub fn _mm_maskz_cvtps_ph<const IMM8: i32>(k: __mmask8, a: __m128) -> __m128i {
1579915799
unsafe {
15800-
static_assert_uimm_bits!(IMM8, 8);
15800+
static_assert_round_mode!(IMM8);
1580115801
let a = a.as_f32x4();
1580215802
let r = vcvtps2ph128(a, IMM8, i16x8::ZERO, k);
1580315803
transmute(r)
@@ -50942,19 +50942,19 @@ mod tests {
5094250942
fn test_mm256_mask_cvt_roundps_ph() {
5094350943
let a = _mm256_set1_ps(1.);
5094450944
let src = _mm_set1_epi16(0);
50945-
let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
50945+
let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
5094650946
assert_eq_m128i(r, src);
50947-
let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0b11111111, a);
50947+
let r = _mm256_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b11111111, a);
5094850948
let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
5094950949
assert_eq_m128i(r, e);
5095050950
}
5095150951

5095250952
#[simd_test(enable = "avx512f,avx512vl")]
5095350953
fn test_mm256_maskz_cvt_roundps_ph() {
5095450954
let a = _mm256_set1_ps(1.);
50955-
let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a);
50955+
let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a);
5095650956
assert_eq_m128i(r, _mm_setzero_si128());
50957-
let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0b11111111, a);
50957+
let r = _mm256_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0b11111111, a);
5095850958
let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
5095950959
assert_eq_m128i(r, e);
5096050960
}
@@ -50963,19 +50963,19 @@ mod tests {
5096350963
fn test_mm_mask_cvt_roundps_ph() {
5096450964
let a = _mm_set1_ps(1.);
5096550965
let src = _mm_set1_epi16(0);
50966-
let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
50966+
let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
5096750967
assert_eq_m128i(r, src);
50968-
let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
50968+
let r = _mm_mask_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
5096950969
let e = _mm_setr_epi64x(4323521613979991040, 0);
5097050970
assert_eq_m128i(r, e);
5097150971
}
5097250972

5097350973
#[simd_test(enable = "avx512f,avx512vl")]
5097450974
fn test_mm_maskz_cvt_roundps_ph() {
5097550975
let a = _mm_set1_ps(1.);
50976-
let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0, a);
50976+
let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a);
5097750977
assert_eq_m128i(r, _mm_setzero_si128());
50978-
let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_NO_EXC>(0b00001111, a);
50978+
let r = _mm_maskz_cvt_roundps_ph::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
5097950979
let e = _mm_setr_epi64x(4323521613979991040, 0);
5098050980
assert_eq_m128i(r, e);
5098150981
}
@@ -51018,19 +51018,19 @@ mod tests {
5101851018
fn test_mm256_mask_cvtps_ph() {
5101951019
let a = _mm256_set1_ps(1.);
5102051020
let src = _mm_set1_epi16(0);
51021-
let r = _mm256_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
51021+
let r = _mm256_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
5102251022
assert_eq_m128i(r, src);
51023-
let r = _mm256_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0b11111111, a);
51023+
let r = _mm256_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b11111111, a);
5102451024
let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
5102551025
assert_eq_m128i(r, e);
5102651026
}
5102751027

5102851028
#[simd_test(enable = "avx512f,avx512vl")]
5102951029
fn test_mm256_maskz_cvtps_ph() {
5103051030
let a = _mm256_set1_ps(1.);
51031-
let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a);
51031+
let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a);
5103251032
assert_eq_m128i(r, _mm_setzero_si128());
51033-
let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0b11111111, a);
51033+
let r = _mm256_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0b11111111, a);
5103451034
let e = _mm_setr_epi64x(4323521613979991040, 4323521613979991040);
5103551035
assert_eq_m128i(r, e);
5103651036
}
@@ -51039,19 +51039,19 @@ mod tests {
5103951039
fn test_mm_mask_cvtps_ph() {
5104051040
let a = _mm_set1_ps(1.);
5104151041
let src = _mm_set1_epi16(0);
51042-
let r = _mm_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0, a);
51042+
let r = _mm_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
5104351043
assert_eq_m128i(r, src);
51044-
let r = _mm_mask_cvtps_ph::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
51044+
let r = _mm_mask_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
5104551045
let e = _mm_setr_epi64x(4323521613979991040, 0);
5104651046
assert_eq_m128i(r, e);
5104751047
}
5104851048

5104951049
#[simd_test(enable = "avx512f,avx512vl")]
5105051050
fn test_mm_maskz_cvtps_ph() {
5105151051
let a = _mm_set1_ps(1.);
51052-
let r = _mm_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0, a);
51052+
let r = _mm_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0, a);
5105351053
assert_eq_m128i(r, _mm_setzero_si128());
51054-
let r = _mm_maskz_cvtps_ph::<_MM_FROUND_NO_EXC>(0b00001111, a);
51054+
let r = _mm_maskz_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
5105551055
let e = _mm_setr_epi64x(4323521613979991040, 0);
5105651056
assert_eq_m128i(r, e);
5105751057
}

‎crates/core_arch/src/x86/f16c.rs‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -56,10 +56,10 @@ pub const fn _mm256_cvtph_ps(a: __m128i) -> __m256 {
5656
///
5757
/// Rounding is done according to the `imm_rounding` parameter, which can be one of:
5858
///
59-
/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
60-
/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
61-
/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
62-
/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
59+
/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
60+
/// * [`_MM_FROUND_TO_NEG_INF`] : round down
61+
/// * [`_MM_FROUND_TO_POS_INF`] : round up
62+
/// * [`_MM_FROUND_TO_ZERO`] : truncate
6363
/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
6464
///
6565
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtps_ph)
@@ -69,7 +69,7 @@ pub const fn _mm256_cvtph_ps(a: __m128i) -> __m256 {
6969
#[rustc_legacy_const_generics(1)]
7070
#[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")]
7171
pub fn _mm_cvtps_ph<const IMM_ROUNDING: i32>(a: __m128) -> __m128i {
72-
static_assert_uimm_bits!(IMM_ROUNDING, 3);
72+
static_assert_round_mode!(IMM_ROUNDING);
7373
unsafe {
7474
let a = a.as_f32x4();
7575
let r = llvm_vcvtps2ph_128(a, IMM_ROUNDING);
@@ -82,10 +82,10 @@ pub fn _mm_cvtps_ph<const IMM_ROUNDING: i32>(a: __m128) -> __m128i {
8282
///
8383
/// Rounding is done according to the `imm_rounding` parameter, which can be one of:
8484
///
85-
/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
86-
/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
87-
/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
88-
/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
85+
/// * [`_MM_FROUND_TO_NEAREST_INT`] : round to nearest
86+
/// * [`_MM_FROUND_TO_NEG_INF`] : round down
87+
/// * [`_MM_FROUND_TO_POS_INF`] : round up
88+
/// * [`_MM_FROUND_TO_ZERO`] : truncate
8989
/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
9090
///
9191
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtps_ph)
@@ -95,7 +95,7 @@ pub fn _mm_cvtps_ph<const IMM_ROUNDING: i32>(a: __m128) -> __m128i {
9595
#[rustc_legacy_const_generics(1)]
9696
#[stable(feature = "x86_f16c_intrinsics", since = "1.68.0")]
9797
pub fn _mm256_cvtps_ph<const IMM_ROUNDING: i32>(a: __m256) -> __m128i {
98-
static_assert_uimm_bits!(IMM_ROUNDING, 3);
98+
static_assert_round_mode!(IMM_ROUNDING);
9999
unsafe {
100100
let a = a.as_f32x8();
101101
let r = llvm_vcvtps2ph_256(a, IMM_ROUNDING);

‎crates/core_arch/src/x86/macros.rs‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,14 @@
11
//! Utility macros.
22
3+
// Helper macro used to trigger const eval errors when the const generic immediate value `imm` is
4+
// not a round number.
5+
#[allow(unused)]
6+
macro_rules! static_assert_round_mode {
7+
($imm:ident) => {
8+
static_assert!($imm >= 0 && $imm < 5, "Invalid IMM value")
9+
};
10+
}
11+
312
// Helper macro used to trigger const eval errors when the const generic immediate value `imm` is
413
// not a round number.
514
#[allow(unused)]

‎crates/intrinsic-test/src/x86/constraint.rs‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,24 +9,22 @@ pub fn map_constraints(fn_name: &str, imm_type: &String, imm_width: u32) -> Opti
99
return Some(Constraint::Range(0..max));
1010
}
1111
match imm_type.as_str() {
12-
// Legal values for variables of `_MM_FROUND` type are:
13-
// 8 => (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
14-
// 9 => (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions
15-
// 10 => (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions
16-
// 11 => (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions
17-
// 4 => _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
12+
// _mm512_cvt{_round}ps_ph functions can accept a larger set of values for _MM_FROUND
13+
"_MM_FROUND"
14+
if fn_name.starts_with("_mm512")
15+
&& (fn_name.ends_with("cvtps_ph") || fn_name.ends_with("cvt_roundps_ph")) =>
16+
{
17+
Some(Constraint::Set(vec![0, 1, 2, 3, 4, 8, 9, 10, 11, 12]))
18+
}
1819
"_MM_FROUND" => Some(Constraint::Set(vec![4, 8, 9, 10, 11])),
1920
"_MM_INDEX_SCALE" => Some(Constraint::Set(vec![1, 2, 4, 8])),
2021
"_MM_CMPINT" => Some(Constraint::Range(0..8)),
21-
"_MM_REDUCE" => Some(Constraint::Range(0..8)),
22-
"_MM_FROUND_SAE" => Some(Constraint::Equal(8)),
22+
"_MM_REDUCE" => Some(Constraint::Range(0..256)),
23+
"_MM_FROUND_SAE" => Some(Constraint::Set(vec![4, 8])),
2324
"_MM_MANTISSA_NORM" => Some(Constraint::Range(0..4)),
24-
"_MM_MANTISSA_NORM_ENUM" => Some(Constraint::Range(0..4)),
2525
"_MM_MANTISSA_SIGN" => Some(Constraint::Range(0..3)),
2626
"_MM_PERM" => Some(Constraint::Range(0..256)),
27-
"_MM_PERM_ENUM" => Some(Constraint::Range(0..256)),
28-
"_MM_CMPINT_ENUM" => Some(Constraint::Range(0..8)),
29-
"_MM_ROUND_MODE" => Some(Constraint::Set(vec![0, 0x2, 0x4, 0x6])),
27+
"_MM_ROUND_MODE" => Some(Constraint::Range(0..5)),
3028
"_CMP_" => Some(Constraint::Range(0..32)),
3129
_ => None,
3230
}

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