Remove %FN% from test name

Author: martin-hughes

tests/bank_fields.rs

@@ -16,7 +16,7 @@ fn test_basic_bank_store_and_load() {
     // This is a straightforward test of banked fields.
     // Internally: Apart from setting the bank index beforehand, the field read/write is identical
     // to normal fields. So this test is probably sufficient testing of banked fields.
-    const AML: &str = r#"DefinitionBlock("%FN%", "DSDT", 1, "RSACPI", "BNKFLD", 1) {
+    const AML: &str = r#"DefinitionBlock("", "DSDT", 1, "RSACPI", "BNKFLD", 1) {
     OperationRegion(MEM, SystemMemory, 0x40000, 0x1000)
     Field(MEM, ByteAcc, NoLock, Preserve) {
         INDX, 8

tests/index_fields.rs

@@ -16,7 +16,7 @@ mod test_infra;
 fn test_basic_index_store_and_load_8_bit() {
     // In this test, the data register has the same width as the fields and all fields are correctly
     // aligned. We should see single reads and writes for each store operation.
-    const AML: &str = r#"DefinitionBlock("%FN%", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
+    const AML: &str = r#"DefinitionBlock("", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
     OperationRegion(MEM, SystemMemory, 0x40000, 0x1000)
     Field(MEM, ByteAcc, NoLock, Preserve) {
         OFFSET(0x10),
@@ -70,7 +70,7 @@ fn test_basic_index_store_and_load_8_bit() {
 fn test_basic_index_store_and_load_16_bit() {
     // In this test, the data register has the same width as the fields and all fields are correctly
     // aligned. We should see single reads and writes for each store operation.
-    const AML: &str = r#"DefinitionBlock("%FN%", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
+    const AML: &str = r#"DefinitionBlock("", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
     OperationRegion(MEM, SystemMemory, 0x40000, 0x1000)
     Field(MEM, WordAcc, NoLock, Preserve) {
         OFFSET(0x20),
@@ -124,7 +124,7 @@ fn test_basic_index_store_and_load_16_bit() {
 fn test_index_multiple_aligned_reads() {
     // In this test, the data register is narrower than the fields, so multiple data register
     // reads are needed to access each field.
-    const AML: &str = r#"DefinitionBlock("%FN%", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
+    const AML: &str = r#"DefinitionBlock("", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
     OperationRegion(MEM, SystemMemory, 0x40000, 0x1000)
     Field(MEM, ByteAcc, NoLock, Preserve) {
         OFFSET(0x04),
@@ -174,7 +174,7 @@ fn test_index_narrower_than_data() {
     // In this test, the access width of the index field is smaller than the data register. Even
     // though it looks as though individual 16-bit reads/writes would be OK, actually multiple
     // 8-bit reads/writes are needed to access each field. (Not intuitive, but matches ACPICA)
-    const AML: &str = r#"DefinitionBlock("%FN%", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
+    const AML: &str = r#"DefinitionBlock("", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
     OperationRegion(MEM, SystemMemory, 0x40000, 0x1000)
     Field(MEM, WordAcc, NoLock, Preserve) {
         OFFSET(0x06),
@@ -223,7 +223,7 @@ fn test_index_narrower_than_data() {
 #[test]
 fn test_index_misaligned_field() {
     // Check that we can successfully update non-aligned index fields.
-    const AML: &str = r#"DefinitionBlock("%FN%", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
+    const AML: &str = r#"DefinitionBlock("", "DSDT", 1, "RSACPI", "IDXFLD", 1) {
     OperationRegion(MEM, SystemMemory, 0x40000, 0x1000)
     Field(MEM, ByteAcc, NoLock, Preserve) {
         OFFSET(0x08),