Lab7

RISC_V SIMULATOR with CACHES

Same as that of LAB4 but with extensions ...

commands supported now are ..

• load FILE_NAME
  Load an input file containing RISC-V assembly code.

• run
  Execute the assembly code in the input file.

• exit
  Exit the simulator.

• step
  Execute a single instruction.

• mem ADDRESS COUNT
  Display memory values from ADDRESS to ADDRESS+COUNT-1.

• show-stack
  Show the call stack at the current moment.

• break LINE_NUM
  Set a breakpoint at the given line number.

• del break LINE_NUM
  Delete a breakpoint at the specified line. Returns an error if no breakpoint exists at that line.

• cache_sim enable FILE_NAME
  Enable cache simulation with configurations from FILE_NAME.

• cache_sim disable
  Disable cache simulation.

• cache_sim status
  Display whether cache simulation is enabled or disabled.

• cache_sim invalidate
  Invalidate all valid cache entries.

• cache_sim dump FILE_NAME
  Write all current valid cache entries to FILE_NAME.

• cache_sim stats
  Show cache statistics at the current program state.