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Merge branch 'main' of github01.hclpnp.com:Modeling/rtistic-pub-doc
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‎art-comp-test/art-comp-test.code-workspace‎

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{
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"path": "tests/part_inheritance"
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},
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{
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"path": "tests/passive_class_sm_entry_exit"
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},
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{
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"path": "tests/passive_class_sm_shallow_history"
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},

‎art-comp-test/connectors.code-workspace‎

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{
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"path": "tests/delegation_connector_02"
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},
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{
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"path": "tests/delegation_connector_03"
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},
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{
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"path": "tests/delegation_connector_nested"
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},

‎art-comp-test/tests/delegation_connector_03/delegation_connector_03.art‎

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protocol Proto {
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in init();
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out init_done();
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};
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protocol HEvents {
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in init();
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out init_done();
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in h();
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out h_done();
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};
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protocol SEvents {
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in init();
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out init_done();
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in s();
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out s_done();
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};
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capsule S {
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service behavior port p_s : SEvents;
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service behavior port r_s~ : SEvents;
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statemachine {
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state State, Initialized;
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initial -> State;
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State -> Initialized on p_s.init
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`
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r_s.init().send();
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`;
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};
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};
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capsule H {
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part x : S;
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part y : S;
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service port r_xs~ : SEvents, r_ys~ : SEvents;
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connect x.r_s with r_xs; // delegation connector
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connect y.r_s with r_ys; // delegation connector
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behavior port xs~ : SEvents, ys~ : SEvents;
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connect xs with x.p_s;
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connect ys with y.p_s;
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service behavior port p_h : HEvents;
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service behavior port r_h~ : HEvents;
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statemachine {
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state State, Initialized;
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initial -> State;
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State -> Initialized on p_h.init
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`
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xs.init().send();
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ys.init().send();
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r_h.init().send();
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`;
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};
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};
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capsule Main {
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part h : H;
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service port r_h~ : HEvents, r_xs~ : SEvents, r_ys~ : SEvents;
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connect h.r_h with r_h; // delegation connector
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connect h.r_xs with r_xs; // delegation connector
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connect h.r_ys with r_ys; // delegation connector
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behavior port p_h~ : HEvents;
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connect p_h with h.p_h;
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service behavior port p_main : Proto;
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service behavior port r_main~ : Proto;
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statemachine {
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state State, Initialized;
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initial -> State;
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State -> Initialized on p_main.init
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`
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p_h.init().send();
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r_main.init().send();
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`;
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};
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};
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capsule Tester {
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[[rt::decl]]
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`
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bool xi = false, yi = false, hi = false, mi = false;
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`
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service behavior port p~ : Proto;
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service behavior port r : Proto;
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service behavior port h : HEvents, xs : SEvents, ys : SEvents;
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behavior port timer : Timing;
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statemachine {
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state Initialized;
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initial -> State `
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p.init().send();
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timer.informEvery(RTTimespec(0, 100));
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`;
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state State {
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on xs.init `xi = true;`;
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on ys.init `yi = true;`;
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on h.init `hi = true;`;
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on r.init `mi = true;`;
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};
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State -> Initialized on timer.timeout when `xi && yi && hi && mi`
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`
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PASS();
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`;
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};
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};
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capsule Top [[rt::properties(color="#100f0f")]] {
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part tester : Tester;
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part main : Main;
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connect tester.p with main.p_main;
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connect tester.r with main.r_main;
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connect tester.h with main.r_h;
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connect tester.xs with main.r_xs;
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connect tester.ys with main.r_ys;
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statemachine {
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state State;
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initial -> State;
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};
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};

‎art-comp-test/tests/delegation_connector_03/testcase.md‎

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---
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group: cpp_code_generation
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---
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Model contains complex structure of ports and connectors. Delegation connectors are used for sending reflection events from various components to top tester.

‎art-comp-test/tests/delegation_connector_03/top.tcjs‎

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let tc = TCF.define(TCF.ART_TO_CPP);
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tc.topCapsule = 'Top';
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tc.prerequisites = ["../../TestUtils/testlib.tcjs"];
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tc.targetFolder = 'delegation_connector_03_target';
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tc.commonPreface = `
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#include "testlib.art.h"
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#include <stdio.h>
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`;

‎art-comp-test/tests/passive_class_sm_entry_exit/MyClass.art‎

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class MyClass {
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[[rt::header_preface]]
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`
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#include <iostream>
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#include <string>
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`
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[[rt::decl]]
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`
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public:
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MyClass();
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public:
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std::string entryStack = "";
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bool route_to_s4 = false;
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`
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[[rt::impl]]
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`
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MyClass::MyClass() {
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rtg_init1();
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}
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`
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/* Trigger Operations */
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trigger op();
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/* State Machine */
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statemachine {
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state State1 {
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entry
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`
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entryStack += " entry#State1";
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`;
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exit
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`
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entryStack += " exit#State1 ";
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`;
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}, State3 {
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entry
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`
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entryStack += " entry#State3 ";
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`;
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exit
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`
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entryStack += " exit#State3 ";
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`;
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}, State2 {
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entry
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`
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entryStack += " entry#State2 ";
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`;
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exit
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`
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entryStack += " exit#State2 ";
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`;
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entrypoint ep;
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_state_s1_on_true: ep -> S1.ep when
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`route_to_s4`
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`
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entryStack += "-->state_s1_on_true-->";
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`;
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_state_s1_on_false: ep -> S1.ep2 when
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`!route_to_s4`
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`
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entryStack += "-->state_s1_on_false-->";
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`;
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state S1 {
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entry
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`
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entryStack += " entry#S1 ";
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`;
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exit
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`
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entryStack += " exit#S1 ";
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`;
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entrypoint ep, ep2;
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_s1_s2_on_true: ep -> S2.ep when
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`route_to_s4`
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`
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entryStack += "-->s1_s2_on_true-->";
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`;
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_s1_s2_on_false: ep2 -> S2.ep2 when
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`!route_to_s4`
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`
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entryStack += "-->s1_s2_on_false-->";
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`;
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state S2 {
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entrypoint ep, ep2;
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entry
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`
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entryStack += " entry#S2 ";
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`;
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exit
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`
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entryStack += " exit#S2 ";
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`;
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_s2_s4_on_true: ep -> S4 when
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`route_to_s4`
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`
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entryStack += "-->s2_s4_on_true-->";
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`;
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_s2_s3_on_false: ep2 -> S3 when
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`!route_to_s4`
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`
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entryStack += "-->s2_s3_on_false-->";
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`;
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state S3 {
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entry
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`
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entryStack += " entry#S3";
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`;
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exit
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`
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entryStack += " exit#S3 ";
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`;
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};
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state S4 {
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entry
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`
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entryStack += " entry#S4";
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`;
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exit
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`
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entryStack += " exit#S4 ";
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`;
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};
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};
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};
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};
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_init_State: initial -> State1
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`
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entryStack += "init_State1-->";
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`;
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_State_State2: State1 -> State2.ep on op()
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`
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entryStack += "State1_State2-->";
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`;
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_State2_State3: State2 -> State3 on op()
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`
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entryStack += "-->State2_State3-->";
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`;
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_State3_State2: State3 -> State1 on op()
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`
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entryStack += "-->State3_State1-->";
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`;
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};
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};
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‎art-comp-test/tests/passive_class_sm_entry_exit/Top.art‎

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capsule Top {
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[[rt::header_preface]]
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`
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#include "testlib.art.h"
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#include "MyClass.h"
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#include <iostream>
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`
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[[rt::decl]]
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`
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private:
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MyClass _myClass;
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`
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behavior port t : Timing;
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statemachine {
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state State2;
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initial -> State2
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`
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ASSERT(_myClass.entryStack == "init_State1--> entry#State1", "Expected to call init_State");
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_myClass.entryStack = "";
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_myClass.op();
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ASSERT(_myClass.entryStack == " exit#State1 State1_State2--> entry#State2 -->state_s1_on_false--> entry#S1 -->s1_s2_on_false--> entry#S2 -->s2_s3_on_false--> entry#S3", "Stack not called as expected");
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_myClass.entryStack = "";
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_myClass.op();
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ASSERT(_myClass.entryStack == " exit#S3 exit#S2 exit#S1 exit#State2 -->State2_State3--> entry#State3 ", "Stack not called as expected");
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_myClass.entryStack = "";
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_myClass.op();
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ASSERT(_myClass.entryStack == " exit#State3 -->State3_State1--> entry#State1", "Stack not called as expected");
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_myClass.entryStack = "";
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_myClass.route_to_s4 = true;
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_myClass.op();
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ASSERT(_myClass.entryStack == " exit#State1 State1_State2--> entry#State2 -->state_s1_on_true--> entry#S1 -->s1_s2_on_true--> entry#S2 -->s2_s4_on_true--> entry#S4", "Stack not called as expected");
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PASS();
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`;
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};
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};

‎art-comp-test/tests/passive_class_sm_entry_exit/testcase.md‎

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---
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group: cpp_code_generation
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---
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This test case verifies that the passive state machine triggerOp handles transitions correctly when they occur between two entry points. It ensures the following:
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State entry actions are called in the correct order.
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Effect code executes properly when the transition occurs between multiple entry points.
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Exit actions are called in the correct order.
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In the above example, _State_State1 is split into two transitions based on conditions. This test case verifies that the effect code for the transition _State_State1 is executed in both cases.
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‎art-comp-test/tests/passive_class_sm_entry_exit/top.tcjs‎

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const tc = TCF.define(TCF.ART_TO_CPP);
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tc.topCapsule = 'Top';
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tc.prerequisites = ["../../TestUtils/testlib.tcjs"];
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tc.targetFolder = 'passive_class_sm_entry_exit_target';

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