corrected parameters on module trng

Author: seemsLgit

src/user_peripherals/trng/TRNG_20RO7FF_PC.sv

@@ -6,8 +6,8 @@
 `default_nettype none
 
 module tqvp_TRNG_20RO7FF_PC #(
-    parameter SIZE_RO = 6 //size of the RO will be SIZE_RO + 1 inverter gates (7 in this case)
-    parameter N_RO = 20 //number of ROs in parallel
+    parameter SIZE_RO = 6; //size of the RO will be SIZE_RO + 1 inverter gates (7 in this case)
+    parameter N_RO = 20; //number of ROs in parallel
   )(
     input         clk,          // Clock - the TinyQV project clock is normally set to 64MHz.
     input         rst_n,        // Reset_n - low to reset.