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pbaradaanchao
pbarada
authored and
anchao
committed
arch/arm/stm32*: Use PRIx32 format specifier where appropriate
Replace 'x' printf format specifier with PRIx32 where corresponding value is uint32_t type. Signed-off-by Peter Barada <peter.barada@gmail.com>
1 parent bd885b7 commit efdbdfe

82 files changed

Lines changed: 850 additions & 706 deletions

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‎arch/arm/src/stm32/stm32_adc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2144,7 +2144,7 @@ static void adc_power_down_delay(struct stm32_dev_s *priv, bool pdd_high)
21442144
static void adc_dels_after_conversion(struct stm32_dev_s *priv,
21452145
uint32_t delay)
21462146
{
2147-
ainfo("Delay selected: 0x%08x\n", delay);
2147+
ainfo("Delay selected: 0x%08" PRIx32 "\n", delay);
21482148

21492149
adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_DELS_MASK, delay);
21502150
}

‎arch/arm/src/stm32/stm32_dma2d.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -332,7 +332,7 @@ static int stm32_dma2dirq(int irq, void *context, void *arg)
332332
uint32_t regval = getreg32(STM32_DMA2D_ISR);
333333
struct stm32_interrupt_s *priv = &g_interrupt;
334334

335-
reginfo("irq = %d, regval = %08x\n", irq, regval);
335+
reginfo("irq = %d, regval = %08" PRIx32 "\n", irq, regval);
336336

337337
if (regval & DMA2D_ISR_TCIF)
338338
{
@@ -471,9 +471,9 @@ static int stm32_dma2d_loadclut(uintptr_t pfcreg)
471471

472472
regval = getreg32(pfcreg);
473473
regval |= DMA2D_XGPFCCR_START;
474-
reginfo("set regval=%08x\n", regval);
474+
reginfo("set regval=%08" PRIx32 "\n", regval);
475475
putreg32(regval, pfcreg);
476-
reginfo("configured regval=%08x\n", getreg32(pfcreg));
476+
reginfo("configured regval=%08" PRIx32 "\n", getreg32(pfcreg));
477477

478478
/* Wait until clut is finished */
479479

‎arch/arm/src/stm32/stm32_dma_v1.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -847,19 +847,19 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
847847
uint32_t dmabase = DMA_BASE(dmach->base);
848848

849849
dmainfo("DMA Registers: %s\n", msg);
850-
dmainfo(" ISRC[%08x]: %08x\n",
850+
dmainfo(" ISRC[%08" PRIx32 "]: %08" PRIx32 "\n",
851851
dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
852852
#ifdef DMA_HAVE_CSELR
853-
dmainfo(" CSELR[%08x]: %08x\n",
853+
dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n",
854854
dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr);
855855
#endif
856-
dmainfo(" CCR[%08x]: %08x\n",
856+
dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n",
857857
dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
858-
dmainfo(" CNDTR[%08x]: %08x\n",
858+
dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n",
859859
dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
860-
dmainfo(" CPAR[%08x]: %08x\n",
860+
dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n",
861861
dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
862-
dmainfo(" CMAR[%08x]: %08x\n",
862+
dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n",
863863
dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
864864
}
865865
#endif

‎arch/arm/src/stm32/stm32_dma_v1mux.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -907,19 +907,19 @@ static void stm32_dma12_dump(DMA_HANDLE handle,
907907
dmainfo("DMA%d Registers: %s\n",
908908
dmachan->ctrl + 1,
909909
msg);
910-
dmainfo(" ISR[%08x]: %08x\n",
910+
dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n",
911911
dmabase + STM32_DMA_ISR_OFFSET,
912912
regs->isr);
913-
dmainfo(" CCR[%08x]: %08x\n",
913+
dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n",
914914
dmachan->base + STM32_DMACHAN_CCR_OFFSET,
915915
regs->ccr);
916-
dmainfo(" CNDTR[%08x]: %08x\n",
916+
dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n",
917917
dmachan->base + STM32_DMACHAN_CNDTR_OFFSET,
918918
regs->cndtr);
919-
dmainfo(" CPAR[%08x]: %08x\n",
919+
dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n",
920920
dmachan->base + STM32_DMACHAN_CPAR_OFFSET,
921921
regs->cpar);
922-
dmainfo(" CMAR[%08x]: %08x\n",
922+
dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n",
923923
dmachan->base + STM32_DMACHAN_CMAR_OFFSET,
924924
regs->cmar);
925925

@@ -958,20 +958,20 @@ static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel,
958958
const struct stm32_dmaregs_s *regs)
959959
{
960960
dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel);
961-
dmainfo(" CCR[%08x]: %08x\n",
961+
dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n",
962962
dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel),
963963
regs->dmamux.ccr);
964-
dmainfo(" CSR[%08x]: %08x\n",
964+
dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n",
965965
dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr);
966-
dmainfo(" RG0CR[%08x]: %08x\n",
966+
dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n",
967967
dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr);
968-
dmainfo(" RG1CR[%08x]: %08x\n",
968+
dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n",
969969
dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr);
970-
dmainfo(" RG2CR[%08x]: %08x\n",
970+
dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n",
971971
dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr);
972-
dmainfo(" RG3CR[%08x]: %08x\n",
972+
dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n",
973973
dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr);
974-
dmainfo(" RGSR[%08x]: %08x\n",
974+
dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n",
975975
dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr);
976976
};
977977
#endif

‎arch/arm/src/stm32/stm32_dma_v2.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1069,21 +1069,21 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
10691069
uint32_t dmabase = DMA_BASE(dmast->base);
10701070

10711071
dmainfo("DMA Registers: %s\n", msg);
1072-
dmainfo(" LISR[%08x]: %08x\n",
1072+
dmainfo(" LISR[%08" PRIx32 "]: %08" PRIx32 "\n",
10731073
dmabase + STM32_DMA_LISR_OFFSET, regs->lisr);
1074-
dmainfo(" HISR[%08x]: %08x\n",
1074+
dmainfo(" HISR[%08" PRIx32 "]: %08" PRIx32 "\n",
10751075
dmabase + STM32_DMA_HISR_OFFSET, regs->hisr);
1076-
dmainfo(" SCR[%08x]: %08x\n",
1076+
dmainfo(" SCR[%08" PRIx32 "]: %08" PRIx32 "\n",
10771077
dmast->base + STM32_DMA_SCR_OFFSET, regs->scr);
1078-
dmainfo(" SNDTR[%08x]: %08x\n",
1078+
dmainfo(" SNDTR[%08" PRIx32 "]: %08" PRIx32 "\n",
10791079
dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr);
1080-
dmainfo(" SPAR[%08x]: %08x\n",
1080+
dmainfo(" SPAR[%08" PRIx32 "]: %08" PRIx32 "\n",
10811081
dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
1082-
dmainfo(" SM0AR[%08x]: %08x\n",
1082+
dmainfo(" SM0AR[%08" PRIx32 "]: %08" PRIx32 "\n",
10831083
dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
1084-
dmainfo(" SM1AR[%08x]: %08x\n",
1084+
dmainfo(" SM1AR[%08" PRIx32 "]: %08" PRIx32 "\n",
10851085
dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
1086-
dmainfo(" SFCR[%08x]: %08x\n",
1086+
dmainfo(" SFCR[%08" PRIx32 "]: %08" PRIx32 "\n",
10871087
dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
10881088
}
10891089
#endif

‎arch/arm/src/stm32/stm32_dumpgpio.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
138138
#elif defined(CONFIG_STM32_STM32L15XX)
139139
DEBUGASSERT(port < STM32_NGPIO_PORTS);
140140

141-
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
141+
_info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n",
142142
g_portchar[port], pinset, base, msg);
143143

144144
if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
@@ -217,7 +217,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
217217
}
218218
else
219219
{
220-
_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
220+
_info(" GPIO%c not enabled: AHB1ENR: %08" PRIx32 "\n",
221221
g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
222222
}
223223

‎arch/arm/src/stm32/stm32_eth.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -846,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr)
846846

847847
/* Show the register value read */
848848

849-
ninfo("%08x->%08x\n", addr, val);
849+
ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val);
850850
return val;
851851
}
852852
#endif
@@ -873,7 +873,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
873873
{
874874
/* Show the register value being written */
875875

876-
ninfo("%08x<-%08x\n", addr, val);
876+
ninfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val);
877877

878878
/* Write the value */
879879

‎arch/arm/src/stm32/stm32_hrtim.c‎

Lines changed: 42 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -2023,24 +2023,27 @@ static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer,
20232023
{
20242024
case HRTIM_TIMER_MASTER:
20252025
{
2026-
tmrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n",
2026+
tmrinfo("\tCR:\t0x%08" PRIx32 "\tISR:\t0x%08" PRIx32
2027+
"\tICR:\t0x%08" PRIx32 "\n",
20272028
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET),
20282029
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET),
20292030
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET));
20302031

2031-
tmrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n",
2032+
tmrinfo("\tDIER:\t0x%08" PRIx32 "\tCNTR:\t0x%08" PRIx32
2033+
"\tPER:\t0x%08" PRIx32 "\n",
20322034
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET),
20332035
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET),
20342036
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET));
20352037

2036-
tmrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP2:\t0x%08x\n",
2038+
tmrinfo("\tREP:\t0x%08" PRIx32 "\tCMP1:\t0x%08" PRIx32
2039+
"\tCMP2:\t0x%08" PRIx32 "\n",
20372040
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET),
20382041
hrtim_tim_getreg(priv, timer,
20392042
STM32_HRTIM_TIM_CMP1R_OFFSET),
20402043
hrtim_tim_getreg(priv, timer,
20412044
STM32_HRTIM_TIM_CMP2R_OFFSET));
20422045

2043-
tmrinfo("\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n",
2046+
tmrinfo("\tCMP3:\t0x%08" PRIx32 "\tCMP4:\t0x%08" PRIx32 "\n",
20442047
hrtim_tim_getreg(priv, timer,
20452048
STM32_HRTIM_TIM_CMP3R_OFFSET),
20462049
hrtim_tim_getreg(priv, timer,
@@ -2064,61 +2067,70 @@ static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer,
20642067
case HRTIM_TIMER_TIME:
20652068
#endif
20662069
{
2067-
tmrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n",
2070+
tmrinfo("\tCR:\t0x%08" PRIx32 "\tISR:\t0x%08" PRIx32
2071+
"\tICR:\t0x%08" PRIx32 "\n",
20682072
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET),
20692073
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET),
20702074
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET));
20712075

2072-
tmrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n",
2076+
tmrinfo("\tDIER:\t0x%08" PRIx32 "\tCNTR:\t0x%08" PRIx32
2077+
"\tPER:\t0x%08" PRIx32 "\n",
20732078
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET),
20742079
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET),
20752080
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET));
20762081

2077-
tmrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP1C:\t0x%08x\n",
2082+
tmrinfo("\tREP:\t0x%08" PRIx32 "\tCMP1:\t0x%08" PRIx32
2083+
"\tCMP1C:\t0x%08" PRIx32 "\n",
20782084
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET),
20792085
hrtim_tim_getreg(priv, timer,
20802086
STM32_HRTIM_TIM_CMP1R_OFFSET),
20812087
hrtim_tim_getreg(priv, timer,
20822088
STM32_HRTIM_TIM_CMP1CR_OFFSET));
20832089

2084-
tmrinfo("\tCMP2:\t0x%08x\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n",
2090+
tmrinfo("\tCMP2:\t0x%08" PRIx32 "\tCMP3:\t0x%08" PRIx32
2091+
"\tCMP4:\t0x%08" PRIx32 "\n",
20852092
hrtim_tim_getreg(priv, timer,
20862093
STM32_HRTIM_TIM_CMP2R_OFFSET),
20872094
hrtim_tim_getreg(priv, timer,
20882095
STM32_HRTIM_TIM_CMP3R_OFFSET),
20892096
hrtim_tim_getreg(priv, timer,
20902097
STM32_HRTIM_TIM_CMP4R_OFFSET));
20912098

2092-
tmrinfo("\tCPT1:\t0x%08x\tCPT2:\t0x%08x\tDTR:\t0x%08x\n",
2099+
tmrinfo("\tCPT1:\t0x%08" PRIx32 "\tCPT2:\t0x%08" PRIx32
2100+
"\tDTR:\t0x%08" PRIx32 "\n",
20932101
hrtim_tim_getreg(priv, timer,
20942102
STM32_HRTIM_TIM_CPT1R_OFFSET),
20952103
hrtim_tim_getreg(priv, timer,
20962104
STM32_HRTIM_TIM_CPT2R_OFFSET),
20972105
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET));
20982106

2099-
tmrinfo("\tSET1:\t0x%08x\tRST1:\t0x%08x\tSET2:\t0x%08x\n",
2107+
tmrinfo("\tSET1:\t0x%08" PRIx32 "\tRST1:\t0x%08" PRIx32
2108+
"\tSET2:\t0x%08" PRIx32 "\n",
21002109
hrtim_tim_getreg(priv, timer,
21012110
STM32_HRTIM_TIM_SET1R_OFFSET),
21022111
hrtim_tim_getreg(priv, timer,
21032112
STM32_HRTIM_TIM_RST1R_OFFSET),
21042113
hrtim_tim_getreg(priv, timer,
21052114
STM32_HRTIM_TIM_SET2R_OFFSET));
21062115

2107-
tmrinfo("\tRST2:\t0x%08x\tEEF1:\t0x%08x\tEEF2:\t0x%08x\n",
2116+
tmrinfo("\tRST2:\t0x%08" PRIx32 "\tEEF1:\t0x%08" PRIx32
2117+
"\tEEF2:\t0x%08" PRIx32 "\n",
21082118
hrtim_tim_getreg(priv, timer,
21092119
STM32_HRTIM_TIM_RST2R_OFFSET),
21102120
hrtim_tim_getreg(priv, timer,
21112121
STM32_HRTIM_TIM_EEFR1_OFFSET),
21122122
hrtim_tim_getreg(priv, timer,
21132123
STM32_HRTIM_TIM_EEFR2_OFFSET));
21142124

2115-
tmrinfo("\tRSTR:\t0x%08x\tCHPR:\t0x%08x\tCPT1C:\t0x%08x\n",
2125+
tmrinfo("\tRSTR:\t0x%08" PRIx32 "\tCHPR:\t0x%08" PRIx32
2126+
"\tCPT1C:\t0x%08" PRIx32 "\n",
21162127
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET),
21172128
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET),
21182129
hrtim_tim_getreg(priv, timer,
21192130
STM32_HRTIM_TIM_CPT1CR_OFFSET));
21202131

2121-
tmrinfo("\tCPT2C:\t0x%08x\tOUT:\t0x%08x\tFLT:\t0x%08x\n",
2132+
tmrinfo("\tCPT2C:\t0x%08" PRIx32 "\tOUT:\t0x%08" PRIx32
2133+
"\tFLT:\t0x%08" PRIx32 "\n",
21222134
hrtim_tim_getreg(priv, timer,
21232135
STM32_HRTIM_TIM_CPT2CR_OFFSET),
21242136
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET),
@@ -2130,47 +2142,55 @@ static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer,
21302142

21312143
case HRTIM_TIMER_COMMON:
21322144
{
2133-
tmrinfo("\tCR1:\t0x%08x\tCR2:\t0x%08x\tISR:\t0x%08x\n",
2145+
tmrinfo("\tCR1:\t0x%08" PRIx32 "\tCR2:\t0x%08" PRIx32
2146+
"\tISR:\t0x%08" PRIx32 "\n",
21342147
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR1_OFFSET),
21352148
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR2_OFFSET),
21362149
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET));
21372150

2138-
tmrinfo("\tICR:\t0x%08x\tIER:\t0x%08x\tOENR:\t0x%08x\n",
2151+
tmrinfo("\tICR:\t0x%08" PRIx32 "\tIER:\t0x%08" PRIx32
2152+
"\tOENR:\t0x%08" PRIx32 "\n",
21392153
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ICR_OFFSET),
21402154
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_IER_OFFSET),
21412155
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_OENR_OFFSET));
21422156

2143-
tmrinfo("\tODISR:\t0x%08x\tODSR:\t0x%08x\tBMCR:\t0x%08x\n",
2157+
tmrinfo("\tODISR:\t0x%08" PRIx32 "\tODSR:\t0x%08" PRIx32
2158+
"\tBMCR:\t0x%08" PRIx32 "\n",
21442159
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODISR_OFFSET),
21452160
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODSR_OFFSET),
21462161
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET));
21472162

2148-
tmrinfo("\tBMTRG:\t0x%08x\tBMCMPR:\t0x%08x\tBMPER:\t0x%08x\n",
2163+
tmrinfo("\tBMTRG:\t0x%08" PRIx32 "\tBMCMPR:\t0x%08" PRIx32
2164+
"\tBMPER:\t0x%08" PRIx32 "\n",
21492165
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET),
21502166
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET),
21512167
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET));
21522168

2153-
tmrinfo("\tADC1R:\t0x%08x\tADC2R:\t0x%08x\tADC3R:\t0x%08x\n",
2169+
tmrinfo("\tADC1R:\t0x%08" PRIx32 "\tADC2R:\t0x%08" PRIx32
2170+
"\tADC3R:\t0x%08" PRIx32 "\n",
21542171
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET),
21552172
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET),
21562173
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET));
21572174

2158-
tmrinfo("\tADC4R:\t0x%08x\tDLLCR:\t0x%08x\tFLTIN1:\t0x%08x\n",
2175+
tmrinfo("\tADC4R:\t0x%08" PRIx32 "\tDLLCR:\t0x%08" PRIx32
2176+
"\tFLTIN1:\t0x%08" PRIx32 "\n",
21592177
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET),
21602178
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET),
21612179
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET));
21622180

2163-
tmrinfo("\tFLTIN2:\t0x%08x\tBDMUPD:\t0x%08x\tBDTAUP:\t0x%08x\n",
2181+
tmrinfo("\tFLTIN2:\t0x%08" PRIx32 "\tBDMUPD:\t0x%08" PRIx32
2182+
"\tBDTAUP:\t0x%08" PRIx32 "\n",
21642183
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET),
21652184
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMUPDR_OFFSET),
21662185
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTAUPR_OFFSET));
21672186

2168-
tmrinfo("\tBDTBUP: 0x%08x\tBDTCUP:\t0x%08x\tBDTDUP:\t0x%08x\n",
2187+
tmrinfo("\tBDTBUP: 0x%08" PRIx32 "\tBDTCUP:\t0x%08" PRIx32
2188+
"\tBDTDUP:\t0x%08" PRIx32 "\n",
21692189
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTBUPR_OFFSET),
21702190
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTCUPR_OFFSET),
21712191
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTDUPR_OFFSET));
21722192

2173-
tmrinfo("\tBDTEUP:\t0x%08x\tBDMAD:\t0x%08x\n",
2193+
tmrinfo("\tBDTEUP:\t0x%08" PRIx32 "\tBDMAD:\t0x%08" PRIx32 "\n",
21742194
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTEUPR_OFFSET),
21752195
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMADR_OFFSET));
21762196

‎arch/arm/src/stm32/stm32_i2c.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -96,11 +96,11 @@
9696
****************************************************************************/
9797

9898
#if STM32_PCLK1_FREQUENCY < 4000000
99-
# warning STM32_I2C: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
99+
# warning "STM32_I2C: Periph clk must be at least 4MHz to support 400kHz."
100100
#endif
101101

102102
#if STM32_PCLK1_FREQUENCY < 2000000
103-
# error STM32_I2C: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
103+
# error "STM32_I2C: Periph clk must be at least 2MHz to support 100kHz."
104104
#endif
105105

106106
/* Configuration ************************************************************/
@@ -832,7 +832,8 @@ static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv)
832832
{
833833
trace = &priv->trace[i];
834834
syslog(LOG_DEBUG,
835-
"%2d. STATUS: %08x COUNT: %3d EVENT: %s(%2d) PARM: %08x TIME: %d\n",
835+
"%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %s(%2d) PARM:"
836+
" %08" PRIx32 " TIME: %d\n",
836837
i + 1, trace->status, trace->count, g_trace_names[trace->event],
837838
trace->event, trace->parm, trace->time - priv->start_time);
838839
}

‎arch/arm/src/stm32/stm32_i2c_alt.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -857,7 +857,8 @@ static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv)
857857
{
858858
trace = &priv->trace[i];
859859
syslog(LOG_DEBUG,
860-
"%2d. STATUS: %08x COUNT: %4d EVENT: %4d PARM: %08x TIME: %d\n",
860+
"%2d. STATUS: %08" PRIx32 " COUNT: %4d EVENT: %4d PARM:"
861+
" %08" PRIx32 " TIME: %d\n",
861862
i + 1, trace->status, trace->count, trace->event, trace->parm,
862863
trace->time - priv->start_time);
863864
}

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