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4 | 4 |
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5 | 5 | #if defined(_STM32_DEF_) || defined(TARGET_STM32H7) // if stm32duino or portenta |
6 | 6 |
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| 7 | +#if defined(HAL_TIM_MODULE_ONLY) |
| 8 | + |
| 9 | +//Functions copied over and modified from HardwareTimer to allow disabling HardwareTimer |
| 10 | + |
| 11 | +void enableTimerClock(TIM_HandleTypeDef *htim) |
| 12 | +{ |
| 13 | + // Enable TIM clock |
| 14 | +#if defined(TIM1_BASE) |
| 15 | + if (htim->Instance == TIM1) { |
| 16 | + __HAL_RCC_TIM1_CLK_ENABLE(); |
| 17 | + } |
| 18 | +#endif |
| 19 | +#if defined(TIM2_BASE) |
| 20 | + if (htim->Instance == TIM2) { |
| 21 | + __HAL_RCC_TIM2_CLK_ENABLE(); |
| 22 | + } |
| 23 | +#endif |
| 24 | +#if defined(TIM3_BASE) |
| 25 | + if (htim->Instance == TIM3) { |
| 26 | + __HAL_RCC_TIM3_CLK_ENABLE(); |
| 27 | + } |
| 28 | +#endif |
| 29 | +#if defined(TIM4_BASE) |
| 30 | + if (htim->Instance == TIM4) { |
| 31 | + __HAL_RCC_TIM4_CLK_ENABLE(); |
| 32 | + } |
| 33 | +#endif |
| 34 | +#if defined(TIM5_BASE) |
| 35 | + if (htim->Instance == TIM5) { |
| 36 | + __HAL_RCC_TIM5_CLK_ENABLE(); |
| 37 | + } |
| 38 | +#endif |
| 39 | +#if defined(TIM6_BASE) |
| 40 | + if (htim->Instance == TIM6) { |
| 41 | + __HAL_RCC_TIM6_CLK_ENABLE(); |
| 42 | + } |
| 43 | +#endif |
| 44 | +#if defined(TIM7_BASE) |
| 45 | + if (htim->Instance == TIM7) { |
| 46 | + __HAL_RCC_TIM7_CLK_ENABLE(); |
| 47 | + } |
| 48 | +#endif |
| 49 | +#if defined(TIM8_BASE) |
| 50 | + if (htim->Instance == TIM8) { |
| 51 | + __HAL_RCC_TIM8_CLK_ENABLE(); |
| 52 | + } |
| 53 | +#endif |
| 54 | +#if defined(TIM9_BASE) |
| 55 | + if (htim->Instance == TIM9) { |
| 56 | + __HAL_RCC_TIM9_CLK_ENABLE(); |
| 57 | + } |
| 58 | +#endif |
| 59 | +#if defined(TIM10_BASE) |
| 60 | + if (htim->Instance == TIM10) { |
| 61 | + __HAL_RCC_TIM10_CLK_ENABLE(); |
| 62 | + } |
| 63 | +#endif |
| 64 | +#if defined(TIM11_BASE) |
| 65 | + if (htim->Instance == TIM11) { |
| 66 | + __HAL_RCC_TIM11_CLK_ENABLE(); |
| 67 | + } |
| 68 | +#endif |
| 69 | +#if defined(TIM12_BASE) |
| 70 | + if (htim->Instance == TIM12) { |
| 71 | + __HAL_RCC_TIM12_CLK_ENABLE(); |
| 72 | + } |
| 73 | +#endif |
| 74 | +#if defined(TIM13_BASE) |
| 75 | + if (htim->Instance == TIM13) { |
| 76 | + __HAL_RCC_TIM13_CLK_ENABLE(); |
| 77 | + } |
| 78 | +#endif |
| 79 | +#if defined(TIM14_BASE) |
| 80 | + if (htim->Instance == TIM14) { |
| 81 | + __HAL_RCC_TIM14_CLK_ENABLE(); |
| 82 | + } |
| 83 | +#endif |
| 84 | +#if defined(TIM15_BASE) |
| 85 | + if (htim->Instance == TIM15) { |
| 86 | + __HAL_RCC_TIM15_CLK_ENABLE(); |
| 87 | + } |
| 88 | +#endif |
| 89 | +#if defined(TIM16_BASE) |
| 90 | + if (htim->Instance == TIM16) { |
| 91 | + __HAL_RCC_TIM16_CLK_ENABLE(); |
| 92 | + } |
| 93 | +#endif |
| 94 | +#if defined(TIM17_BASE) |
| 95 | + if (htim->Instance == TIM17) { |
| 96 | + __HAL_RCC_TIM17_CLK_ENABLE(); |
| 97 | + } |
| 98 | +#endif |
| 99 | +#if defined(TIM18_BASE) |
| 100 | + if (htim->Instance == TIM18) { |
| 101 | + __HAL_RCC_TIM18_CLK_ENABLE(); |
| 102 | + } |
| 103 | +#endif |
| 104 | +#if defined(TIM19_BASE) |
| 105 | + if (htim->Instance == TIM19) { |
| 106 | + __HAL_RCC_TIM19_CLK_ENABLE(); |
| 107 | + } |
| 108 | +#endif |
| 109 | +#if defined(TIM20_BASE) |
| 110 | + if (htim->Instance == TIM20) { |
| 111 | + __HAL_RCC_TIM20_CLK_ENABLE(); |
| 112 | + } |
| 113 | +#endif |
| 114 | +#if defined(TIM21_BASE) |
| 115 | + if (htim->Instance == TIM21) { |
| 116 | + __HAL_RCC_TIM21_CLK_ENABLE(); |
| 117 | + } |
| 118 | +#endif |
| 119 | +#if defined(TIM22_BASE) |
| 120 | + if (htim->Instance == TIM22) { |
| 121 | + __HAL_RCC_TIM22_CLK_ENABLE(); |
| 122 | + } |
| 123 | +#endif |
| 124 | +} |
| 125 | + |
| 126 | +uint8_t getTimerClkSrc(TIM_TypeDef *tim) |
| 127 | +{ |
| 128 | + uint8_t clkSrc = 0; |
| 129 | + |
| 130 | + if (tim != (TIM_TypeDef *)NC) |
| 131 | +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) |
| 132 | + /* TIMx source CLK is PCKL1 */ |
| 133 | + clkSrc = 1; |
| 134 | +#else |
| 135 | + { |
| 136 | + /* Get source clock depending on TIM instance */ |
| 137 | + switch ((uint32_t)tim) { |
| 138 | +#if defined(TIM2_BASE) |
| 139 | + case (uint32_t)TIM2_BASE: |
| 140 | +#endif |
| 141 | +#if defined(TIM3_BASE) |
| 142 | + case (uint32_t)TIM3_BASE: |
| 143 | +#endif |
| 144 | +#if defined(TIM4_BASE) |
| 145 | + case (uint32_t)TIM4_BASE: |
| 146 | +#endif |
| 147 | +#if defined(TIM5_BASE) |
| 148 | + case (uint32_t)TIM5_BASE: |
| 149 | +#endif |
| 150 | +#if defined(TIM6_BASE) |
| 151 | + case (uint32_t)TIM6_BASE: |
| 152 | +#endif |
| 153 | +#if defined(TIM7_BASE) |
| 154 | + case (uint32_t)TIM7_BASE: |
| 155 | +#endif |
| 156 | +#if defined(TIM12_BASE) |
| 157 | + case (uint32_t)TIM12_BASE: |
| 158 | +#endif |
| 159 | +#if defined(TIM13_BASE) |
| 160 | + case (uint32_t)TIM13_BASE: |
| 161 | +#endif |
| 162 | +#if defined(TIM14_BASE) |
| 163 | + case (uint32_t)TIM14_BASE: |
| 164 | +#endif |
| 165 | +#if defined(TIM18_BASE) |
| 166 | + case (uint32_t)TIM18_BASE: |
| 167 | +#endif |
| 168 | + clkSrc = 1; |
| 169 | + break; |
| 170 | +#if defined(TIM1_BASE) |
| 171 | + case (uint32_t)TIM1_BASE: |
| 172 | +#endif |
| 173 | +#if defined(TIM8_BASE) |
| 174 | + case (uint32_t)TIM8_BASE: |
| 175 | +#endif |
| 176 | +#if defined(TIM9_BASE) |
| 177 | + case (uint32_t)TIM9_BASE: |
| 178 | +#endif |
| 179 | +#if defined(TIM10_BASE) |
| 180 | + case (uint32_t)TIM10_BASE: |
| 181 | +#endif |
| 182 | +#if defined(TIM11_BASE) |
| 183 | + case (uint32_t)TIM11_BASE: |
| 184 | +#endif |
| 185 | +#if defined(TIM15_BASE) |
| 186 | + case (uint32_t)TIM15_BASE: |
| 187 | +#endif |
| 188 | +#if defined(TIM16_BASE) |
| 189 | + case (uint32_t)TIM16_BASE: |
| 190 | +#endif |
| 191 | +#if defined(TIM17_BASE) |
| 192 | + case (uint32_t)TIM17_BASE: |
| 193 | +#endif |
| 194 | +#if defined(TIM19_BASE) |
| 195 | + case (uint32_t)TIM19_BASE: |
| 196 | +#endif |
| 197 | +#if defined(TIM20_BASE) |
| 198 | + case (uint32_t)TIM20_BASE: |
| 199 | +#endif |
| 200 | +#if defined(TIM21_BASE) |
| 201 | + case (uint32_t)TIM21_BASE: |
| 202 | +#endif |
| 203 | +#if defined(TIM22_BASE) |
| 204 | + case (uint32_t)TIM22_BASE: |
| 205 | +#endif |
| 206 | + clkSrc = 2; |
| 207 | + break; |
| 208 | + default: |
| 209 | + _Error_Handler("TIM: Unknown timer instance", (int)tim); |
| 210 | + break; |
| 211 | + } |
| 212 | + } |
| 213 | +#endif |
| 214 | + return clkSrc; |
| 215 | +} |
| 216 | +#endif |
7 | 217 |
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8 | 218 | void stm32_pauseTimer(TIM_HandleTypeDef* handle){ |
9 | 219 | /* Disable timer unconditionally. Required to guarantee timer is stopped, |
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