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10 | 10 |
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11 | 11 | void enableTimerClock(TIM_HandleTypeDef *htim) |
12 | 12 | { |
13 | | - // Enable TIM clock |
| 13 | + switch ((uintptr_t)htim->Instance) |
| 14 | + { |
14 | 15 | #if defined(TIM1_BASE) |
15 | | - if (htim->Instance == TIM1) { |
| 16 | + case TIM1_BASE: |
16 | 17 | __HAL_RCC_TIM1_CLK_ENABLE(); |
17 | | - } |
| 18 | + return; |
18 | 19 | #endif |
19 | 20 | #if defined(TIM2_BASE) |
20 | | - if (htim->Instance == TIM2) { |
| 21 | + case TIM2_BASE: |
21 | 22 | __HAL_RCC_TIM2_CLK_ENABLE(); |
22 | | - } |
| 23 | + return; |
23 | 24 | #endif |
24 | 25 | #if defined(TIM3_BASE) |
25 | | - if (htim->Instance == TIM3) { |
| 26 | + case TIM3_BASE: |
26 | 27 | __HAL_RCC_TIM3_CLK_ENABLE(); |
27 | | - } |
| 28 | + return; |
28 | 29 | #endif |
29 | 30 | #if defined(TIM4_BASE) |
30 | | - if (htim->Instance == TIM4) { |
| 31 | + case TIM4_BASE: |
31 | 32 | __HAL_RCC_TIM4_CLK_ENABLE(); |
32 | | - } |
| 33 | + return; |
33 | 34 | #endif |
34 | 35 | #if defined(TIM5_BASE) |
35 | | - if (htim->Instance == TIM5) { |
| 36 | + case TIM5_BASE: |
36 | 37 | __HAL_RCC_TIM5_CLK_ENABLE(); |
37 | | - } |
| 38 | + return; |
38 | 39 | #endif |
39 | 40 | #if defined(TIM6_BASE) |
40 | | - if (htim->Instance == TIM6) { |
| 41 | + case TIM6_BASE: |
41 | 42 | __HAL_RCC_TIM6_CLK_ENABLE(); |
42 | | - } |
| 43 | + return; |
43 | 44 | #endif |
44 | 45 | #if defined(TIM7_BASE) |
45 | | - if (htim->Instance == TIM7) { |
| 46 | + case TIM7_BASE: |
46 | 47 | __HAL_RCC_TIM7_CLK_ENABLE(); |
47 | | - } |
| 48 | + return; |
48 | 49 | #endif |
49 | 50 | #if defined(TIM8_BASE) |
50 | | - if (htim->Instance == TIM8) { |
| 51 | + case TIM8_BASE: |
51 | 52 | __HAL_RCC_TIM8_CLK_ENABLE(); |
52 | | - } |
| 53 | + return; |
53 | 54 | #endif |
54 | 55 | #if defined(TIM9_BASE) |
55 | | - if (htim->Instance == TIM9) { |
| 56 | + case TIM9_BASE: |
56 | 57 | __HAL_RCC_TIM9_CLK_ENABLE(); |
57 | | - } |
| 58 | + return; |
58 | 59 | #endif |
59 | 60 | #if defined(TIM10_BASE) |
60 | | - if (htim->Instance == TIM10) { |
| 61 | + case TIM10_BASE: |
61 | 62 | __HAL_RCC_TIM10_CLK_ENABLE(); |
62 | | - } |
| 63 | + return; |
63 | 64 | #endif |
64 | 65 | #if defined(TIM11_BASE) |
65 | | - if (htim->Instance == TIM11) { |
| 66 | + case TIM11_BASE: |
66 | 67 | __HAL_RCC_TIM11_CLK_ENABLE(); |
67 | | - } |
| 68 | + return; |
68 | 69 | #endif |
69 | 70 | #if defined(TIM12_BASE) |
70 | | - if (htim->Instance == TIM12) { |
| 71 | + case TIM12_BASE: |
71 | 72 | __HAL_RCC_TIM12_CLK_ENABLE(); |
72 | | - } |
| 73 | + return; |
73 | 74 | #endif |
74 | 75 | #if defined(TIM13_BASE) |
75 | | - if (htim->Instance == TIM13) { |
| 76 | + case TIM13_BASE: |
76 | 77 | __HAL_RCC_TIM13_CLK_ENABLE(); |
77 | | - } |
| 78 | + return; |
78 | 79 | #endif |
79 | 80 | #if defined(TIM14_BASE) |
80 | | - if (htim->Instance == TIM14) { |
| 81 | + case TIM14_BASE: |
81 | 82 | __HAL_RCC_TIM14_CLK_ENABLE(); |
82 | | - } |
| 83 | + return; |
83 | 84 | #endif |
84 | 85 | #if defined(TIM15_BASE) |
85 | | - if (htim->Instance == TIM15) { |
| 86 | + case TIM15_BASE: |
86 | 87 | __HAL_RCC_TIM15_CLK_ENABLE(); |
87 | | - } |
| 88 | + return; |
88 | 89 | #endif |
89 | 90 | #if defined(TIM16_BASE) |
90 | | - if (htim->Instance == TIM16) { |
| 91 | + case TIM16_BASE: |
91 | 92 | __HAL_RCC_TIM16_CLK_ENABLE(); |
92 | | - } |
| 93 | + return; |
93 | 94 | #endif |
94 | 95 | #if defined(TIM17_BASE) |
95 | | - if (htim->Instance == TIM17) { |
| 96 | + case TIM17_BASE: |
96 | 97 | __HAL_RCC_TIM17_CLK_ENABLE(); |
97 | | - } |
| 98 | + return; |
98 | 99 | #endif |
99 | 100 | #if defined(TIM18_BASE) |
100 | | - if (htim->Instance == TIM18) { |
| 101 | + case TIM18_BASE: |
101 | 102 | __HAL_RCC_TIM18_CLK_ENABLE(); |
102 | | - } |
| 103 | + return; |
103 | 104 | #endif |
104 | 105 | #if defined(TIM19_BASE) |
105 | | - if (htim->Instance == TIM19) { |
| 106 | + case TIM19_BASE: |
106 | 107 | __HAL_RCC_TIM19_CLK_ENABLE(); |
107 | | - } |
| 108 | + return; |
108 | 109 | #endif |
109 | 110 | #if defined(TIM20_BASE) |
110 | | - if (htim->Instance == TIM20) { |
| 111 | + case TIM20_BASE: |
111 | 112 | __HAL_RCC_TIM20_CLK_ENABLE(); |
112 | | - } |
| 113 | + return; |
113 | 114 | #endif |
114 | 115 | #if defined(TIM21_BASE) |
115 | | - if (htim->Instance == TIM21) { |
| 116 | + case TIM21_BASE: |
116 | 117 | __HAL_RCC_TIM21_CLK_ENABLE(); |
117 | | - } |
| 118 | + return; |
118 | 119 | #endif |
119 | 120 | #if defined(TIM22_BASE) |
120 | | - if (htim->Instance == TIM22) { |
| 121 | + case TIM22_BASE: |
121 | 122 | __HAL_RCC_TIM22_CLK_ENABLE(); |
122 | | - } |
| 123 | + return; |
123 | 124 | #endif |
124 | | -} |
125 | | - |
126 | | -uint8_t getTimerClkSrc(TIM_TypeDef *tim) |
127 | | -{ |
128 | | - uint8_t clkSrc = 0; |
129 | | - |
130 | | - if (tim != (TIM_TypeDef *)NC) |
131 | | -#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) |
132 | | - /* TIMx source CLK is PCKL1 */ |
133 | | - clkSrc = 1; |
134 | | -#else |
135 | | - { |
136 | | - /* Get source clock depending on TIM instance */ |
137 | | - switch ((uint32_t)tim) { |
138 | | -#if defined(TIM2_BASE) |
139 | | - case (uint32_t)TIM2_BASE: |
140 | | -#endif |
141 | | -#if defined(TIM3_BASE) |
142 | | - case (uint32_t)TIM3_BASE: |
143 | | -#endif |
144 | | -#if defined(TIM4_BASE) |
145 | | - case (uint32_t)TIM4_BASE: |
146 | | -#endif |
147 | | -#if defined(TIM5_BASE) |
148 | | - case (uint32_t)TIM5_BASE: |
149 | | -#endif |
150 | | -#if defined(TIM6_BASE) |
151 | | - case (uint32_t)TIM6_BASE: |
152 | | -#endif |
153 | | -#if defined(TIM7_BASE) |
154 | | - case (uint32_t)TIM7_BASE: |
155 | | -#endif |
156 | | -#if defined(TIM12_BASE) |
157 | | - case (uint32_t)TIM12_BASE: |
158 | | -#endif |
159 | | -#if defined(TIM13_BASE) |
160 | | - case (uint32_t)TIM13_BASE: |
161 | | -#endif |
162 | | -#if defined(TIM14_BASE) |
163 | | - case (uint32_t)TIM14_BASE: |
164 | | -#endif |
165 | | -#if defined(TIM18_BASE) |
166 | | - case (uint32_t)TIM18_BASE: |
167 | | -#endif |
168 | | - clkSrc = 1; |
169 | | - break; |
170 | | -#if defined(TIM1_BASE) |
171 | | - case (uint32_t)TIM1_BASE: |
172 | | -#endif |
173 | | -#if defined(TIM8_BASE) |
174 | | - case (uint32_t)TIM8_BASE: |
175 | | -#endif |
176 | | -#if defined(TIM9_BASE) |
177 | | - case (uint32_t)TIM9_BASE: |
178 | | -#endif |
179 | | -#if defined(TIM10_BASE) |
180 | | - case (uint32_t)TIM10_BASE: |
181 | | -#endif |
182 | | -#if defined(TIM11_BASE) |
183 | | - case (uint32_t)TIM11_BASE: |
184 | | -#endif |
185 | | -#if defined(TIM15_BASE) |
186 | | - case (uint32_t)TIM15_BASE: |
187 | | -#endif |
188 | | -#if defined(TIM16_BASE) |
189 | | - case (uint32_t)TIM16_BASE: |
190 | | -#endif |
191 | | -#if defined(TIM17_BASE) |
192 | | - case (uint32_t)TIM17_BASE: |
193 | | -#endif |
194 | | -#if defined(TIM19_BASE) |
195 | | - case (uint32_t)TIM19_BASE: |
196 | | -#endif |
197 | | -#if defined(TIM20_BASE) |
198 | | - case (uint32_t)TIM20_BASE: |
199 | | -#endif |
200 | | -#if defined(TIM21_BASE) |
201 | | - case (uint32_t)TIM21_BASE: |
202 | | -#endif |
203 | | -#if defined(TIM22_BASE) |
204 | | - case (uint32_t)TIM22_BASE: |
205 | | -#endif |
206 | | - clkSrc = 2; |
207 | | - break; |
208 | | - default: |
209 | | - _Error_Handler("TIM: Unknown timer instance", (int)tim); |
210 | | - break; |
211 | | - } |
| 125 | + |
| 126 | + default: |
| 127 | + break; |
212 | 128 | } |
213 | | -#endif |
214 | | - return clkSrc; |
215 | 129 | } |
| 130 | + |
216 | 131 | #endif |
217 | 132 |
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218 | 133 | void stm32_pauseTimer(TIM_HandleTypeDef* handle){ |
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