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initial config - not 100% working
1 parent 222e547 commit dcc51d2

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Lines changed: 55 additions & 24 deletions

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src/current_sense/hardware_specific/esp32/esp32_adc_driver.cpp

Lines changed: 55 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -98,29 +98,6 @@ uint16_t IRAM_ATTR adcRead(uint8_t pin)
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#include "soc/sens_reg.h"
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101-
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// configure the ADCs in RTC mode
103-
// no real gain - see if we do something with it later
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// void __configFastADCs(){
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// SET_PERI_REG_MASK(SENS_SAR_READER1_CTRL_REG, SENS_SAR1_DATA_INV);
107-
// SET_PERI_REG_MASK(SENS_SAR_READER2_CTRL_REG, SENS_SAR2_DATA_INV);
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// SET_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_MEAS1_START_FORCE_M); //SAR ADC1 controller (in RTC) is started by SW
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// SET_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_SAR1_EN_PAD_FORCE_M); //SAR ADC1 pad enable bitmap is controlled by SW
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// SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_MEAS2_START_FORCE_M); //SAR ADC2 controller (in RTC) is started by SW
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// SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_SAR2_EN_PAD_FORCE_M); //SAR ADC2 pad enable bitmap is controlled by SW
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// CLEAR_PERI_REG_MASK(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR_M); //force XPD_SAR=0, use XPD_FSM
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// SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_AMP, 0x2, SENS_FORCE_XPD_AMP_S); //force XPD_AMP=0
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// CLEAR_PERI_REG_MASK(SENS_SAR_AMP_CTRL3_REG, 0xfff << SENS_AMP_RST_FB_FSM_S); //clear FSM
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// SET_PERI_REG_BITS(SENS_SAR_AMP_CTRL1_REG, SENS_SAR_AMP_WAIT1, 0x1, SENS_SAR_AMP_WAIT1_S);
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// SET_PERI_REG_BITS(SENS_SAR_AMP_CTRL1_REG, SENS_SAR_AMP_WAIT2, 0x1, SENS_SAR_AMP_WAIT2_S);
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// SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_SAR_AMP_WAIT3, 0x1, SENS_SAR_AMP_WAIT3_S);
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// while (GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR1_REG, 0x7, SENS_SARADC_MEAS_STATUS_S) != 0); //wait det_fsm==
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// }
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uint16_t IRAM_ATTR adcRead(uint8_t pin)
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{
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int8_t channel = digitalPinToAnalogChannel(pin);
@@ -171,6 +148,60 @@ uint16_t IRAM_ATTR adcRead(uint8_t pin)
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return value;
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}
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151+
#elif CONFIG_IDF_TARGET_ESP32C6 // if esp32 c6 variant
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#include "hal/adc_ll.h"
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#include "hal/adc_oneshot_hal.h"
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static adc_oneshot_hal_ctx_t adc1_oneshot_hal;
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static bool adc1_oneshot_hal_initialized = false;
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void IRAM_ATTR __configFastADCs(){
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if (adc1_oneshot_hal_initialized) return;
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adc_oneshot_hal_cfg_t config;
163+
config.unit = ADC_UNIT_1;
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config.work_mode = ADC_HAL_SINGLE_READ_MODE;
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config.clk_src = ADC_DIGI_CLK_SRC_DEFAULT;
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config.clk_src_freq_hz = 0;
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adc_oneshot_hal_init(&adc1_oneshot_hal, &config);
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adc1_oneshot_hal_initialized = true;
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}
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uint16_t IRAM_ATTR adcRead(uint8_t pin)
173+
{
174+
int8_t channel = digitalPinToAnalogChannel(pin);
175+
if(channel < 0){
176+
SIMPLEFOC_ESP32_CS_DEBUG("ERROR: Not ADC pin: "+String(pin));
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return false; //not adc pin
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}
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if (channel >= SOC_ADC_MAX_CHANNEL_NUM) {
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SIMPLEFOC_ESP32_CS_DEBUG("ERROR: ESP32C6 supports only ADC1 channels. Pin: "+String(pin));
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return false;
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}
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if (!adc1_oneshot_hal_initialized) {
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__configFastADCs();
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}
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uint16_t value = 0;
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int raw = 0;
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// Protects against core migration, on single core chips this is noop.
193+
portENTER_CRITICAL(&spinlock);
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adc_oneshot_hal_setup(&adc1_oneshot_hal, (adc_channel_t)channel);
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if (adc_oneshot_hal_convert(&adc1_oneshot_hal, &raw)) {
197+
value = (uint16_t)raw;
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}
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portEXIT_CRITICAL(&spinlock);
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return value;
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}
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#else // if others just use analogRead
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#pragma message("SimpleFOC: Using analogRead for ADC reading, no fast ADC configuration available!")
@@ -205,7 +236,7 @@ bool IRAM_ATTR adcInit(uint8_t pin){
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analogRead(pin);
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analogSetPinAttenuation(pin, SIMPLEFOC_ADC_ATTEN);
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208-
#if CONFIG_IDF_TARGET_ESP32 // if esp32 variant
239+
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C6 // if esp32 / esp32c6 variant
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__configFastADCs();
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#endif
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