@@ -98,29 +98,6 @@ uint16_t IRAM_ATTR adcRead(uint8_t pin)
9898
9999#include " soc/sens_reg.h"
100100
101-
102- // configure the ADCs in RTC mode
103- // no real gain - see if we do something with it later
104- // void __configFastADCs(){
105-
106- // SET_PERI_REG_MASK(SENS_SAR_READER1_CTRL_REG, SENS_SAR1_DATA_INV);
107- // SET_PERI_REG_MASK(SENS_SAR_READER2_CTRL_REG, SENS_SAR2_DATA_INV);
108-
109- // SET_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_MEAS1_START_FORCE_M); //SAR ADC1 controller (in RTC) is started by SW
110- // SET_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_SAR1_EN_PAD_FORCE_M); //SAR ADC1 pad enable bitmap is controlled by SW
111- // SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_MEAS2_START_FORCE_M); //SAR ADC2 controller (in RTC) is started by SW
112- // SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_SAR2_EN_PAD_FORCE_M); //SAR ADC2 pad enable bitmap is controlled by SW
113-
114- // CLEAR_PERI_REG_MASK(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR_M); //force XPD_SAR=0, use XPD_FSM
115- // SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_AMP, 0x2, SENS_FORCE_XPD_AMP_S); //force XPD_AMP=0
116-
117- // CLEAR_PERI_REG_MASK(SENS_SAR_AMP_CTRL3_REG, 0xfff << SENS_AMP_RST_FB_FSM_S); //clear FSM
118- // SET_PERI_REG_BITS(SENS_SAR_AMP_CTRL1_REG, SENS_SAR_AMP_WAIT1, 0x1, SENS_SAR_AMP_WAIT1_S);
119- // SET_PERI_REG_BITS(SENS_SAR_AMP_CTRL1_REG, SENS_SAR_AMP_WAIT2, 0x1, SENS_SAR_AMP_WAIT2_S);
120- // SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_SAR_AMP_WAIT3, 0x1, SENS_SAR_AMP_WAIT3_S);
121- // while (GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR1_REG, 0x7, SENS_SARADC_MEAS_STATUS_S) != 0); //wait det_fsm==
122- // }
123-
124101uint16_t IRAM_ATTR adcRead (uint8_t pin)
125102{
126103 int8_t channel = digitalPinToAnalogChannel (pin);
@@ -171,6 +148,60 @@ uint16_t IRAM_ATTR adcRead(uint8_t pin)
171148 return value;
172149}
173150
151+ #elif CONFIG_IDF_TARGET_ESP32C6 // if esp32 c6 variant
152+
153+ #include " hal/adc_ll.h"
154+ #include " hal/adc_oneshot_hal.h"
155+
156+ static adc_oneshot_hal_ctx_t adc1_oneshot_hal;
157+ static bool adc1_oneshot_hal_initialized = false ;
158+
159+ void IRAM_ATTR __configFastADCs (){
160+ if (adc1_oneshot_hal_initialized) return ;
161+
162+ adc_oneshot_hal_cfg_t config;
163+ config.unit = ADC_UNIT_1 ;
164+ config.work_mode = ADC_HAL_SINGLE_READ_MODE ;
165+ config.clk_src = ADC_DIGI_CLK_SRC_DEFAULT ;
166+ config.clk_src_freq_hz = 0 ;
167+
168+ adc_oneshot_hal_init (&adc1_oneshot_hal, &config);
169+ adc1_oneshot_hal_initialized = true ;
170+ }
171+
172+ uint16_t IRAM_ATTR adcRead (uint8_t pin)
173+ {
174+ int8_t channel = digitalPinToAnalogChannel (pin);
175+ if (channel < 0 ){
176+ SIMPLEFOC_ESP32_CS_DEBUG (" ERROR: Not ADC pin: " +String (pin));
177+ return false ; // not adc pin
178+ }
179+
180+ if (channel >= SOC_ADC_MAX_CHANNEL_NUM ) {
181+ SIMPLEFOC_ESP32_CS_DEBUG (" ERROR: ESP32C6 supports only ADC1 channels. Pin: " +String (pin));
182+ return false ;
183+ }
184+
185+ if (!adc1_oneshot_hal_initialized) {
186+ __configFastADCs ();
187+ }
188+
189+ uint16_t value = 0 ;
190+ int raw = 0 ;
191+
192+ // Protects against core migration, on single core chips this is noop.
193+ portENTER_CRITICAL (&spinlock);
194+
195+ adc_oneshot_hal_setup (&adc1_oneshot_hal, (adc_channel_t )channel);
196+ if (adc_oneshot_hal_convert (&adc1_oneshot_hal, &raw)) {
197+ value = (uint16_t )raw;
198+ }
199+
200+ portEXIT_CRITICAL (&spinlock);
201+
202+ return value;
203+ }
204+
174205#else // if others just use analogRead
175206
176207#pragma message("SimpleFOC: Using analogRead for ADC reading, no fast ADC configuration available!")
@@ -205,7 +236,7 @@ bool IRAM_ATTR adcInit(uint8_t pin){
205236 analogRead (pin);
206237 analogSetPinAttenuation (pin, SIMPLEFOC_ADC_ATTEN );
207238
208- #if CONFIG_IDF_TARGET_ESP32 // if esp32 variant
239+ #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C6 // if esp32 / esp32c6 variant
209240 __configFastADCs ();
210241#endif
211242
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