GitHub - sinasoltani123/32-bit-pipelined-MIPS-processor-implemented-using-Verilog-with-booth-multiplication-algorithm: 32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.v		ALU.v
ALUControl.v		ALUControl.v
ALUControl_tb.v		ALUControl_tb.v
ALUControl_tb2.v		ALUControl_tb2.v
ALU_tb.v		ALU_tb.v
BoothCU_tb.v		BoothCU_tb.v
BoothMultipilcation.v		BoothMultipilcation.v
BoothMultiplication_tb.v		BoothMultiplication_tb.v
BoothTB.v		BoothTB.v
Booth_AdderSubtractor.v		Booth_AdderSubtractor.v
Booth_AdderSubtractor_tb.v		Booth_AdderSubtractor_tb.v
Booth_ControlUnit.v		Booth_ControlUnit.v
Booth_ControlUnit_tb.v		Booth_ControlUnit_tb.v
Booth_ControlUnit_test.v		Booth_ControlUnit_test.v
Cache.v		Cache.v
ControlUnit.v		ControlUnit.v
ControlUnit_tb.v		ControlUnit_tb.v
DataMemory.v		DataMemory.v
DataMemory_tb.v		DataMemory_tb.v
Decode.v		Decode.v
Decode_new_tb.v		Decode_new_tb.v
Decode_tb.v		Decode_tb.v
EX_MEM.v		EX_MEM.v
EX_MEM_TB.v		EX_MEM_TB.v
Execute.v		Execute.v
Execute_tb.v		Execute_tb.v
Fetch.v		Fetch.v
Fetch_tb.v		Fetch_tb.v
ID_EX.v		ID_EX.v
ID_EX_tb.v		ID_EX_tb.v
IFID.v		IFID.v
IFID_tb.v		IFID_tb.v
InstructionMemory.v		InstructionMemory.v
MEM_WB.v		MEM_WB.v
MEM_WB_tb.v		MEM_WB_tb.v
MIPS.v		MIPS.v
MIPS_tb.v		MIPS_tb.v
MIPS_tb1.v		MIPS_tb1.v
Multiplexer.v		Multiplexer.v
PCRegister.v		PCRegister.v
RegisterFile.v		RegisterFile.v
SignExtend.v		SignExtend.v
WriteBack.v		WriteBack.v
Write_back_tb.v		Write_back_tb.v
booth_test.v		booth_test.v
fetch_new_test_bench.v		fetch_new_test_bench.v
mux.v		mux.v
mux_tb.v		mux_tb.v
mux_tb4.v		mux_tb4.v