AArch64: Add support for csel_xzr_ne to the A55, A72 uArch model

This commit adds support for the csel_xzr_ne instruction to the
A55, A72 uArch model.

This pattern is a variant of csel using the zero register xzr.
This commit reuses the existing csel uArch model definition for the
uArch model

- a55 SWOG CSEL(page: 18/48)
  - latency: 1
  - Inverse throughput: 2/2 = 1
  - ExecutionUnit: SCALAR (ALU0, ALU1)

- a72 SWOG CSEL(page: 8/42)
  - latency: 1
  - Inverse throughput: 2/2 = 1
  - ExecutionUnit: INT (INT0, INT1)

Signed-off-by: willieyz <willie.zhao@chelpis.com>

Author: willieyz

slothy/targets/aarch64/cortex_a55.py

@@ -66,6 +66,7 @@
     vmul,
     Instruction,
     csel,
+    csel_xzr_ne,
     fcsel,
     Q_Ld2_Lane_Post_Inc,
     q_ld2_lane_s,
@@ -461,7 +462,7 @@ def get_min_max_objective(slothy):
     # NOTE: AESE/AESMC and AESD/AESIMC pairs can be dual-issued on A55 but this
     # is not modeled
     AESInstruction: [[ExecutionUnit.VEC0, ExecutionUnit.VEC1]],
-    csel: ExecutionUnit.SCALAR(),
+    (csel, csel_xzr_ne): ExecutionUnit.SCALAR(),
     (
         crc32b,
         crc32h,
@@ -518,7 +519,7 @@ def get_min_max_objective(slothy):
     vshrn: 2,
     vtbl: 1,  # N cycles (N = number of registers in the table)
     (fcsel): 1,
-    csel: 1,
+    (csel, csel_xzr_ne): 1,
     (VecToGprMov, Mov_xtov_d, mov_wtov_s): 1,
     (
         movk_imm,
@@ -626,7 +627,7 @@ def get_min_max_objective(slothy):
     (Vins, umov_d): 2,
     (tst_wform): 1,
     (fcsel): 2,
-    csel: 1,
+    (csel, csel_xzr_ne): 1,
     (VecToGprMov, Mov_xtov_d, mov_wtov_s): 2,
     (
         movk_imm,

slothy/targets/aarch64/cortex_a72_frontend.py

@@ -125,6 +125,7 @@
     cmp,
     cmp_imm,
     csel,
+    csel_xzr_ne,
     q_ldp_with_inc,
     AArch64CRC32,
     asr,
@@ -239,7 +240,7 @@ def get_min_max_objective(slothy):
     ],
     (AArch64NeonShiftInsert, vusra): [ExecutionUnit.ASIMD1],
     fcsel: ExecutionUnit.ASIMD(),
-    csel: ExecutionUnit.INT(),
+    (csel, csel_xzr_ne): ExecutionUnit.INT(),
     AArch64ConditionalCompare: ExecutionUnit.INT(),
     AArch64Logical: [ExecutionUnit.INT()],
     # 8B/8H occupies both F0, F1
@@ -294,7 +295,7 @@ def get_min_max_objective(slothy):
     AArch64NeonLogical: 1,
     (AArch64NeonShiftInsert, vusra): 1,
     fcsel: 1,
-    csel: 1,
+    (csel, csel_xzr_ne): 1,
     AArch64ConditionalCompare: 1,
     AArch64Logical: 1,
     Vins: 1,
@@ -363,7 +364,7 @@ def get_min_max_objective(slothy):
     AArch64NeonShiftInsert: 3,
     vusra: 4,
     fcsel: 3,
-    csel: 1,
+    (csel, csel_xzr_ne): 1,
     AArch64ConditionalCompare: 1,
     AArch64Logical: 1,
     (Ldr_D, Ldr_Q, Ldr_X, Str_Q, Str_X): 4,  # approx

tests/naive/aarch64/instructions.s

@@ -219,5 +219,9 @@ fmov x5, d7
 
 asr x11, x12, x7
 asr x11, x12, #7
+csel x11, x10, xzr, eq
+csel x11, x10, xzr, ne
+csel x11, x10, xzr, lt
+csel x11, x10, xzr, gt
 
 end: