Add ASIMD widening/narrowing, FP vec, and LD1/ST1 multi-reg instructions

- Add new instruction classes to aarch64_neon.py: uaddl/uaddw/saddl
  family, rshrn/sqxtun/sqrshrun, urhadd, fmla/fmls/fmul/fadd/fsub vec
  and by-element forms, faddp vec/scalar, vmovi, Stp_Q, subs_imm,
  sub_shifted, sxtw, vdup_lane, Vrev, mov_vtov_s, vins_d_from_v,
  q_ld1_2/q_ld1_4 families (as independent classes, not Ldr_Q subclasses)
- Add timing (execution units, inverse throughput, latency) for all new
  instructions in cortex_a55, cortex_a72_frontend, neoverse_n1_experimental
- Update is_vector_load to include q_ld1_2/q_ld1_4 families
- Add test coverage in instructions.s

Author: dop-amin