From 037f93ff0d33cf575fee4b42c8e9f0ab3780b828 Mon Sep 17 00:00:00 2001
From: Amin Abdulrahman <amin@abdulrahman.de>
Date: Mon, 16 Jun 2025 12:43:22 +0200
Subject: [PATCH 1/2] feat: Add ifelse test for armv8m

---
 tests/naive/armv8m/_test.py | 10 ++++++++++
 tests/naive/armv8m/ifelse.s | 12 ++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 tests/naive/armv8m/ifelse.s

diff --git a/tests/naive/armv8m/_test.py b/tests/naive/armv8m/_test.py
index a86b84d41..9d4e357f6 100644
--- a/tests/naive/armv8m/_test.py
+++ b/tests/naive/armv8m/_test.py
@@ -130,6 +130,15 @@ def core(self, slothy):
         slothy.optimize()
 
 
+class IfElse(OptimizationRunner):
+    def __init__(self):
+        super().__init__("ifelse", base_dir="tests")
+
+    def core(self, slothy):
+        slothy.config.allow_useless_instructions = True
+        slothy.optimize(start="start", end="end")
+
+
 test_instances = [
     Instructions(),
     Instructions(target=Target_CortexM85r1),
@@ -141,4 +150,5 @@ def core(self, slothy):
     LoopLetp(),
     HintTest(),
     TagTest(),
+    IfElse(),
 ]
diff --git a/tests/naive/armv8m/ifelse.s b/tests/naive/armv8m/ifelse.s
new file mode 100644
index 000000000..4ef2c1ae6
--- /dev/null
+++ b/tests/naive/armv8m/ifelse.s
@@ -0,0 +1,12 @@
+.equ RCxy_44, 14
+.macro shift x, y
+.if (RCxy_\x\()\y % 2) == 0
+    vshr.u32 q<SHR_l>, q<A_l>, #32-(RCxy_\x\()\y/2)
+.else
+    vshr.u32 q<SHR_h>, q<A_l>, #32-((RCxy_\x\()\y-1)/2)
+.endif
+.endm
+
+start:
+shift 4, 4
+end:
\ No newline at end of file

From 37232ea85bb53db9d7f323206855060693fe480f Mon Sep 17 00:00:00 2001
From: Amin Abdulrahman <amin@abdulrahman.de>
Date: Tue, 24 Jun 2025 15:42:08 +0200
Subject: [PATCH 2/2] feat: Make ifelse armv8m test fail on wrong condition
 evaluation

---
 tests/naive/armv8m/ifelse.s | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/naive/armv8m/ifelse.s b/tests/naive/armv8m/ifelse.s
index 4ef2c1ae6..0fafab63c 100644
--- a/tests/naive/armv8m/ifelse.s
+++ b/tests/naive/armv8m/ifelse.s
@@ -3,7 +3,7 @@
 .if (RCxy_\x\()\y % 2) == 0
     vshr.u32 q<SHR_l>, q<A_l>, #32-(RCxy_\x\()\y/2)
 .else
-    vshr.u32 q<SHR_h>, q<A_l>, #32-((RCxy_\x\()\y-1)/2)
+    unimp
 .endif
 .endm