Add ASIMD widening/narrowing, FP vec, and LD1/ST1 multi-reg instructions#433
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Add ASIMD widening/narrowing, FP vec, and LD1/ST1 multi-reg instructions#433dop-amin wants to merge 2 commits into
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- Add new instruction classes to aarch64_neon.py: uaddl/uaddw/saddl family, rshrn/sqxtun/sqrshrun, urhadd, fmla/fmls/fmul/fadd/fsub vec and by-element forms, faddp vec/scalar, vmovi, Stp_Q, subs_imm, sub_shifted, sxtw, vdup_lane, Vrev, mov_vtov_s, vins_d_from_v, q_ld1_2/q_ld1_4 families (as independent classes, not Ldr_Q subclasses)
- Add timing (execution units, inverse throughput, latency) for all new instructions in cortex_a55, cortex_a72_frontend, neoverse_n1_experimental
- Update is_vector_load to include q_ld1_2/q_ld1_4 families
- Add test coverage in instructions.s
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* Add fast mul->mla forwarding (accumulate_latency=1): vmul/vmul_lane result forwarding to the accumulate operand of vmla/vmla_lane/vmls/vmls_lane * Add fast mla->mla forwarding (accumulate_latency=1): chained vmla/vmla_lane/vmls/vmls_lane accumulate operand forwarding * Add fast mull->mlal forwarding (accumulate_latency=1): Vmull result forwarding to the accumulate operand of Vmlal subclasses
- Add new instruction classes to aarch64_neon.py: uaddl/uaddw/saddl family, rshrn/sqxtun/sqrshrun, urhadd, fmla/fmls/fmul/fadd/fsub vec and by-element forms, faddp vec/scalar, vmovi, Stp_Q, subs_imm, sub_shifted, sxtw, vdup_lane, Vrev, mov_vtov_s, vins_d_from_v, q_ld1_2/q_ld1_4 families (as independent classes, not Ldr_Q subclasses) - Add timing (execution units, inverse throughput, latency) for all new instructions in cortex_a55, cortex_a72_frontend, neoverse_n1_experimental - Update is_vector_load to include q_ld1_2/q_ld1_4 families - Add test coverage in instructions.s - Add subs_wform to cortex_a72_frontend (latency=1, ITP=1, units=INT)
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