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RISC-V: Add vector support#435

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thisisjube wants to merge 41 commits into
slothy-optimizer:mainfrom
thisisjube:riscv-rvv
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RISC-V: Add vector support#435
thisisjube wants to merge 41 commits into
slothy-optimizer:mainfrom
thisisjube:riscv-rvv

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Adds support for the RISC-V "V"-Extension v1.0-rc1.

…rce LMUL=1), unfold ntt_kyber example and add multiple optimization regions (vsetvli/ lmul problem), linting
…fter optimization. wip: make vsetvl* write to CSR regs and vector instructions read from it to prevent wrong scheduling
Previously, we had to set lmul manually for each optimization region.
SLOTHY was already able to set LMUL when it parsed a vsetvl* instruction.
However, there were no constraints that connected vector incstructions
to their corresponding vsetvl* instruction. This has been modeled now,
as vsetvl* now has a CSR reg as output and all vector instructions inherntly
read from that CSR reg. Moreover, all vector instructions store the
lmul value they are constrained to as well.
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