AArch64: Missing instructions: asr, csel_xzr_ne, cmp_xzr#444
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This commit add the asr (register) and asr (immediate)instruction support the a55, a72 model. According to A64 Base Instruction Descriptions, page C6-1820 and page C6-1822, these two instructions are the aliases of: asr (register) ---> ASRV, asr (immediate) ---> SBFM, - a55 SWOG ASRV(page: 19/48) - latency: 1 - Inverse throughput: 2/1 = 2 - ExecutionUnit: SCALAR (ALU0, ALU1) - a55 SWOG SBFM (page: 21/48) - latency: 2 - Inverse throughput: 2/2 = 1 - ExecutionUnit: SCALAR (ALU0, ALU1) - a72 SWOG ASRV (page: 9/42) - latency: 1 - Inverse throughput: 2/2 = 1 - ExecutionUnit: INT (INT0, INT1) - a72 SWOG SBFM (page: 12/42) - latency: 1 - Inverse throughput: 2/2 = 1 - ExecutionUnit: INT (INT0, INT1) - This commit also refactor the existed asr_wform's latency, it should be 2 instead of 1.(reference from SBFM, since asr (immediate) is alias of SBFM) Signed-off-by: willieyz <willie.zhao@chelpis.com>
This commit adds support for the csel_xzr_ne instruction to the A55, A72 uArch model. This pattern is a variant of csel using the zero register xzr. This commit reuses the existing csel uArch model definition for the uArch model - a55 SWOG CSEL(page: 18/48) - latency: 1 - Inverse throughput: 2/2 = 1 - ExecutionUnit: SCALAR (ALU0, ALU1) - a72 SWOG CSEL(page: 8/42) - latency: 1 - Inverse throughput: 2/2 = 1 - ExecutionUnit: INT (INT0, INT1) Signed-off-by: willieyz <willie.zhao@chelpis.com>
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This commit adds support for the `cmp_xzr` instruction to the A55, A72 uArch model. This pattern is a variant of cmp using the zero register xzr. This commit reuses the existing cmp uArch model definition for the uArch model, and cmp (shift register) is alias of SUBS(according to page C6-1953 of Aarch64 Base Instruction Descriptions), so we reference the SUBS to model this instruction. - a55 SWOG SUBS(page: 18/48) - latency: 2 - Inverse throughput: 2/2 = 1 - ExecutionUnit: SCALAR (ALU0, ALU1) - a72 SWOG SUBS(page: 8/48) - latency: 2 - Inverse throughput: 1/1 = 1 - ExecutionUnit: MINT(M) Signed-off-by: willieyz <willie.zhao@chelpis.com>
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Hi @willieyz, Thanks for the changes! the PR says: I think the former should be correct and is also what the code reflects. Could you, for the sake of consistency, update the description if you agree with me on this one? Amin |
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Hello @dop-amin, Thank you very much for the review, I really appreciate it. Yes, I totally agree with you. The PR description is inconsistent and should align with the commit message. Willie |
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This PR add following instructions:
to support aarch64, and uArch model a55/a72.
asr(register) and asr(immediate)
According to A64 Base Instruction Descriptions, page C6-1820 and
page C6-1822, these two instructions are the aliases of:
asr (register) ---> ASRV,
asr (immediate) ---> SBFM,
a55 SWOG ASRV(page: 19/48)
a55 SWOG SBFM (page: 21/48)
a72 SWOG ASRV (page: 9/42)
a72 SWOG SBFM (page: 12/42)
csel_xzr_ne
This pattern is a variant of csel using the zero register xzr.
This commit reuses the existing csel uArch model definition for the
uArch model
a55 SWOG CSEL(page: 18/48)
a72 SWOG CSEL(page: 8/42)
cmp_xzr
This pattern is a variant of cmp using the zero register xzr.
This commit reuses the existing cmp uArch model definition for the
uArch model, and cmp is alias of SUBS, so we reference the SUBS to
model this instruction.
a55 SWOG SUBS(page: 18/48)
a72 SWOG SUBS(page: 8/48)