@@ -31,7 +31,7 @@ def test_sets(dev):
3131
3232 # --- MODE ---
3333 dev .set_mode ("continuous" )
34- r = dev .read_reg (LIS2MDL_CFG_REG_A )
34+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
3535 exp = 0b00
3636 print (
3737 "set_mode(continuous): MD=" ,
@@ -44,7 +44,7 @@ def test_sets(dev):
4444 ok &= _bits (r , 1 , 0 ) == exp
4545
4646 dev .set_mode ("single" )
47- r = dev .read_reg (LIS2MDL_CFG_REG_A )
47+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
4848 exp = 0b01
4949 print (
5050 "set_mode(single): MD=" ,
@@ -57,7 +57,7 @@ def test_sets(dev):
5757 ok &= _bits (r , 1 , 0 ) == exp
5858
5959 dev .set_mode ("idle" )
60- r = dev .read_reg (LIS2MDL_CFG_REG_A )
60+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
6161 exp = 0b11
6262 print (
6363 "set_mode(idle): MD=" ,
@@ -71,7 +71,7 @@ def test_sets(dev):
7171
7272 # --- ODR ---
7373 dev .set_odr (50 )
74- r = dev .read_reg (LIS2MDL_CFG_REG_A )
74+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
7575 exp = 0b10
7676 print (
7777 "set_odr(50): ODR=" ,
@@ -84,7 +84,7 @@ def test_sets(dev):
8484 ok &= _bits (r , 3 , 2 ) == exp
8585
8686 dev .set_odr (100 )
87- r = dev .read_reg (LIS2MDL_CFG_REG_A )
87+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
8888 exp = 0b11
8989 print (
9090 "set_odr(100): ODR=" ,
@@ -98,7 +98,7 @@ def test_sets(dev):
9898
9999 # --- Low power ---
100100 dev .set_low_power (True )
101- r = dev .read_reg (LIS2MDL_CFG_REG_A )
101+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
102102 print (
103103 "set_low_power(True): LP=" ,
104104 (r >> 4 ) & 1 ,
@@ -107,7 +107,7 @@ def test_sets(dev):
107107 )
108108 ok &= ((r >> 4 ) & 1 ) == 1
109109 dev .set_low_power (False )
110- r = dev .read_reg (LIS2MDL_CFG_REG_A )
110+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
111111 print (
112112 "set_low_power(False): LP=" ,
113113 (r >> 4 ) & 1 ,
@@ -118,7 +118,7 @@ def test_sets(dev):
118118
119119 # --- LPF ---
120120 dev .set_low_pass (True )
121- r = dev .read_reg (LIS2MDL_CFG_REG_B )
121+ r = dev ._read_reg (LIS2MDL_CFG_REG_B )
122122 print (
123123 "set_low_pass(True): LPF=" ,
124124 r & 1 ,
@@ -127,7 +127,7 @@ def test_sets(dev):
127127 )
128128 ok &= (r & 1 ) == 1
129129 dev .set_low_pass (False )
130- r = dev .read_reg (LIS2MDL_CFG_REG_B )
130+ r = dev ._read_reg (LIS2MDL_CFG_REG_B )
131131 print (
132132 "set_low_pass(False): LPF=" ,
133133 r & 1 ,
@@ -138,7 +138,7 @@ def test_sets(dev):
138138
139139 # --- Offset cancellation ---
140140 dev .set_offset_cancellation (True , oneshot = False )
141- r = dev .read_reg (LIS2MDL_CFG_REG_B )
141+ r = dev ._read_reg (LIS2MDL_CFG_REG_B )
142142 print (
143143 "set_offset_cancellation(True,False): OFF_CANC(bit1)=" ,
144144 (r >> 1 ) & 1 ,
@@ -150,7 +150,7 @@ def test_sets(dev):
150150 ok &= ((r >> 1 ) & 1 ) == 1 and ((r >> 4 ) & 1 ) == 0
151151
152152 dev .set_offset_cancellation (True , oneshot = True )
153- r = dev .read_reg (LIS2MDL_CFG_REG_B )
153+ r = dev ._read_reg (LIS2MDL_CFG_REG_B )
154154 print (
155155 "set_offset_cancellation(True,True): OFF_CANC(bit1)=" ,
156156 (r >> 1 ) & 1 ,
@@ -163,7 +163,7 @@ def test_sets(dev):
163163
164164 # --- BDU / Endianness / SPI4 ---
165165 dev .set_bdu (True )
166- r = dev .read_reg (LIS2MDL_CFG_REG_C )
166+ r = dev ._read_reg (LIS2MDL_CFG_REG_C )
167167 print (
168168 "set_bdu(True): BDU(bit4)=" ,
169169 (r >> 4 ) & 1 ,
@@ -173,7 +173,7 @@ def test_sets(dev):
173173 ok &= ((r >> 4 ) & 1 ) == 1
174174
175175 dev .set_endianness (True )
176- r = dev .read_reg (LIS2MDL_CFG_REG_C )
176+ r = dev ._read_reg (LIS2MDL_CFG_REG_C )
177177 print (
178178 "set_endianness(True): BLE(bit3)=" ,
179179 (r >> 3 ) & 1 ,
@@ -183,7 +183,7 @@ def test_sets(dev):
183183 ok &= ((r >> 3 ) & 1 ) == 1
184184
185185 dev .use_spi_4wire (True )
186- r = dev .read_reg (LIS2MDL_CFG_REG_C )
186+ r = dev ._read_reg (LIS2MDL_CFG_REG_C )
187187 print (
188188 "use_spi_4wire(True): 4WSPI(bit2)=" ,
189189 (r >> 2 ) & 1 ,
@@ -216,8 +216,8 @@ def test_sets(dev):
216216 # If you want to push the correction into the sensor:
217217 dev .set_hw_offsets (0 , 0 , 0 ) # e.g., reset to 0
218218 # You can read the registers to verify (optional)
219- oxL = dev .read_reg (LIS2MDL_OFFSET_X_REG_L )
220- oxH = dev .read_reg (LIS2MDL_OFFSET_X_REG_L + 1 )
219+ oxL = dev ._read_reg (LIS2MDL_OFFSET_X_REG_L )
220+ oxH = dev ._read_reg (LIS2MDL_OFFSET_X_REG_L + 1 )
221221 print (
222222 "set_hw_offsets(...): OFFSET_X* =" , (oxH << 8 ) | oxL , "expected written value"
223223 )
@@ -516,7 +516,7 @@ def test_power_modes(dev):
516516
517517 # Wake in continuous
518518 dev .power_on ("continuous" )
519- r = dev .read_reg (LIS2MDL_CFG_REG_A )
519+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
520520 md = _bits (r , 1 , 0 )
521521 print (
522522 "wake('continuous') => MD=" ,
@@ -528,7 +528,7 @@ def test_power_modes(dev):
528528
529529 # Wake in single
530530 dev .power_on ("single" )
531- r = dev .read_reg (LIS2MDL_CFG_REG_A )
531+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
532532 md = _bits (r , 1 , 0 )
533533 print (
534534 "wake('single') => MD=" ,
@@ -540,7 +540,7 @@ def test_power_modes(dev):
540540
541541 # Power down
542542 dev .power_off ()
543- r = dev .read_reg (LIS2MDL_CFG_REG_A )
543+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
544544 md = _bits (r , 1 , 0 )
545545 print (
546546 "power_off() => MD=" ,
@@ -559,7 +559,7 @@ def test_power_modes(dev):
559559
560560 # Back to continuous
561561 dev .power_on ("continuous" )
562- r = dev .read_reg (LIS2MDL_CFG_REG_A )
562+ r = dev ._read_reg (LIS2MDL_CFG_REG_A )
563563 md = _bits (r , 1 , 0 )
564564 print (
565565 "wake('continuous') => MD=" ,
@@ -582,9 +582,9 @@ def test_soft_reset(dev):
582582 dev .set_low_pass (True ) # CFG_B bit0 = 1
583583 dev .set_bdu (True ) # CFG_C bit4 = 1
584584
585- ra_before = dev .read_reg (LIS2MDL_CFG_REG_A )
586- rb_before = dev .read_reg (LIS2MDL_CFG_REG_B )
587- rc_before = dev .read_reg (LIS2MDL_CFG_REG_C )
585+ ra_before = dev ._read_reg (LIS2MDL_CFG_REG_A )
586+ rb_before = dev ._read_reg (LIS2MDL_CFG_REG_B )
587+ rc_before = dev ._read_reg (LIS2MDL_CFG_REG_C )
588588 print (
589589 f"Before reset: CFG_A=0x{ ra_before :02X} CFG_B=0x{ rb_before :02X} CFG_C=0x{ rc_before :02X} "
590590 )
@@ -593,9 +593,9 @@ def test_soft_reset(dev):
593593 dev .soft_reset (wait_ms = 15 )
594594
595595 # Read after reset
596- ra = dev .read_reg (LIS2MDL_CFG_REG_A )
597- rb = dev .read_reg (LIS2MDL_CFG_REG_B )
598- rc = dev .read_reg (LIS2MDL_CFG_REG_C )
596+ ra = dev ._read_reg (LIS2MDL_CFG_REG_A )
597+ rb = dev ._read_reg (LIS2MDL_CFG_REG_B )
598+ rc = dev ._read_reg (LIS2MDL_CFG_REG_C )
599599 print (f"After reset: CFG_A=0x{ ra :02X} CFG_B=0x{ rb :02X} CFG_C=0x{ rc :02X} " )
600600
601601 # Realistic expectations (typical default values):
@@ -635,12 +635,12 @@ def test_reboot(dev):
635635
636636 # Put into a known state
637637 dev .set_odr (20 ) # ODR=01
638- ra_before = dev .read_reg (LIS2MDL_CFG_REG_A )
638+ ra_before = dev ._read_reg (LIS2MDL_CFG_REG_A )
639639 print (f"Before reboot: CFG_A=0x{ ra_before :02X} " )
640640
641641 # Reboot
642642 dev .reboot (wait_ms = 15 )
643- ra = dev .read_reg (LIS2MDL_CFG_REG_A )
643+ ra = dev ._read_reg (LIS2MDL_CFG_REG_A )
644644 print (f"After reboot: CFG_A=0x{ ra :02X} " )
645645
646646 # The REBOOT bit (bit6) must have cleared back to 0
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