tests: Add board qualification tests for user pins (edge connector).

[nedseb]

Description

Add board qualification tests for the user-accessible pins on the STeaMi edge connector and crocodile clip pads. These tests verify electrical continuity and GPIO/ADC functionality of each pin.

Components

Analog pins (GPIO + ADC)

Pin	Signal	STM32WB55 Pin	Connectors
P0	ANALOG02_EDGE	PC4	Edge, Croc
P1	ANALOG04_EDGE	PA5	Edge, Croc
P2	ANALOG06_EDGE	PC5	Edge, Croc
P3	ANALOG01_EDGE	PA2	Edge
P4	ANALOG03_EDGE	PA4	Edge
P10	ANALOG05_EDGE	PA6	Edge

Digital GPIO pins

Pin	Signal	STM32WB55 Pin
P5	GPIO1_EDGE (A button)	PA7
P6	GPIO2_EDGE	PC3
P7	GPIO3_EDGE (PWM)	PA9
P8	GPIO4_EDGE	PA15
P9	GPIO5_EDGE	PC2
P11	GPIO6_EDGE (B button)	PA8
P12	GPIO7_EDGE	PC6
P16	GPIO8_EDGE	PE4

I2C external

Pin	Signal	STM32WB55 Pin
P19	I2C3_SCL_EDGE	PC0
P20	I2C3_SDA_EDGE	PC1

SPI external

Pin	Signal	STM32WB55 Pin
P13	SPI2_SCK_EDGE	PB13
P14	SPI2_MISO_EDGE	PB14
P15	SPI2_MOSI_EDGE	PB15

I/O Expander crocodile pads

Pin	Signal	Expander Pin
P24	GPIO3	GP2
P25	GPIO4	GP3
P28	GPIO1	GP0
P29	GPIO2	GP1

Test approach

These tests require a physical test bench (jig) that connects each pin to a verification circuit (loopback, pull-up/pull-down, or ADC measurement). The exact test methodology will be refined during test bench design.

Basic tests per pin:

• Digital GPIO: configure as output, set high, reconfigure as input, verify read-back
• Analog: read ADC value, verify within expected range
• I2C/SPI: verify bus communication with external test device on jig

Scenario: tests/scenarios/board_pins.yaml

The scenario will be fully detailed once the test bench hardware is designed.

Depends on

• tests: Extend test framework for driverless board qualification scenarios. #83 (framework extension for `type: board` scenarios)
• Test bench hardware design (TBD)