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jameswalmsleyjameswalmsley
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implement stm32h5 series, erase, read and write
1 parent 8c34a4e commit 1899194

23 files changed

Lines changed: 1563 additions & 158 deletions

‎config/chips/H5xx.chip‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,13 @@
33
dev_type STM32H5xx
44
ref_manual_id 0481
55
chip_id 0x484 // STM32_CHIPID_H5xx
6-
flash_type L5_U5_H5
6+
flash_type H5
77
flash_size_reg 0x08fff80c
88
flash_pagesize 0x2000 // 8 KB
99
sram_size 0xa0000 // 640 KB
1010
bootrom_base 0x0bf80000
1111
bootrom_size 0x8000 // 32 KB
1212
option_base 0x0
1313
option_size 0x0
14+
target_ap 1
1415
flags dualbank

‎config/chips/L5x2xx.chip‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
dev_type STM32L5x2xx
44
ref_manual_id 0438
55
chip_id 0x472 // STM32_CHIPID_L5x2xx
6-
flash_type L5_U5_H5
6+
flash_type L5_U5
77
flash_size_reg 0x0bfa05e0
88
flash_pagesize 0x1000 // 4 KB
99
sram_size 0x40000 // 256 KB

‎config/chips/U535_U545.chip‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
dev_type STM32U535_U545
44
ref_manual_id 0456
55
chip_id 0x455 // STM32_CHIPID_U535_545
6-
flash_type L5_U5_H5
6+
flash_type L5_U5
77
flash_size_reg 0x0bfa07a0
88
flash_pagesize 0x2000 // 8 KB
99
sram_size 0x44800 // 274 KB

‎config/chips/U575_U585.chip‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
dev_type STM32U575_U585
44
ref_manual_id 0456
55
chip_id 0x482 // STM32_CHIPID_U575_U585
6-
flash_type L5_U5_H5
6+
flash_type L5_U5
77
flash_size_reg 0x0bfa07a0
88
flash_pagesize 0x2000 // 8 KB
99
sram_size 0xc4800 // 786 KB

‎config/chips/U59x_U5Ax.chip‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
dev_type STM32U59x_U5Ax
44
ref_manual_id 0456
55
chip_id 0x481 // STM32_CHIPID_U59x_5Ax
6-
flash_type L5_U5_H5
6+
flash_type L5_U5
77
flash_size_reg 0x0bfa07a0
88
flash_pagesize 0x2000 // 8 KB
99
sram_size 0x274800 // 2514 KB

‎config/chips/U5Fx_U5Gx.chip‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
dev_type STM32U5Fx_U5Gx
44
ref_manual_id 0456
55
chip_id 0x476 // STM32_CHIPID_U5Fx5_5Gx
6-
flash_type L5_U5_H5
6+
flash_type L5_U5
77
flash_size_reg 0x0bfa07a0
88
flash_pagesize 0x2000 // 8 KB
99
sram_size 0x2f4800 // 3026 KB

‎flashloaders/Makefile‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,9 @@ XXDFLAGS = -i -c 4
1111

1212
CFLAGS_ARMV6_M = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib
1313
CFLAGS_ARMV7_M = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib
14+
CFLAGS_ARMV8_M = -mcpu=Cortex-M33 -Tlinker.ld -ffreestanding -nostdlib
1415

15-
all: stm32vl.h stm32f0.h stm32wb0.h stm32lx.h stm32f4.h stm32f4lv.h stm32l4.h stm32f7.h stm32f7lv.h
16+
all: stm32vl.h stm32f0.h stm32wb0.h stm32lx.h stm32f4.h stm32f4lv.h stm32l4.h stm32f7.h stm32f7lv.h stm32h5.h
1617

1718

1819
%.h: %.bin
@@ -43,5 +44,8 @@ stm32lx.o: stm32lx.s
4344
%.o: %.s
4445
$(CC) $< $(CFLAGS_ARMV7_M) -o $@
4546

47+
stm32h5.o: stm32h5.s
48+
$(CC) stm32h5.s $(CFLAGS_ARMV8_M) -o stm32h5.o
49+
4650
clean:
4751
rm -f *.h

‎flashloaders/cleanroom.md‎

Lines changed: 29 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -122,4 +122,32 @@ Copy one word each time. No wait for write.
122122

123123
Copy one double word each time (More than one register is allowed).
124124

125-
How to wait for the write process: read a half word from `FLASH_BSY`, loop until the busy bit is reset.
125+
How to wait for the write process: read a half word from `FLASH_BSY`, loop until the busy bit is reset.
126+
127+
## stm32h5.s
128+
129+
Bank 1 registers:
130+
131+
`FLASH_NSSR`: 0x40022020
132+
133+
`FLASH_NSCR`: 0x40022028
134+
135+
`FLASH_NSCCR`: 0x40022030
136+
137+
Bank 2 registers:
138+
139+
`FLASH_NSSR`: 0x50022020
140+
141+
`FLASH_NSCR`: 0x50022028
142+
143+
`FLASH_NSCCR`: 0x50022030
144+
145+
**Special Requirements**:
146+
147+
Copy one quadword each time (16 bytes, four 32-bit words).
148+
149+
Use `r3` to select the bank-specific flash register block. Clear sticky status
150+
once before starting, wait for `BSY`, `WBNE`, and `DBNE` to clear, then keep
151+
`PG` set for the whole chunk. The loader should accept an exact byte count and
152+
pad the last quadword with `0xFF` locally. Clear `PG` and the sticky status
153+
bits once on exit.

‎flashloaders/stm32h5.h‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
unsigned char stm32h5_bin[] = {
2+
0x00, 0x2b, 0x06, 0xd0,
3+
0xdf, 0xf8, 0xb8, 0xc0,
4+
0xdf, 0xf8, 0xb8, 0xb0,
5+
0xdf, 0xf8, 0xb8, 0xa0,
6+
0x05, 0xe0, 0xdf, 0xf8,
7+
0xa0, 0xc0, 0xdf, 0xf8,
8+
0xa0, 0xb0, 0xdf, 0xf8,
9+
0xa0, 0xa0, 0xef, 0xf3,
10+
0x10, 0x83, 0x72, 0xb6,
11+
0x84, 0xb0, 0xdf, 0xf8,
12+
0xa4, 0x90, 0xdf, 0xf8,
13+
0xa4, 0x80, 0xca, 0xf8,
14+
0x00, 0x90, 0xdc, 0xf8,
15+
0x00, 0x40, 0x14, 0xf0,
16+
0x0b, 0x0f, 0xfa, 0xd1,
17+
0xdb, 0xf8, 0x00, 0x40,
18+
0x44, 0xf0, 0x02, 0x04,
19+
0xcb, 0xf8, 0x00, 0x40,
20+
0x00, 0x2a, 0x26, 0xdd,
21+
0x10, 0x2a, 0x01, 0xd3,
22+
0xf0, 0xc8, 0x11, 0xe0,
23+
0x6f, 0xf0, 0x00, 0x04,
24+
0x00, 0x94, 0x01, 0x94,
25+
0x02, 0x94, 0x03, 0x94,
26+
0x6d, 0x46, 0x16, 0x46,
27+
0x00, 0x2e, 0x05, 0xd0,
28+
0x10, 0xf8, 0x01, 0x4b,
29+
0x05, 0xf8, 0x01, 0x4b,
30+
0x01, 0x3e, 0xf7, 0xe7,
31+
0x9d, 0xe8, 0xf0, 0x00,
32+
0xf0, 0xc1, 0xbf, 0xf3,
33+
0x4f, 0x8f, 0xdc, 0xf8,
34+
0x00, 0x40, 0x14, 0xf0,
35+
0x0b, 0x0f, 0xfa, 0xd1,
36+
0x14, 0xea, 0x08, 0x0f,
37+
0x05, 0xd1, 0x10, 0x2a,
38+
0x01, 0xd3, 0x10, 0x3a,
39+
0xd8, 0xe7, 0x00, 0x22,
40+
0xd6, 0xe7, 0x20, 0x46,
41+
0xdb, 0xf8, 0x00, 0x40,
42+
0x24, 0xf0, 0x02, 0x04,
43+
0xcb, 0xf8, 0x00, 0x40,
44+
0xca, 0xf8, 0x00, 0x90,
45+
0x04, 0xb0, 0x83, 0xf3,
46+
0x10, 0x88, 0x00, 0xbe,
47+
0x20, 0x20, 0x02, 0x40,
48+
0x28, 0x20, 0x02, 0x40,
49+
0x30, 0x20, 0x02, 0x40,
50+
0x20, 0x20, 0x02, 0x50,
51+
0x28, 0x20, 0x02, 0x50,
52+
0x30, 0x20, 0x02, 0x50,
53+
0x00, 0x00, 0x9f, 0x00,
54+
0x00, 0x00, 0x9e, 0x00
55+
};
56+
unsigned int stm32h5_bin_len = 212;

‎flashloaders/stm32h5.s‎

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,133 @@
1+
.syntax unified
2+
.text
3+
4+
/*
5+
* Arguments:
6+
* r0 - source SRAM ptr
7+
* r1 - target flash ptr
8+
* r2 - exact count of bytes to program
9+
* r3 - flash bank selector (0 = bank 1, 1 = bank 2)
10+
*
11+
* Return:
12+
* r0 - last observed NSSR value
13+
* r2 - remaining bytes (0 on success)
14+
*/
15+
16+
.global copy
17+
copy:
18+
cmp r3, #0
19+
beq bank1
20+
21+
bank2:
22+
ldr r12, flash_bank2_nssr
23+
ldr r11, flash_bank2_nscr
24+
ldr r10, flash_bank2_nsccr
25+
b prepare
26+
27+
bank1:
28+
ldr r12, flash_bank1_nssr
29+
ldr r11, flash_bank1_nscr
30+
ldr r10, flash_bank1_nsccr
31+
32+
prepare:
33+
mrs r3, primask
34+
cpsid i
35+
sub sp, sp, #16
36+
ldr r9, flash_clear_mask
37+
ldr r8, flash_error_mask
38+
str r9, [r10]
39+
40+
wait_ready:
41+
ldr r4, [r12]
42+
43+
# wait until BSY, WBNE and DBNE are all clear
44+
tst r4, #0xb
45+
bne wait_ready
46+
47+
# keep PG set for the full chunk write
48+
ldr r4, [r11]
49+
orr r4, r4, #0x2
50+
str r4, [r11]
51+
52+
loop:
53+
cmp r2, #0
54+
ble exit
55+
56+
cmp r2, #16
57+
blo tail
58+
59+
# copy one quadword as four consecutive 32-bit writes
60+
ldmia r0!, {r4-r7}
61+
b program_quad
62+
63+
tail:
64+
mvn r4, #0
65+
str r4, [sp, #0]
66+
str r4, [sp, #4]
67+
str r4, [sp, #8]
68+
str r4, [sp, #12]
69+
mov r5, sp
70+
mov r6, r2
71+
72+
tail_copy:
73+
cmp r6, #0
74+
beq tail_load
75+
ldrb r4, [r0], #1
76+
strb r4, [r5], #1
77+
subs r6, r6, #1
78+
b tail_copy
79+
80+
tail_load:
81+
ldmia sp, {r4-r7}
82+
83+
program_quad:
84+
stmia r1!, {r4-r7}
85+
dsb sy
86+
87+
wait:
88+
ldr r4, [r12]
89+
90+
# wait until BSY, WBNE and DBNE are all clear
91+
tst r4, #0xb
92+
bne wait
93+
94+
# stop early and leave r2 pointing at the first unwritten quadword
95+
tst r4, r8
96+
bne exit
97+
98+
cmp r2, #16
99+
blo tail_done
100+
subs r2, r2, #16
101+
b loop
102+
103+
tail_done:
104+
movs r2, #0
105+
b loop
106+
107+
exit:
108+
mov r0, r4
109+
ldr r4, [r11]
110+
bic r4, r4, #0x2
111+
str r4, [r11]
112+
str r9, [r10]
113+
add sp, sp, #16
114+
msr primask, r3
115+
bkpt
116+
117+
.align 2
118+
flash_bank1_nssr:
119+
.word 0x40022020
120+
flash_bank1_nscr:
121+
.word 0x40022028
122+
flash_bank1_nsccr:
123+
.word 0x40022030
124+
flash_bank2_nssr:
125+
.word 0x50022020
126+
flash_bank2_nscr:
127+
.word 0x50022028
128+
flash_bank2_nsccr:
129+
.word 0x50022030
130+
flash_clear_mask:
131+
.word 0x009f0000
132+
flash_error_mask:
133+
.word 0x009e0000

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