fix: Cygnet initialization

Fixes clock initialization clash by mirroring Nucleo L432KC init.

Reported to Blues here: https://discuss.blues.com/t/wire-begin-causes-mcu-reset-hang-on-cygnet/3486

    Identifies odd dependency between Wire and USB.

stm32duino issue: #2930

    Identifies clock config as possible root cause.

Author: zfields

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.cpp

@@ -75,19 +75,49 @@ WEAK void initVariant(void)
 {
   /* All pins set to high-Z (floating) initially */
   /* DS11449 Rev 8, Section 3.9.5 - Reset Mode: */
-  /* In order to improve the consumption under reset, the I/Os state under and after reset is
-   * “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
-   * deactivated when the reset source is internal.
+  /* In order to improve the consumption under reset, the I/Os state under
+   * and after reset is “analog state” (the I/O schmitt trigger is disable).
+   * In addition, the internal reset pull-up is deactivated when the reset
+   * source is internal.
    */
 
-  /* Turn on the 3V3 regulator */
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  GPIO_InitTypeDef  GPIO_InitStruct;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
-  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); /* PH0 is ENABLE_3V3, PH1 is DISCHARGE_3V3 */
-  HAL_GPIO_WritePin(GPIOH, GPIO_InitStruct.Pin, GPIO_PIN_SET); /* Enable 3V3 regulator and disable discharging */
+  /* Configure the USB charge detection; leaks ~80uA if not configured. */
+  {
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    GPIO_InitTypeDef  GPIO_InitStruct = {};
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+    /* PA15 is CHARGE_DETECT */
+    GPIO_InitStruct.Pin = GPIO_PIN_15;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  }
+
+  /* Configure D13 manually, to avoid stray current on D13 */
+  {
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef  GPIO_InitStruct = {};
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+    /* PB4 is D13 */
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+  }
+
+  /* Configure the 3V3 regulator */
+  {
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+    GPIO_InitTypeDef  GPIO_InitStruct = {};
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+    /* PH0 is ENABLE_3V3, PH1 is DISCHARGE_3V3 */
+    GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
+    HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+    /* Enable 3V3 regulator and disable discharging */
+    HAL_GPIO_WritePin(GPIOH, GPIO_InitStruct.Pin, GPIO_PIN_SET);
+  }
 }
 
 /**
@@ -101,66 +131,154 @@ WEAK void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
 
+  /** Enable PWR peripheral clock
+  *
+  * RM0394 §5.1.2: PWR registers are on APB1. PWREN (RCC_APB1ENR1 bit 28)
+  * resets to 1, so this is defensive rather than strictly necessary, but
+  * required for correctness if PWREN has been cleared by prior code.
+  * CubeMX generates this unconditionally for all STM32L4 projects.
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
   /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
     Error_Handler();
   }
 
   /** Configure LSE Drive Capability
+  *
+  * Use MEDIUMLOW (not LOW): RCC_LSEDRIVE_LOW risks marginal LSE startup
+  * on units near the crystal ESR tolerance limit and degrades MSI PLL mode
+  * (MSIPLLEN) lock quality. ST recommends MEDIUMLOW as the minimum when
+  * MSIPLLEN is in use.
+  *
+  * Backup domain access must be enabled before configuring LSE or selecting
+  * the RTC clock source, as those registers (RCC->BDCR) are write-protected
+  * after reset and silently ignore writes until the lock is cleared.
   */
   HAL_PWR_EnableBkUpAccess();
-  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);
 
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
+  *
+  * Cygnet config:
+  *   - MSI: MSIRANGE_6 (4 MHz) — used as PLL input
+  *   - HSI: OFF — nothing in this config uses it
+  *   - PLL: NONE → ON  (MSI 4 MHz × PLLN=40 / PLLR=2 → SYSCLK = 80 MHz)
+  *   - SYSCLK: MSI (48 MHz) → PLLCLK (80 MHz)
+  *   - USB clock: removed from PeriphCLKConfig (MSI) → PLLSAI1 (48 MHz)
+  *   - MSIRDY transient can not stall SysTick because SYSCLK = PLL, not MSI.
+  *   - FLASH_LATENCY: 2 → 4  (required for 80 MHz / VOS1 per RM0394 §3.3)
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE
-                                     | RCC_OSCILLATORTYPE_MSI
-                                     | RCC_OSCILLATORTYPE_HSI;
+                                      | RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  /* HSI is not used as SYSCLK source, PLL/PLLSAI1 input, or any peripheral
+   * clock reference. Disabling it saves ~200-300 µA. */
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
   RCC_OscInitStruct.MSIState = RCC_MSI_ON;
   RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  /* MSIRANGE_6 = 4 MHz — same as Nucleo. Low-frequency reference fed into
+   * the main PLL (×40/÷2 = 80 MHz) and PLLSAI1 (×24/÷2 = 48 MHz). */
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 40;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;  /* 4 × 40 / 2 = 80 MHz */
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
     Error_Handler();
   }
 
   /** Initializes the CPU, AHB and APB buses clocks
+  *
+  * SYSCLK = PLLCLK (80 MHz). SysTick and HAL_GetTick() are now driven by
+  * the PLL output, completely decoupled from MSI. Any subsequent MSIRDY
+  * transient (from HAL_RCCEx_EnableMSIPLLMode below) cannot stall SysTick.
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
                                 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-  // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+  /* FLASH_LATENCY_4: required for HCLK > 64 MHz at VOS1 (RM0394 §3.3.3) */
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
     Error_Handler();
   }
 
   /** Initializes the Peripheral clocks
+  *
+  * USB clock: PLLSAI1 (MSI 4 MHz × PLLSAI1N=24 / PLLSAI1Q=2 = 48 MHz).
+  * This mirrors the Nucleo L432KC exactly. RCCEx_PLLSAI1_Config() waits
+  * for PLLSAI1RDY using HAL_GetTick(). Because SYSCLK is now PLL-based,
+  * HAL_GetTick() is immune to MSI transients — the wait is reliable.
+  * PLLSAI1 and the main PLL share the same source (MSI) and M divider (1),
+  * which the HAL enforces; both are configured consistently here.
+  *
+  * HAL_RCCEx_PeriphCLKConfig writes CLK48SEL first (pointing at PLLSAI1
+  * before it is running), then enables PLLSAI1 and waits for its RDY flag.
+  * During that brief window the USB peripheral has no 48 MHz clock and
+  * stays quiescent — avoiding the race where a live MSI clock is handed
+  * to USB before the peripheral is ready to handle the absence of VBUS.
   */
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SDMMC1
-                                       | RCC_PERIPHCLK_ADC /* | RCC_PERIPHCLK_OSPI */;
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
   PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
-  // PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK;
-  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
-  PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_MSI;
+  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+  PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
+  PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+  PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
+  PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;  /* 4 × 24 / 2 = 48 MHz */
+  PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+  PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
     Error_Handler();
   }
 
-  /** Enable MSI Auto calibration
-  */
-  HAL_RCCEx_EnableMSIPLLMode();
+/** Enable MSI Auto calibration (MSIPLLEN, RCC_CR[2])
+ *
+ * RM0394 §6.2 (MSI clock): setting MSIPLLEN causes the MSI hardware
+ * to automatically trim itself against LSE as a phase reference,
+ * reducing MSI frequency error to < ±0.25%. LSE must already be
+ * stable (LSERDY=1) before the bit is set — guaranteed here because
+ * HAL_RCC_OscConfig() waited for LSERDY before returning.
+ *
+ * Setting MSIPLLEN causes MSIRDY to deassert transiently while MSI
+ * re-synchronises to LSE. HAL_RCCEx_EnableMSIPLLMode() returns
+ * immediately (it is a single SET_BIT); no MSIRDY wait is performed
+ * inside it. Two conclusions follow:
+ *
+ *   (1) This call must come AFTER any HAL routine that polls MSIRDY
+ *       under a HAL_GetTick() timeout — if MSIRDY drops inside such
+ *       a routine, the routine returns HAL_TIMEOUT and leaves the
+ *       clock tree in an undefined state.
+ *
+ *   (2) If SYSCLK were MSI, a deadlock would be possible: MSIRDY
+ *       drops → SysTick stalls → HAL_GetTick() freezes → any
+ *       subsequent timeout loop never exits. RM0394 §6.2.9 confirms
+ *       SysTick is driven by HCLK (= SYSCLK / AHBdiv). Because
+ *       SYSCLK is now PLLCLK (80 MHz), SysTick is completely
+ *       decoupled from MSI and the transient is harmless.
+ *
+ * Placement here — after PeriphCLKConfig — satisfies both constraints
+ * and mirrors the ordering generated by CubeMX for the Nucleo L432KC.
+ */
+HAL_RCCEx_EnableMSIPLLMode();
 
   /** Ensure that MSI is wake-up system clock
+  *
+  * After STOP mode, the PLL is not automatically re-enabled. MSI is used
+  * as the initial wake-up clock; firmware must re-lock the PLL manually
+  * if 80 MHz is required after wake. This is the same behaviour as any
+  * PLL-based design on STM32L4.
   */
-  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
+  HAL_RCCEx_WakeUpStopCLKConfig(RCC_STOP_WAKEUPCLOCK_MSI);
+#pragma message("Compiled using local Arduino_Core_STM32: 2.13.0-dev.")
 }
 
 #ifdef __cplusplus