Skip to content

Commit 1b50ae1

Browse files
fpistmfpistm
committed
system(u3) update STM32U3xx HAL Drivers to v1.2.0
Included in STM32CubeU3 FW v1.3.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 1b98ba7 commit 1b50ae1

File tree

94 files changed

+13834
-1971
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

94 files changed

+13834
-1971
lines changed

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 18 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,9 @@ extern "C" {
361361
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
362362
defined(STM32L4S7xx) || defined(STM32L4S9xx)
363363
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
364-
#endif
364+
#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
365+
#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI
366+
#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
365367

366368
#endif /* STM32L4 */
367369

@@ -564,6 +566,9 @@ extern "C" {
564566
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
565567
#define OB_nBOOT0_SET OB_NBOOT0_SET
566568
#endif /* STM32U0 */
569+
#if defined(STM32H5)
570+
#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1
571+
#endif /* STM32H5 */
567572

568573
/**
569574
* @}
@@ -2025,6 +2030,9 @@ extern "C" {
20252030

20262031
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
20272032
#endif
2033+
#if defined (STM32H7RS)
2034+
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO
2035+
#endif
20282036

20292037
/**
20302038
* @}
@@ -2146,6 +2154,13 @@ extern "C" {
21462154
#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
21472155
#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
21482156

2157+
#if defined(STM32H7RS) || defined(STM32N6)
2158+
#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0
2159+
#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1
2160+
#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig
2161+
#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig
2162+
#endif /* STM32H7RS || STM32N6 */
2163+
21492164
/**
21502165
* @}
21512166
*/
@@ -3698,10 +3713,8 @@ extern "C" {
36983713
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
36993714
#endif
37003715

3701-
37023716
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3703-
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3704-
defined(STM32U0)
3717+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
37053718
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
37063719
#else
37073720
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3952,7 +3965,7 @@ extern "C" {
39523965
*/
39533966
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39543967
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3955-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
3968+
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
39563969
defined (STM32U0) || defined (STM32U3)
39573970
#else
39583971
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h‎

Lines changed: 102 additions & 84 deletions
Large diffs are not rendered by default.

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_comp.h‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -289,6 +289,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
289289
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKSEL_1) /*!< TIM2 OC3 selected as blanking source for COMP1 */
290290
#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKSEL_2) /*!< TIM3 OC3 selected as blanking source for COMP1 */
291291
#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CSR_BLANKSEL_0) /*!< TIM3 OC4 selected as blanking source for COMP2 */
292+
#define COMP_BLANKINGSRC_TIM15_OC1 (COMP2_CSR_BLANKSEL_2) /*!< TIM15 OC1 selected as blanking source for COMP2 (xx1xx) */
293+
#if defined(COMP2_CSR_BLANKSEL_1)
294+
#define COMP_BLANKINGSRC_TIM8_OC5 (COMP2_CSR_BLANKSEL_1) /*!< TIM8 OC5 selected as blanking source for COMP2 (xxx1x) */
295+
#endif /* COMP_CSR_BLANKSEL_1 */
292296
/**
293297
* @}
294298
*/
@@ -702,6 +706,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
702706
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
703707
((__POL__) == COMP_OUTPUTPOL_INVERTED))
704708

709+
#if defined(COMP2_CSR_BLANKSEL_1) && (COMP2_CSR_BLANKSEL_2)
705710
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
706711
(((__INSTANCE__) == COMP1) \
707712
? (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
@@ -710,8 +715,34 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
710715
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) ) \
711716
: \
712717
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
718+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) || \
719+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5) || \
713720
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) ) \
714721
)
722+
#elif defined(COMP2_CSR_BLANKSEL_2)
723+
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
724+
(((__INSTANCE__) == COMP1) \
725+
? (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
726+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
727+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
728+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) ) \
729+
: \
730+
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
731+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) || \
732+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) ) \
733+
)
734+
#else
735+
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
736+
(((__INSTANCE__) == COMP1) \
737+
? (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
738+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
739+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
740+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) ) \
741+
: \
742+
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
743+
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) ) \
744+
)
745+
#endif /* COMP2_CSR_BLANKSEL_2 */
715746

716747
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
717748
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_conf_template.h‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ extern "C" {
5252
#define HAL_GTZC_MODULE_ENABLED
5353
#define HAL_HASH_MODULE_ENABLED
5454
#define HAL_HCD_MODULE_ENABLED
55+
#define HAL_HSP_MODULE_ENABLED
5556
#define HAL_I2C_MODULE_ENABLED
5657
#define HAL_I3C_MODULE_ENABLED
5758
#define HAL_ICACHE_MODULE_ENABLED
@@ -124,7 +125,7 @@ extern "C" {
124125
#if !defined (LSI_VALUE)
125126
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
126127
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may
127-
vary depending on the variations in voltage and temperature.*/
128+
vary depending on the variations in voltage and temperature.*/
128129

129130
#if !defined (LSI_STARTUP_TIMEOUT)
130131
#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in ms */
@@ -142,7 +143,7 @@ extern "C" {
142143
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
143144
#endif /* LSE_STARTUP_TIMEOUT */
144145

145-
/**
146+
/**
146147
* @brief Internal Multiple Speed oscillator (MSI) default value.
147148
* These values are the default maximum frequencies of each MSI RC.
148149
* These values are used by the RCC HAL module to compute the system frequency
@@ -217,6 +218,7 @@ extern "C" {
217218
#define USE_HAL_GTZC_REGISTER_CALLBACKS 1U
218219
#define USE_HAL_HASH_REGISTER_CALLBACKS 1U
219220
#define USE_HAL_HCD_REGISTER_CALLBACKS 1U
221+
#define USE_HAL_HSP_REGISTER_CALLBACKS 1U
220222
#define USE_HAL_I2C_REGISTER_CALLBACKS 1U
221223
#define USE_HAL_I3C_REGISTER_CALLBACKS 1U
222224
#define USE_HAL_ICACHE_REGISTER_CALLBACKS 1U
@@ -262,6 +264,7 @@ extern "C" {
262264
#define USE_HAL_GTZC_REGISTER_CALLBACKS 0U
263265
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U
264266
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U
267+
#define USE_HAL_HSP_REGISTER_CALLBACKS 0U
265268
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
266269
#define USE_HAL_I3C_REGISTER_CALLBACKS 0U
267270
#define USE_HAL_ICACHE_REGISTER_CALLBACKS 0U

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_cryp.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -502,7 +502,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
502502
& (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \
503503
((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \
504504
& (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \
505-
((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET)
505+
((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == \
506+
(CRYP_FLAG_CCF)))?SET:RESET)
506507

507508
/** @brief Clear the CRYP pending status flag.
508509
* @param __HANDLE__ specifies the CRYP handle.

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_dma_ex.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -560,15 +560,15 @@ typedef struct
560560
#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
561561
#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
562562

563-
#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
564-
#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
565-
#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
566-
#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
567-
#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
568-
#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
569-
#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
570-
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
571-
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
563+
#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */
564+
#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */
565+
#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */
566+
#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */
567+
#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */
568+
#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */
569+
#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */
570+
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */
571+
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */
572572

573573
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
574574
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_exti.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -177,19 +177,19 @@ typedef struct
177177
* @brief EXTI Line property definition
178178
*/
179179
#define EXTI_PROPERTY_SHIFT 24U
180-
#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT)
181-
#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT)
182-
#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
183-
#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT)
180+
#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT)
181+
#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT)
182+
#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
183+
#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT)
184184
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
185185

186186
/**
187187
* @brief EXTI Register and bit usage
188188
*/
189189
#define EXTI_REG_SHIFT 16U
190-
#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT)
190+
#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT)
191191
#define EXTI_REG_MASK EXTI_REG1
192-
#define EXTI_PIN_MASK 0x0000001FU
192+
#define EXTI_PIN_MASK 0x0000001FUL
193193

194194
/**
195195
* @brief EXTI Mask for interrupt & event mode
@@ -277,7 +277,7 @@ typedef struct
277277
* @{
278278
*/
279279
/* Configuration functions ****************************************************/
280-
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
280+
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig);
281281
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
282282
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
283283
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_flash.h‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,8 @@ typedef struct
8686
@ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_SRAM2_PE,
8787
@ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_NSWBOOT0,
8888
@ref FLASH_OB_USER_NBOOT0, @ref FLASH_OB_USER_IO_VDD_HSLV,
89-
@ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */
89+
@ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN
90+
@ref FLASH_OB_USER_SRAM3_PE */
9091
#if defined (CPU_IN_SECURE_STATE)
9192
uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for @ref OPTIONBYTE_WMSEC).
9293
This parameter must be a value of @ref FLASH_OB_WMSEC */
@@ -338,20 +339,33 @@ typedef struct
338339
#define OB_USER_SWAP_BANK FLASH_OPTR_SWAP_BANK /*!< Swap banks */
339340
#define OB_USER_DUALBANK FLASH_OPTR_DUALBANK /*!< Dual-Bank on 1MB/512kB Flash memory devices */
340341
#define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check enable */
342+
#if defined(FLASH_OPTR_SRAM3_PE)
343+
#define OB_USER_SRAM3_PE FLASH_OPTR_SRAM3_PE /*!< SRAM3 parity check enable */
344+
#endif /* FLASH_OPTR_SRAM3_PE */
341345
#define OB_USER_SRAM2_RST FLASH_OPTR_SRAM2_RST /*!< SRAM2 erase when system reset */
342346
#define OB_USER_NSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */
343347
#define OB_USER_NBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */
344348
#define OB_USER_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV /*!< High speed IO at low VDD voltage configuration bit */
345349
#define OB_USER_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV /*!< High speed IO at low VDDIO2 voltage configuration bit */
346350
#define OB_USER_TZEN FLASH_OPTR_TZEN /*!< Global TrustZone security enable */
347351

352+
#if defined(FLASH_OPTR_SRAM3_PE)
353+
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BDRST_POR | OB_USER_NRST_STOP | \
354+
OB_USER_NRST_STDBY | OB_USER_NRST_SHDW | OB_USER_SRAM1_RST | \
355+
OB_USER_IWDG_SW | OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | \
356+
OB_USER_WWDG_SW | OB_USER_SWAP_BANK | OB_USER_DUALBANK | \
357+
OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | OB_USER_NSWBOOT0 | \
358+
OB_USER_NBOOT0 | OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | \
359+
OB_USER_TZEN | OB_USER_SRAM3_PE) /*!< All User option bits */
360+
#else
348361
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BDRST_POR | OB_USER_NRST_STOP | \
349362
OB_USER_NRST_STDBY | OB_USER_NRST_SHDW | OB_USER_SRAM1_RST | \
350363
OB_USER_IWDG_SW | OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | \
351364
OB_USER_WWDG_SW | OB_USER_SWAP_BANK | OB_USER_DUALBANK | \
352365
OB_USER_SRAM2_PE | OB_USER_SRAM2_RST | OB_USER_NSWBOOT0 | \
353366
OB_USER_NBOOT0 | OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | \
354367
OB_USER_TZEN) /*!< All User option bits */
368+
#endif /* FLASH_OPTR_SRAM3_PE */
355369
/**
356370
* @}
357371
*/
@@ -472,6 +486,18 @@ typedef struct
472486
*/
473487
#define OB_SRAM2_PE_ENABLE 0x00000000U /*!< SRAM2 Parity check enable */
474488
#define OB_SRAM2_PE_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 Parity check disable */
489+
/**
490+
* @}
491+
*/
492+
493+
#if defined(FLASH_OPTR_SRAM3_PE)
494+
/** @defgroup FLASH_OB_USER_SRAM3_PE FLASH Option Bytes User SRAM3 Parity Check Enable
495+
* @{
496+
*/
497+
#define OB_SRAM3_PE_ENABLE 0x00000000U /*!< SRAM3 Parity check enable */
498+
#define OB_SRAM3_PE_DISABLE FLASH_OPTR_SRAM3_PE /*!< SRAM3 Parity check disable */
499+
#endif /* FLASH_OPTR_SRAM3_PE */
500+
475501
/**
476502
* @}
477503
*/
@@ -1160,6 +1186,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
11601186

11611187
#define IS_OB_USER_SRAM2_PE(VALUE) (((VALUE) == OB_SRAM2_PE_ENABLE) || ((VALUE) == OB_SRAM2_PE_DISABLE))
11621188

1189+
#if defined(FLASH_OPTR_SRAM3_PE)
1190+
#define IS_OB_USER_SRAM3_PE(VALUE) (((VALUE) == OB_SRAM3_PE_ENABLE) || ((VALUE) == OB_SRAM3_PE_DISABLE))
1191+
#endif /* FLASH_OPTR_SRAM3_PE */
1192+
11631193
#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
11641194

11651195
#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))

‎system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_flash_ex.h‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,13 @@ extern "C" {
3939
/** @defgroup FLASHEx_Private_Constants FLASH Extended Private Constants
4040
* @{
4141
*/
42+
#if defined(FLASH_PRIVBB1R5_PRIV0)
43+
#define FLASH_BLOCKBASED_NB_REG (8U) /*!< Number of block-based registers available */
44+
#elif defined(FLASH_PRIVBB1R3_PRIV0)
4245
#define FLASH_BLOCKBASED_NB_REG (4U) /*!< Number of block-based registers available */
43-
46+
#else
47+
#define FLASH_BLOCKBASED_NB_REG (2U) /*!< Number of block-based registers available */
48+
#endif /* defined(STM32U3C5xx) || defined(STM32U3B5xx) */
4449
/**
4550
* @}
4651
*/
@@ -232,7 +237,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
232237
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
233238
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
234239
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
235-
HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
240+
HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(const FLASH_BBAttributesTypeDef *pBBAttributes);
236241
void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
237242
#if defined (CPU_IN_SECURE_STATE)
238243
void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks);

0 commit comments

Comments
 (0)