chore: Cygnet BSP clean-up

Author: zfields

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins_CYGNET.c

@@ -36,7 +36,7 @@ WEAK const PinMap PinMap_ADC[] = {
   {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC1_IN6  - A1
   {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7,  0)}, // ADC1_IN7  - A2
   {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC1_IN8  - A3
-  {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9,  0)}, // ADC1_IN9  - BAT_VOLTAGE
+  {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9,  0)}, // ADC1_IN9  - A6/BATTERY_VOLTAGE (STAT)
   {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - CK
   {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - MI
   {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - A5

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.cpp

@@ -16,53 +16,53 @@
 
 // Digital PinName array
 const PinName digitalPin[] = {
-  PA_0,   // 0 - D0/A0
-  PA_1,   // 1 - D1/A1
-  PA_2,   // 2 - D2/A2
-  PA_3,   // 3 - D3/A3
-  PB_1,   // 4 - D4/A4
-  PB_8,   // 5 - D5
-  PB_9,   // 6 - D6
-  PA_4,   // 7 - BAT_VOLTAGE
-  PA_8,   // 8 - LED_BUILTIN
-  PB_14,  // 9 - D9
+  PA_0,   //  0 - A0/D0
+  PA_1,   //  1 - A1/D1
+  PA_2,   //  2 - A2/D2
+  PA_3,   //  3 - A3/D3
+  PB_1,   //  4 - A4/D4
+  PB_8,   //  5 - D5
+  PB_9,   //  6 - D6
+  PA_8,   //  7 - LED_BUILTIN
+  PC_13,  //  8 - USER_BTN
+  PB_14,  //  9 - D9
   PB_13,  // 10 - D10
   PB_0,   // 11 - D11
   PB_15,  // 12 - D12
   PB_4,   // 13 - D13
-  PA_5,   // 14 - CK
-  PA_6,   // 15 - MI
-  PA_7,   // 16 - A5
-  PA_9,   // 17 - TX
+  PA_7,   // 14 - A5
+  PA_5,   // 15 - CK
+  PB_5,   // 16 - MO
+  PA_6,   // 17 - MI
   PA_10,  // 18 - RX
-  PA_11,  // 19 - USB_DM
-  PA_12,  // 20 - USB_DP
-  PA_13,  // 21 - SWDIO
-  PA_14,  // 22 - SWCLK
-  PA_15,  // 23 - CHARGE_DETECT
-  PB_3,   // 24 - USB_DETECT
-  PB_5,   // 25 - MO
-  PB_6,   // 26 - SCL
-  PB_7,   // 27 - SDA
-  PB_10,  // 28 - LPUART1_VCP_RX
-  PB_11,  // 29 - LPUART1_VCP_TX
-  PC_13,  // 30 - USER_BTN
-  PC_14,  // 31 - OSC32_IN
-  PC_15,  // 32 - OSC32_OUT
-  PH_0,   // 33 - ENABLE_3V3
-  PH_1,   // 34 - DISCHARGE_3V3
-  PH_3    // 35 - B
+  PA_9,   // 19 - TX
+  PH_3,   // 20 - B
+  PB_6,   // 21 - SCL
+  PB_7,   // 22 - SDA
+  PA_13,  // 23 - SWDIO
+  PA_14,  // 24 - SWCLK
+  PB_10,  // 25 - LPUART1_VCP_RX
+  PB_11,  // 26 - LPUART1_VCP_TX
+  PH_0,   // 27 - ENABLE_3V3
+  PH_1,   // 28 - DISCHARGE_3V3
+  PA_15,  // 29 - CHARGE_DETECT
+  PA_4,   // 30 - A6/BATTERY_VOLTAGE (STAT)
+  PB_3,   // 31 - USB_DETECT
+  PA_11,  // 32 - USB_DM
+  PA_12,  // 33 - USB_DP
+  PC_14,  // 34 - OSC32_IN (LSE)
+  PC_15   // 35 - OSC32_OUT (LSE)
 };
 
 // Analog (Ax) to digital pin number array
 const uint32_t analogInputPin[] = {
-  0,  // PA0, A0
-  1,  // PA1, A1
-  2,  // PA2, A2
-  3,  // PA3, A3
-  4,  // PB1, A4
-  16, // PA7, A5
-  7   // PA4, BAT_VOLTAGE
+   0,  // PA0, A0
+   1,  // PA1, A1
+   2,  // PA2, A2
+   3,  // PA3, A3
+   4,  // PB1, A4
+  14,  // PA7, A5
+  30   // PA4, A6/BATTERY_VOLTAGE (STAT)
 };
 
 // ----------------------------------------------------------------------------
@@ -76,7 +76,7 @@ WEAK void initVariant(void)
   /* All pins set to high-Z (floating) initially */
   /* DS11449 Rev 8, Section 3.9.5 - Reset Mode: */
   /* In order to improve the consumption under reset, the I/Os state under
-   * and after reset is “analog state” (the I/O schmitt trigger is disable).
+   * and after reset is "analog state" (the I/O schmitt trigger is disabled).
    * In addition, the internal reset pull-up is deactivated when the reset
    * source is internal.
    */
@@ -121,10 +121,24 @@ WEAK void initVariant(void)
 }
 
 /**
-  * @brief  System Clock Configuration
-  * @param  None
-  * @retval None
-  */
+ * @brief  System Clock Configuration - PLL-based STM32L433 with native USB FS
+ *
+ * Key features:
+ *   - SYSCLK = 80 MHz from MSI (4 MHz, Range 6) via PLL (4MHz x 40/2)
+ *   - USB FS (48 MHz) sourced from PLLSAI1 (4MHz x 24/2)
+ *   - HSI disabled to reduce current consumption (~200-300 uA)
+ *   - LSE enabled with medium-low drive for RTC and MSI auto-calibration (MSIPLLEN)
+ *   - Voltage Scale 1 required for 80 MHz operation
+ *   - FLASH_LATENCY_4 required for HCLK > 64 MHz at VOS1 (RM0394 s.3.3.3)
+ *   - MSI PLL-mode (MSIPLLEN) enabled after SYSCLK moves to PLL to avoid MSIRDY stall
+ *   - Wake-up clock after STOP: MSI (PLL must be re-locked manually after wake)
+ *
+ * References:
+ *   - RM0394 Rev 6 (STM32L43x/L44x) - s.6.2 "MSI clock"
+ *   - RM0394 s.6.2.9 "MSI PLL-mode"
+ *   - RM0394 s.3.3.3 "Performance versus VDD and clock frequency"
+ *   - AN2867 Rev 11 - "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs"
+ */
 WEAK void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {};
@@ -133,15 +147,16 @@ WEAK void SystemClock_Config(void)
 
   /** Enable PWR peripheral clock
   *
-  * RM0394 §5.1.2: PWR registers are on APB1. PWREN (RCC_APB1ENR1 bit 28)
+  * RM0394 s.5.1.2: PWR registers are on APB1. PWREN (RCC_APB1ENR1 bit 28)
   * resets to 1, so this is defensive rather than strictly necessary, but
   * required for correctness if PWREN has been cleared by prior code.
   * CubeMX generates this unconditionally for all STM32L4 projects.
   */
   __HAL_RCC_PWR_CLK_ENABLE();
 
-  /** Configure the main internal regulator output voltage
-  */
+  /* Voltage scaling - Scale 1 required for SYSCLK = 80 MHz
+   * RM0394 s.6.1: VOS2 supports up to 26 MHz only
+   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
     Error_Handler();
   }
@@ -163,33 +178,29 @@ WEAK void SystemClock_Config(void)
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   *
-  * Cygnet config:
-  *   - MSI: MSIRANGE_6 (4 MHz) — used as PLL input
-  *   - HSI: OFF — nothing in this config uses it
-  *   - PLL: NONE → ON  (MSI 4 MHz × PLLN=40 / PLLR=2 → SYSCLK = 80 MHz)
-  *   - SYSCLK: MSI (48 MHz) → PLLCLK (80 MHz)
-  *   - USB clock: removed from PeriphCLKConfig (MSI) → PLLSAI1 (48 MHz)
+  * Oscillator configuration summary:
+  *   - MSI: MSIRANGE_6 (4 MHz) -- used as PLL input
+  *   - HSI: OFF -- Unused, disabling it saves ~200-300 uA
+  *   - PLL: ON  (MSI 4MHz x PLLN=40 / PLLR=2 = 80 MHz)
+  *   - SYSCLK: PLLCLK (80 MHz)
+  *   - USB clock: PLLSAI1 (48 MHz)
   *   - MSIRDY transient can not stall SysTick because SYSCLK = PLL, not MSI.
-  *   - FLASH_LATENCY: 2 → 4  (required for 80 MHz / VOS1 per RM0394 §3.3)
+  *   - FLASH_LATENCY: 4 (required for 80 MHz / VOS1 per RM0394 s.3.3)
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE
                                       | RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-  /* HSI is not used as SYSCLK source, PLL/PLLSAI1 input, or any peripheral
-   * clock reference. Disabling it saves ~200-300 µA. */
   RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
   RCC_OscInitStruct.MSIState = RCC_MSI_ON;
   RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  /* MSIRANGE_6 = 4 MHz — same as Nucleo. Low-frequency reference fed into
-   * the main PLL (×40/÷2 = 80 MHz) and PLLSAI1 (×24/÷2 = 48 MHz). */
   RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
   RCC_OscInitStruct.PLL.PLLM = 1;
   RCC_OscInitStruct.PLL.PLLN = 40;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
-  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;  /* 4 × 40 / 2 = 80 MHz */
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;  /* 4MHz x 40 / 2 = 80 MHz */
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
     Error_Handler();
   }
@@ -206,24 +217,24 @@ WEAK void SystemClock_Config(void)
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  /* FLASH_LATENCY_4: required for HCLK > 64 MHz at VOS1 (RM0394 §3.3.3) */
+  /* FLASH_LATENCY_4: required for HCLK > 64 MHz at VOS1 (RM0394 s.3.3.3) */
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
     Error_Handler();
   }
 
   /** Initializes the Peripheral clocks
   *
-  * USB clock: PLLSAI1 (MSI 4 MHz × PLLSAI1N=24 / PLLSAI1Q=2 = 48 MHz).
+  * USB clock: PLLSAI1 (MSI 4 MHz x PLLSAI1N=24 / PLLSAI1Q=2 = 48 MHz).
   * This mirrors the Nucleo L432KC exactly. RCCEx_PLLSAI1_Config() waits
   * for PLLSAI1RDY using HAL_GetTick(). Because SYSCLK is now PLL-based,
-  * HAL_GetTick() is immune to MSI transients — the wait is reliable.
+  * HAL_GetTick() is immune to MSI transients -- the wait is reliable.
   * PLLSAI1 and the main PLL share the same source (MSI) and M divider (1),
   * which the HAL enforces; both are configured consistently here.
   *
   * HAL_RCCEx_PeriphCLKConfig writes CLK48SEL first (pointing at PLLSAI1
   * before it is running), then enables PLLSAI1 and waits for its RDY flag.
   * During that brief window the USB peripheral has no 48 MHz clock and
-  * stays quiescent — avoiding the race where a live MSI clock is handed
+  * stays quiescent -- avoiding the race where a live MSI clock is handed
   * to USB before the peripheral is ready to handle the absence of VBUS.
   */
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
@@ -233,7 +244,7 @@ WEAK void SystemClock_Config(void)
   PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
   PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
   PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
-  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;  /* 4 × 24 / 2 = 48 MHz */
+  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;  /* 4 x 24 / 2 = 48 MHz */
   PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
   PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
@@ -242,10 +253,10 @@ WEAK void SystemClock_Config(void)
 
 /** Enable MSI Auto calibration (MSIPLLEN, RCC_CR[2])
  *
- * RM0394 §6.2 (MSI clock): setting MSIPLLEN causes the MSI hardware
+ * RM0394 s.6.2 (MSI clock): setting MSIPLLEN causes the MSI hardware
  * to automatically trim itself against LSE as a phase reference,
- * reducing MSI frequency error to < ±0.25%. LSE must already be
- * stable (LSERDY=1) before the bit is set — guaranteed here because
+ * reducing MSI frequency error to < +/-0.25%. LSE must already be
+ * stable (LSERDY=1) before the bit is set -- guaranteed here because
  * HAL_RCC_OscConfig() waited for LSERDY before returning.
  *
  * Setting MSIPLLEN causes MSIRDY to deassert transiently while MSI
@@ -254,18 +265,18 @@ WEAK void SystemClock_Config(void)
  * inside it. Two conclusions follow:
  *
  *   (1) This call must come AFTER any HAL routine that polls MSIRDY
- *       under a HAL_GetTick() timeout — if MSIRDY drops inside such
+ *       under a HAL_GetTick() timeout -- if MSIRDY drops inside such
  *       a routine, the routine returns HAL_TIMEOUT and leaves the
  *       clock tree in an undefined state.
  *
  *   (2) If SYSCLK were MSI, a deadlock would be possible: MSIRDY
- *       drops → SysTick stalls → HAL_GetTick() freezes → any
- *       subsequent timeout loop never exits. RM0394 §6.2.9 confirms
+ *       drops -> SysTick stalls -> HAL_GetTick() freezes -> any
+ *       subsequent timeout loop never exits. RM0394 s.6.2.9 confirms
  *       SysTick is driven by HCLK (= SYSCLK / AHBdiv). Because
  *       SYSCLK is now PLLCLK (80 MHz), SysTick is completely
  *       decoupled from MSI and the transient is harmless.
  *
- * Placement here — after PeriphCLKConfig — satisfies both constraints
+ * Placement here -- after PeriphCLKConfig -- satisfies both constraints
  * and mirrors the ordering generated by CubeMX for the Nucleo L432KC.
  */
 HAL_RCCEx_EnableMSIPLLMode();
@@ -278,7 +289,6 @@ HAL_RCCEx_EnableMSIPLLMode();
   * PLL-based design on STM32L4.
   */
   HAL_RCCEx_WakeUpStopCLKConfig(RCC_STOP_WAKEUPCLOCK_MSI);
-#pragma message("Compiled using local Arduino_Core_STM32: 2.13.0-dev.")
 }
 
 #ifdef __cplusplus