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Merge pull request #2925 from fpistm/stm32cubeG4_update
chore(g4): update to latest STM32CubeG4 v1.6.2
2 parents 1b98ba7 + 23693f7 commit b6fa63c

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108 files changed

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‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g411xb.h‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2995,7 +2995,7 @@ typedef struct
29952995

29962996
/******************** Bits definition for DMAMUX_CxCR register **************/
29972997
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
2998-
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
2998+
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
29992999
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
30003000
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
30013001
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
@@ -3004,6 +3004,8 @@ typedef struct
30043004
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
30053005
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
30063006
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3007+
3008+
/* Legacy defines */
30073009
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
30083010

30093011
#define DMAMUX_CxCR_SOIE_Pos (8U)
@@ -8008,8 +8010,8 @@ typedef struct
80088010
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
80098011
#define RNG_CR_IE RNG_CR_IE_Msk
80108012
#define RNG_CR_CED_Pos (5U)
8011-
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
8012-
#define RNG_CR_CED RNG_CR_IE_Msk
8013+
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
8014+
#define RNG_CR_CED RNG_CR_CED_Msk
80138015

80148016
/******************** Bits definition for RNG_SR register *******************/
80158017
#define RNG_SR_DRDY_Pos (0U)
@@ -9997,27 +9999,27 @@ typedef struct
99979999

999810000
/******************* Bit definition for TIM_CCR1 register *******************/
999910001
#define TIM_CCR1_CCR1_Pos (0U)
10000-
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
10002+
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
1000110003
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
1000210004

1000310005
/******************* Bit definition for TIM_CCR2 register *******************/
1000410006
#define TIM_CCR2_CCR2_Pos (0U)
10005-
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
10007+
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
1000610008
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
1000710009

1000810010
/******************* Bit definition for TIM_CCR3 register *******************/
1000910011
#define TIM_CCR3_CCR3_Pos (0U)
10010-
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
10012+
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
1001110013
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
1001210014

1001310015
/******************* Bit definition for TIM_CCR4 register *******************/
1001410016
#define TIM_CCR4_CCR4_Pos (0U)
10015-
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
10017+
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
1001610018
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
1001710019

1001810020
/******************* Bit definition for TIM_CCR5 register *******************/
1001910021
#define TIM_CCR5_CCR5_Pos (0U)
10020-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
10022+
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
1002110023
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1002210024
#define TIM_CCR5_GC5C1_Pos (29U)
1002310025
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -10031,7 +10033,7 @@ typedef struct
1003110033

1003210034
/******************* Bit definition for TIM_CCR6 register *******************/
1003310035
#define TIM_CCR6_CCR6_Pos (0U)
10034-
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
10036+
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
1003510037
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
1003610038

1003710039
/******************* Bit definition for TIM_BDTR register *******************/

‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g411xc.h‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3083,7 +3083,7 @@ typedef struct
30833083

30843084
/******************** Bits definition for DMAMUX_CxCR register **************/
30853085
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3086-
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3086+
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
30873087
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
30883088
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
30893089
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
@@ -3092,6 +3092,8 @@ typedef struct
30923092
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
30933093
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
30943094
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3095+
3096+
/* Legacy defines */
30953097
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
30963098

30973099
#define DMAMUX_CxCR_SOIE_Pos (8U)
@@ -8196,8 +8198,8 @@ typedef struct
81968198
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
81978199
#define RNG_CR_IE RNG_CR_IE_Msk
81988200
#define RNG_CR_CED_Pos (5U)
8199-
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
8200-
#define RNG_CR_CED RNG_CR_IE_Msk
8201+
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
8202+
#define RNG_CR_CED RNG_CR_CED_Msk
82018203

82028204
/******************** Bits definition for RNG_SR register *******************/
82038205
#define RNG_SR_DRDY_Pos (0U)
@@ -10215,27 +10217,27 @@ typedef struct
1021510217

1021610218
/******************* Bit definition for TIM_CCR1 register *******************/
1021710219
#define TIM_CCR1_CCR1_Pos (0U)
10218-
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
10220+
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
1021910221
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
1022010222

1022110223
/******************* Bit definition for TIM_CCR2 register *******************/
1022210224
#define TIM_CCR2_CCR2_Pos (0U)
10223-
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
10225+
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
1022410226
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
1022510227

1022610228
/******************* Bit definition for TIM_CCR3 register *******************/
1022710229
#define TIM_CCR3_CCR3_Pos (0U)
10228-
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
10230+
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
1022910231
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
1023010232

1023110233
/******************* Bit definition for TIM_CCR4 register *******************/
1023210234
#define TIM_CCR4_CCR4_Pos (0U)
10233-
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
10235+
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
1023410236
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
1023510237

1023610238
/******************* Bit definition for TIM_CCR5 register *******************/
1023710239
#define TIM_CCR5_CCR5_Pos (0U)
10238-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
10240+
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
1023910241
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1024010242
#define TIM_CCR5_GC5C1_Pos (29U)
1024110243
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -10249,7 +10251,7 @@ typedef struct
1024910251

1025010252
/******************* Bit definition for TIM_CCR6 register *******************/
1025110253
#define TIM_CCR6_CCR6_Pos (0U)
10252-
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
10254+
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
1025310255
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
1025410256

1025510257
/******************* Bit definition for TIM_BDTR register *******************/

‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g414xx.h‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3448,7 +3448,7 @@ typedef struct {
34483448

34493449
/******************** Bits definition for DMAMUX_CxCR register **************/
34503450
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3451-
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3451+
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
34523452
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
34533453
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
34543454
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
@@ -3457,6 +3457,8 @@ typedef struct {
34573457
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
34583458
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
34593459
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3460+
3461+
/* Legacy defines */
34603462
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
34613463

34623464
#define DMAMUX_CxCR_SOIE_Pos (8U)
@@ -12099,8 +12101,8 @@ typedef struct {
1209912101
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
1210012102
#define RNG_CR_IE RNG_CR_IE_Msk
1210112103
#define RNG_CR_CED_Pos (5U)
12102-
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
12103-
#define RNG_CR_CED RNG_CR_IE_Msk
12104+
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
12105+
#define RNG_CR_CED RNG_CR_CED_Msk
1210412106

1210512107
/******************** Bits definition for RNG_SR register *******************/
1210612108
#define RNG_SR_DRDY_Pos (0U)
@@ -14233,27 +14235,27 @@ typedef struct {
1423314235

1423414236
/******************* Bit definition for TIM_CCR1 register *******************/
1423514237
#define TIM_CCR1_CCR1_Pos (0U)
14236-
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
14238+
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
1423714239
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
1423814240

1423914241
/******************* Bit definition for TIM_CCR2 register *******************/
1424014242
#define TIM_CCR2_CCR2_Pos (0U)
14241-
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
14243+
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
1424214244
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
1424314245

1424414246
/******************* Bit definition for TIM_CCR3 register *******************/
1424514247
#define TIM_CCR3_CCR3_Pos (0U)
14246-
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
14248+
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
1424714249
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
1424814250

1424914251
/******************* Bit definition for TIM_CCR4 register *******************/
1425014252
#define TIM_CCR4_CCR4_Pos (0U)
14251-
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
14253+
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
1425214254
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
1425314255

1425414256
/******************* Bit definition for TIM_CCR5 register *******************/
1425514257
#define TIM_CCR5_CCR5_Pos (0U)
14256-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14258+
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
1425714259
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1425814260
#define TIM_CCR5_GC5C1_Pos (29U)
1425914261
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -14267,7 +14269,7 @@ typedef struct {
1426714269

1426814270
/******************* Bit definition for TIM_CCR6 register *******************/
1426914271
#define TIM_CCR6_CCR6_Pos (0U)
14270-
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
14272+
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
1427114273
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
1427214274

1427314275
/******************* Bit definition for TIM_BDTR register *******************/

‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3122,7 +3122,7 @@ typedef struct
31223122

31233123
/******************** Bits definition for DMAMUX_CxCR register **************/
31243124
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3125-
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3125+
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
31263126
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
31273127
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
31283128
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
@@ -3131,6 +3131,8 @@ typedef struct
31313131
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
31323132
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
31333133
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3134+
3135+
/* Legacy defines */
31343136
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
31353137

31363138
#define DMAMUX_CxCR_SOIE_Pos (8U)
@@ -8210,8 +8212,8 @@ typedef struct
82108212
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
82118213
#define RNG_CR_IE RNG_CR_IE_Msk
82128214
#define RNG_CR_CED_Pos (5U)
8213-
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
8214-
#define RNG_CR_CED RNG_CR_IE_Msk
8215+
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
8216+
#define RNG_CR_CED RNG_CR_CED_Msk
82158217

82168218
/******************** Bits definition for RNG_SR register *******************/
82178219
#define RNG_SR_DRDY_Pos (0U)
@@ -10539,27 +10541,27 @@ typedef struct
1053910541

1054010542
/******************* Bit definition for TIM_CCR1 register *******************/
1054110543
#define TIM_CCR1_CCR1_Pos (0U)
10542-
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
10544+
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
1054310545
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
1054410546

1054510547
/******************* Bit definition for TIM_CCR2 register *******************/
1054610548
#define TIM_CCR2_CCR2_Pos (0U)
10547-
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
10549+
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
1054810550
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
1054910551

1055010552
/******************* Bit definition for TIM_CCR3 register *******************/
1055110553
#define TIM_CCR3_CCR3_Pos (0U)
10552-
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
10554+
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
1055310555
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
1055410556

1055510557
/******************* Bit definition for TIM_CCR4 register *******************/
1055610558
#define TIM_CCR4_CCR4_Pos (0U)
10557-
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
10559+
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
1055810560
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
1055910561

1056010562
/******************* Bit definition for TIM_CCR5 register *******************/
1056110563
#define TIM_CCR5_CCR5_Pos (0U)
10562-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
10564+
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
1056310565
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1056410566
#define TIM_CCR5_GC5C1_Pos (29U)
1056510567
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -10573,7 +10575,7 @@ typedef struct
1057310575

1057410576
/******************* Bit definition for TIM_CCR6 register *******************/
1057510577
#define TIM_CCR6_CCR6_Pos (0U)
10576-
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
10578+
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
1057710579
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
1057810580

1057910581
/******************* Bit definition for TIM_BDTR register *******************/

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