lemp14: NVMe power sequence

Change-Id: I412d890ccb61a0bc3283d6050a36f54b315a00b8
Signed-off-by: Tim Crawford <tcrawford@system76.com>

Author: crawfxrd

src/mainboard/system76/ptl/variants/lemp14/gpio.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootstate.h>
 #include <mainboard/gpio.h>
 #include <soc/gpio.h>
 
@@ -30,8 +31,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
 	PAD_NC(GPP_B07, NONE),
 	PAD_NC(GPP_B08, NONE),
-	PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD1_RST#
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
+	//PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD1_RST#
+	//PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
 	PAD_CFG_GPI(GPP_B11, NONE, PLTRST),
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
@@ -91,7 +92,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_D15, NONE, DEEP), // CNVI_WAKE#
 	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST#
 	PAD_NC(GPP_D17, NONE),
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD1_CLKREQ#_N
+	//PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD1_CLKREQ#_N
 	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SD_PCIE_RST_N
 	PAD_NC(GPP_D20, NONE),
 	PAD_NC(GPP_D21, NONE),
@@ -198,3 +199,26 @@ void mainboard_configure_gpios(void)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
+
+static const struct pad_config nvme_pwr_seq2[] = {
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD1_CLKREQ#_N
+};
+
+static void nvme_enable_power(void *unused)
+{
+	gpio_configure_pads(nvme_pwr_seq2, ARRAY_SIZE(nvme_pwr_seq2));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, nvme_enable_power, NULL);
+
+static const struct pad_config nvme_pwr_seq3[] = {
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD1_RST#
+};
+
+static void nvme_deassert_perst(void *unused)
+{
+	gpio_configure_pads(nvme_pwr_seq3, ARRAY_SIZE(nvme_pwr_seq3));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, nvme_deassert_perst, NULL);

src/mainboard/system76/ptl/variants/lemp14/gpio_early.c

@@ -8,6 +8,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI(GPP_E15, NONE, DEEP), // BOARD_ID3
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+
+	PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPO(GPP_B10, 0, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP), // SSD1_CLKREQ#_N
 };
 
 void mainboard_configure_early_gpios(void)