mb/system76/ptl: addp6: GPIOs and devicetree

crawfxrd · crawfxrd · commit 4071682a376a · 2026-06-04T19:43:17.000-06:00
Change-Id: Ic17b7b0039698ef78869abee1c7500ee5953b1c3
Signed-off-by: Tim Crawford &lt;tcrawford@system76.com&gt;
diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SYSTEM76_ADDP6
 	select BOARD_SYSTEM76_PTL_COMMON
 	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_OLED
 
 config BOARD_SYSTEM76_LEMP14
 	select BOARD_SYSTEM76_PTL_COMMON
diff --git a/src/mainboard/system76/ptl/acpi/mainboard.asl b/src/mainboard/system76/ptl/acpi/mainboard.asl
@@ -7,6 +7,9 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
+#if !CONFIG(EC_SYSTEM76_EC_OLED)
 		#include "backlight.asl"
+#endif
+		/* TODO: Add NVIDIA include */
 	}
 }
diff --git a/src/mainboard/system76/ptl/variants/addp6/gpio.c b/src/mainboard/system76/ptl/variants/addp6/gpio.c
@@ -16,28 +16,28 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A08, NONE), // SOC_SML_SCL (NC)
 	PAD_NC(GPP_A09, NONE), // SOC_SML_SDA (NC)
 	PAD_NC(GPP_A10, NONE),
-	PAD_NC(GPP_A11, NONE), // WLAN_RST#
+	PAD_CFG_GPO(GPP_A11, 1, DEEP), // WLAN_RST#
 	PAD_NC(GPP_A12, NONE), // WLAN_WAKEUP# (NC)
-	PAD_NC(GPP_A13, NONE), // NVVDD_TALERT#
+	PAD_NC(GPP_A13, NONE), // NVVDD_TALERT# (NC?)
 	PAD_NC(GPP_A15, NONE), // EPD_ON_GCD_IN
-	PAD_NC(GPP_A16, NONE), // PCH_BT_EN
-	PAD_NC(GPP_A17, NONE), // WIFI_RF_EN
+	PAD_NC(GPP_A16, NONE), // PCH_BT_EN (NC)
+	PAD_CFG_GPO(GPP_A17, 1, NONE), // WIFI_RF_EN
 
-	PAD_NC(GPP_B00, NONE), // SOC_SMLINK_I2C_SCL
-	PAD_NC(GPP_B01, NONE), // SOC_SMLINK_I2C_SDA
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), // SOC_SMLINK_I2C_SCL
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), // SOC_SMLINK_I2C_SDA
 	PAD_NC(GPP_B02, NONE),
 	PAD_NC(GPP_B03, NONE),
-	PAD_NC(GPP_B04, NONE), // CPU_ME_WE / Flash Descriptor Security Override strap
+	PAD_CFG_GPI(GPP_B04, NONE), // CPU_ME_WE / Flash Descriptor Security Override strap
 	PAD_NC(GPP_B05, NONE), // PS8461_SW_PCH (NC)
 	PAD_NC(GPP_B06, NONE),
 	PAD_NC(GPP_B07, NONE),
 	PAD_NC(GPP_B08, NONE),
 	//PAD_NC(GPP_B09, NONE), // M2_SSD2_RST#
-	PAD_NC(GPP_B10, NONE), // CPU_HDMI_HPD
-	PAD_NC(GPP_B11, NONE), // TCP2_HPD (CPU_TYPEC1_DP_HPD)
+	PAD_NC(GPP_B10, NONE), // CPU_HDMI_HPD (NC?)
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // TCP2_HPD (CPU_TYPEC1_DP_HPD)
 	PAD_NC(GPP_B12, NONE), // SLP_S0# (NC)
-	PAD_NC(GPP_B13, NONE), // PLT_RST#
-	PAD_NC(GPP_B14, NONE), // TCP3_HPD (CPU_TYPEC2_DP_HPD)
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // TCP3_HPD (CPU_TYPEC2_DP_HPD)
 	PAD_CFG_GPI(GPP_B15, NONE), // USB_OC3# (10k P/U to 1.8VA)
 	//PAD_NC(GPP_B16, NONE), // SSD1_PWR_EN
 	PAD_NC(GPP_B17, NONE),
@@ -85,13 +85,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D07, NONE),
 	PAD_NC(GPP_D08, NONE),
 	//PAD_NC(GPP_D09, NONE), // DGPU_RST#
-	PAD_NC(GPP_D10, NONE), // HDA_BITCLK
-	PAD_NC(GPP_D11, NONE), // HDA_SYNC
-	PAD_NC(GPP_D12, NONE), // HDA_SDOUT
-	PAD_NC(GPP_D13, NONE), // HDA_SDIN0
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), // HDA_SDIN0
 	PAD_NC(GPP_D14, NONE),
 	PAD_NC(GPP_D15, NONE), // CNVI_WAKE#
-	PAD_NC(GPP_D16, NONE), // HDA_RST#
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST#
 	PAD_NC(GPP_D17, NONE),
 	//PAD_NC(GPP_D18, NONE), // SSD2_CLK6REQ#_N
 	PAD_CFG_GPI(GPP_D19, NONE, PLTRST), // 10k P/U to 1.8VS
@@ -102,7 +102,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D24, NONE),
 	PAD_NC(GPP_D25, NONE),
 
-	PAD_NC(GPP_E01, NONE), // TPM_PIRQ#
+	PAD_CFG_GPI_SCI_LOW(GPP_E01, NONE, DEEP, EDGE_SINGLE), // TPM_PIRQ#
 	PAD_NC(GPP_E02, NONE), // VRALERT# (NC)
 	//PAD_NC(GPP_E03, NONE), // M2_SSD1_RST#
 	PAD_NC(GPP_E05, NONE),
@@ -119,18 +119,18 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E16, NONE),
 	//PAD_NC(GPP_E17, NONE), // BOARD_ID4
 	PAD_NC(GPP_E18, NONE),
-	PAD_NC(GPP_E19, NONE), // PCH_GPIO_LANRTD3
+	PAD_NC(GPP_E19, NONE), // PCH_GPIO_LANRTD3 (NC)
 	PAD_NC(GPP_E20, NONE),
 	PAD_NC(GPP_E21, NONE), // SOC_SMLINK_I2C_INT (NC)
 	PAD_NC(GPP_E22, NONE),
 
-	PAD_NC(GPP_F00, NONE), // CNVI_BRI_DT
-	PAD_NC(GPP_F01, NONE), // CNVI_BRI_RSP
-	PAD_NC(GPP_F02, NONE), // CNVI_RGI_DT / M.2 CNVi mode strap
-	PAD_NC(GPP_F03, NONE), // CNVI_RGI_RSP
-	PAD_NC(GPP_F04, NONE), // CNVI_RST#
-	PAD_NC(GPP_F05, NONE), // CNVI_CLKREQ
-	PAD_NC(GPP_F06, NONE), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, NONE, UP_20K, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi mode strap
+	PAD_CFG_NF(GPP_F03, NONE, UP_20K, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
 	PAD_NC(GPP_F07, NONE),
 	PAD_NC(GPP_F08, NONE),
 	PAD_CFG_GPI(GPP_F09, NONE, PLTRST), // TPM_DET: 0=None, 1=Present
@@ -139,9 +139,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), // I2C_SCL_TP
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), // I2C_SDA_TP
 	//PAD_NC(GPP_F14, NONE), // DGPU_PWR_EN
-	PAD_NC(GPP_F15, NONE), // GPIO4_GC6_NVVDD_EN
-	PAD_NC(GPP_F16, NONE), // CCD_WP#
-	PAD_NC(GPP_F17, NONE), // GC6_FB_EN_PCH
+	PAD_CFG_GPI(GPP_F15, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN (10k P/U to 1V8_AON)
+	PAD_CFG_GPO(GPP_F16, 0, DEEP), // CCD_WP#
+	PAD_CFG_GPI(GPP_F17, NONE), // GC6_FB_EN_PCH
 	PAD_CFG_GPI_APIC_LOW(GPP_F18, NONE, DEEP), // TP_ATTN#
 	PAD_NC(GPP_F19, NONE), // Reserved strap
 	//PAD_NC(GPP_F20, NONE), // DGPU_PWRGD
@@ -179,20 +179,20 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_S06, NONE), // M.2_BT_PCMOUT_CLKREQ0 (NC)
 	PAD_NC(GPP_S07, NONE), // M.2_BT_PCMIN (NC)
 
-	PAD_NC(GPP_V00, NONE), // PM_BATLOW#
-	PAD_NC(GPP_V01, NONE), // SOC_AC_PRESENT
-	PAD_NC(GPP_V02, NONE), // PCH_LAN_WAKE# (NC)
-	PAD_NC(GPP_V03, NONE), // SOC_PWR_BTN#
-	PAD_NC(GPP_V04, NONE), // SUSB#_PCH
-	PAD_NC(GPP_V05, NONE), // SUSC#_PCH
-	PAD_NC(GPP_V06, NONE), // SLP_A# (NC)
-	PAD_NC(GPP_V07, NONE), // SUS_CLK
-	PAD_NC(GPP_V08, NONE), // SLP_WLAN# (NC)
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // SOC_AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // PCH_LAN_WAKE# (NC?)
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // SOC_PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // SLP_A# (NC?)
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), // SUS_CLK
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), // SLP_WLAN# (NC?)
 	PAD_NC(GPP_V09, NONE),
-	PAD_NC(GPP_V10, NONE), // LANPHYPC
-	PAD_NC(GPP_V11, NONE), // LAN_CTRL_PWREN (NC)
-	PAD_NC(GPP_V12, NONE), // PCH_WAKEUP#
-	PAD_NC(GPP_V16, NONE), // VCCST_EN
+	PAD_NC(GPP_V10, NONE),
+	PAD_NC(GPP_V11, NONE),
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // PCH_WAKEUP#
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN
 	PAD_NC(GPP_V17, NONE),
 };
 
diff --git a/src/mainboard/system76/ptl/variants/addp6/hda_verb.c b/src/mainboard/system76/ptl/variants/addp6/hda_verb.c
@@ -3,7 +3,7 @@
 #include <device/azalia_device.h>
 
 static const u32 realtek_alc255_verbs[] = {
-	AZALIA_SUBVENDOR(0, 0x15580000), // TODO
+	AZALIA_SUBVENDOR(0, 0x1558f551),
 	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)),
@@ -23,7 +23,7 @@ struct azalia_codec mainboard_azalia_codecs[] = {
 	{
 		.name = "Realtek ALC255",
 		.vendor_id = 0x10ec0255,
-		.subsystem_id = 0, // TODO
+		.subsystem_id = 0x1558f551,
 		.address = 0,
 		.verbs = realtek_alc255_verbs,
 		.verb_count = ARRAY_SIZE(realtek_alc255_verbs),
diff --git a/src/mainboard/system76/ptl/variants/addp6/overridetree.cb b/src/mainboard/system76/ptl/variants/addp6/overridetree.cb
@@ -9,7 +9,207 @@ chip soc/intel/pantherlake
 		}
 	}"
 
+	# TODO
+	#register "power_limits_config[]" = "{
+	#	.tdp_pl1_override = ,
+	#	.tdp_pl2_override = ,
+	#}"
+
 	device domain 0 on
-		#subsystemid 0x1558 0x000 inherit
+		subsystemid 0x1558 0xf551 inherit
+
+		device ref igpu on
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			chip drivers/gfx/generic
+				register "device_count" = "3"
+				# DDIA: eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = ""panel""
+				# TCP2: USB3.2 Gen2 + DP1.4 (J_TYPEC1)
+				register "device[1].name" = ""DD01""
+				register "device[1].use_pld" = "true"
+				register "device[1].pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
+				# TCP3: USB3.2 Gen2 + DP1.4  (J_TYPEC2)
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 2))"
+				# HDMI connected through dGPU
+				device generic 0 on end
+			end
+		end
+		device ref tcss_xhci on
+			register "tcss_ports" = "{
+				[2] = TCSS_PORT_DEFAULT(OC_SKIP),
+				[3] = TCSS_PORT_DEFAULT(OC_SKIP),
+			}"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""J_TYPEC1""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref tcss_usb3_port2
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""J_TYPEC2""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref tcss_usb3_port3
+					end
+				end
+			end
+		end
+		device ref heci_1 on end # XXX: Needed?
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),		/* USB Type-A */
+				[1] = USB2_PORT_MID(OC_SKIP),		/* J_TYPEC2 */
+				[2] = USB2_PORT_MID(OC_SKIP),		/* J_TYPEC1 */
+				[4] = USB2_PORT_MID(OC_SKIP),		/* USB Type-A*/
+				[6] = USB2_PORT_MID(OC_SKIP),		/* Camera */
+				[7] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB Type-A */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB Type-A */
+			}"
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3.2 Gen 1 (ARJ_USB1)""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3.2 Gen2 + DP1.4 (J_TYPEC2)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3.2 Gen2 + DP1.4 (J_TYPEC1)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3.2 Gen 1 (RJ_USB1)""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3.2 Gen 1 (ARJ_USB1)""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3.2 Gen 1 (RJ_USB1)""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref i2c3 on end # XXX: USB-PD?
+		device ref eheci1 on end # XXX: Needed?
+		device ref i2c5 on
+			# Touchpad
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref pcie_rp1 on
+			# SSD2
+			register "pcie_rp[PCIE_RP(1)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E08)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp7 on
+			# LAN
+			register "pcie_rp[PCIE_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			# No RTD3
+		end
+		device ref pcie_rp8 on
+			# WLAN
+			register "pcie_rp[PCIE_RP(8)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "srcclk_pin" = "4"
+				device generic 0 on end
+			end
+			chip drivers/wifi/generic
+				use usb2_port8 as bluetooth_companion
+				device pci 00.0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp9 on
+			# SSD1
+			register "pcie_rp[PCIE_RP(9)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "srcclk_pin" = "5"
+				device generic 0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp11 on
+			# DGPU
+			register "pcie_rp[PCIE_RP(11)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
 	end
 end

Original file line number	Diff line number	Diff line change
`@@ -7,6 +7,9 @@`
`7`	`7`	`Scope (\_SB) {`
`8`	`8`	`#include "sleep.asl"`
`9`	`9`	`Scope (PCI0) {`
	`10`	`+#if !CONFIG(EC_SYSTEM76_EC_OLED)`
`10`	`11`	`#include "backlight.asl"`
	`12`	`+#endif`
	`13`	`+ /* TODO: Add NVIDIA include */`
`11`	`14`	`}`
`12`	`15`	`}`