Labels

• Area: Formal

  Formal Verification flow and test cases
• Area: IP Integration

  Third-party IP integration
• Area: Micro-Architecture

  Micro-Architecture design and specification
• Area: Physical Design

  Physical design flow(Floorplan, placement, CTS, routing, DRC, LVS)
• Area: RTL

  SystemVerilog RTL
• Area: Synthesis

  SDC(Timing constraints), UPF(Universal power format) and synthesis flow
• Area: Test plan

  Verification test plan document
• Area: Testbench

  Simple testbench
• Area: Verification

  UVM verification environment and test cases