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Lines changed: 117 additions & 113 deletions

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‎zjit/src/backend/arm64/mod.rs‎

Lines changed: 61 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1614,64 +1614,67 @@ impl Assembler {
16141614

16151615
asm_dump!(asm, split);
16161616

1617-
let (intervals, assignments, num_stack_slots) = trace_compile_phase("regalloc", || {
1618-
trace_compile_phase("number_instructions", || asm.number_instructions(0));
1617+
trace_compile_phase("regalloc", || {
1618+
trace_compile_phase("number_instructions", || asm.number_instructions(0));
16191619

1620-
let live_in = trace_compile_phase("analyze_liveness", || asm.analyze_liveness());
1621-
let intervals = trace_compile_phase("build_intervals", || asm.build_intervals(live_in));
1620+
let live_in = trace_compile_phase("analyze_liveness", || asm.analyze_liveness());
1621+
let intervals = trace_compile_phase("build_intervals", || asm.build_intervals(live_in));
16221622

1623-
// Dump live intervals if requested
1624-
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1625-
if dump_lirs.contains(&crate::options::DumpLIR::live_intervals) {
1626-
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1623+
// Dump live intervals if requested
1624+
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1625+
if dump_lirs.contains(&crate::options::DumpLIR::live_intervals) {
1626+
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1627+
}
16271628
}
1628-
}
16291629

1630-
let preferred_registers = asm.preferred_register_assignments(&intervals);
1631-
let (assignments, num_stack_slots) = trace_compile_phase("linear_scan", || asm.linear_scan(intervals.clone(), regs.len(), &preferred_registers));
1632-
(intervals, assignments, num_stack_slots)
1633-
});
1630+
let preferred_registers = trace_compile_phase("preferred_registers", || asm.preferred_register_assignments(&intervals));
1631+
let (assignments, num_stack_slots) = trace_compile_phase("linear_scan", || asm.linear_scan(intervals.clone(), regs.len(), &preferred_registers));
16341632

1635-
let total_stack_slots = asm.stack_base_idx + num_stack_slots;
1636-
if total_stack_slots > Self::MAX_FRAME_STACK_SLOTS {
1637-
return Err(CompileError::NativeStackTooLarge);
1638-
}
1633+
let total_stack_slots = asm.stack_base_idx + num_stack_slots;
1634+
if total_stack_slots > Self::MAX_FRAME_STACK_SLOTS {
1635+
return Err(CompileError::NativeStackTooLarge);
1636+
}
16391637

1640-
// Dump vreg-to-physical-register mapping if requested
1641-
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1642-
if dump_lirs.contains(&crate::options::DumpLIR::alloc_regs) {
1643-
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1644-
1645-
println!("VReg assignments:");
1646-
for (i, alloc) in assignments.iter().enumerate() {
1647-
if let Some(alloc) = alloc {
1648-
let range = &intervals[i].range;
1649-
let alloc_str = match alloc {
1650-
Allocation::Reg(n) => format!("{}", regs[*n]),
1651-
Allocation::Fixed(reg) => format!("{}", reg),
1652-
Allocation::Stack(n) => format!("Stack[{}]", n),
1653-
};
1654-
println!(" v{} => {} (range: {:?}..{:?})", i, alloc_str, range.start, range.end);
1638+
// Dump vreg-to-physical-register mapping if requested
1639+
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1640+
if dump_lirs.contains(&crate::options::DumpLIR::alloc_regs) {
1641+
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1642+
1643+
println!("VReg assignments:");
1644+
for (i, alloc) in assignments.iter().enumerate() {
1645+
if let Some(alloc) = alloc {
1646+
let range = &intervals[i].range;
1647+
let alloc_str = match alloc {
1648+
Allocation::Reg(n) => format!("{}", regs[*n]),
1649+
Allocation::Fixed(reg) => format!("{}", reg),
1650+
Allocation::Stack(n) => format!("Stack[{}]", n),
1651+
};
1652+
println!(" v{} => {} (range: {:?}..{:?})", i, alloc_str, range.start, range.end);
1653+
}
16551654
}
16561655
}
16571656
}
1658-
}
16591657

1660-
// Update FrameSetup slot_count to account for:
1661-
// 1) stack slots reserved for block params (stack_base_idx), and
1662-
// 2) register allocator spills (num_stack_slots).
1663-
for block in asm.basic_blocks.iter_mut() {
1664-
for insn in block.insns.iter_mut() {
1665-
if let Insn::FrameSetup { slot_count, .. } = insn {
1666-
*slot_count = total_stack_slots;
1658+
// Update FrameSetup slot_count to account for:
1659+
// 1) stack slots reserved for block params (stack_base_idx), and
1660+
// 2) register allocator spills (num_stack_slots).
1661+
trace_compile_phase("count_stack_slots", || {
1662+
for block in asm.basic_blocks.iter_mut() {
1663+
for insn in block.insns.iter_mut() {
1664+
if let Insn::FrameSetup { slot_count, .. } = insn {
1665+
*slot_count = total_stack_slots;
1666+
}
1667+
}
16671668
}
1668-
}
1669-
}
1669+
});
16701670

1671-
trace_compile_phase("resolve_ssa", || {
1672-
asm.handle_caller_saved_regs(&intervals, &assignments, &C_ARG_REGREGS);
1673-
asm.resolve_ssa(&intervals, &assignments);
1674-
});
1671+
trace_compile_phase("resolve_ssa", || {
1672+
asm.handle_caller_saved_regs(&intervals, &assignments, &C_ARG_REGREGS);
1673+
asm.resolve_ssa(&intervals, &assignments);
1674+
});
1675+
1676+
Ok(())
1677+
})?;
16751678
asm_dump!(asm, alloc_regs);
16761679

16771680
// We are moved out of SSA after resolve_ssa
@@ -1703,22 +1706,22 @@ impl Assembler {
17031706
}
17041707

17051708
trace_compile_phase("emit", || {
1706-
// Create label instances in the code block
1707-
for (idx, name) in asm.label_names.iter().enumerate() {
1708-
let label = cb.new_label(name.to_string());
1709-
assert_eq!(label, Label(idx));
1710-
}
1709+
// Create label instances in the code block
1710+
for (idx, name) in asm.label_names.iter().enumerate() {
1711+
let label = cb.new_label(name.to_string());
1712+
assert_eq!(label, Label(idx));
1713+
}
17111714

1712-
let start_ptr = cb.get_write_ptr();
1713-
let gc_offsets = asm.arm64_emit(cb).inspect_err(|_| cb.clear_labels())?;
1714-
assert!(!cb.has_dropped_bytes(), "emit should not drop bytes without error");
1715+
let start_ptr = cb.get_write_ptr();
1716+
let gc_offsets = asm.arm64_emit(cb).inspect_err(|_| cb.clear_labels())?;
1717+
assert!(!cb.has_dropped_bytes(), "emit should not drop bytes without error");
17151718

1716-
cb.link_labels().or(Err(CompileError::LabelLinkingFailure))?;
1719+
cb.link_labels().or(Err(CompileError::LabelLinkingFailure))?;
17171720

1718-
// Invalidate icache for newly written out region so we don't run stale code.
1719-
unsafe { rb_jit_icache_invalidate(start_ptr.raw_ptr(cb) as _, cb.get_write_ptr().raw_ptr(cb) as _) };
1721+
// Invalidate icache for newly written out region so we don't run stale code.
1722+
unsafe { rb_jit_icache_invalidate(start_ptr.raw_ptr(cb) as _, cb.get_write_ptr().raw_ptr(cb) as _) };
17201723

1721-
Ok((start_ptr, gc_offsets))
1724+
Ok((start_ptr, gc_offsets))
17221725
})
17231726
}
17241727
}

‎zjit/src/backend/x86_64/mod.rs‎

Lines changed: 56 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -1147,63 +1147,64 @@ impl Assembler {
11471147

11481148
asm_dump!(asm, split);
11491149

1150-
let (intervals, assignments, num_stack_slots) = trace_compile_phase("regalloc", || {
1151-
trace_compile_phase("number_instructions", || asm.number_instructions(0));
1150+
trace_compile_phase("regalloc", || {
1151+
trace_compile_phase("number_instructions", || asm.number_instructions(0));
11521152

1153-
let live_in = trace_compile_phase("analyze_liveness", || asm.analyze_liveness());
1154-
let intervals = trace_compile_phase("build_intervals", || asm.build_intervals(live_in));
1153+
let live_in = trace_compile_phase("analyze_liveness", || asm.analyze_liveness());
1154+
let intervals = trace_compile_phase("build_intervals", || asm.build_intervals(live_in));
11551155

1156-
// Dump live intervals if requested
1157-
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1158-
if dump_lirs.contains(&crate::options::DumpLIR::live_intervals) {
1159-
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1156+
// Dump live intervals if requested
1157+
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1158+
if dump_lirs.contains(&crate::options::DumpLIR::live_intervals) {
1159+
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1160+
}
11601161
}
1161-
}
11621162

1163-
let preferred_registers = asm.preferred_register_assignments(&intervals);
1164-
let (assignments, num_stack_slots) = trace_compile_phase("linear_scan", || asm.linear_scan(intervals.clone(), regs.len(), &preferred_registers));
1165-
(intervals, assignments, num_stack_slots)
1166-
});
1163+
let preferred_registers = trace_compile_phase("preferred_registers", || asm.preferred_register_assignments(&intervals));
1164+
let (assignments, num_stack_slots) = trace_compile_phase("linear_scan", || asm.linear_scan(intervals.clone(), regs.len(), &preferred_registers));
11671165

1168-
let total_stack_slots = asm.stack_base_idx + num_stack_slots;
1169-
if total_stack_slots > Self::MAX_FRAME_STACK_SLOTS {
1170-
return Err(CompileError::NativeStackTooLarge);
1171-
}
1166+
let total_stack_slots = asm.stack_base_idx + num_stack_slots;
1167+
if total_stack_slots > Self::MAX_FRAME_STACK_SLOTS {
1168+
return Err(CompileError::NativeStackTooLarge);
1169+
}
11721170

1173-
// Dump vreg-to-physical-register mapping if requested
1174-
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1175-
if dump_lirs.contains(&crate::options::DumpLIR::alloc_regs) {
1176-
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1177-
1178-
println!("VReg assignments:");
1179-
for (i, alloc) in assignments.iter().enumerate() {
1180-
if let Some(alloc) = alloc {
1181-
let range = &intervals[i].range;
1182-
let alloc_str = match alloc {
1183-
Allocation::Reg(n) => format!("{}", regs[*n]),
1184-
Allocation::Fixed(reg) => format!("{}", reg),
1185-
Allocation::Stack(n) => format!("Stack[{}]", n),
1186-
};
1187-
println!(" v{} => {} (range: {:?}..{:?})", i, alloc_str, range.start, range.end);
1171+
// Dump vreg-to-physical-register mapping if requested
1172+
if let Some(crate::options::Options { dump_lir: Some(dump_lirs), .. }) = unsafe { crate::options::OPTIONS.as_ref() } {
1173+
if dump_lirs.contains(&crate::options::DumpLIR::alloc_regs) {
1174+
println!("LIR live_intervals:\n{}", crate::backend::lir::debug_intervals(&asm, &intervals));
1175+
1176+
println!("VReg assignments:");
1177+
for (i, alloc) in assignments.iter().enumerate() {
1178+
if let Some(alloc) = alloc {
1179+
let range = &intervals[i].range;
1180+
let alloc_str = match alloc {
1181+
Allocation::Reg(n) => format!("{}", regs[*n]),
1182+
Allocation::Fixed(reg) => format!("{}", reg),
1183+
Allocation::Stack(n) => format!("Stack[{}]", n),
1184+
};
1185+
println!(" v{} => {} (range: {:?}..{:?})", i, alloc_str, range.start, range.end);
1186+
}
11881187
}
11891188
}
11901189
}
1191-
}
11921190

1193-
// Update FrameSetup slot_count to account for:
1194-
// 1) stack slots reserved for block params (stack_base_idx), and
1195-
// 2) register allocator spills (num_stack_slots).
1196-
for block in asm.basic_blocks.iter_mut() {
1197-
for insn in block.insns.iter_mut() {
1198-
if let Insn::FrameSetup { slot_count, .. } = insn {
1199-
*slot_count = total_stack_slots;
1191+
// Update FrameSetup slot_count to account for:
1192+
// 1) stack slots reserved for block params (stack_base_idx), and
1193+
// 2) register allocator spills (num_stack_slots).
1194+
trace_compile_phase("count_stack_slots", || {
1195+
for block in asm.basic_blocks.iter_mut() {
1196+
for insn in block.insns.iter_mut() {
1197+
if let Insn::FrameSetup { slot_count, .. } = insn {
1198+
*slot_count = total_stack_slots;
1199+
}
1200+
}
12001201
}
1201-
}
1202-
}
1202+
});
12031203

1204-
trace_compile_phase("resolve_ssa", || {
1205-
asm.handle_caller_saved_regs(&intervals, &assignments, &C_ARG_REGREGS);
1206-
asm.resolve_ssa(&intervals, &assignments);
1204+
trace_compile_phase("resolve_ssa", || {
1205+
asm.handle_caller_saved_regs(&intervals, &assignments, &C_ARG_REGREGS);
1206+
asm.resolve_ssa(&intervals, &assignments);
1207+
});
12071208
});
12081209
asm_dump!(asm, alloc_regs);
12091210

@@ -1236,18 +1237,18 @@ impl Assembler {
12361237
}
12371238

12381239
trace_compile_phase("emit", || {
1239-
// Create label instances in the code block
1240-
for (idx, name) in asm.label_names.iter().enumerate() {
1241-
let label = cb.new_label(name.to_string());
1242-
assert_eq!(label, Label(idx));
1243-
}
1240+
// Create label instances in the code block
1241+
for (idx, name) in asm.label_names.iter().enumerate() {
1242+
let label = cb.new_label(name.to_string());
1243+
assert_eq!(label, Label(idx));
1244+
}
12441245

1245-
let start_ptr = cb.get_write_ptr();
1246-
let gc_offsets = asm.x86_emit(cb).inspect_err(|_| cb.clear_labels())?;
1247-
assert!(!cb.has_dropped_bytes(), "emit should not drop bytes without error");
1246+
let start_ptr = cb.get_write_ptr();
1247+
let gc_offsets = asm.x86_emit(cb).inspect_err(|_| cb.clear_labels())?;
1248+
assert!(!cb.has_dropped_bytes(), "emit should not drop bytes without error");
12481249

1249-
cb.link_labels().or(Err(CompileError::LabelLinkingFailure))?;
1250-
Ok((start_ptr, gc_offsets))
1250+
cb.link_labels().or(Err(CompileError::LabelLinkingFailure))?;
1251+
Ok((start_ptr, gc_offsets))
12511252
})
12521253
}
12531254
}

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