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MIPS: loongson64: add IRQ work based on self-IPI
Since the commit 91840be ("irq_work: Fix use-after-free in irq_work_single() on PREEMPT_RT"), we observed the performance of execve() is significantly impacted on MIPS. While we are unsure how that commit caused the impact or how to improve it (or even if it can be improved at all), implementing IRQ work with self-IPI seems able to mitigate the impaction. Perhaps this can/should be implemented for other MIPS architecture processors as well, but we don't have the enough knowledge of them, nor access to the hardware. So only implement it for loongson64 here. Link: https://lore.kernel.org/6be1cdd5f91dd7418a32ff372a6f3ae259b19195.camel@xry111.site/ Signed-off-by: Xi Ruoyao <xry111@xry111.site> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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arch/mips/include/asm/irq_work.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_MIPS_IRQ_WORK_H
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#define _ASM_MIPS_IRQ_WORK_H
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static inline bool arch_irq_work_has_interrupt(void)
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{
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return IS_ENABLED(CONFIG_MACH_LOONGSON64) && IS_ENABLED(CONFIG_SMP);
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}
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#endif /* _ASM_MIPS_IRQ_WORK_H */

arch/mips/include/asm/smp.h

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@@ -50,6 +50,8 @@ extern int __cpu_logical_map[NR_CPUS];
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#define SMP_CALL_FUNCTION 0x2
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/* Octeon - Tell another core to flush its icache */
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#define SMP_ICACHE_FLUSH 0x4
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/* Loongson64 - Self IPI for IRQ work */
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#define SMP_IRQ_WORK 0x8
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/* Mask of CPUs which are currently definitely operating coherently */
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extern cpumask_t cpu_coherent_mask;

arch/mips/loongson64/smp.c

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@@ -381,6 +381,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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ipi_write_action(cpu_logical_map(i), (u32)action);
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}
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#ifdef CONFIG_IRQ_WORK
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void arch_irq_work_raise(void)
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{
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loongson3_send_ipi_single(smp_processor_id(), SMP_IRQ_WORK);
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}
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#endif
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static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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irq_exit();
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}
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if (action & SMP_IRQ_WORK)
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irq_work_run();
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return IRQ_HANDLED;
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}
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