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Merge tag 'drm-fixes-2026-05-02' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Fixes for rc2, the usual amdgpu/xe double header, I think xe had a couple of weeks combined due to some maintainer access issues, otherwise there's just a few misc fixes and documentation fixups. core and helpers: - calculate framebuffer geometry with format helpers - fix docs amdgpu: - GFX12 fix for CONFIG_DRM_DEBUG_MM configs - Fix DC analog support - Userq fixes - GART placement fix - Aldebaran SMU fixes - AMDGPU_INFO_READ_MMR_REG fix - UVD 3.1 fix - GC 6 TCC fix - Fix root reservation in amdgpu_vm_handle_fault() - RAS fix - Module reload fix for APUs - Fix build for CONFIG_DRM_FBDEV_EMULATION=n - IGT DWB regression fix - GC 11.5.4 fix - VCN user fence fixes - JPEG user fence fixes - SMU 13.0.6 fix - VCN 3/4 IB parser fixes - NV3x+ dGPU vblank fix - DCE6/8 fixes for LVDS/eDP panels without an EDID amdkfd: - Fix for when CONFIG_HSA_AMD is not set - SVM fixes xe: - uapi: Add missing pad and extensions check - uapi: Reject unsafe PAT indices for CPU cached memory - Drop registration of guc_submit_wedged_fini from xe_guc_submit_wedge - Xe3p tuning and workaround fixes - USE drm mm instead of drm SA for CCS read/write - Fix leaks and null derefs - Fix Wa_18022495364 appletbdrm: - allocate protocol buffers with kvzalloc() dma-buf: - fix docs imagination: - avoid segfault in debugfs ofdrm: - put PCI device reference on errors udl: - increase USB timeout" * tag 'drm-fixes-2026-05-02' of https://gitlab.freedesktop.org/drm/kernel: (77 commits) drm/xe/uapi: Reject coh_none PAT index for CPU_ADDR_MIRROR drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise drm/xe/xelp: Fix Wa_18022495364 drm/xe/gsc: Fix BO leak on error in query_compatibility_version() drm/xe/eustall: Fix drm_dev_put called before stream disable in close drm/xe: Fix error cleanup in xe_exec_queue_create_ioctl() drm/xe: Fix dma-buf attachment leak in xe_gem_prime_import() drm/xe: Fix bo leak in xe_dma_buf_init_obj() on allocation failure drm/xe/bo: Fix bo leak on GGTT flag validation in xe_bo_init_locked() drm/xe/bo: Fix bo leak on unaligned size validation in xe_bo_init_locked() drm/xe: Fix potential NULL deref in xe_exec_queue_tlb_inval_last_fence_put_unlocked drm/xe/vf: Use drm mm instead of drm sa for CCS read/write drm/xe: Add memory pool with shadow support drm/xe/debugfs: Correct printing of register whitelist ranges drm/xe: Mark ROW_CHICKEN5 as a masked register drm/xe/tuning: Use proper register offset for GAMSTLB_CTRL drm/xe/xe3p_lpg: Add missing indirect ring state feature flag drm/xe: Drop redundant rtp entries for Wa_14019988906 & Wa_14019877138 drm/xe/vm: Add missing pad and extensions check drm/xe: Drop registration of guc_submit_wedged_fini from xe_guc_submit_wedge() ...
2 parents cd546f7 + f0997a0 commit f1a5e78

88 files changed

Lines changed: 1085 additions & 269 deletions

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‎.mailmap‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ Abhinav Kumar <quic_abhinavk@quicinc.com> <abhinavk@codeaurora.org>
1919
Ahmad Masri <quic_amasri@quicinc.com> <amasri@codeaurora.org>
2020
Adam Oldham <oldhamca@gmail.com>
2121
Adam Radford <aradford@gmail.com>
22+
Aditya Garg <gargaditya08@proton.me> <gargaditya08@live.com>
2223
Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
2324
Adrian Bunk <bunk@stusta.de>
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Ajay Kaher <ajay.kaher@broadcom.com> <akaher@vmware.com>

‎MAINTAINERS‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7873,7 +7873,7 @@ F: drivers/gpu/drm/sun4i/sun8i*
78737873

78747874
DRM DRIVER FOR APPLE TOUCH BARS
78757875
M: Aun-Ali Zaidi <admin@kodeit.net>
7876-
M: Aditya Garg <gargaditya08@live.com>
7876+
M: Aditya Garg <gargaditya08@proton.me>
78777877
L: dri-devel@lists.freedesktop.org
78787878
S: Maintained
78797879
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2839,8 +2839,12 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
28392839
* that checks whether the PSP is running. A solution for those issues
28402840
* in the APU is to trigger a GPU reset, but this should be done during
28412841
* the unload phase to avoid adding boot latency and screen flicker.
2842+
* GFX V11 has GC block as default off IP. Every time AMDGPU driver sends
2843+
* a request to PMFW to unload MP1, PMFW will put GC in reset and power down
2844+
* the voltage. Hence, skipping reset for APUs with GFX V11 or later.
28422845
*/
2843-
if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu) {
2846+
if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu &&
2847+
amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 0, 0)) {
28442848
r = amdgpu_asic_reset(adev);
28452849
if (r)
28462850
dev_err(adev->dev, "asic reset on %s failed\n", __func__);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3090,10 +3090,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
30903090
case IP_VERSION(11, 5, 1):
30913091
case IP_VERSION(11, 5, 2):
30923092
case IP_VERSION(11, 5, 3):
3093-
adev->family = AMDGPU_FAMILY_GC_11_5_0;
3094-
break;
30953093
case IP_VERSION(11, 5, 4):
3096-
adev->family = AMDGPU_FAMILY_GC_11_5_4;
3094+
adev->family = AMDGPU_FAMILY_GC_11_5_0;
30973095
break;
30983096
case IP_VERSION(12, 0, 0):
30993097
case IP_VERSION(12, 0, 1):

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3158,8 +3158,10 @@ static int __init amdgpu_init(void)
31583158
amdgpu_register_atpx_handler();
31593159
amdgpu_acpi_detect();
31603160

3161-
/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
3162-
amdgpu_amdkfd_init();
3161+
/* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */
3162+
r = amdgpu_amdkfd_init();
3163+
if (r && r != -ENOENT)
3164+
goto error_fence;
31633165

31643166
if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {
31653167
add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -314,7 +314,10 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
314314
mc->gart_start = max_mc_address - mc->gart_size + 1;
315315
break;
316316
case AMDGPU_GART_PLACEMENT_LOW:
317-
mc->gart_start = 0;
317+
if (size_bf >= mc->gart_size)
318+
mc->gart_start = 0;
319+
else
320+
mc->gart_start = ALIGN(mc->fb_end, four_gb);
318321
break;
319322
case AMDGPU_GART_PLACEMENT_BEST_FIT:
320323
default:

‎drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c‎

Lines changed: 24 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -873,68 +873,59 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
873873
? -EFAULT : 0;
874874
}
875875
case AMDGPU_INFO_READ_MMR_REG: {
876-
int ret = 0;
877-
unsigned int n, alloc_size;
878-
uint32_t *regs;
879876
unsigned int se_num = (info->read_mmr_reg.instance >>
880877
AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
881878
AMDGPU_INFO_MMR_SE_INDEX_MASK;
882879
unsigned int sh_num = (info->read_mmr_reg.instance >>
883880
AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
884881
AMDGPU_INFO_MMR_SH_INDEX_MASK;
885-
886-
if (!down_read_trylock(&adev->reset_domain->sem))
887-
return -ENOENT;
882+
unsigned int alloc_size;
883+
uint32_t *regs;
884+
int ret;
888885

889886
/* set full masks if the userspace set all bits
890887
* in the bitfields
891888
*/
892-
if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {
889+
if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
893890
se_num = 0xffffffff;
894-
} else if (se_num >= AMDGPU_GFX_MAX_SE) {
895-
ret = -EINVAL;
896-
goto out;
897-
}
891+
else if (se_num >= AMDGPU_GFX_MAX_SE)
892+
return -EINVAL;
898893

899-
if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {
894+
if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
900895
sh_num = 0xffffffff;
901-
} else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {
902-
ret = -EINVAL;
903-
goto out;
904-
}
896+
else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
897+
return -EINVAL;
905898

906-
if (info->read_mmr_reg.count > 128) {
907-
ret = -EINVAL;
908-
goto out;
909-
}
899+
if (info->read_mmr_reg.count > 128)
900+
return -EINVAL;
910901

911-
regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
912-
if (!regs) {
913-
ret = -ENOMEM;
914-
goto out;
915-
}
902+
regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs),
903+
GFP_KERNEL);
904+
if (!regs)
905+
return -ENOMEM;
916906

907+
down_read(&adev->reset_domain->sem);
917908
alloc_size = info->read_mmr_reg.count * sizeof(*regs);
918-
919909
amdgpu_gfx_off_ctrl(adev, false);
910+
ret = 0;
920911
for (i = 0; i < info->read_mmr_reg.count; i++) {
921912
if (amdgpu_asic_read_register(adev, se_num, sh_num,
922913
info->read_mmr_reg.dword_offset + i,
923914
&regs[i])) {
924915
DRM_DEBUG_KMS("unallowed offset %#x\n",
925916
info->read_mmr_reg.dword_offset + i);
926-
kfree(regs);
927-
amdgpu_gfx_off_ctrl(adev, true);
928917
ret = -EFAULT;
929-
goto out;
918+
break;
930919
}
931920
}
932921
amdgpu_gfx_off_ctrl(adev, true);
933-
n = copy_to_user(out, regs, min(size, alloc_size));
934-
kfree(regs);
935-
ret = (n ? -EFAULT : 0);
936-
out:
937922
up_read(&adev->reset_domain->sem);
923+
924+
if (!ret) {
925+
ret = copy_to_user(out, regs, min(size, alloc_size))
926+
? -EFAULT : 0;
927+
}
928+
kfree(regs);
938929
return ret;
939930
}
940931
case AMDGPU_INFO_DEV_INFO: {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1950,7 +1950,7 @@ void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev)
19501950
if (!control || amdgpu_bad_page_threshold == 0)
19511951
return;
19521952

1953-
if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) {
1953+
if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) {
19541954
if (amdgpu_dpm_send_rma_reason(adev))
19551955
dev_warn(adev->dev, "Unable to send out-of-band RMA CPER");
19561956
else

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,9 @@ static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
7575
unsigned int type,
7676
uint64_t size_in_page)
7777
{
78+
if (!size_in_page)
79+
return 0;
80+
7881
return ttm_range_man_init(&adev->mman.bdev, type,
7982
false, size_in_page);
8083
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,19 @@ void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue)
205205
msecs_to_jiffies(timeout_ms));
206206
}
207207

208+
void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell)
209+
{
210+
struct xarray *xa = &adev->userq_doorbell_xa;
211+
struct amdgpu_usermode_queue *queue;
212+
unsigned long flags;
213+
214+
xa_lock_irqsave(xa, flags);
215+
queue = xa_load(xa, doorbell);
216+
if (queue)
217+
amdgpu_userq_fence_driver_process(queue->fence_drv);
218+
xa_unlock_irqrestore(xa, flags);
219+
}
220+
208221
static void amdgpu_userq_init_hang_detect_work(struct amdgpu_usermode_queue *queue)
209222
{
210223
INIT_DELAYED_WORK(&queue->hang_detect_work, amdgpu_userq_hang_detect_work);
@@ -643,12 +656,6 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que
643656
#endif
644657
amdgpu_userq_detect_and_reset_queues(uq_mgr);
645658
r = amdgpu_userq_unmap_helper(queue);
646-
/*TODO: It requires a reset for userq hw unmap error*/
647-
if (r) {
648-
drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n");
649-
queue->state = AMDGPU_USERQ_STATE_HUNG;
650-
}
651-
652659
atomic_dec(&uq_mgr->userq_count[queue->queue_type]);
653660
amdgpu_userq_cleanup(queue);
654661
mutex_unlock(&uq_mgr->userq_mutex);
@@ -1187,7 +1194,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr)
11871194
bo = range->bo;
11881195
ret = amdgpu_ttm_tt_get_user_pages(bo, range);
11891196
if (ret)
1190-
goto unlock_all;
1197+
goto free_ranges;
11911198
}
11921199

11931200
invalidated = true;
@@ -1214,6 +1221,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr)
12141221

12151222
unlock_all:
12161223
drm_exec_fini(&exec);
1224+
free_ranges:
12171225
xa_for_each(&xa, tmp_key, range) {
12181226
if (!range)
12191227
continue;

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