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sneha-voonaDINESHKUMARK1
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DINESHKUMARK1
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platform: add ACP_7_X platform support for native Zephyr
Add ACP_7_X platform support for native Zephyr drivers. Changes include: - Add platform-specific files for ACP_7_X native Zephyr support - Add ACP_7_X in zephyr/CMakeLists.txt with platform sources, include directories and PLATFORM variable - Add app/boards/acp_7_x_adsp.conf with ACP_7_X Kconfig options for native Zephyr drivers (DMA, DAI, interrupts) Signed-off-by: Sneha Voona <sneha.voona@amd.com> Co-authored-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
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‎app/boards/acp_7_x_adsp.conf‎

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CONFIG_ACP_7_X=y
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CONFIG_HAVE_AGENT=n
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CONFIG_DCACHE_LINE_SIZE_DETECT=n
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CONFIG_DCACHE_LINE_SIZE=128
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CONFIG_DYNAMIC_INTERRUPTS=y
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CONFIG_SHARED_INTERRUPTS=n
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CONFIG_ZEPHYR_LOG=y
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CONFIG_LOG_MODE_DEFERRED=n
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CONFIG_LOG_MODE_MINIMAL=y
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CONFIG_DMA=y
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CONFIG_DMA_DOMAIN=n
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CONFIG_ZEPHYR_NATIVE_DRIVERS=y
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CONFIG_INTC_AMD_ACP=y
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CONFIG_DMA_AMD_ACP_HOST=y
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CONFIG_DMA_AMD_ACP_SDW=y
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CONFIG_DAI_AMD_SDW=y
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CONFIG_AMS=n
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CONFIG_WRAP_ACTUAL_POSITION=y
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CONFIG_TRACE=n
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CONFIG_COMP_VOLUME=y
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CONFIG_COMP_SRC=n
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CONFIG_COMP_FIR=n
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CONFIG_COMP_IIR=n
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CONFIG_COMP_DCBLOCK=n
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CONFIG_COMP_CROSSOVER=n
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CONFIG_COMP_DRC=n
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CONFIG_COMP_MULTIBAND_DRC=n
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CONFIG_COMP_TONE=n
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CONFIG_COMP_KPB=n
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CONFIG_MAXIM_DSM=n
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CONFIG_COMP_ASRC=n
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CONFIG_COMP_IGO_NR=n
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CONFIG_COMP_COPIER=n
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CONFIG_COMP_RTNR=n
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CONFIG_COMP_ARIA=n
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CONFIG_COMP_BASEFW_IPC4=n
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CONFIG_COMP_UP_DOWN_MIXER=n
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CONFIG_COMP_TDFB=n
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CONFIG_COMP_SEL=n
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CONFIG_COMP_MIXER=n
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CONFIG_ASRC_SUPPORT_CONVERSION_24000_TO_08000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_24000_TO_16000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_08000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_11025=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_12000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_16000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_22050=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_24000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_32000=n
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CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_44100=n
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CONFIG_CORE_COUNT=1
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CONFIG_FORMAT_CONVERT_HIFI3=n

‎src/drivers/amd/acp_7_x/CMakeLists.txt‎

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# SPDX-License-Identifier: BSD-3-Clause
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add_local_sources(sof
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ipc.c
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)

‎src/drivers/amd/acp_7_x/ipc.c‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2026 AMD. All rights reserved.
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*
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* Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
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* Sneha Voona <sneha.voona@amd.com>
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* DineshKumar Kalva <DineshKumar.Kalva@amd.com>
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*/
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#include <rtos/panic.h>
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#include <rtos/interrupt.h>
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#include <sof/ipc/driver.h>
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#include <sof/ipc/msg.h>
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#include <sof/ipc/schedule.h>
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#include <rtos/alloc.h>
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#include <sof/lib/dma.h>
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#include <sof/lib/mailbox.h>
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#include <sof/lib/memory.h>
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#include <sof/lib/uuid.h>
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#include <rtos/wait.h>
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#include <sof/list.h>
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#include <sof/platform.h>
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#include <sof/schedule/edf_schedule.h>
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#include <sof/schedule/schedule.h>
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#include <rtos/task.h>
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#include <rtos/spinlock.h>
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#include <ipc/header.h>
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#include <ipc/topology.h>
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#include <errno.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <platform/platform.h>
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#include <platform/ipc.h>
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#include <zephyr/logging/log.h>
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volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
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(volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE +
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SCRATCH_REG_OFFSET);
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SOF_DEFINE_REG_UUID(ipc_task_amd);
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LOG_MODULE_REGISTER(ipc_handler_file, LOG_LEVEL_DBG);
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#define HOST_TO_DSP_INTR 1
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#define INTERRUPT_DISABLE 0
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#define IRQ_NUM_EXT_LEVEL3 3
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#define IRQ_EXT_IPC_LEVEL_3 3
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/* This function triggers a host interrupt from ACP DSP */
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void acp_dsp_to_host_intr_trig(void)
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{
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acp_sw_intr_trig_t sw_intr_trig;
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/* Read the Software Interrupt controller register and update */
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sw_intr_trig = (acp_sw_intr_trig_t) io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
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/* Write the Software Interrupt controller register */
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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}
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/* Clear the Acknowledge ( status) for the host to DSP interrupt */
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static void acp_ack_intr_from_host(void)
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{
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/* acknowledge the host interrupt */
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acp_dsp_sw_intr_stat_t sw_intr_stat;
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sw_intr_stat.u32all = 0;
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sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all);
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}
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inline uint32_t sof_ipc_host_status(void)
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{
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return (pscratch_mem_cfg->acp_host_ack_write | pscratch_mem_cfg->acp_host_msg_write);
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}
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inline uint32_t sof_ipc_host_msg_flag(void)
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{
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return pscratch_mem_cfg->acp_host_msg_write;
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}
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inline uint32_t sof_ipc_host_ack_flag(void)
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{
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return pscratch_mem_cfg->acp_host_ack_write;
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}
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inline uint32_t sof_ipc_dsp_status(void)
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{
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return (pscratch_mem_cfg->acp_dsp_msg_write | pscratch_mem_cfg->acp_dsp_ack_write);
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}
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inline void sof_ipc_host_ack_clear(void)
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{
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pscratch_mem_cfg->acp_host_ack_write = 0;
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}
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inline void sof_ipc_host_msg_clear(void)
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{
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pscratch_mem_cfg->acp_host_msg_write = 0;
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}
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inline void sof_ipc_dsp_ack_set(void)
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{
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pscratch_mem_cfg->acp_dsp_ack_write = 1;
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}
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inline void sof_ipc_dsp_msg_set(void)
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{
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pscratch_mem_cfg->acp_dsp_msg_write = 1;
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}
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enum task_state ipc_platform_do_cmd(struct ipc *ipc)
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{
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struct ipc_cmd_hdr *hdr;
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hdr = mailbox_validate();
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ipc_cmd(hdr);
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return SOF_TASK_STATE_COMPLETED;
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}
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int platform_ipc_init(struct ipc *ipc)
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{
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ipc_set_drvdata(ipc, NULL);
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/* schedule */
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schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_amd_uuid),
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&ipc_task_ops, ipc, 0, 0);
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interrupt_disable(IRQ_EXT_IPC_LEVEL_3, ipc);
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interrupt_unregister(IRQ_EXT_IPC_LEVEL_3, ipc);
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interrupt_register(IRQ_EXT_IPC_LEVEL_3, amd_irq_handler, ipc);
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/* Enabling software interuppts */
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interrupt_enable(IRQ_EXT_IPC_LEVEL_3, ipc);
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return 0;
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}
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void amd_irq_handler(void *arg)
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{
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struct ipc *ipc = arg;
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uint32_t status;
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uint32_t lock;
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acp_dsp_sw_intr_stat_t swintrstat;
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acp_sw_intr_trig_t swintrtrig;
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swintrstat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
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status = swintrstat.u32all & HOST_TO_DSP_INTR;
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if (status) {
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/* Interrupt source */
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lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
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/* Removed unbounded while(lock) loop - using bounded loop below instead */
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int timeout = 20000;
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while (lock && --timeout > 0) {
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lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
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}
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if (timeout == 0) {
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/* Give up, don't block forever */
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LOG_ERR("ACP semaphore timeout in IRQ handler");
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return;
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}
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/***************************************************** */
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/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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swintrtrig = (acp_sw_intr_trig_t)
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io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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swintrtrig.bits.trig_host_to_dsp0_intr1 = INTERRUPT_DISABLE;
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swintrtrig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG),
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swintrtrig.u32all);
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/* Clear the Host to DSP Status Register */
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acp_ack_intr_from_host();
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/********************************************* */
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if (sof_ipc_host_status()) {
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if (sof_ipc_host_ack_flag()) {
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/* Clear the ACK from host */
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sof_ipc_host_ack_clear();
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}
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/* Check if new message from host */
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if (sof_ipc_host_msg_flag()) {
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/* Clear the msg bit from host*/
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sof_ipc_host_msg_clear();
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ipc_schedule_process(ipc);
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}
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} else {
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tr_err(&ipc_tr, "IPC:interrupt without setting flags host status 0x%x", sof_ipc_host_status());
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io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), 0);
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}
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}
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}
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void ipc_platform_complete_cmd(struct ipc *ipc)
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{
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acp_sw_intr_trig_t sw_intr_trig;
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/* Set Dsp Ack for msg from host */
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sof_ipc_dsp_ack_set();
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/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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sw_intr_trig = (acp_sw_intr_trig_t)
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io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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sw_intr_trig.bits.trig_host_to_dsp0_intr1 = INTERRUPT_DISABLE;
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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/* now interrupt host to tell it we have sent a message */
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acp_dsp_to_host_intr_trig();
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/* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), 0);
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LOG_DBG("IPC cmd completed");
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if (ipc->pm_prepare_D3) {
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while (1) {
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wait_for_interrupt(0);
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}
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}
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}
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int ipc_platform_send_msg(const struct ipc_msg *msg)
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{
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int ret = 0;
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acp_sw_intr_trig_t sw_intr_trig;
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acp_dsp_sw_intr_stat_t sw_intr_stat;
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uint32_t status;
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uint32_t lock;
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/* Check if host cleared the status for previous messages */
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sw_intr_stat = (acp_dsp_sw_intr_stat_t)
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io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT);
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status = sw_intr_stat.bits.dsp0_to_host_intr_stat;
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if (sof_ipc_dsp_status() || status) {
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return -EBUSY;
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}
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lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
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int timeout = 20000;
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while (lock && --timeout > 0) {
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lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0);
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}
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if (timeout == 0) {
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/* Give up, don't block forever */
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LOG_ERR("ACP semaphore timeout in IPC send");
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return -EBUSY;
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}
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/* Write new message in the mailbox */
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mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
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/* Need to set DSP message flag */
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sof_ipc_dsp_msg_set();
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/* Trigger host interrupt to notify new message from DSP */
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/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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sw_intr_trig = (acp_sw_intr_trig_t)
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io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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sw_intr_trig.bits.trig_host_to_dsp0_intr1 = INTERRUPT_DISABLE;
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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acp_dsp_to_host_intr_trig();
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/* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), lock);
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return ret;
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}
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void ipc_platform_send_msg_direct(const struct ipc_msg *msg)
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{
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acp_sw_intr_trig_t sw_intr_trig;
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/* Write message directly to mailbox - no status checks for emergency */
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mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
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/* Set DSP message flag */
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sof_ipc_dsp_msg_set();
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/* Interrupt host immediately */
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acp_dsp_to_host_intr_trig();
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/* Disable the trigger bit */
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sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE;
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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}

‎src/platform/amd/acp_7_x/CMakeLists.txt‎

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# SPDX-License-Identifier: BSD-3-Clause
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add_subdirectory(lib)
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add_local_sources(sof platform.c)

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