ipc4: assert IPC4 pipeline triggering logic

With IPC4, each pipeline is triggered separately. Exactly 1 pipeline is
expected in the pipelines list in pipeline_schedule_triggered().
Unfortunately, we still have considerable complex IPC3 pipeline triggering
code being used with IPC4. This assertion ensures that the code works
correctly for the IPC4 case.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>

Author: serhiy-katsyuba-intel

src/audio/pipeline/pipeline-schedule.c

@@ -284,6 +284,16 @@ void pipeline_schedule_triggered(struct pipeline_walk_context *ctx,
 	struct pipeline *p;
 	uint32_t flags;
 
+#ifdef CONFIG_IPC_MAJOR_4
+	/*
+	 * With IPC4, each pipeline is triggered separately. Exactly 1 pipeline
+	 * is expected in the pipelines list (it's unclear whether an empty list
+	 * should be tolerated).
+	 */
+	assert(list_is_empty(&ctx->pipelines) ||
+	       list_item_is_last(ctx->pipelines.next, &ctx->pipelines));
+#endif
+
 	/*
 	 * Interrupts have to be disabled while adding tasks to or removing them
 	 * from the scheduler list. Without that scheduling can begin