dai: acp_7_x: add SDW DMA and DAI support for ACP_7_X

Add ACP_7_X SDW DMA channel support in zephyr/lib/dma.c for native
Zephyr DMA operations.

Update dai.c to set dai_index from dd->dai->index for AMD SDW DAI,
add ACP_7_X SDW instance handling with per-instance pin index array,
and free DAI-specific data on DMA release for AMD.

Signed-off-by: Sneha Voona <sneha.voona@amd.com>

Author: sneha-voona

src/ipc/ipc3/dai.c

@@ -29,6 +29,8 @@
 
 LOG_MODULE_DECLARE(ipc, CONFIG_SOF_LOG_LEVEL);
 
+#define DAI_INDEX_INVALID	0xFFFF
+
 void dai_set_link_hda_config(uint16_t *link_config,
 			    struct ipc_config_dai *common_config,
 			    const void *spec_config)
@@ -93,7 +95,10 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void
 		break;
 	case SOF_DAI_AMD_HS:
 	case SOF_DAI_AMD_HS_VIRTUAL:
-	case SOF_DAI_AMD_SDW:
+	case SOF_DAI_AMD_SDW: {
+		struct dai_config *params = (struct dai_config *)dd->dai->dev->config;
+
+		params->dai_index = dd->dai->index;
 		channel = dai_get_handshake(dd->dai, dai->direction,
 					    dd->stream_id);
 #if defined(CONFIG_SOC_ACP_7_0)
@@ -102,6 +107,7 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void
 		}
 #endif
 		break;
+	}
 	case SOF_DAI_MEDIATEK_AFE:
 		handshake = dai_get_handshake(dd->dai, dai->direction,
 					      dd->stream_id);
@@ -210,12 +216,18 @@ int ipc_dai_data_config(struct dai_data *dd, struct comp_dev *dev)
 		pin_data->pin_num = dd->dai->index;
 		pin_data->pin_dir = dai->direction;
 #ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
-		pin_data->dma_channel = dd->chan_index >= 0 ? dd->chan_index : 0xFFFF;
+		pin_data->dma_channel = dd->chan_index >= 0 ? dd->chan_index : DAI_INDEX_INVALID;
+#else
+		pin_data->dma_channel = dd->chan ? dd->chan->index : DAI_INDEX_INVALID;
+#endif
+#if defined(CONFIG_SOC_ACP_7_X)
+		for (int i = 0; i < SDW_INSTANCES; i++) {
+			pin_data->index[i] = DAI_INDEX_INVALID;
+		}
 #else
-		pin_data->dma_channel = dd->chan ? dd->chan->index : 0xFFFF;
+			pin_data->index = DAI_INDEX_INVALID;
 #endif
-		pin_data->index = 0xFFFF;
-		pin_data->instance = 0xFFFF;
+		pin_data->instance = DAI_INDEX_INVALID;
 		dev_data->dai_index_ptr = pin_data;
 	}
 #endif
@@ -314,6 +326,18 @@ void dai_dma_release(struct dai_data *dd, struct comp_dev *dev)
 		return;
 	}
 
+#if defined(CONFIG_AMD)
+	/* Free DAI-specific data allocated in ipc_dai_data_config() */
+	if (dd->dma && dd->dma->z_dev && dd->dma->z_dev->data) {
+		struct acp_dma_dev_data *dev_data = dd->dma->z_dev->data;
+
+		if (dev_data->dai_index_ptr) {
+			rfree(dev_data->dai_index_ptr);
+			dev_data->dai_index_ptr = NULL;
+		}
+	}
+#endif
+
 	/* put the allocated DMA channel first */
 #ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 	if (dd->chan_index >= 0) {

zephyr/lib/dma.c

@@ -212,7 +212,7 @@ SHARED_DATA struct sof_dma dma[] = {
 	.z_dev = DEVICE_DT_GET(DT_NODELABEL(host_dma)),
 },
 #endif /* CONFIG_SOC_MIMX9596_M7 */
-#if defined(CONFIG_SOC_ACP_7_0)
+#if defined(CONFIG_SOC_ACP_7_0) || defined(CONFIG_SOC_ACP_7_X)
 {
 	.plat_data = {
 		.dir		= SOF_DMA_DIR_LMEM_TO_HMEM |
@@ -233,7 +233,7 @@ SHARED_DATA struct sof_dma dma[] = {
 		.caps		= SOF_DMA_CAP_SW,
 		.base		= DMA0_BASE,
 		.chan_size	= DMA0_SIZE,
-		.channels	= 12,
+		.channels	= DT_PROP(DT_NODELABEL(acp_sdw_dma), dma_channels),
 		.period_count	= 2,
 	},
 	.z_dev = DEVICE_DT_GET(DT_NODELABEL(acp_sdw_dma)),