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ipc4: harden IPC4 pipeline triggering logic #10893

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Merged
kv2019i merged 2 commits into from
Jun 15, 2026
+14 −4
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ipc4: harden IPC4 pipeline triggering logic #10893

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ipc4: harden IPC4 pipeline triggering logic
serhiy-katsyuba-intel Jun 10, 2026
66e41b0
ipc4: assert IPC4 pipeline triggering logic
serhiy-katsyuba-intel Jun 10, 2026
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10 changes: 10 additions & 0 deletions src/audio/pipeline/pipeline-schedule.c
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Original file line number Diff line number Diff line change
Expand Up @@ -284,6 +284,16 @@ void pipeline_schedule_triggered(struct pipeline_walk_context *ctx,
struct pipeline *p;
uint32_t flags;

#ifdef CONFIG_IPC_MAJOR_4
/*
* With IPC4, each pipeline is triggered separately. Exactly 1 pipeline
* is expected in the pipelines list (it's unclear whether an empty list
* should be tolerated).
*/
assert(list_is_empty(&ctx->pipelines) ||
list_item_is_last(ctx->pipelines.next, &ctx->pipelines));

@lyakh lyakh Jun 15, 2026

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doesn't this contradict this comment? #10868 (comment)

@serhiy-katsyuba-intel serhiy-katsyuba-intel Jun 15, 2026

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I'm not sure what you mean. The link goes to Kai's comment on a different PR. Is the link to the comment correct?

@lyakh lyakh Jun 15, 2026

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@serhiy-katsyuba-intel no worries, the link was correct, but indeed it's a different side of that multi-pipeline triggering. So, yes, I think this change is good.

#endif

/*
* Interrupts have to be disabled while adding tasks to or removing them
* from the scheduler list. Without that scheduling can begin
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