OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

my UVM training projects

Python implementation of the exact Riemann solver of Toro (1999).

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI b…

NWPeval is a Python package designed to facilitate the evaluation and analysis of numerical weather prediction (NWP) models.

Basics of UVM via an APB slave

This Repository contains the verification of a Synchronous FIFO design using SystemVerilog and SystemVerilogAssertions

This repository hosts examples and documentation for System Verilog used for Testbench Development

ATM-Utopia module and testbench.

🔒 This project is an educational simulation of a complete digital signature, encryption, and document verification process between a company and a supplier. It uses Python's cryptography library to demonstrate how Public Key Infrastructure (PKI) works in a secure digital environment.

Laravel Verification techniques Course on Udemy

This repo contains golden vector and randomization testbenches for SRAM module.

An inference engine for Leon (https://github.com/epfl-lara/leon) that verifies resource bounds of functional Scala programs

Verification, Validation, Uncertainty Quantification and Qualification Project

BIVREST — a group verification protocol for role-based behavior. "Believe/Don't Believe" voting with structured logging of actions and group decisions. A data collection method for behavioral research.

Wu is a media forensics toolkit with special support for Legal teams.

This project is about the implementation of a RV32I ISA based CPU in Verilog. This project's end goal is to start with a RTL Design to GDSII (Final File Format)

Example which helps understand modelling of a simple SV TB. For UVM implementation refer the repository "fifo_tb_uvm".