arch/tricore: bring up CPU2 secondaries for 3-core SMP

- Macro secondary cold entry for DSPR1/DSPR2 CSA segments
- Per-core ISP in secondary_init; start CPU2 via board API + GPSR2
- generate_ld: HAVE_CSA_CPU2 / csa_pool_cpu2.ld.in

Author: uLipe

arch/tricore/linker/csa_pool_cpu2.ld.in

@@ -0,0 +1,24 @@
+/* arch/tricore/linker/csa_pool_cpu2.ld.in
+ * Layer 2 — TriCore SMP: CSA + ISP + park stack in DSPR2 (KERNEL_RAM_CPU2).
+ * Included by generate_ld.py when HAVE_CSA_CPU2 = 1 in the chip memory.ld.
+ *
+ * CPU2 must never share FCX/LCX with CPU0/CPU1 — CSA is a per-core CSFR.
+ */
+
+    .csa_pool_cpu2 (NOLOAD) : ALIGN(64) {
+        _ulmk_csa_pool_cpu2_start = .;
+        . += ULMK_CSA_POOL_CPU2_SIZE;
+        _ulmk_csa_pool_cpu2_end = .;
+    } > KERNEL_RAM_CPU2
+
+    .isr_stack_cpu2 (NOLOAD) : ALIGN(8) {
+        _ulmk_isr_stack_cpu2_bottom = .;
+        . += ULMK_ISR_STACK_SIZE;
+        _ulmk_isr_stack_cpu2_top = .;
+    } > KERNEL_RAM_CPU2
+
+    .park_stack_cpu2 (NOLOAD) : ALIGN(8) {
+        _ulmk_park_stack_cpu2_bottom = .;
+        . += ULMK_KERNEL_STACK_SIZE;
+        _ulmk_park_stack_cpu2_top = .;
+    } > KERNEL_RAM_CPU2

arch/tricore/secondary.S

@@ -1,65 +1,67 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * CPU1 cold entry — arch/tricore/secondary.S
+ * Secondary cold entry — arch/tricore/secondary.S
  *
- * Reset leaves CPU1 halted.  CPU0 programs PC to _ulmk_cpu1_start and clears
- * DBGSR.HALT.  This prologue builds a private CSA free list in DSPR1
- * (segment 0x6), loads park SP + small-data anchors, then jumps to
- * ulmk_arch_smp_park() which waits for release and calls the kernel entry.
+ * Reset leaves secondaries halted.  CPU0 programs each PC to _ulmk_cpuN_start
+ * and clears DBGSR.HALT.  The prologue builds a private CSA free list in that
+ * core's DSPR (segment 0x6 / 0x5), loads park SP + small-data anchors, then
+ * jumps to ulmk_arch_smp_park().
  *
  * Board WDT for this core is handled by ulmk_board_cpu_wdt_disable_self()
  * inside ulmk_arch_smp_park() — no board SFRs in this file.
  */
 
-    .extern _ulmk_park_stack_cpu1_top
-    .extern _ulmk_csa_pool_cpu1_start
-    .extern _ulmk_csa_pool_cpu1_end
     .extern _small_data_
     .extern _small_data2_
     .extern _small_data3_
     .extern _small_data4_
     .extern ulmk_arch_smp_park
 
-    .section .text._ulmk_cpu1_start, "ax"
-    .global _ulmk_cpu1_start
-    .type   _ulmk_cpu1_start, @function
-_ulmk_cpu1_start:
+/*
+ * N: cpu index suffix (1 / 2)
+ * SEG: CSA link segment field (6 = DSPR1 @ 0x6xxx, 5 = DSPR2 @ 0x5xxx)
+ */
+.macro SECONDARY_COLD_ENTRY name, park_top, csa_start, csa_end, seg
+    .extern \park_top
+    .extern \csa_start
+    .extern \csa_end
+
+    .section .text.\name, "ax"
+    .global \name
+    .type   \name, @function
+\name:
     disable
 
-    movh.a  %a10, hi:_ulmk_park_stack_cpu1_top
-    lea     %a10, [%a10] lo:_ulmk_park_stack_cpu1_top
+    movh.a  %a10, hi:\park_top
+    lea     %a10, [%a10] lo:\park_top
 
-    /*
-     * CSA free list for DSPR1 @ 0x6xxx_xxxx:
-     *   link = 0x00060000 | extr.u(addr, 6, 16)
-     */
-    movh.a  %a2, hi:_ulmk_csa_pool_cpu1_start
-    lea     %a2, [%a2] lo:_ulmk_csa_pool_cpu1_start
-    movh.a  %a3, hi:_ulmk_csa_pool_cpu1_end
-    lea     %a3, [%a3] lo:_ulmk_csa_pool_cpu1_end
+    movh.a  %a2, hi:\csa_start
+    lea     %a2, [%a2] lo:\csa_start
+    movh.a  %a3, hi:\csa_end
+    lea     %a3, [%a3] lo:\csa_end
 
     lea     %a4, [%a2] 0
 
-.L_csa1_link:
+.L_\name\()_link:
     lea     %a5, [%a4] 64
     mov.d   %d0, %a5
     extr.u  %d0, %d0, 6, 16
-    movh    %d1, 6
+    movh    %d1, \seg
     or      %d0, %d1
     mov.d   %d2, %a5
     mov.d   %d3, %a3
-    jge     %d2, %d3, .L_csa1_last
+    jge     %d2, %d3, .L_\name\()_last
     st.w    [%a4], %d0
     lea     %a4, [%a5] 0
-    j       .L_csa1_link
+    j       .L_\name\()_link
 
-.L_csa1_last:
+.L_\name\()_last:
     mov     %d0, 0
     st.w    [%a4], %d0
 
     mov.d   %d0, %a2
     extr.u  %d0, %d0, 6, 16
-    movh    %d1, 6
+    movh    %d1, \seg
     or      %d0, %d1
     dsync
     mtcr    0xFE38, %d0          /* FCX */
@@ -68,7 +70,7 @@ _ulmk_cpu1_start:
     lea     %a6, [%a4] 0
     mov.d   %d0, %a6
     extr.u  %d0, %d0, 6, 16
-    movh    %d1, 6
+    movh    %d1, \seg
     or      %d0, %d1
     dsync
     mtcr    0xFE3C, %d0          /* LCX */
@@ -85,4 +87,15 @@ _ulmk_cpu1_start:
 
     j       ulmk_arch_smp_park
 
-    .size   _ulmk_cpu1_start, . - _ulmk_cpu1_start
+    .size   \name, . - \name
+.endm
+
+    SECONDARY_COLD_ENTRY _ulmk_cpu1_start, \
+	_ulmk_park_stack_cpu1_top, \
+	_ulmk_csa_pool_cpu1_start, \
+	_ulmk_csa_pool_cpu1_end, 6
+
+    SECONDARY_COLD_ENTRY _ulmk_cpu2_start, \
+	_ulmk_park_stack_cpu2_top, \
+	_ulmk_csa_pool_cpu2_start, \
+	_ulmk_csa_pool_cpu2_end, 5

arch/tricore/smp.c

@@ -11,7 +11,7 @@
 #include <arch_config.h>
 #include <board_config.h>
 
-#if defined(ULMK_BOARD_CPU1_PC)
+#if defined(ULMK_BOARD_CPU1_PC) || defined(ULMK_BOARD_CPU2_PC)
 #include <board_smp.h>
 #endif
 
@@ -36,6 +36,10 @@ extern char _trap_class0[];
 extern char _ulmk_int_table[];
 extern char _ulmk_isr_stack_cpu1_top[];
 extern void _ulmk_cpu1_start(void);
+#if defined(ULMK_BOARD_CPU2_PC)
+extern char _ulmk_isr_stack_cpu2_top[];
+extern void _ulmk_cpu2_start(void);
+#endif
 
 static volatile uint32_t *ipi_src(uint32_t cpu)
 {
@@ -151,12 +155,24 @@ static void ipi_src_arm(uint32_t cpu)
 
 void ulmk_arch_secondary_init(void)
 {
-	uint32_t cpu = ulmk_arch_cpu_id();
+	uint32_t  cpu = ulmk_arch_cpu_id();
+	uintptr_t isp;
+
+	if (cpu == 1u) {
+		isp = (uintptr_t)_ulmk_isr_stack_cpu1_top;
+#if defined(ULMK_BOARD_CPU2_PC)
+	} else if (cpu == 2u) {
+		isp = (uintptr_t)_ulmk_isr_stack_cpu2_top;
+#endif
+	} else {
+		for (;;)
+			;
+	}
 
 	ulmk_arch_irq_vectors_init(
 		(uintptr_t)_trap_class0,
 		(uintptr_t)_ulmk_int_table,
-		(uintptr_t)_ulmk_isr_stack_cpu1_top);
+		isp);
 	ulmk_arch_mpu_init();
 	ulmk_arch_mpu_enable();
 	/*
@@ -191,7 +207,12 @@ void ulmk_arch_start_secondary(uint32_t cpu_id, void (*entry)(void))
 #if defined(ULMK_BOARD_CPU1_PC)
 	if (cpu_id == 1u)
 		ulmk_board_cpu_start(1u, _ulmk_cpu1_start);
-#else
+#endif
+#if defined(ULMK_BOARD_CPU2_PC)
+	if (cpu_id == 2u)
+		ulmk_board_cpu_start(2u, _ulmk_cpu2_start);
+#endif
+#if !defined(ULMK_BOARD_CPU1_PC) && !defined(ULMK_BOARD_CPU2_PC)
 	(void)cpu_id;
 #endif
 
@@ -213,7 +234,7 @@ void ulmk_arch_smp_park(void)
 			;
 	}
 
-#if defined(ULMK_BOARD_CPU1_PC)
+#if defined(ULMK_BOARD_CPU1_PC) || defined(ULMK_BOARD_CPU2_PC)
 	/* Own WDT — cannot be unlocked safely from CPU0. */
 	ulmk_board_cpu_wdt_disable_self();
 #endif

cmake/generate_ld.py

@@ -53,7 +53,8 @@ def render_snippet(path: str, substitutions: dict) -> str:
 def parse_flags(chip_memory_ld: str) -> dict:
     """Extract HAVE_* flag values from the chip memory.ld as integers."""
     flags = {}
-    for name in ("HAVE_CSA", "HAVE_CSA_CPU1", "HAVE_SMALL_DATA", "HAVE_BMHD"):
+    for name in ("HAVE_CSA", "HAVE_CSA_CPU1", "HAVE_CSA_CPU2",
+                 "HAVE_SMALL_DATA", "HAVE_BMHD"):
         m = re.search(rf"^\s*{name}\s*=\s*(\d+)\s*;", chip_memory_ld, re.MULTILINE)
         flags[name] = int(m.group(1)) if m else 0
     return flags
@@ -164,12 +165,16 @@ def main():
     # 4q. User pool (always last in KERNEL_RAM)
     out.append(read_fragment(os.path.join(args.kernel_dir, "user_pool.ld.in")))
 
-    # 4r. CPU1 DSPR CSA/ISP/park — AFTER KERNEL_RAM so VMA '.' is not left
-    #     in 0x60000000 (would corrupt user_ram_start / zero_words span).
+    # 4r. Secondary DSPR CSA/ISP/park — AFTER KERNEL_RAM so VMA '.' is not
+    #     left in 0x6xxx/0x5xxx (would corrupt user_ram_start / zero_words).
     if flags.get("HAVE_CSA_CPU1"):
         cpu1 = os.path.join(args.arch_dir, "csa_pool_cpu1.ld.in")
         if os.path.exists(cpu1):
             out.append(read_fragment(cpu1))
+    if flags.get("HAVE_CSA_CPU2"):
+        cpu2 = os.path.join(args.arch_dir, "csa_pool_cpu2.ld.in")
+        if os.path.exists(cpu2):
+            out.append(read_fragment(cpu2))
 
     out.append("\n} /* SECTIONS */\n")