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6 | 6 | * DBGSR.HALT. This prologue builds a private CSA free list in DSPR1 |
7 | 7 | * (segment 0x6), loads park SP + small-data anchors, then jumps to |
8 | 8 | * ulmk_arch_smp_park() which waits for release and calls the kernel entry. |
| 9 | + * |
| 10 | + * Board WDT for this core is handled by ulmk_board_cpu_wdt_disable_self() |
| 11 | + * inside ulmk_arch_smp_park() — no board SFRs in this file. |
9 | 12 | */ |
10 | 13 |
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11 | 14 | .extern _ulmk_park_stack_cpu1_top |
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20 | 23 | .section .text._ulmk_cpu1_start, "ax" |
21 | 24 | .global _ulmk_cpu1_start |
22 | 25 | .type _ulmk_cpu1_start, @function |
23 | | - .set WDTCPU1_CON0, 0xF003610C |
24 | | - .set WDTCPU1_CON1, 0xF0036110 |
25 | | - |
26 | 26 | _ulmk_cpu1_start: |
27 | 27 | disable |
28 | 28 |
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29 | 29 | movh.a %a10, hi:_ulmk_park_stack_cpu1_top |
30 | 30 | lea %a10, [%a10] lo:_ulmk_park_stack_cpu1_top |
31 | 31 |
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32 | | - /* |
33 | | - * Disarm WDTCPU1 before CSA construction. OpenOCD reset-end may |
34 | | - * already have set DR, but button/PORST and flash paths without a |
35 | | - * sticky DAP poke leave the default timeout armed — CSA init is |
36 | | - * long enough to expire it. Own-core EndInit only (never from CPU0). |
37 | | - */ |
38 | | - movh.a %a2, hi:WDTCPU1_CON0 |
39 | | - lea %a2, [%a2] lo:WDTCPU1_CON0 |
40 | | - ld.w %d0, [%a2]0 |
41 | | - extr.u %d8, %d0, 2, 14 /* PW */ |
42 | | - mov %d1, 0x3F |
43 | | - xor %d8, %d1 |
44 | | - extr.u %d9, %d0, 16, 16 /* REL */ |
45 | | - extr.u %d2, %d0, 1, 1 /* LCK? */ |
46 | | - jz %d2, .L_wdt1_cle2 |
47 | | - sh %d0, %d8, 2 |
48 | | - mov %d1, 1 |
49 | | - or %d0, %d1 |
50 | | - sh %d1, %d9, 16 |
51 | | - or %d0, %d1 |
52 | | - st.w [%a2]0, %d0 |
53 | | -.L_wdt1_cle2: |
54 | | - sh %d0, %d8, 2 |
55 | | - mov %d1, 2 /* ENDINIT=0 LCK=1 */ |
56 | | - or %d0, %d1 |
57 | | - sh %d1, %d9, 16 |
58 | | - or %d0, %d1 |
59 | | - st.w [%a2]0, %d0 |
60 | | -.L_wdt1_wait0: |
61 | | - ld.w %d0, [%a2]0 |
62 | | - and %d1, %d0, 1 |
63 | | - jnz %d1, .L_wdt1_wait0 |
64 | | - |
65 | | - movh.a %a3, hi:WDTCPU1_CON1 |
66 | | - lea %a3, [%a3] lo:WDTCPU1_CON1 |
67 | | - mov %d0, 8 /* DR=1 */ |
68 | | - st.w [%a3]0, %d0 |
69 | | - |
70 | | - ld.w %d0, [%a2]0 |
71 | | - extr.u %d9, %d0, 16, 16 |
72 | | - extr.u %d2, %d0, 1, 1 |
73 | | - jz %d2, .L_wdt1_set2 |
74 | | - sh %d0, %d8, 2 |
75 | | - mov %d1, 1 |
76 | | - or %d0, %d1 |
77 | | - sh %d1, %d9, 16 |
78 | | - or %d0, %d1 |
79 | | - st.w [%a2]0, %d0 |
80 | | -.L_wdt1_set2: |
81 | | - sh %d0, %d8, 2 |
82 | | - mov %d1, 3 /* ENDINIT=1 LCK=1 */ |
83 | | - or %d0, %d1 |
84 | | - sh %d1, %d9, 16 |
85 | | - or %d0, %d1 |
86 | | - st.w [%a2]0, %d0 |
87 | | -.L_wdt1_wait1: |
88 | | - ld.w %d0, [%a2]0 |
89 | | - and %d1, %d0, 1 |
90 | | - jz %d1, .L_wdt1_wait1 |
91 | | - |
92 | 32 | /* |
93 | 33 | * CSA free list for DSPR1 @ 0x6xxx_xxxx: |
94 | 34 | * link = 0x00060000 | extr.u(addr, 6, 16) |
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