arch/riscv: preserve t3–t6 across traps and recover U-mode faults

- Save/restore t3–t6 in the trap frame so ecall cannot clobber lui bases for BSS/data
- Treat all U-mode illegal/load/store/fetch faults as recoverable thread kills

Author: uLipe

arch/riscv/arch.c

@@ -10,7 +10,7 @@
 #include <ulmk_arch.h>
 #include "irq_internal.h"
 
-#define TF_SIZE		128u
+#define TF_SIZE		144u
 #define TF_RA		0u
 #define TF_S0		28u
 #define TF_S1		32u
@@ -509,14 +509,13 @@ void _ulmk_trap_dispatch(struct riscv_trap_frame *frame)
 	/*
 	 * U-mode fetch of kernel text may raise INST_FAULT (PMP deny) or,
 	 * when a NAPOT user RX window overlaps and the first insn is a
-	 * privileged CSR (-O1+), ILLEGAL_INST.  Both mean the thread must
-	 * die; only panic if the fault came from M-mode.
+	 * privileged CSR (-O1+), ILLEGAL_INST.  Userspace load/store/fetch
+	 * faults are recoverable (kill thread).  M-mode faults panic.
 	 */
 	mstatus = frame->regs[TF_MSTATUS / 4u];
-	if (code == MCAUSE_LOAD_FAULT || code == MCAUSE_STORE_FAULT ||
-	    code == MCAUSE_INST_FAULT ||
-	    (code == MCAUSE_ILLEGAL_INST &&
-	     ((mstatus >> MSTATUS_MPP_SHIFT) & 3u) == 0u))
+	if (((mstatus >> MSTATUS_MPP_SHIFT) & 3u) == 0u &&
+	    (code == MCAUSE_LOAD_FAULT || code == MCAUSE_STORE_FAULT ||
+	     code == MCAUSE_INST_FAULT || code == MCAUSE_ILLEGAL_INST))
 		ulmk_arch_trap_entry(0u, (uint8_t)code);
 	else
 		ulmk_arch_trap_entry(mcause_to_trap_class(mcause), (uint8_t)code);

arch/riscv/trap.S

@@ -3,7 +3,12 @@
  * RISC-V trap entry — arch/riscv/trap.S
  */
 
-	.equ TF_SIZE, 128
+	/*
+	 * Must save t3–t6: GCC keeps lui bases for .bss/.data in temps across
+	 * ecall; leaving them live lets the callee (or IRQ C path) clobber them
+	 * and userspace reloads as `lw rd, %lo(sym)(zero)` → mtval=lo12.
+	 */
+	.equ TF_SIZE, 144
 	.equ TF_RA, 0
 	.equ TF_SP, 4
 	.equ TF_GP, 8
@@ -33,6 +38,10 @@
 	.equ TF_S11, 104
 	.equ TF_MEPC, 108
 	.equ TF_MSTATUS, 112
+	.equ TF_T3, 116
+	.equ TF_T4, 120
+	.equ TF_T5, 124
+	.equ TF_T6, 128
 
 	.extern _ulmk_trap_dispatch
 	.extern g_trap_sp
@@ -51,6 +60,10 @@ _trap_handler:
 	sw      t0, TF_T0(sp)
 	sw      t1, TF_T1(sp)
 	sw      t2, TF_T2(sp)
+	sw      t3, TF_T3(sp)
+	sw      t4, TF_T4(sp)
+	sw      t5, TF_T5(sp)
+	sw      t6, TF_T6(sp)
 	sw      s0, TF_S0(sp)
 	sw      s1, TF_S1(sp)
 	sw      a0, TF_A0(sp)
@@ -91,6 +104,10 @@ _trap_handler:
 	lw      t0, TF_T0(sp)
 	lw      t1, TF_T1(sp)
 	lw      t2, TF_T2(sp)
+	lw      t3, TF_T3(sp)
+	lw      t4, TF_T4(sp)
+	lw      t5, TF_T5(sp)
+	lw      t6, TF_T6(sp)
 	lw      s0, TF_S0(sp)
 	lw      s1, TF_S1(sp)
 	lw      a0, TF_A0(sp)