arch/tricore: bring up CPU2 secondaries for 3-core SMP

- Backport from main for 0.1.0

Author: uLipe

arch/tricore/linker/csa_pool_cpu2.ld.in

@@ -0,0 +1,24 @@
+/* arch/tricore/linker/csa_pool_cpu2.ld.in
+ * Layer 2 — TriCore SMP: CSA + ISP + park stack in DSPR2 (KERNEL_RAM_CPU2).
+ * Included by generate_ld.py when HAVE_CSA_CPU2 = 1 in the chip memory.ld.
+ *
+ * CPU2 must never share FCX/LCX with CPU0/CPU1 — CSA is a per-core CSFR.
+ */
+
+    .csa_pool_cpu2 (NOLOAD) : ALIGN(64) {
+        _ulmk_csa_pool_cpu2_start = .;
+        . += ULMK_CSA_POOL_CPU2_SIZE;
+        _ulmk_csa_pool_cpu2_end = .;
+    } > KERNEL_RAM_CPU2
+
+    .isr_stack_cpu2 (NOLOAD) : ALIGN(8) {
+        _ulmk_isr_stack_cpu2_bottom = .;
+        . += ULMK_ISR_STACK_SIZE;
+        _ulmk_isr_stack_cpu2_top = .;
+    } > KERNEL_RAM_CPU2
+
+    .park_stack_cpu2 (NOLOAD) : ALIGN(8) {
+        _ulmk_park_stack_cpu2_bottom = .;
+        . += ULMK_KERNEL_STACK_SIZE;
+        _ulmk_park_stack_cpu2_top = .;
+    } > KERNEL_RAM_CPU2

arch/tricore/secondary.S

@@ -1,65 +1,67 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * CPU1 cold entry — arch/tricore/secondary.S
+ * Secondary cold entry — arch/tricore/secondary.S
  *
- * Reset leaves CPU1 halted.  CPU0 programs PC to _ulmk_cpu1_start and clears
- * DBGSR.HALT.  This prologue builds a private CSA free list in DSPR1
- * (segment 0x6), loads park SP + small-data anchors, then jumps to
- * ulmk_arch_smp_park() which waits for release and calls the kernel entry.
+ * Reset leaves secondaries halted.  CPU0 programs each PC to _ulmk_cpuN_start
+ * and clears DBGSR.HALT.  The prologue builds a private CSA free list in that
+ * core's DSPR (segment 0x6 / 0x5), loads park SP + small-data anchors, then
+ * jumps to ulmk_arch_smp_park().
  *
  * Board WDT for this core is handled by ulmk_board_cpu_wdt_disable_self()
  * inside ulmk_arch_smp_park() — no board SFRs in this file.
  */
 
-    .extern _ulmk_park_stack_cpu1_top
-    .extern _ulmk_csa_pool_cpu1_start
-    .extern _ulmk_csa_pool_cpu1_end
     .extern _small_data_
     .extern _small_data2_
     .extern _small_data3_
     .extern _small_data4_
     .extern ulmk_arch_smp_park
 
-    .section .text._ulmk_cpu1_start, "ax"
-    .global _ulmk_cpu1_start
-    .type   _ulmk_cpu1_start, @function
-_ulmk_cpu1_start:
+/*
+ * N: cpu index suffix (1 / 2)
+ * SEG: CSA link segment field (6 = DSPR1 @ 0x6xxx, 5 = DSPR2 @ 0x5xxx)
+ */
+.macro SECONDARY_COLD_ENTRY name, park_top, csa_start, csa_end, seg
+    .extern \park_top
+    .extern \csa_start
+    .extern \csa_end
+
+    .section .text.\name, "ax"
+    .global \name
+    .type   \name, @function
+\name:
     disable
 
-    movh.a  %a10, hi:_ulmk_park_stack_cpu1_top
-    lea     %a10, [%a10] lo:_ulmk_park_stack_cpu1_top
+    movh.a  %a10, hi:\park_top
+    lea     %a10, [%a10] lo:\park_top
 
-    /*
-     * CSA free list for DSPR1 @ 0x6xxx_xxxx:
-     *   link = 0x00060000 | extr.u(addr, 6, 16)
-     */
-    movh.a  %a2, hi:_ulmk_csa_pool_cpu1_start
-    lea     %a2, [%a2] lo:_ulmk_csa_pool_cpu1_start
-    movh.a  %a3, hi:_ulmk_csa_pool_cpu1_end
-    lea     %a3, [%a3] lo:_ulmk_csa_pool_cpu1_end
+    movh.a  %a2, hi:\csa_start
+    lea     %a2, [%a2] lo:\csa_start
+    movh.a  %a3, hi:\csa_end
+    lea     %a3, [%a3] lo:\csa_end
 
     lea     %a4, [%a2] 0
 
-.L_csa1_link:
+.L_\name\()_link:
     lea     %a5, [%a4] 64
     mov.d   %d0, %a5
     extr.u  %d0, %d0, 6, 16
-    movh    %d1, 6
+    movh    %d1, \seg
     or      %d0, %d1
     mov.d   %d2, %a5
     mov.d   %d3, %a3
-    jge     %d2, %d3, .L_csa1_last
+    jge     %d2, %d3, .L_\name\()_last
     st.w    [%a4], %d0
     lea     %a4, [%a5] 0
-    j       .L_csa1_link
+    j       .L_\name\()_link
 
-.L_csa1_last:
+.L_\name\()_last:
     mov     %d0, 0
     st.w    [%a4], %d0
 
     mov.d   %d0, %a2
     extr.u  %d0, %d0, 6, 16
-    movh    %d1, 6
+    movh    %d1, \seg
     or      %d0, %d1
     dsync
     mtcr    0xFE38, %d0          /* FCX */
@@ -68,7 +70,7 @@ _ulmk_cpu1_start:
     lea     %a6, [%a4] 0
     mov.d   %d0, %a6
     extr.u  %d0, %d0, 6, 16
-    movh    %d1, 6
+    movh    %d1, \seg
     or      %d0, %d1
     dsync
     mtcr    0xFE3C, %d0          /* LCX */
@@ -85,4 +87,15 @@ _ulmk_cpu1_start:
 
     j       ulmk_arch_smp_park
 
-    .size   _ulmk_cpu1_start, . - _ulmk_cpu1_start
+    .size   \name, . - \name
+.endm
+
+    SECONDARY_COLD_ENTRY _ulmk_cpu1_start, \
+	_ulmk_park_stack_cpu1_top, \
+	_ulmk_csa_pool_cpu1_start, \
+	_ulmk_csa_pool_cpu1_end, 6
+
+    SECONDARY_COLD_ENTRY _ulmk_cpu2_start, \
+	_ulmk_park_stack_cpu2_top, \
+	_ulmk_csa_pool_cpu2_start, \
+	_ulmk_csa_pool_cpu2_end, 5