arch/tricore: keep board details out of startup.S

- Only ulmk_board_init() may touch board SFRs; drop early WDT hook from
  startup and hard-coded WDTCPU1 from secondary (park uses board API)
- HIL serial expect: hot-attach ulmk_release_run so CSA is not raced by
  the default watchdog before board_init

Author: uLipe

arch/tricore/board_wdt_early_stub.S

@@ -6,6 +6,9 @@
  * DBGSR.HALT.  This prologue builds a private CSA free list in DSPR1
  * (segment 0x6), loads park SP + small-data anchors, then jumps to
  * ulmk_arch_smp_park() which waits for release and calls the kernel entry.
+ *
+ * Board WDT for this core is handled by ulmk_board_cpu_wdt_disable_self()
+ * inside ulmk_arch_smp_park() — no board SFRs in this file.
  */
 
     .extern _ulmk_park_stack_cpu1_top
@@ -20,75 +23,12 @@
     .section .text._ulmk_cpu1_start, "ax"
     .global _ulmk_cpu1_start
     .type   _ulmk_cpu1_start, @function
-	.set WDTCPU1_CON0, 0xF003610C
-	.set WDTCPU1_CON1, 0xF0036110
-
 _ulmk_cpu1_start:
     disable
 
     movh.a  %a10, hi:_ulmk_park_stack_cpu1_top
     lea     %a10, [%a10] lo:_ulmk_park_stack_cpu1_top
 
-    /*
-     * Disarm WDTCPU1 before CSA construction.  OpenOCD reset-end may
-     * already have set DR, but button/PORST and flash paths without a
-     * sticky DAP poke leave the default timeout armed — CSA init is
-     * long enough to expire it.  Own-core EndInit only (never from CPU0).
-     */
-    movh.a  %a2, hi:WDTCPU1_CON0
-    lea     %a2, [%a2] lo:WDTCPU1_CON0
-    ld.w    %d0, [%a2]0
-    extr.u  %d8, %d0, 2, 14		/* PW */
-    mov     %d1, 0x3F
-    xor     %d8, %d1
-    extr.u  %d9, %d0, 16, 16		/* REL */
-    extr.u  %d2, %d0, 1, 1		/* LCK? */
-    jz      %d2, .L_wdt1_cle2
-    sh      %d0, %d8, 2
-    mov     %d1, 1
-    or      %d0, %d1
-    sh      %d1, %d9, 16
-    or      %d0, %d1
-    st.w    [%a2]0, %d0
-.L_wdt1_cle2:
-    sh      %d0, %d8, 2
-    mov     %d1, 2			/* ENDINIT=0 LCK=1 */
-    or      %d0, %d1
-    sh      %d1, %d9, 16
-    or      %d0, %d1
-    st.w    [%a2]0, %d0
-.L_wdt1_wait0:
-    ld.w    %d0, [%a2]0
-    and     %d1, %d0, 1
-    jnz     %d1, .L_wdt1_wait0
-
-    movh.a  %a3, hi:WDTCPU1_CON1
-    lea     %a3, [%a3] lo:WDTCPU1_CON1
-    mov     %d0, 8			/* DR=1 */
-    st.w    [%a3]0, %d0
-
-    ld.w    %d0, [%a2]0
-    extr.u  %d9, %d0, 16, 16
-    extr.u  %d2, %d0, 1, 1
-    jz      %d2, .L_wdt1_set2
-    sh      %d0, %d8, 2
-    mov     %d1, 1
-    or      %d0, %d1
-    sh      %d1, %d9, 16
-    or      %d0, %d1
-    st.w    [%a2]0, %d0
-.L_wdt1_set2:
-    sh      %d0, %d8, 2
-    mov     %d1, 3			/* ENDINIT=1 LCK=1 */
-    or      %d0, %d1
-    sh      %d1, %d9, 16
-    or      %d0, %d1
-    st.w    [%a2]0, %d0
-.L_wdt1_wait1:
-    ld.w    %d0, [%a2]0
-    and     %d1, %d0, 1
-    jz      %d1, .L_wdt1_wait1
-
     /*
      * CSA free list for DSPR1 @ 0x6xxx_xxxx:
      *   link = 0x00060000 | extr.u(addr, 6, 16)

arch/tricore/secondary.S

@@ -11,6 +11,9 @@
  *   2. Build CSA free list (FCX/LCX) — mandatory before ANY call
  *   3. Set small-data address registers (A0, A1, A8, A9)
  *   4. Jump to ulmk_kern_start() — does not return
+ *
+ * Board-specific bring-up (WDT, PLL, …) belongs in ulmk_board_init(), called
+ * from ulmk_kern_start() — never from this file.
  */
 
     .extern _ulmk_kernel_stack_top
@@ -21,7 +24,6 @@
     .extern _small_data3_
     .extern _small_data4_
     .extern ulmk_kern_start
-    .extern ulmk_board_wdt_disable_early
 
     .section .text._start, "ax"
     .global _start
@@ -30,21 +32,6 @@ _start:
     /* 0. Interrupts off until the kernel unlocks them. */
     disable
 
-    /*
-     * Board hook: disable CPU0 + Safety WDT before CSA construction.
-     * Default timeout can expire during the CSA loop on standalone reset
-     * (OpenOCD reset-end pokes WDT only under OCDS).  Weak stub is ji %a11.
-     * No CALL (CSA not ready).  ji needs a register operand; local .L labels
-     * have no hi/lo reloc — use a global continue label.
-     */
-    movh.a  %a11, hi:_start_after_wdt
-    lea     %a11, [%a11] lo:_start_after_wdt
-    movh.a  %a2, hi:ulmk_board_wdt_disable_early
-    lea     %a2, [%a2] lo:ulmk_board_wdt_disable_early
-    ji      %a2
-    .global _start_after_wdt
-_start_after_wdt:
-
     /* 1. Supervisor stack + clear PSW.IS
      *
      * SSW / cold reset may leave PSW.IS=1.  board_init runs before arch_init
@@ -122,7 +109,7 @@ _start_after_wdt:
     movh.a  %a9, hi:_small_data4_
     lea     %a9, [%a9] lo:_small_data4_
 
-    /* 4. Common C runtime bring-up (relocates .data/.bss, calls kernel). */
+    /* 4. Common C runtime bring-up (relocates .data/.bss, calls board_init). */
     j       ulmk_kern_start
 
 .L_hang:

arch/tricore/startup.S

@@ -7,7 +7,6 @@ if(ULMK_ARCH STREQUAL "tricore")
 		${ULMK_ARCH_DIR}/ctx_switch.S)
 	set(ULMK_ARCH_EXE_SOURCES
 		${ULMK_ARCH_DIR}/startup.S
-		${ULMK_ARCH_DIR}/board_wdt_early_stub.S
 		${ULMK_ARCH_DIR}/secondary.S
 		${ULMK_ARCH_DIR}/vectors.S)
 elseif(ULMK_ARCH STREQUAL "riscv")

cmake/arch_sources.cmake

@@ -17,7 +17,6 @@ ARCH_LDFLAGS := -mcpu=tc39xx
 
 ARCH_KERNEL_SRCS := \
 	$(ROOT)/arch/tricore/startup.S \
-	$(ROOT)/arch/tricore/board_wdt_early_stub.S \
 	$(ROOT)/arch/tricore/arch.c \
 	$(ROOT)/arch/tricore/smp.c \
 	$(ROOT)/arch/tricore/ctx_switch.S \

tests/arch/tricore.mk

@@ -55,9 +55,11 @@ sleep 0.2
 
 if [[ -n "${ULMK_HIL_OCD:-}" && -n "${ULMK_HIL_OCD_CFG:-}" ]]; then
 	pkill -9 -x openocd 2>/dev/null || true
+	# Prefer hot-attach release (WDT disarm + HARR clear).  "reset halt" races
+	# the OCDS sequencer on TAS and can leave the core stuck at STAD.
 	"${ULMK_HIL_OCD}" -s "${ULMK_HIL_OCD_SCRIPTS}" -s "${ULMK_HIL_OCD_BOARD_DIR}" \
 		-f "${ULMK_HIL_OCD_CFG}" \
-		-c "gdb port disabled; init; reset halt; resume; shutdown" \
+		-c "gdb port disabled; reset_config none separate; init; targets tc27x.cpu0; ulmk_release_run; resume; after 200; shutdown" \
 		>/dev/null 2>&1 || true
 fi