Bug with clock and node emit the same reference#468
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July 27, 2015 18:16
not created in with a val. Fixed testsuite forcing this behaviour
Conflicts: src/main/scala/Verilog.scala
fix multiple reset issue by ensuring unique def and correct clock names for unnamed clock
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I think perhaps i will rework this. |
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If a clock is created without a reference val, it is given a name with emit ref which may give it the same name as another node and hence result in invalid verilog