Bump version to 2.4 and document RTL8201F timing

Update the firmware version constant to "2.4" and rename SOFTWARE_VERSION to kSoftwareVersion, updating usages in Art-Net and sACN firmware mains. Add a detailed doxygen-style comment to rtl8201f CustomizedTiming that documents the RMSR timing fields, platform-specific RMII timing behavior, chosen RX/TX offset values for GD32F4 variants, and the masked read-modify-write update strategy. Also remove the -fprefetch-loop-arrays GCC optimize pragma from crc32.cpp.

Author: vanvught

firmware-template-gd32/include/software_version.h

@@ -26,6 +26,6 @@
 #ifndef SOFTWARE_VERSION_H_
 #define SOFTWARE_VERSION_H_
 
-constexpr char SOFTWARE_VERSION[] = "2.3";
+constexpr char kSoftwareVersion[] = "2.4";
 
 #endif // SOFTWARE_VERSION_H_

gd32_emac_artnet_dmx_multi/firmware/main.cpp

@@ -55,7 +55,7 @@ int main() // NOLINT
     DisplayUdf display;
     ConfigStore config_store;
     network::Init();
-    FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__);
+    FirmwareVersion fw(kSoftwareVersion, __DATE__, __TIME__);
 
     fw.Print("Art-Net 4 DMX/RDM controller {" STR(DMXNODE_PORTS) " Universes}");
 

gd32_emac_e131_dmx_multi/firmware/main.cpp

@@ -59,7 +59,7 @@ int main() // NOLINT
     DisplayUdf display;
     ConfigStore config_store;
     network::Init();
-    FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__);
+    FirmwareVersion fw(kSoftwareVersion, __DATE__, __TIME__);
 
     fw.Print("sACN E1.31 DMX  {" STR(DMXNODE_PORTS) " Universes}");
 

lib-clib/src/crc32/crc32.cpp

@@ -11,7 +11,6 @@
 #pragma GCC push_options
 #pragma GCC optimize ("O2")
 #pragma GCC optimize ("-funroll-loops")
-#pragma GCC optimize ("-fprefetch-loop-arrays")
 
 #include <cstdint>
 #include <cstddef>

lib-network/src/emac/phy/rtl8201f/phy.cpp

@@ -89,7 +89,59 @@ void CustomizedLed()
 #define RMSR_TX_TIMING_SHIFT 8
 #define RMSR_TX_TIMING_MASK 0xF00
 
-void CustomizedTiming()
+/**
+ * @brief Apply RMII timing compensation for the RTL8201F PHY.
+ *
+ * The RTL8201F PHY provides programmable RMII interface timing adjustment
+ * through the RMII Mode Setting Register (RMSR), located at page 7, register 16.
+ *
+ * Relevant RMSR fields:
+ *
+ *   Bits [11:8]  Rg_rmii_tx_offset   RMII transmit timing offset
+ *   Bits [7:4]   Rg_rmii_rx_offset   RMII receive timing offset
+ *
+ * These fields allow the PHY to shift the internal sampling/drive timing
+ * relative to the RMII 50 MHz reference clock. The RTL8201F datasheet specifies
+ * a minimum timing adjustment resolution of approximately 2 ns per step.
+ *
+ * In principle the PHY default timing values are intended to be optimal,
+ * however the effective RMII timing budget depends on the entire system:
+ *
+ *   - MAC peripheral timing characteristics
+ *   - REFCLK distribution and clock phase
+ *   - GPIO pad delays
+ *   - PCB routing skew
+ *   - SoC internal bus and clock frequency
+ *
+ * Because of this, some platforms require PHY timing compensation to achieve
+ * reliable RMII communication.
+ *
+ * In this implementation:
+ *
+ *   GD32F1x7 and GD32F2x7 platforms operate correctly using the RTL8201F
+ *   default timing configuration and therefore require no adjustment.
+ *
+ *   GD32F4xx platforms require modified RMII timing to ensure stable
+ *   Ethernet operation. The RX and TX offsets are therefore programmed
+ *   explicitly via the RMSR register.
+ *
+ * Selected values:
+ *
+ *   RX offset: 0x4
+ *   TX offset:
+ *       GD32F407  -> 0x2  (system typically running at higher core clock)
+ *       GD32F470  -> 0x1
+ *       other F4  -> 0xF (fallback/default PHY setting)
+ *
+ * Only the RX/TX timing fields are modified. The register is updated using
+ * a masked read-modify-write sequence so that other RMSR bits (RMII mode,
+ * clock direction, CRS_DV behavior, etc.) remain unchanged.
+ *
+ * This configuration is platform-specific and compensates for MAC/PHY
+ * interface timing differences on the GD32F4xx family.
+ */
+
+ void CustomizedTiming()
 {
     DEBUG_ENTRY();
 #if defined(GD32F4XX)