From 327c0347fe268a7e82ca9e6e8f0faf16c5612f0c Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 5 Oct 2025 13:06:55 +0200 Subject: [PATCH 01/30] feat: add bms project --- bms/bms/README.md | 11 + .../bms_config_default/components/adc0.yml | 207 ++++++++++++ .../bms_config_default/components/can0.yml | 31 ++ .../bms_config_default/components/cmsis.yml | 24 ++ .../bms_config_default/components/core.yml | 296 ++++++++++++++++++ .../mcc/bms_config_default/components/dfp.yml | 20 ++ .../bms_config_default/components/evsys.yml | 31 ++ .../bms_config_default/components/nvmctrl.yml | 31 ++ .../mcc/bms_config_default/mcc-config.mc4 | 16 + .../bms_config/mcc/mcc-manifest-autosave.yml | 22 ++ bms/bms/bms_config/mcc/mcc.vscode | 11 + bms/bms/cmake/bms/default/CMakeLists.txt | 22 ++ bms/bms/cmake/bms/default/CMakePresets.json | 21 ++ bms/bms/main.c | 12 + 14 files changed, 755 insertions(+) create mode 100644 bms/bms/README.md create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/can0.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/core.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 create mode 100644 bms/bms/bms_config/mcc/mcc-manifest-autosave.yml create mode 100644 bms/bms/bms_config/mcc/mcc.vscode create mode 100644 bms/bms/cmake/bms/default/CMakeLists.txt create mode 100644 bms/bms/cmake/bms/default/CMakePresets.json create mode 100644 bms/bms/main.c diff --git a/bms/bms/README.md b/bms/bms/README.md new file mode 100644 index 00000000..40233c27 --- /dev/null +++ b/bms/bms/README.md @@ -0,0 +1,11 @@ + +# bms + +## Structure + +| Path | Purpose | +|------------------------|-- -| +| _build | Stores build artifacts, can be deleted | +| cmake | Generated [CMake](https://cmake.org/) files. May be deleted if user.cmake has not been added | +| .vscode | See [VSCode Settings](https://code.visualstudio.com/docs/getstarted/settings) | +| .vscode/bms.mplab.json | The MPLAB project file, should not be deleted | diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml new file mode 100644 index 00000000..62058303 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml @@ -0,0 +1,207 @@ +configVersion: 1.0.0 +componentName: adc0 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc0 + x: '37' + y: '233' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc0 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc0 + value: ADC0_RESRDY_IRQn + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml new file mode 100644 index 00000000..f5b68f49 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: can0 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: can0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: can0 + x: '197' + y: '235' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml b/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml new file mode 100644 index 00000000..ada4695f --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml @@ -0,0 +1,24 @@ +configVersion: 1.0.0 +componentName: cmsis +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: cmsis + type: module + version: '' +- dependencyPackage: '' + name: CMSIS_5 + type: package + version: 5.9.1-dev +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml new file mode 100644 index 00000000..fac3385d --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -0,0 +1,296 @@ +configVersion: 1.0.0 +componentName: core +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: core + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: + ADC0_CLOCK_ENABLE: + attributes: + id: ADC0_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC0_CLOCK_FREQUENCY: + attributes: + id: ADC0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + CAN0_CLOCK_ENABLE: + attributes: + id: CAN0_CLOCK_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_CLOCK_FREQUENCY: + attributes: + id: CAN0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_22_CHEN: + attributes: + id: GCLK_ID_22_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_22_FREQ: + attributes: + id: GCLK_ID_22_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_25_CHEN: + attributes: + id: GCLK_ID_25_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_25_FREQ: + attributes: + id: GCLK_ID_25_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_26_CHEN: + attributes: + id: GCLK_ID_26_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_26_FREQ: + attributes: + id: GCLK_ID_26_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_33_CHEN: + attributes: + id: GCLK_ID_33_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_33_FREQ: + attributes: + id: GCLK_ID_33_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + MCLK_AHB_INITIAL_VALUE: + attributes: + id: MCLK_AHB_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1dff' + type: Dynamic + type: Values + type: String + MCLK_APBC_INITIAL_VALUE: + attributes: + id: MCLK_APBC_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x20000' + type: Dynamic + type: Values + type: String + NVIC_12_0_ENABLE: + attributes: + id: NVIC_12_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_HANDLER: + attributes: + id: NVIC_12_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM3_Handler + type: Dynamic + type: Values + type: String + NVIC_12_0_HANDLER_LOCK: + attributes: + id: NVIC_12_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_ENABLE: + attributes: + id: NVIC_14_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_HANDLER: + attributes: + id: NVIC_14_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM5_Handler + type: Dynamic + type: Values + type: String + NVIC_14_0_HANDLER_LOCK: + attributes: + id: NVIC_14_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM3_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM3_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM5_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM5_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM5_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM5_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + userData: + children: + - attributes: + canvasHeight: '0' + canvasWidth: '0' + type: GraphSettings + - children: + - attributes: + id: profile0 + name: Main + type: Profile + type: PowerProfiles + type: UserData diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml b/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml new file mode 100644 index 00000000..5993bb4c --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: dfp +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: dfp + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml new file mode 100644 index 00000000..8c05dd58 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: evsys +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: evsys + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: evsys + x: '281' + y: '61' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml b/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml new file mode 100644 index 00000000..f489f102 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: nvmctrl +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: nvmctrl + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: nvmctrl + x: '438' + y: '69' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 new file mode 100644 index 00000000..53db5149 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -0,0 +1,16 @@ +configVersion: 1.0.0 +coreVersion: 5.8.2 +spaHostVersion: 1.0.0 +device: ATSAMC21J18A +deviceLibrary: + className: null +groupModules: [] +modules: +- adc0 +- can0 +- cmsis +- core +- dfp +- evsys +- nvmctrl +generatedFileHashHistoryMap: [] diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml new file mode 100644 index 00000000..23588f4e --- /dev/null +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -0,0 +1,22 @@ +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. + +manifest_file_version: 1.0.0 +project: bms_config +creation_date: 2025-10-05T13:03:38.592+02:00[Europe/Oslo] +operating_system: Linux +mcc_mode: VSCodePlugin +mcc_mode_version: Unknown +device_name: ATSAMC21J18A +compiler: N/A +mcc_version: 5.6.2 +mcc_core_version: 5.8.2 +content_manager_version: 6.0.2 +is_mcc_offline: false +is_using_prerelease_versions: false +mcc_content_registries: https://registry.npmjs.org/ +device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, + version: Bundled} +packs: {name: SAMC21_DFP, version: 3.8.119} +modules: +- {name: csp, type: HARMONY, version: v3.23.0} +- {name: CMSIS_5, type: HARMONY, version: 5.9.1-dev} diff --git a/bms/bms/bms_config/mcc/mcc.vscode b/bms/bms/bms_config/mcc/mcc.vscode new file mode 100644 index 00000000..334f0efb --- /dev/null +++ b/bms/bms/bms_config/mcc/mcc.vscode @@ -0,0 +1,11 @@ +# This file has been autogenerated by MCC. Please do not edit this file. + +configName: bms_config +fileVersion: 1.0.0 +device: ATSAMC21J18A +associatedIDEProjects: + MPLAB: + - name: bms + path: ../../.vscode + config: default + device: ATSAMC21J18A diff --git a/bms/bms/cmake/bms/default/CMakeLists.txt b/bms/bms/cmake/bms/default/CMakeLists.txt new file mode 100644 index 00000000..0d8a1629 --- /dev/null +++ b/bms/bms/cmake/bms/default/CMakeLists.txt @@ -0,0 +1,22 @@ + +# This CMakeLists.txt is generated. +# Do not modify directly. +# If you want to customize cmake behavior create a user.cmake in this +# directory and add it to your version control system. + +if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/user.cmake) + include(user.cmake) +endif() + +# format v1.00 +# { + +cmake_minimum_required(VERSION 3.24.0) +set(CMAKE_SYSTEM_NAME "Generic") + +project(bms_default_project LANGUAGES C CXX ASM) + +include("${CMAKE_CURRENT_LIST_DIR}/.generated/main.cmake") + +# } + diff --git a/bms/bms/cmake/bms/default/CMakePresets.json b/bms/bms/cmake/bms/default/CMakePresets.json new file mode 100644 index 00000000..7bcc3148 --- /dev/null +++ b/bms/bms/cmake/bms/default/CMakePresets.json @@ -0,0 +1,21 @@ +{ + "version": 6, + "configurePresets": [ + { + "name": "bms_default_conf", + "binaryDir": "${fileDir}/../../../_build/bms/default", + "generator": "Ninja", + "toolchainFile": "${fileDir}/.generated/toolchain.cmake", + "cacheVariables": { + "CMAKE_USER_MAKE_RULES_OVERRIDE": { + "type": "FILEPATH", + "value": "${fileDir}/.generated/overrides.cmake" + }, + "CMAKE_EXPORT_COMPILE_COMMANDS": { + "type": "BOOL", + "value": "ON" + } + } + } + ] +} \ No newline at end of file diff --git a/bms/bms/main.c b/bms/bms/main.c new file mode 100644 index 00000000..7d073795 --- /dev/null +++ b/bms/bms/main.c @@ -0,0 +1,12 @@ +/** + * @file main.c + * @author alihs + * @date 2025-10-05 + * @brief Main function + */ +int main(){ + + // Add your code here and press Ctrl + Shift + B to build + + return 0; +} From 2e3a141d502faddac0af6a3f36d399891ae3d258 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 9 Oct 2025 17:43:10 +0200 Subject: [PATCH 02/30] feat: peripheral configs --- .../bms_config_default/components/adc0.yml | 34 +- .../bms_config_default/components/adc1.yml | 207 ++ .../bms_config_default/components/can0.yml | 312 +- .../bms_config_default/components/core.yml | 455 ++- .../mcc/bms_config_default/components/dfp.yml | 13 +- .../bms_config_default/components/evsys.yml | 4 +- .../bms_config_default/components/nvmctrl.yml | 4 +- .../bms_config_default/components/sercom1.yml | 308 ++ .../bms_config_default/components/sercom4.yml | 275 ++ .../bms_config_default/components/stdio.yml | 64 + .../mcc/bms_config_default/mcc-config.mc4 | 262 +- .../bms_config/mcc/mcc-manifest-autosave.yml | 4 +- .../mcc/mcc-manifest-generated-success.yml | 22 + .../src/config/default/ATSAMC21J18A.ld | 241 ++ .../src/config/default/definitions.h | 149 + .../bms_config/src/config/default/device.h | 65 + .../src/config/default/device_cache.h | 94 + .../src/config/default/device_vectors.h | 118 + .../src/config/default/exceptions.c | 89 + .../default/harmony-manifest-success.yml | 22 + .../src/config/default/initialization.c | 191 ++ .../src/config/default/interrupts.c | 169 ++ .../src/config/default/interrupts.h | 67 + .../src/config/default/libc_syscalls.c | 61 + .../config/default/peripheral/adc/plib_adc0.c | 228 ++ .../config/default/peripheral/adc/plib_adc0.h | 127 + .../config/default/peripheral/adc/plib_adc1.c | 228 ++ .../config/default/peripheral/adc/plib_adc1.h | 127 + .../default/peripheral/adc/plib_adc_common.h | 156 + .../config/default/peripheral/can/plib_can0.c | 911 ++++++ .../config/default/peripheral/can/plib_can0.h | 123 + .../default/peripheral/can/plib_can_common.h | 668 +++++ .../default/peripheral/clock/plib_clock.c | 148 + .../default/peripheral/clock/plib_clock.h | 143 + .../default/peripheral/evsys/plib_evsys.c | 52 + .../default/peripheral/evsys/plib_evsys.h | 68 + .../default/peripheral/nvic/plib_nvic.c | 121 + .../default/peripheral/nvic/plib_nvic.h | 72 + .../default/peripheral/nvmctrl/plib_nvmctrl.c | 260 ++ .../default/peripheral/nvmctrl/plib_nvmctrl.h | 137 + .../default/peripheral/port/plib_port.c | 309 ++ .../default/peripheral/port/plib_port.h | 999 +++++++ .../i2c_master/plib_sercom1_i2c_master.c | 680 +++++ .../i2c_master/plib_sercom1_i2c_master.h | 104 + .../plib_sercom_i2c_master_common.h | 260 ++ .../sercom/usart/plib_sercom4_usart.c | 454 +++ .../sercom/usart/plib_sercom4_usart.h | 115 + .../sercom/usart/plib_sercom_usart_common.h | 405 +++ .../src/config/default/startup_xc32.c | 145 + .../src/config/default/stdio/xc32_monitor.c | 73 + .../src/config/default/toolchain_specifics.h | 61 + bms/bms/bms_config/src/main.c | 57 + .../src/packs/ATSAMC21J18A_DFP/component/ac.h | 490 ++++ .../packs/ATSAMC21J18A_DFP/component/adc.h | 523 ++++ .../packs/ATSAMC21J18A_DFP/component/can.h | 2527 +++++++++++++++++ .../packs/ATSAMC21J18A_DFP/component/ccl.h | 217 ++ .../packs/ATSAMC21J18A_DFP/component/dac.h | 216 ++ .../packs/ATSAMC21J18A_DFP/component/divas.h | 126 + .../packs/ATSAMC21J18A_DFP/component/dmac.h | 882 ++++++ .../packs/ATSAMC21J18A_DFP/component/dsu.h | 424 +++ .../packs/ATSAMC21J18A_DFP/component/eic.h | 333 +++ .../packs/ATSAMC21J18A_DFP/component/evsys.h | 552 ++++ .../packs/ATSAMC21J18A_DFP/component/freqm.h | 150 + .../packs/ATSAMC21J18A_DFP/component/fuses.h | 277 ++ .../packs/ATSAMC21J18A_DFP/component/gclk.h | 395 +++ .../ATSAMC21J18A_DFP/component/hmatrixb.h | 348 +++ .../packs/ATSAMC21J18A_DFP/component/mclk.h | 309 ++ .../packs/ATSAMC21J18A_DFP/component/mtb.h | 235 ++ .../ATSAMC21J18A_DFP/component/nvmctrl.h | 273 ++ .../ATSAMC21J18A_DFP/component/osc32kctrl.h | 269 ++ .../ATSAMC21J18A_DFP/component/oscctrl.h | 527 ++++ .../packs/ATSAMC21J18A_DFP/component/pac.h | 470 +++ .../src/packs/ATSAMC21J18A_DFP/component/pm.h | 80 + .../packs/ATSAMC21J18A_DFP/component/port.h | 338 +++ .../packs/ATSAMC21J18A_DFP/component/ptc.h | 39 + .../packs/ATSAMC21J18A_DFP/component/rstc.h | 65 + .../packs/ATSAMC21J18A_DFP/component/rtc.h | 1050 +++++++ .../packs/ATSAMC21J18A_DFP/component/sdadc.h | 429 +++ .../packs/ATSAMC21J18A_DFP/component/sercom.h | 1957 +++++++++++++ .../packs/ATSAMC21J18A_DFP/component/supc.h | 328 +++ .../src/packs/ATSAMC21J18A_DFP/component/tc.h | 589 ++++ .../packs/ATSAMC21J18A_DFP/component/tcc.h | 1344 +++++++++ .../packs/ATSAMC21J18A_DFP/component/tsens.h | 279 ++ .../packs/ATSAMC21J18A_DFP/component/wdt.h | 223 ++ .../src/packs/ATSAMC21J18A_DFP/instance/ac.h | 36 + .../packs/ATSAMC21J18A_DFP/instance/adc0.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/adc1.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/can0.h | 35 + .../packs/ATSAMC21J18A_DFP/instance/can1.h | 35 + .../src/packs/ATSAMC21J18A_DFP/instance/ccl.h | 35 + .../src/packs/ATSAMC21J18A_DFP/instance/dac.h | 33 + .../packs/ATSAMC21J18A_DFP/instance/divas.h | 27 + .../packs/ATSAMC21J18A_DFP/instance/dmac.h | 42 + .../src/packs/ATSAMC21J18A_DFP/instance/dsu.h | 31 + .../src/packs/ATSAMC21J18A_DFP/instance/eic.h | 35 + .../packs/ATSAMC21J18A_DFP/instance/evsys.h | 51 + .../packs/ATSAMC21J18A_DFP/instance/freqm.h | 33 + .../packs/ATSAMC21J18A_DFP/instance/fuses.h | 27 + .../packs/ATSAMC21J18A_DFP/instance/gclk.h | 47 + .../ATSAMC21J18A_DFP/instance/hmatrixhs.h | 44 + .../packs/ATSAMC21J18A_DFP/instance/mclk.h | 35 + .../src/packs/ATSAMC21J18A_DFP/instance/mtb.h | 31 + .../packs/ATSAMC21J18A_DFP/instance/nvmctrl.h | 54 + .../ATSAMC21J18A_DFP/instance/osc32kctrl.h | 32 + .../packs/ATSAMC21J18A_DFP/instance/oscctrl.h | 36 + .../src/packs/ATSAMC21J18A_DFP/instance/pac.h | 33 + .../src/packs/ATSAMC21J18A_DFP/instance/pm.h | 33 + .../packs/ATSAMC21J18A_DFP/instance/port.h | 37 + .../src/packs/ATSAMC21J18A_DFP/instance/ptc.h | 39 + .../packs/ATSAMC21J18A_DFP/instance/rstc.h | 32 + .../src/packs/ATSAMC21J18A_DFP/instance/rtc.h | 36 + .../packs/ATSAMC21J18A_DFP/instance/sdadc.h | 34 + .../packs/ATSAMC21J18A_DFP/instance/sercom0.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/sercom1.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/sercom2.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/sercom3.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/sercom4.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/sercom5.h | 37 + .../packs/ATSAMC21J18A_DFP/instance/supc.h | 34 + .../src/packs/ATSAMC21J18A_DFP/instance/tc0.h | 39 + .../src/packs/ATSAMC21J18A_DFP/instance/tc1.h | 39 + .../src/packs/ATSAMC21J18A_DFP/instance/tc2.h | 39 + .../src/packs/ATSAMC21J18A_DFP/instance/tc3.h | 39 + .../src/packs/ATSAMC21J18A_DFP/instance/tc4.h | 39 + .../packs/ATSAMC21J18A_DFP/instance/tcc0.h | 47 + .../packs/ATSAMC21J18A_DFP/instance/tcc1.h | 45 + .../packs/ATSAMC21J18A_DFP/instance/tcc2.h | 45 + .../packs/ATSAMC21J18A_DFP/instance/tsens.h | 33 + .../src/packs/ATSAMC21J18A_DFP/instance/wdt.h | 31 + .../packs/ATSAMC21J18A_DFP/pio/samc21j18a.h | 2035 +++++++++++++ .../src/packs/ATSAMC21J18A_DFP/samc21j18a.h | 683 +++++ .../CMSIS/CMSIS/Core/Include/cachel1_armv7.h | 411 +++ .../CMSIS/CMSIS/Core/Include/cmsis_armcc.h | 888 ++++++ .../CMSIS/CMSIS/Core/Include/cmsis_armclang.h | 1503 ++++++++++ .../CMSIS/Core/Include/cmsis_armclang_ltm.h | 1928 +++++++++++++ .../CMSIS/CMSIS/Core/Include/cmsis_compiler.h | 283 ++ .../CMSIS/CMSIS/Core/Include/cmsis_gcc.h | 2211 ++++++++++++++ .../CMSIS/CMSIS/Core/Include/cmsis_iccarm.h | 1002 +++++++ .../CMSIS/CMSIS/Core/Include/cmsis_version.h | 39 + .../CMSIS/CMSIS/Core/Include/core_cm0plus.h | 1087 +++++++ .../CMSIS/CMSIS/Core/Include/mpu_armv7.h | 275 ++ bms/bms/main.c | 12 - 142 files changed, 40724 insertions(+), 27 deletions(-) create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml create mode 100644 bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml create mode 100644 bms/bms/bms_config/src/config/default/ATSAMC21J18A.ld create mode 100644 bms/bms/bms_config/src/config/default/definitions.h create mode 100644 bms/bms/bms_config/src/config/default/device.h create mode 100644 bms/bms/bms_config/src/config/default/device_cache.h create mode 100644 bms/bms/bms_config/src/config/default/device_vectors.h create mode 100644 bms/bms/bms_config/src/config/default/exceptions.c create mode 100644 bms/bms/bms_config/src/config/default/harmony-manifest-success.yml create mode 100644 bms/bms/bms_config/src/config/default/initialization.c create mode 100644 bms/bms/bms_config/src/config/default/interrupts.c create mode 100644 bms/bms/bms_config/src/config/default/interrupts.h create mode 100644 bms/bms/bms_config/src/config/default/libc_syscalls.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h create mode 100644 bms/bms/bms_config/src/config/default/startup_xc32.c create mode 100644 bms/bms/bms_config/src/config/default/stdio/xc32_monitor.c create mode 100644 bms/bms/bms_config/src/config/default/toolchain_specifics.h create mode 100644 bms/bms/bms_config/src/main.c create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/adc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/can.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ccl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/divas.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dmac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dsu.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/eic.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/evsys.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/freqm.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/fuses.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/gclk.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/hmatrixb.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/mclk.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/mtb.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/nvmctrl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/osc32kctrl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/oscctrl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/pac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/pm.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/port.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ptc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/rstc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/rtc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/sdadc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/sercom.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/supc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/tc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/tcc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/tsens.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/wdt.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/ac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/adc0.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/adc1.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/can0.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/can1.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/ccl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/dac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/divas.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/dmac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/dsu.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/eic.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/evsys.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/freqm.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/fuses.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/gclk.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/hmatrixhs.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/mclk.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/mtb.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/nvmctrl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/osc32kctrl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/oscctrl.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/pac.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/pm.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/port.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/ptc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/rstc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/rtc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sdadc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sercom0.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sercom1.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sercom2.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sercom3.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sercom4.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/sercom5.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/supc.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tc0.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tc1.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tc2.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tc3.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tc4.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tcc0.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tcc1.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tcc2.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/tsens.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/instance/wdt.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/pio/samc21j18a.h create mode 100644 bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/samc21j18a.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h create mode 100644 bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h delete mode 100644 bms/bms/main.c diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml index 62058303..f745043b 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml @@ -22,8 +22,8 @@ data: - children: - attributes: id: adc0 - x: '37' - y: '233' + x: '30' + y: '216' type: ElementPosition type: ElementPositions type: ComponentGraph @@ -204,4 +204,34 @@ data: type: Dynamic type: Values type: String + ADC_CTRLB_PRESCALER: + attributes: + id: ADC_CTRLB_PRESCALER + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + ADC_CTRLC_DIFFMODE: + attributes: + id: ADC_CTRLC_DIFFMODE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + ADC_CONV_TRIGGER: + attributes: + id: ADC_CONV_TRIGGER + children: + - children: + - attributes: + value: SW Trigger + type: User + type: Values + type: Combo userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml new file mode 100644 index 00000000..e001386a --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml @@ -0,0 +1,207 @@ +configVersion: 1.0.0 +componentName: adc1 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc1 + x: '30' + y: '148' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc1 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc1 + value: ADC1_RESRDY_IRQn + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml index f5b68f49..b66d0283 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml @@ -22,10 +22,316 @@ data: - children: - attributes: id: can0 - x: '197' - y: '235' + x: '196' + y: '220' type: ElementPosition type: ElementPositions type: ComponentGraph - symbols: {} + symbols: + NBTP_NBRP: + attributes: + id: NBTP_NBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + type: Values + type: Integer + NOMINAL_SAMPLE_POINT: + attributes: + id: NOMINAL_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '96.875' + type: Dynamic + type: Values + type: Float + NBTP_TOTAL_TIME_QUANTA: + attributes: + id: NBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '32' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG1: + attributes: + id: NBTP_NTSEG1 + children: + - children: + - attributes: + id: can0 + value: '30' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG2: + attributes: + id: NBTP_NTSEG2 + children: + - children: + - attributes: + id: can0 + value: '1' + type: Dynamic + type: Values + type: Integer + NBTP_NSJW: + attributes: + id: NBTP_NSJW + children: + - children: + - attributes: + id: can0 + value: '1' + type: Dynamic + type: Values + type: Integer + CALCULATED_NOMINAL_BITRATE: + attributes: + id: CALCULATED_NOMINAL_BITRATE + children: + - children: + - attributes: + id: can0 + value: '500' + type: Dynamic + type: Values + type: Integer + NOMINAL_TIME_QUANTA_PERIOD: + attributes: + id: NOMINAL_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '62.500' + type: Dynamic + type: Values + type: String + CALCULATED_NOMINAL_ERRORRATE: + attributes: + id: CALCULATED_NOMINAL_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + AUTO_NOMINAL_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_NOMINAL_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + DBTP_TOTAL_TIME_QUANTA: + attributes: + id: DBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '8' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG1: + attributes: + id: DBTP_DTSEG1 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG2: + attributes: + id: DBTP_DTSEG2 + children: + - children: + - attributes: + id: can0 + value: '1' + type: Dynamic + type: Values + type: Integer + DBTP_DSJW: + attributes: + id: DBTP_DSJW + children: + - children: + - attributes: + id: can0 + value: '1' + type: Dynamic + type: Values + type: Integer + CALCULATED_DATA_BITRATE: + attributes: + id: CALCULATED_DATA_BITRATE + children: + - children: + - attributes: + id: can0 + value: '2000' + type: Dynamic + type: Values + type: Integer + DATA_TIME_QUANTA_PERIOD: + attributes: + id: DATA_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '62.500' + type: Dynamic + type: Values + type: String + CALCULATED_DATA_ERRORRATE: + attributes: + id: CALCULATED_DATA_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + CAN_OPMODE: + attributes: + id: CAN_OPMODE + children: + - children: + - attributes: + value: CAN FD + type: User + type: Values + type: Combo + instHeaderFile: + attributes: + id: instHeaderFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_interrupt.h.ftl + type: String + type: Attributes + type: File + sourceFile: + attributes: + id: sourceFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_interrupt.c.ftl + type: String + type: Attributes + type: File + INTERRUPT_MODE: + attributes: + id: INTERRUPT_MODE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + DBTP_DBRP: + attributes: + id: DBTP_DBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + type: Values + type: Integer + DATA_SAMPLE_POINT: + attributes: + id: DATA_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '87.5' + type: Dynamic + type: Values + type: Float + AUTO_DATA_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_DATA_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + DATA_BITRATE: + attributes: + id: DATA_BITRATE + children: + - children: + - attributes: + value: '2000' + type: User + type: Values + type: Integer userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index fac3385d..eefe1ac3 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -15,7 +15,18 @@ dependency: customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData data: attachments: {} - elementPosition: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: core + x: '80' + y: '4' + type: ElementPosition + type: ElementPositions + type: ComponentGraph symbols: ADC0_CLOCK_ENABLE: attributes: @@ -167,7 +178,7 @@ data: - children: - attributes: id: core - value: '0x20000' + value: '0x60024' type: Dynamic type: Values type: String @@ -281,6 +292,446 @@ data: type: Dynamic type: Values type: Boolean + ADC1_CLOCK_FREQUENCY: + attributes: + id: ADC1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_FREQ: + attributes: + id: GCLK_ID_34_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_CHEN: + attributes: + id: GCLK_ID_34_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_ENABLE: + attributes: + id: ADC1_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_CLOCK_FREQUENCY: + attributes: + id: CAN1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_FREQ: + attributes: + id: GCLK_ID_27_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_CHEN: + attributes: + id: GCLK_ID_27_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM1_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_FREQ: + attributes: + id: GCLK_ID_20_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_CHEN: + attributes: + id: GCLK_ID_20_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_ENABLE: + attributes: + id: NVIC_10_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER_LOCK: + attributes: + id: NVIC_10_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER: + attributes: + id: NVIC_10_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + CAN1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_16_0_ENABLE: + attributes: + id: NVIC_16_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_16_0_HANDLER: + attributes: + id: NVIC_16_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN1_Handler + type: Dynamic + type: Values + type: String + NVIC_16_0_HANDLER_LOCK: + attributes: + id: NVIC_16_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_ENABLE: + attributes: + id: NVIC_15_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE: + attributes: + id: CAN0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_HANDLER: + attributes: + id: NVIC_15_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + CAN0_INTERRUPT_HANDLER: + attributes: + id: CAN0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: can0 + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_15_0_HANDLER_LOCK: + attributes: + id: NVIC_15_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_HANDLER_LOCK: + attributes: + id: CAN0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM4_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_FREQ: + attributes: + id: GCLK_ID_23_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_CHEN: + attributes: + id: GCLK_ID_23_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM4_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_ENABLE: + attributes: + id: NVIC_13_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER_LOCK: + attributes: + id: NVIC_13_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM4_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER: + attributes: + id: NVIC_13_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM4_INTERRUPT_HANDLER: + attributes: + id: SERCOM4_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom4 + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM1_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM1_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER: + attributes: + id: SERCOM1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom1 + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml b/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml index 5993bb4c..f1de5cb7 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml @@ -15,6 +15,17 @@ dependency: customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData data: attachments: {} - elementPosition: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: dfp + x: '520' + y: '11' + type: ElementPosition + type: ElementPositions + type: ComponentGraph symbols: {} userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml index 8c05dd58..749f3a60 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml @@ -22,8 +22,8 @@ data: - children: - attributes: id: evsys - x: '281' - y: '61' + x: '202' + y: '10' type: ElementPosition type: ElementPositions type: ComponentGraph diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml b/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml index f489f102..d52779ca 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml @@ -22,8 +22,8 @@ data: - children: - attributes: id: nvmctrl - x: '438' - y: '69' + x: '339' + y: '7' type: ElementPosition type: ElementPositions type: ComponentGraph diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml new file mode 100644 index 00000000..5ebba36e --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml @@ -0,0 +1,308 @@ +configVersion: 1.0.0 +componentName: sercom1 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom1 + x: '368' + y: '153' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom1 + value: '232' + type: Dynamic + type: Values + type: Hex + I2C_CLOCK_SPEED_HZ: + attributes: + id: I2C_CLOCK_SPEED_HZ + children: + - children: + - attributes: + id: sercom1 + value: '100000' + type: Dynamic + type: Values + type: Integer + I2C_SCLSM: + attributes: + id: I2C_SCLSM + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + SERCOM_I2CM_HEADER: + attributes: + id: SERCOM_I2CM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_MASTER_HEADER: + attributes: + id: SERCOM_I2CM_MASTER_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_SOURCE: + attributes: + id: SERCOM_I2CM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '2' + type: User + type: Values + type: KeyValueSet + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom1 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom1 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml new file mode 100644 index 00000000..411058c4 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml @@ -0,0 +1,275 @@ +configVersion: 1.0.0 +componentName: sercom4 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom4 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: SERCOM4_I2C + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_SPI + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: stdio + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: UART + type: String + type: Attributes + type: DirectCapability + type: Attachments + type: sercom4 + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom4 + x: '60' + y: '344' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom4 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM4_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM4_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_OPERATING_MODE: + attributes: + id: USART_OPERATING_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom4 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml b/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml new file mode 100644 index 00000000..fe6cfec9 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml @@ -0,0 +1,64 @@ +configVersion: 1.0.0 +componentName: stdio +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: stdio + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: sercom4 + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: SERCOM4_UART + type: String + type: Attributes + type: DirectDependency + type: Attachments + type: stdio + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: stdio + x: '307' + y: '350' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + DEBUG_PERIPHERAL: + attributes: + id: DEBUG_PERIPHERAL + children: + - children: + - attributes: + id: stdio + value: sercom4 + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index 53db5149..b34a641e 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -7,10 +7,270 @@ deviceLibrary: groupModules: [] modules: - adc0 +- adc1 - can0 - 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Please do not edit this file. manifest_file_version: 1.0.0 -project: bms_config -creation_date: 2025-10-05T13:03:38.592+02:00[Europe/Oslo] +project: bms_config_default +creation_date: 2025-10-09T17:41:06.423+02:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml new file mode 100644 index 00000000..fbab818a --- /dev/null +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -0,0 +1,22 @@ +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. + +manifest_file_version: 1.0.0 +project: bms_config_default +creation_date: 2025-10-09T17:41:06.334+02:00[Europe/Oslo] +operating_system: Linux +mcc_mode: VSCodePlugin +mcc_mode_version: Unknown +device_name: ATSAMC21J18A +compiler: N/A +mcc_version: 5.6.2 +mcc_core_version: 5.8.2 +content_manager_version: 6.0.2 +is_mcc_offline: false +is_using_prerelease_versions: false +mcc_content_registries: https://registry.npmjs.org/ +device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, + version: Bundled} +packs: {name: SAMC21_DFP, version: 3.8.119} +modules: +- {name: csp, type: HARMONY, version: v3.23.0} +- {name: CMSIS_5, type: HARMONY, version: 5.9.1-dev} diff --git a/bms/bms/bms_config/src/config/default/ATSAMC21J18A.ld b/bms/bms/bms_config/src/config/default/ATSAMC21J18A.ld new file mode 100644 index 00000000..bf31bd85 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/ATSAMC21J18A.ld @@ -0,0 +1,241 @@ +/*-------------------------------------------------------------------------- + * MPLAB XC32 Compiler - ATSAMC21J18A linker script + * + * Copyright (c) 2022, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* + * Define the __XC32_RESET_HANDLER_NAME macro on the command line when you + * want to use a different name for the Reset Handler function. + */ +#ifndef __XC32_RESET_HANDLER_NAME +#define __XC32_RESET_HANDLER_NAME Reset_Handler +#endif /* __XC32_RESET_HANDLER_NAME */ + +/* Set the entry point in the ELF file. Once the entry point is in the ELF + * file, you can then use the --write-sla option to xc32-bin2hex to place + * the address into the hex file using the SLA field (RECTYPE 5). This hex + * record may be useful for a bootloader that needs to determine the entry + * point to the application. + */ +ENTRY(__XC32_RESET_HANDLER_NAME) + +/************************************************************************* + * Memory-Region Macro Definitions + * The XC32 linker preprocesses linker scripts. You may define these + * macros in the MPLAB X project properties or on the command line when + * calling the linker via the xc32-gcc shell. + *************************************************************************/ + +#ifndef ROM_ORIGIN +# define ROM_ORIGIN 0x0 +#endif +#ifndef ROM_LENGTH +# define ROM_LENGTH 0x40000 +#elif (ROM_LENGTH > 0x40000) +# error ROM_LENGTH is greater than the max size of 0x40000 +#endif +#ifndef RAM_ORIGIN +# define RAM_ORIGIN 0x20000000 +#endif +#ifndef RAM_LENGTH +# define RAM_LENGTH 0x8000 +#elif (RAM_LENGTH > 0x8000) +# error RAM_LENGTH is greater than the max size of 0x8000 +#endif + + +/************************************************************************* + * Memory-Region Definitions + * The MEMORY command describes the location and size of blocks of memory + * on the target device. The command below uses the macros defined above. + *************************************************************************/ +MEMORY +{ + rom (LRX) : ORIGIN = ROM_ORIGIN, LENGTH = ROM_LENGTH + ram (WX!R) : ORIGIN = RAM_ORIGIN, LENGTH = RAM_LENGTH + config_00804000 : ORIGIN = 0x00804000, LENGTH = 0x4 + config_00804004 : ORIGIN = 0x00804004, LENGTH = 0x4 + +} +/************************************************************************* + * Output region definitions. + * CODE_REGION defines the output region for .text/.rodata. + * DATA_REGION defines the output region for .data/.bss + * VECTOR_REGION defines the output region for .vectors. + * + * CODE_REGION defaults to 'rom', if rom is present (non-zero length), + * and 'ram' otherwise. + * DATA_REGION defaults to 'ram', which must be present. + * VECTOR_REGION defaults to CODE_REGION, unless 'boot_rom' is present. + */ +#ifndef CODE_REGION +# if ROM_LENGTH > 0 +# define CODE_REGION rom +# else +# define CODE_REGION ram +# endif +#endif +#ifndef DATA_REGION +# define DATA_REGION ram +#endif +#ifndef VECTOR_REGION +# define VECTOR_REGION CODE_REGION +#endif + +__rom_end = ORIGIN(rom) + LENGTH(rom); +__ram_end = ORIGIN(ram) + LENGTH(ram); + +/************************************************************************* + * Section Definitions - Map input sections to output sections + *************************************************************************/ +SECTIONS +{ + .config_00804000 : { + KEEP(*(.config_00804000)) + } > config_00804000 + .config_00804004 : { + KEEP(*(.config_00804004)) + } > config_00804004 + + /* + * The linker moves the .vectors section into itcm when itcm is + * enabled via the -mitcm option, but only when this .vectors output + * section exists in the linker script. + */ + .vectors : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.* .vectors_default .vectors_default.*)) + KEEP(*(.isr_vector)) + KEEP(*(.reset*)) + KEEP(*(.after_vectors)) + } > VECTOR_REGION + /* + * Code Sections - Note that standard input sections such as + * *(.text), *(.text.*), *(.rodata), & *(.rodata.*) + * are not mapped here. The best-fit allocator locates them, + * so that input sections may flow around absolute sections + * as needed. + */ + .text : + { + . = ALIGN(4); + *(.glue_7t) *(.glue_7) + *(.gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > CODE_REGION + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > CODE_REGION + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + + /* + * Align here to ensure that the .bss section occupies space up to + * _end. Align after .bss to ensure correct alignment even if the + * .bss section disappears because there are no input sections. + * + * Note that input sections named .bss* are no longer mapped here. + * The best-fit allocator locates them, so that they may flow + * around absolute sections as needed. + */ + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = . ; + _szero = .; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = . ; + _ezero = .; + } > DATA_REGION + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; + +} + diff --git a/bms/bms/bms_config/src/config/default/definitions.h b/bms/bms/bms_config/src/config/default/definitions.h new file mode 100644 index 00000000..3e0cb6ea --- /dev/null +++ b/bms/bms/bms_config/src/config/default/definitions.h @@ -0,0 +1,149 @@ +/******************************************************************************* + System Definitions + + File Name: + definitions.h + + Summary: + project system definitions. + + Description: + This file contains the system-wide prototypes and definitions for a project. + + *******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +//DOM-IGNORE-END + +#ifndef DEFINITIONS_H +#define DEFINITIONS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include +#include +#include +#include +#include "peripheral/nvmctrl/plib_nvmctrl.h" +#include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" +#include "peripheral/evsys/plib_evsys.h" +#include "peripheral/adc/plib_adc0.h" +#include "peripheral/port/plib_port.h" +#include "peripheral/clock/plib_clock.h" +#include "peripheral/nvic/plib_nvic.h" +#include "peripheral/adc/plib_adc1.h" +#include "peripheral/can/plib_can0.h" +#include "peripheral/sercom/usart/plib_sercom4_usart.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +/* Device Information */ +#define DEVICE_NAME "ATSAMC21J18A" +#define DEVICE_ARCH "CORTEX-M0PLUS" +#define DEVICE_FAMILY "SAMC" +#define DEVICE_SERIES "SAMC21" + +/* CPU clock frequency */ +#define CPU_CLOCK_FREQUENCY 48000000U + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* System Initialization Function + + Function: + void SYS_Initialize( void *data ) + + Summary: + Function that initializes all modules in the system. + + Description: + This function initializes all modules in the system, including any drivers, + services, middleware, and applications. + + Precondition: + None. + + Parameters: + data - Pointer to the data structure containing any data + necessary to initialize the module. This pointer may + be null if no data is required and default initialization + is to be used. + + Returns: + None. + + Example: + + SYS_Initialize ( NULL ); + + while ( true ) + { + SYS_Tasks ( ); + } + + + Remarks: + This function will only be called once, after system reset. +*/ + +void SYS_Initialize( void *data ); + +/* Nullify SYS_Tasks() if only PLIBs are used. */ +#define SYS_Tasks() + +// ***************************************************************************** +// ***************************************************************************** +// Section: extern declarations +// ***************************************************************************** +// ***************************************************************************** + + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* DEFINITIONS_H */ +/******************************************************************************* + End of File +*/ + diff --git a/bms/bms/bms_config/src/config/default/device.h b/bms/bms/bms_config/src/config/default/device.h new file mode 100644 index 00000000..4bd8fbbe --- /dev/null +++ b/bms/bms/bms_config/src/config/default/device.h @@ -0,0 +1,65 @@ +/******************************************************************************* + Device Header File + + Company: + Microchip Technology Inc. + + File Name: + device.h + + Summary: + This file includes the selected device from within the project. + The device will provide access to respective device packs. + + Description: + None + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_H +#define DEVICE_H + +#pragma GCC diagnostic push +#ifndef __cplusplus +#pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#ifndef DONT_USE_PREDEFINED_CORE_HANDLERS + #define DONT_USE_PREDEFINED_CORE_HANDLERS +#endif //DONT_USE_PREDEFINED_CORE_HANDLERS +#ifndef DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#endif //DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#include "samc21j18a.h" +#pragma GCC diagnostic pop +#include "device_cache.h" +#include "toolchain_specifics.h" + +#endif //DEVICE_H diff --git a/bms/bms/bms_config/src/config/default/device_cache.h b/bms/bms/bms_config/src/config/default/device_cache.h new file mode 100644 index 00000000..802e5dc5 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/device_cache.h @@ -0,0 +1,94 @@ +/******************************************************************************* + Cortex-M L1 Cache Header + + File Name: + device_cache.h + + Summary: + Preprocessor definitions to provide L1 Cache control. + + Description: + An MPLAB PLIB or Project can include this header to perform cache cleans, + invalidates etc. For the DCache and ICache. + + Remarks: + This header should not define any prototypes or data definitions, or + include any files that do. The file only provides macro definitions for + build-time. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_CACHE_H +#define DEVICE_CACHE_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section Includes other configuration headers necessary to completely + define this configuration. +*/ + +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: L1 Cache Configuration +// ***************************************************************************** +// ***************************************************************************** + + +#define ICACHE_ENABLE() +#define ICACHE_DISABLE() +#define ICACHE_INVALIDATE() + +#define DCACHE_ENABLE() +#define DCACHE_DISABLE() +#define DCACHE_INVALIDATE() +#define DCACHE_CLEAN() +#define DCACHE_CLEAN_INVALIDATE() +#define DCACHE_CLEAN_BY_ADDR(addr,sz) +#define DCACHE_INVALIDATE_BY_ADDR(addr,sz) +#define DCACHE_CLEAN_INVALIDATE_BY_ADDR(addr,sz) + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif // #ifndef DEVICE_CACHE_H diff --git a/bms/bms/bms_config/src/config/default/device_vectors.h b/bms/bms/bms_config/src/config/default/device_vectors.h new file mode 100644 index 00000000..750253d4 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/device_vectors.h @@ -0,0 +1,118 @@ +/******************************************************************************* + Cortex-M device vectors file + + Company: + Microchip Technology Inc. + + File Name: + device_vectors.h + + Summary: + Harmony3 device handler structure for cortex-M devices + + Description: + This file contains Harmony3 device handler structure for cortex-M devices + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_VECTORS_H +#define DEVICE_VECTORS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +/* Function pointer type for vector handlers */ +typedef void (*pfn_handler_t)(void); + +/* Structure defining device vector types */ +typedef struct H3DeviceVectorsTag +{ + /* Stack pointer */ + uint32_t* pvStack; + + /* CORTEX-M0PLUS handlers */ + pfn_handler_t pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + pfn_handler_t pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + pfn_handler_t pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + pfn_handler_t pfnReservedC12; + pfn_handler_t pfnReservedC11; + pfn_handler_t pfnReservedC10; + pfn_handler_t pfnReservedC9; + pfn_handler_t pfnReservedC8; + pfn_handler_t pfnReservedC7; + pfn_handler_t pfnReservedC6; + pfn_handler_t pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + pfn_handler_t pfnReservedC4; + pfn_handler_t pfnReservedC3; + pfn_handler_t pfnPendSV_Handler; /* -2 Pendable request for system service */ + pfn_handler_t pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + pfn_handler_t pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt */ + pfn_handler_t pfnWDT_Handler; /* 1 Watchdog Timer */ + pfn_handler_t pfnRTC_Handler; /* 2 Real Time Counter */ + pfn_handler_t pfnEIC_Handler; /* 3 External Interrupt Controller */ + pfn_handler_t pfnFREQM_Handler; /* 4 Frequency Meter */ + pfn_handler_t pfnTSENS_Handler; /* 5 Temperature Sensor */ + pfn_handler_t pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + pfn_handler_t pfnDMAC_Handler; /* 7 Direct Memory Controller */ + pfn_handler_t pfnEVSYS_Handler; /* 8 Event Systems */ + pfn_handler_t pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + pfn_handler_t pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + pfn_handler_t pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + pfn_handler_t pfnCAN0_Handler; /* 15 Control Area Network 0 */ + pfn_handler_t pfnCAN1_Handler; /* 16 Control Area Network 1 */ + pfn_handler_t pfnTCC0_Handler; /* 17 Timer/Counter for Control Applications 0 */ + pfn_handler_t pfnTCC1_Handler; /* 18 Timer/Counter for Control Applications 1 */ + pfn_handler_t pfnTCC2_Handler; /* 19 Timer/Counter for Control Applications 2 */ + pfn_handler_t pfnTC0_Handler; /* 20 Timer/Counter 0 */ + pfn_handler_t pfnTC1_Handler; /* 21 Timer/Counter 1 */ + pfn_handler_t pfnTC2_Handler; /* 22 Timer/Counter 2 */ + pfn_handler_t pfnTC3_Handler; /* 23 Timer/Counter 3 */ + pfn_handler_t pfnTC4_Handler; /* 24 Timer/Counter 4 */ + pfn_handler_t pfnADC0_Handler; /* 25 Analog-to-Digital Converter 0 */ + pfn_handler_t pfnADC1_Handler; /* 26 Analog-to-Digital Converter 1 */ + pfn_handler_t pfnAC_Handler; /* 27 Analog Comparators */ + pfn_handler_t pfnDAC_Handler; /* 28 Digital-to-Analog Converter */ + pfn_handler_t pfnSDADC_Handler; /* 29 Sigma-Delat Analog-to-Digital Converter */ + pfn_handler_t pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +}H3DeviceVectors; + +#endif //DEVICE_VECTORS_H diff --git a/bms/bms/bms_config/src/config/default/exceptions.c b/bms/bms/bms_config/src/config/default/exceptions.c new file mode 100644 index 00000000..664dd4ad --- /dev/null +++ b/bms/bms/bms_config/src/config/default/exceptions.c @@ -0,0 +1,89 @@ +/******************************************************************************* + System Exceptions File + + File Name: + exceptions.c + + Summary: + This file contains a function which overrides the default _weak_ exception + handlers provided by the interrupt.c file. + + Description: + This file redefines the default _weak_ exception handler with a more debug + friendly one. If an unexpected exception occurs the code will stop in a + while(1) loop. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "definitions.h" + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Exception Handling Routine +// ***************************************************************************** +// ***************************************************************************** +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 might be violated here if the users provide a strong + implementations to these weak handler functions. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 +*/ + + +/* Brief default interrupt handlers for core IRQs.*/ +void __attribute__((noreturn, weak)) NonMaskableInt_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn, weak)) HardFault_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + + +/* MISRAC 2012 deviation block end for rule 8.6 */ + +/******************************************************************************* + End of File + */ diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml new file mode 100644 index 00000000..24fec660 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -0,0 +1,22 @@ + +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. +# Project "bms_config_default" has been created by using mentioned Harmony 3 packages + + +project: bms_config_default +creation_date: 2025-10-09T17:41:06.372+02:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +operating_system: Linux +mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] +mcc_version: v5.6.2 +mcc_core_version: v5.8.2 +mplabx_version: NA # if MPLAB X plugin only +harmony_version: v5.6.2 +compiler: NA + +modules: + - {name: "csp", version: "v3.23.0"} + - {name: "CMSIS_5", version: "5.9.1-dev"} + +packs: + - {name: "SAMC21_DFP", version: "3.8.119"} + diff --git a/bms/bms/bms_config/src/config/default/initialization.c b/bms/bms/bms_config/src/config/default/initialization.c new file mode 100644 index 00000000..1759e1f1 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/initialization.c @@ -0,0 +1,191 @@ +/******************************************************************************* + System Initialization File + + File Name: + initialization.c + + Summary: + This file contains source code necessary to initialize the system. + + Description: + This file contains source code necessary to initialize the system. It + implements the "SYS_Initialize" function, defines the configuration bits, + and allocates any necessary global system resources, + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "definitions.h" +#include "device.h" + + +// **************************************************************************** +// **************************************************************************** +// Section: Configuration Bits +// **************************************************************************** +// **************************************************************************** +#pragma config NVMCTRL_BOOTPROT = SIZE_0BYTES +#pragma config NVMCTRL_EEPROM_SIZE = SIZE_0BYTES +#pragma config BODVDDUSERLEVEL = 0x8U // Enter Hexadecimal value +#pragma config BODVDD_DIS = DISABLED +#pragma config BODVDD_ACTION = NONE + +#pragma config BODVDD_HYST = DISABLED +#pragma config NVMCTRL_REGION_LOCKS = 0xffffU // Enter Hexadecimal value + +#pragma config WDT_ENABLE = DISABLED +#pragma config WDT_ALWAYSON = DISABLED +#pragma config WDT_PER = CYC8 + +#pragma config WDT_WINDOW = CYC8 +#pragma config WDT_EWOFFSET = CYC8 +#pragma config WDT_WEN = DISABLED + + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Driver Initialization Data +// ***************************************************************************** +// ***************************************************************************** +/* Following MISRA-C rules are deviated in the below code block */ +/* MISRA C-2012 Rule 7.2 - Deviation record ID - H3_MISRAC_2012_R_7_2_DR_1 */ +/* MISRA C-2012 Rule 11.1 - Deviation record ID - H3_MISRAC_2012_R_11_1_DR_1 */ +/* MISRA C-2012 Rule 11.3 - Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1 */ +/* MISRA C-2012 Rule 11.8 - Deviation record ID - H3_MISRAC_2012_R_11_8_DR_1 */ + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Data +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Library/Stack Initialization Data +// ***************************************************************************** +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Initialization +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local initialization functions +// ***************************************************************************** +// ***************************************************************************** + +/******************************************************************************* + Function: + void STDIO_BufferModeSet ( void ) + + Summary: + Sets the buffering mode for stdin and stdout + + Remarks: + ********************************************************************************/ +static void STDIO_BufferModeSet(void) +{ + /* MISRAC 2012 deviation block start */ + /* MISRA C-2012 Rule 21.6 deviated 2 times in this file. Deviation record ID - H3_MISRAC_2012_R_21_6_DR_3 */ + + /* Make stdin unbuffered */ + setbuf(stdin, NULL); + + /* Make stdout unbuffered */ + setbuf(stdout, NULL); + /* MISRAC 2012 deviation block end */ +} + + +/* MISRAC 2012 deviation block end */ + +/******************************************************************************* + Function: + void SYS_Initialize ( void *data ) + + Summary: + Initializes the board, services, drivers, application and other modules. + + Remarks: + */ + +void SYS_Initialize ( void* data ) +{ + + /* MISRAC 2012 deviation block start */ + /* MISRA C-2012 Rule 2.2 deviated in this file. Deviation record ID - H3_MISRAC_2012_R_2_2_DR_1 */ + + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_RWS(3UL); + + STDIO_BufferModeSet(); + + + + + CLOCK_Initialize(); + + + + + NVMCTRL_Initialize( ); + + SERCOM1_I2C_Initialize(); + + EVSYS_Initialize(); + + + ADC0_Initialize(); + + ADC1_Initialize(); + CAN0_Initialize(); + + SERCOM4_USART_Initialize(); + + + NVIC_Initialize(); + + + /* MISRAC 2012 deviation block end */ +} + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/interrupts.c b/bms/bms/bms_config/src/config/default/interrupts.c new file mode 100644 index 00000000..adda0b21 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/interrupts.c @@ -0,0 +1,169 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.c + + Summary: + Interrupt vectors mapping + + Description: + This file maps all the interrupt vectors to their corresponding + implementations. If a particular module interrupt is used, then its ISR + definition can be found in corresponding PLIB source file. If a module + interrupt is not used, then its ISR implementation is mapped to dummy + handler. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "device_vectors.h" +#include "interrupts.h" +#include "definitions.h" + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Interrupt Vector Functions +// ***************************************************************************** +// ***************************************************************************** + +/* MISRA C-2012 Rule 8.6 deviated below. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +extern uint32_t _stack; +extern const H3DeviceVectors exception_table; + +extern void Dummy_Handler(void); + +/* Brief default interrupt handler for unused IRQs.*/ +void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(void) +{ + while (true) + { + } +} + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 deviated 32 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* Device vectors list dummy definition*/ +extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SysTick_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SYSTEM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void WDT_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void RTC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void EIC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void NVMCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void DMAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void EVSYS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SERCOM0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SERCOM2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SERCOM3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SERCOM4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SERCOM5_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void CAN1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void ADC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void ADC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void AC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void DAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SDADC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void PTC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); + + +/* MISRAC 2012 deviation block end */ + +/* Multiple handlers for vector */ + + + +__attribute__ ((section(".vectors"), used)) +const H3DeviceVectors exception_table= +{ + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = &_stack, + + .pfnReset_Handler = Reset_Handler, + .pfnNonMaskableInt_Handler = NonMaskableInt_Handler, + .pfnHardFault_Handler = HardFault_Handler, + .pfnSVCall_Handler = SVCall_Handler, + .pfnPendSV_Handler = PendSV_Handler, + .pfnSysTick_Handler = SysTick_Handler, + .pfnSYSTEM_Handler = SYSTEM_Handler, + .pfnWDT_Handler = WDT_Handler, + .pfnRTC_Handler = RTC_Handler, + .pfnEIC_Handler = EIC_Handler, + .pfnFREQM_Handler = FREQM_Handler, + .pfnTSENS_Handler = TSENS_Handler, + .pfnNVMCTRL_Handler = NVMCTRL_Handler, + .pfnDMAC_Handler = DMAC_Handler, + .pfnEVSYS_Handler = EVSYS_Handler, + .pfnSERCOM0_Handler = SERCOM0_Handler, + .pfnSERCOM1_Handler = SERCOM1_I2C_InterruptHandler, + .pfnSERCOM2_Handler = SERCOM2_Handler, + .pfnSERCOM3_Handler = SERCOM3_Handler, + .pfnSERCOM4_Handler = SERCOM4_Handler, + .pfnSERCOM5_Handler = SERCOM5_Handler, + .pfnCAN0_Handler = CAN0_InterruptHandler, + .pfnCAN1_Handler = CAN1_Handler, + .pfnTCC0_Handler = TCC0_Handler, + .pfnTCC1_Handler = TCC1_Handler, + .pfnTCC2_Handler = TCC2_Handler, + .pfnTC0_Handler = TC0_Handler, + .pfnTC1_Handler = TC1_Handler, + .pfnTC2_Handler = TC2_Handler, + .pfnTC3_Handler = TC3_Handler, + .pfnTC4_Handler = TC4_Handler, + .pfnADC0_Handler = ADC0_Handler, + .pfnADC1_Handler = ADC1_Handler, + .pfnAC_Handler = AC_Handler, + .pfnDAC_Handler = DAC_Handler, + .pfnSDADC_Handler = SDADC_Handler, + .pfnPTC_Handler = PTC_Handler, + + +}; + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/interrupts.h b/bms/bms/bms_config/src/config/default/interrupts.h new file mode 100644 index 00000000..336ef6ce --- /dev/null +++ b/bms/bms/bms_config/src/config/default/interrupts.h @@ -0,0 +1,67 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.h + + Summary: + Interrupt vectors mapping + + Description: + This file contains declarations of device vectors used by Harmony 3 + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Handler Routines +// ***************************************************************************** +// ***************************************************************************** +void Reset_Handler (void); +void NonMaskableInt_Handler (void); +void HardFault_Handler (void); +void SERCOM1_I2C_InterruptHandler (void); +void CAN0_InterruptHandler (void); + + + +#endif // INTERRUPTS_H diff --git a/bms/bms/bms_config/src/config/default/libc_syscalls.c b/bms/bms/bms_config/src/config/default/libc_syscalls.c new file mode 100644 index 00000000..ae819a61 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/libc_syscalls.c @@ -0,0 +1,61 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include +#include "device.h" /* for ARM CMSIS __BKPT() */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated twice. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* Harmony specific + * We implement only the syscalls we want over the stubs provided by libpic32c + */ +extern void _exit(int status); + +void _exit(int status) +{ + /* Software breakpoint */ +#ifdef __DEBUG + __BKPT(0); +#endif + + /* halt CPU */ + while (true) + { + } +} + +#ifdef __cplusplus +} +#endif + +/* MISRAC 2012 deviation block end */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c new file mode 100644 index 00000000..1f7f4eb5 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c @@ -0,0 +1,228 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc0.c + + Summary + ADC0 PLIB Implementation File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "interrupts.h" +#include "plib_adc0.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +#define ADC0_LINEARITY_POS (0U) +#define ADC0_LINEARITY_Msk (0x7UL << ADC0_LINEARITY_POS) + +#define ADC0_BIASCAL_POS (3U) +#define ADC0_BIASCAL_Msk (0x7UL << ADC0_BIASCAL_POS) + + +// ***************************************************************************** +// ***************************************************************************** +// Section: ADC0 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize ADC module */ +void ADC0_Initialize( void ) +{ + /* Reset ADC */ + ADC0_REGS->ADC_CTRLA = (uint8_t)ADC_CTRLA_SWRST_Msk; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization */ + } + /* Write linearity calibration in BIASREFBUF and bias calibration in BIASCOMP */ + uint32_t calib_low_word = (uint32_t)(*(uint64_t*)OTP5_ADDR); + ADC0_REGS->ADC_CALIB = (uint16_t)((ADC_CALIB_BIASREFBUF((calib_low_word & ADC0_LINEARITY_Msk) >> ADC0_LINEARITY_POS)) | + (ADC_CALIB_BIASCOMP((calib_low_word & ADC0_BIASCAL_Msk) >> ADC0_BIASCAL_POS))); + + /* Prescaler */ + ADC0_REGS->ADC_CTRLB = (uint8_t)ADC_CTRLB_PRESCALER_DIV4; + /* Sampling length */ + ADC0_REGS->ADC_SAMPCTRL = (uint8_t)ADC_SAMPCTRL_SAMPLEN(3UL); + + /* Reference */ + ADC0_REGS->ADC_REFCTRL = (uint8_t)ADC_REFCTRL_REFSEL_INTVCC2 | ADC_REFCTRL_REFCOMP_Msk; + + /* Input pin */ + ADC0_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0; + + /* Resolution & Operation Mode */ + ADC0_REGS->ADC_CTRLC = (uint16_t)(ADC_CTRLC_RESSEL_12BIT | ADC_CTRLC_WINMODE(0UL) ); + + + /* Clear all interrupt flags */ + ADC0_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; + + while(0U != ADC0_REGS->ADC_SYNCBUSY) + { + /* Wait for Synchronization */ + } +} + +/* Enable ADC module */ +void ADC0_Enable( void ) +{ + ADC0_REGS->ADC_CTRLA |= (uint8_t)ADC_CTRLA_ENABLE_Msk; + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Disable ADC module */ +void ADC0_Disable( void ) +{ + ADC0_REGS->ADC_CTRLA &= (uint8_t)(~ADC_CTRLA_ENABLE_Msk); + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Configure channel input */ +void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) +{ + /* Configure pin scan mode and positive and negative input pins */ + ADC0_REGS->ADC_INPUTCTRL = (uint16_t) positiveInput | (uint16_t) negativeInput; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Start the ADC conversion by SW */ +void ADC0_ConversionStart( void ) +{ + /* Start conversion */ + ADC0_REGS->ADC_SWTRIG |= (uint8_t)ADC_SWTRIG_START_Msk; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Check whether auto sequence conversion is done */ +bool ADC0_ConversionSequenceIsFinished(void) +{ + bool seq_status = false; + if ((ADC0_REGS->ADC_SEQSTATUS & ADC_SEQSTATUS_SEQBUSY_Msk) != ADC_SEQSTATUS_SEQBUSY_Msk) + { + seq_status = true; + } + return seq_status; +} + +/* Configure window comparison threshold values */ +void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC0_REGS->ADC_WINLT = low_threshold; + ADC0_REGS->ADC_WINUT = high_threshold; + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) + { + /* Wait for Synchronization */ + } + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) + { + /* Wait for Synchronization */ + } +} + +void ADC0_WindowModeSet(ADC_WINMODE mode) +{ + ADC0_REGS->ADC_CTRLC = (ADC0_REGS->ADC_CTRLC & (uint16_t)(~ADC_CTRLC_WINMODE_Msk)) | (uint16_t)((uint32_t)mode << ADC_CTRLC_WINMODE_Pos); + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_CTRLC_Msk) == ADC_SYNCBUSY_CTRLC_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Read the conversion result */ +uint16_t ADC0_ConversionResultGet( void ) +{ + return (uint16_t)ADC0_REGS->ADC_RESULT; +} + +void ADC0_InterruptsClear(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTFLAG = (uint8_t)interruptMask; +} + +void ADC0_InterruptsEnable(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTENSET = (uint8_t)interruptMask; +} + +void ADC0_InterruptsDisable(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTENCLR = (uint8_t)interruptMask; +} + +/* Check whether result is ready */ +bool ADC0_ConversionStatusGet( void ) +{ + bool status; + status = (((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); + if (status == true) + { + ADC0_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_RESRDY_Msk; + } + return status; +} diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.h b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.h new file mode 100644 index 00000000..49ca4421 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.h @@ -0,0 +1,127 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc0.h + + Summary + ADC0 PLIB Header File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC0_H // Guards against multiple inclusion +#define PLIB_ADC0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_adc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +void ADC0_Initialize( void ); + +void ADC0_Enable( void ); + +void ADC0_Disable( void ); + +void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); + +void ADC0_ConversionStart( void ); + +uint16_t ADC0_ConversionResultGet( void ); + +void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); + +void ADC0_WindowModeSet(ADC_WINMODE mode); + +bool ADC0_ConversionSequenceIsFinished(void); + +void ADC0_InterruptsClear(ADC_STATUS interruptMask); + +void ADC0_InterruptsEnable(ADC_STATUS interruptMask); + +void ADC0_InterruptsDisable(ADC_STATUS interruptMask); + + +bool ADC0_ConversionStatusGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC0_H */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.c b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.c new file mode 100644 index 00000000..868eff15 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.c @@ -0,0 +1,228 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC1) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc1.c + + Summary + ADC1 PLIB Implementation File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "interrupts.h" +#include "plib_adc1.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +#define ADC1_LINEARITY_POS (6U) +#define ADC1_LINEARITY_Msk (0x7UL << ADC1_LINEARITY_POS) + +#define ADC1_BIASCAL_POS (9U) +#define ADC1_BIASCAL_Msk (0x7UL << ADC1_BIASCAL_POS) + + +// ***************************************************************************** +// ***************************************************************************** +// Section: ADC1 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize ADC module */ +void ADC1_Initialize( void ) +{ + /* Reset ADC */ + ADC1_REGS->ADC_CTRLA = (uint8_t)ADC_CTRLA_SWRST_Msk; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization */ + } + /* Write linearity calibration in BIASREFBUF and bias calibration in BIASCOMP */ + uint32_t calib_low_word = (uint32_t)(*(uint64_t*)OTP5_ADDR); + ADC1_REGS->ADC_CALIB = (uint16_t)((ADC_CALIB_BIASREFBUF((calib_low_word & ADC1_LINEARITY_Msk) >> ADC1_LINEARITY_POS)) | + (ADC_CALIB_BIASCOMP((calib_low_word & ADC1_BIASCAL_Msk) >> ADC1_BIASCAL_POS))); + + /* Prescaler */ + ADC1_REGS->ADC_CTRLB = (uint8_t)ADC_CTRLB_PRESCALER_DIV8; + /* Sampling length */ + ADC1_REGS->ADC_SAMPCTRL = (uint8_t)ADC_SAMPCTRL_SAMPLEN(3UL); + + /* Reference */ + ADC1_REGS->ADC_REFCTRL = (uint8_t)ADC_REFCTRL_REFSEL_INTVCC2 | ADC_REFCTRL_REFCOMP_Msk; + + /* Input pin */ + ADC1_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0; + + /* Resolution & Operation Mode */ + ADC1_REGS->ADC_CTRLC = (uint16_t)(ADC_CTRLC_RESSEL_12BIT | ADC_CTRLC_WINMODE(0UL) | ADC_CTRLC_FREERUN_Msk); + + + /* Clear all interrupt flags */ + ADC1_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; + + while(0U != ADC1_REGS->ADC_SYNCBUSY) + { + /* Wait for Synchronization */ + } +} + +/* Enable ADC module */ +void ADC1_Enable( void ) +{ + ADC1_REGS->ADC_CTRLA |= (uint8_t)ADC_CTRLA_ENABLE_Msk; + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Disable ADC module */ +void ADC1_Disable( void ) +{ + ADC1_REGS->ADC_CTRLA &= (uint8_t)(~ADC_CTRLA_ENABLE_Msk); + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Configure channel input */ +void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) +{ + /* Configure pin scan mode and positive and negative input pins */ + ADC1_REGS->ADC_INPUTCTRL = (uint16_t) positiveInput | (uint16_t) negativeInput; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Start the ADC conversion by SW */ +void ADC1_ConversionStart( void ) +{ + /* Start conversion */ + ADC1_REGS->ADC_SWTRIG |= (uint8_t)ADC_SWTRIG_START_Msk; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Check whether auto sequence conversion is done */ +bool ADC1_ConversionSequenceIsFinished(void) +{ + bool seq_status = false; + if ((ADC1_REGS->ADC_SEQSTATUS & ADC_SEQSTATUS_SEQBUSY_Msk) != ADC_SEQSTATUS_SEQBUSY_Msk) + { + seq_status = true; + } + return seq_status; +} + +/* Configure window comparison threshold values */ +void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC1_REGS->ADC_WINLT = low_threshold; + ADC1_REGS->ADC_WINUT = high_threshold; + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) + { + /* Wait for Synchronization */ + } + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) + { + /* Wait for Synchronization */ + } +} + +void ADC1_WindowModeSet(ADC_WINMODE mode) +{ + ADC1_REGS->ADC_CTRLC = (ADC1_REGS->ADC_CTRLC & (uint16_t)(~ADC_CTRLC_WINMODE_Msk)) | (uint16_t)((uint32_t)mode << ADC_CTRLC_WINMODE_Pos); + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_CTRLC_Msk) == ADC_SYNCBUSY_CTRLC_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Read the conversion result */ +uint16_t ADC1_ConversionResultGet( void ) +{ + return (uint16_t)ADC1_REGS->ADC_RESULT; +} + +void ADC1_InterruptsClear(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTFLAG = (uint8_t)interruptMask; +} + +void ADC1_InterruptsEnable(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTENSET = (uint8_t)interruptMask; +} + +void ADC1_InterruptsDisable(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTENCLR = (uint8_t)interruptMask; +} + +/* Check whether result is ready */ +bool ADC1_ConversionStatusGet( void ) +{ + bool status; + status = (((ADC1_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); + if (status == true) + { + ADC1_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_RESRDY_Msk; + } + return status; +} diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.h b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.h new file mode 100644 index 00000000..a0fa8afd --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc1.h @@ -0,0 +1,127 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC1) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc1.h + + Summary + ADC1 PLIB Header File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC1_H // Guards against multiple inclusion +#define PLIB_ADC1_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_adc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +void ADC1_Initialize( void ); + +void ADC1_Enable( void ); + +void ADC1_Disable( void ); + +void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); + +void ADC1_ConversionStart( void ); + +uint16_t ADC1_ConversionResultGet( void ); + +void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); + +void ADC1_WindowModeSet(ADC_WINMODE mode); + +bool ADC1_ConversionSequenceIsFinished(void); + +void ADC1_InterruptsClear(ADC_STATUS interruptMask); + +void ADC1_InterruptsEnable(ADC_STATUS interruptMask); + +void ADC1_InterruptsDisable(ADC_STATUS interruptMask); + + +bool ADC1_ConversionStatusGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC1_H */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h new file mode 100644 index 00000000..0d449e87 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h @@ -0,0 +1,156 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC) Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_adc_common.h + + Summary + ADC Peripheral Library Interface Header File. + + Description + This file defines the common types for the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC_COMMON_H // Guards against multiple inclusion +#define PLIB_ADC_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +#define ADC_STATUS_NONE 0U +#define ADC_STATUS_RESRDY ADC_INTFLAG_RESRDY_Msk +#define ADC_STATUS_WINMON ADC_INTFLAG_WINMON_Msk +#define ADC_STATUS_OVERRUN ADC_INTFLAG_OVERRUN_Msk +#define ADC_STATUS_MASK (ADC_STATUS_RESRDY | ADC_STATUS_OVERRUN | ADC_STATUS_WINMON) +#define ADC_STATUS_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +typedef enum +{ + ADC_POSINPUT_AIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, + ADC_POSINPUT_AIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, + ADC_POSINPUT_AIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, + ADC_POSINPUT_AIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, + ADC_POSINPUT_AIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, + ADC_POSINPUT_AIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, + ADC_POSINPUT_AIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, + ADC_POSINPUT_AIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, + ADC_POSINPUT_AIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, + ADC_POSINPUT_AIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, + ADC_POSINPUT_AIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, + ADC_POSINPUT_AIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, + ADC_POSINPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, + ADC_POSINPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, + ADC_POSINPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, + ADC_POSINPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, +}ADC_POSINPUT; + +// ***************************************************************************** + +typedef enum +{ + ADC_NEGINPUT_AIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, + ADC_NEGINPUT_AIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, + ADC_NEGINPUT_AIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, + ADC_NEGINPUT_AIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, + ADC_NEGINPUT_AIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, + ADC_NEGINPUT_AIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, + ADC_NEGINPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, +}ADC_NEGINPUT; + +typedef uint32_t ADC_STATUS; +typedef enum +{ + ADC_WINMODE_DISABLED = ADC_CTRLC_WINMODE_DISABLE_Val, + ADC_WINMODE_GREATER_THAN_WINLT = ADC_CTRLC_WINMODE_MODE1_Val, + ADC_WINMODE_LESS_THAN_WINUT = ADC_CTRLC_WINMODE_MODE2_Val, + ADC_WINMODE_BETWEEN_WINLT_AND_WINUT = ADC_CTRLC_WINMODE_MODE3_Val, + ADC_WINMODE_OUTSIDE_WINLT_AND_WINUT = ADC_CTRLC_WINMODE_MODE4_Val +}ADC_WINMODE; + + +// ***************************************************************************** + + +typedef void (*ADC_CALLBACK)(ADC_STATUS status, uintptr_t context); + + +typedef struct +{ + ADC_CALLBACK callback; + + uintptr_t context; + +} ADC_CALLBACK_OBJ; + + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC_COMMON_H*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c new file mode 100644 index 00000000..4431844a --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c @@ -0,0 +1,911 @@ +/******************************************************************************* + Controller Area Network (CAN) Peripheral Library Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_can0.c + + Summary: + CAN peripheral library interface. + + Description: + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Header Includes +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include "interrupts.h" +#include "plib_can0.h" + +// ***************************************************************************** +// ***************************************************************************** +// Global Data +// ***************************************************************************** +// ***************************************************************************** +#define CAN_STD_ID_Msk 0x7FFU + +static volatile CAN_TX_FIFO_CALLBACK_OBJ can0TxFifoCallbackObj; +static volatile CAN_TX_EVENT_FIFO_CALLBACK_OBJ can0TxEventFifoCallbackObj; +static volatile CAN_RX_FIFO_CALLBACK_OBJ can0RxFifoCallbackObj[2]; +static volatile CAN_CALLBACK_OBJ can0CallbackObj; +static volatile CAN_OBJ can0Obj; + +static inline void CAN0_ZeroInitialize(volatile void* pData, size_t dataSize) +{ + volatile uint8_t* data = (volatile uint8_t*)pData; + for (uint32_t index = 0; index < dataSize; index++) + { + data[index] = 0U; + } +} + +// ***************************************************************************** +// ***************************************************************************** +// CAN0 PLib Interface Routines +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void CAN0_Initialize(void) + + Summary: + Initializes given instance of the CAN peripheral. + + Precondition: + None. + + Parameters: + None. + + Returns: + None +*/ +void CAN0_Initialize(void) +{ + /* Start CAN initialization */ + CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + /* Set Data Bit Timing and Prescaler Register */ + CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(0UL) | CAN_DBTP_DTSEG1(5UL) | CAN_DBTP_DBRP(2UL) | CAN_DBTP_DSJW(0UL); + + /* Set Nominal Bit timing and Prescaler Register */ + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(0UL) | CAN_NBTP_NTSEG1(29UL) | CAN_NBTP_NBRP(2UL) | CAN_NBTP_NSJW(0UL); + + /* Receive Buffer / FIFO Element Size Configuration Register */ + CAN0_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(0UL) | CAN_RXESC_F1DS(0UL); + /* Transmit Buffer/FIFO Element Size Configuration Register */ + CAN0_REGS->CAN_TXESC = CAN_TXESC_TBDS(0UL); + + /* Global Filter Configuration Register */ + CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; + + /* Set the operation mode */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; + + + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Select interrupt line */ + CAN0_REGS->CAN_ILS = 0x0U; + + /* Enable interrupt line */ + CAN0_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; + + /* Enable CAN interrupts */ + CAN0_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk + | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk + | CAN_IE_TFEE_Msk + | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk + | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk + | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk + + | CAN_IE_MRAFE_Msk; + + CAN0_ZeroInitialize(&can0Obj.msgRAMConfig, sizeof(CAN_MSG_RAM_CONFIG)); +} + + +// ***************************************************************************** +/* Function: + bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) + + Summary: + Transmit multiple messages into CAN bus from Tx FIFO. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfMessage - Total number of message. + txBuffer - Pointer to Tx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) +{ + uint8_t *txFifo = NULL; + uint8_t *txBuf = (uint8_t *)txBuffer; + uint32_t bufferNumber = 0U; + uint8_t tfqpi = 0U; + uint8_t count = 0U; + bool transmitFifo_event = false; + + if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) + { + tfqpi = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + + for (count = 0U; count < numberOfMessage; count++) + { + txFifo = (uint8_t *)((uint8_t*)can0Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE)); + + (void) memcpy(txFifo, txBuf, CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE); + + txBuf += CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE; + bufferNumber |= (1UL << tfqpi); + tfqpi++; + if (tfqpi == 1U) + { + tfqpi = 0U; + } + } + + __DSB(); + + /* Set Transmission request */ + CAN0_REGS->CAN_TXBAR = bufferNumber; + + transmitFifo_event = true; + } + return transmitFifo_event; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN0_TxFifoFreeLevelGet(void) + + Summary: + Returns Tx FIFO Free Level. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Tx FIFO Free Level. +*/ +uint8_t CAN0_TxFifoFreeLevelGet(void) +{ + return (uint8_t)(CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) + + Summary: + Check if Transmission request is pending for the specific Tx buffer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + true - Transmission request is pending. + false - Transmission request is not pending. +*/ +bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) +{ + return ((CAN0_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) + + Summary: + Read Tx Event FIFO for the transmitted messages. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfTxEvent - Total number of Tx Event + txEventFifo - Pointer to Tx Event FIFO + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) +{ + uint8_t txefgi = 0U; + uint8_t count = 0U; + uint8_t *txEvent = NULL; + uint8_t *txEvtFifo = (uint8_t *)txEventFifo; + bool txFifo_event = false; + + if (txEventFifo != NULL) + { + /* Read data from the Rx FIFO0 */ + txefgi = (uint8_t)((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); + for (count = 0U; count < numberOfTxEvent; count++) + { + txEvent = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); + + (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); + + if ((count + 1U) == numberOfTxEvent) + { + break; + } + txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); + txefgi++; + if (txefgi == 1U) + { + txefgi = 0U; + } + } + + /* Ack the Tx Event FIFO position */ + CAN0_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); + + txFifo_event = true; + } + return txFifo_event; +} + + +// ***************************************************************************** +/* Function: + bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) + + Summary: + Read messages from Rx FIFO0/FIFO1. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO number + numberOfMessage - Total number of message + rxBuffer - Pointer to Rx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) +{ + uint8_t rxgi = 0U; + uint8_t count = 0U; + uint8_t *rxFifo = NULL; + uint8_t *rxBuf = (uint8_t *)rxBuffer; + bool status = false; + + if (rxBuffer != NULL) + { + switch (rxFifoNum) + { + case CAN_RX_FIFO_0: + /* Read data from the Rx FIFO0 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN0_RX_FIFO0_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO0_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN0_RX_FIFO0_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); + + status = true; + break; + case CAN_RX_FIFO_1: + /* Read data from the Rx FIFO1 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN0_RX_FIFO1_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO1_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN0_RX_FIFO1_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); + + status = true; + break; + default: + /* Do nothing */ + break; + } + } + return status; +} + +// ***************************************************************************** +/* Function: + CAN_ERROR CAN0_ErrorGet(void) + + Summary: + Returns the error during transfer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Error during transfer. +*/ +CAN_ERROR CAN0_ErrorGet(void) +{ + CAN_ERROR error; + uint32_t errorStatus = CAN0_REGS->CAN_PSR; + + error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) + | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); + + if ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + } + + return error; +} + +// ***************************************************************************** +/* Function: + void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) + + Summary: + Returns the transmit and receive error count during transfer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + txErrorCount - Transmit Error Count to be received + rxErrorCount - Receive Error Count to be received + + Returns: + None. +*/ +void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) +{ + *txErrorCount = (uint8_t)(CAN0_REGS->CAN_ECR & CAN_ECR_TEC_Msk); + *rxErrorCount = (uint8_t)((CAN0_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); +} + +// ***************************************************************************** +/* Function: + void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) + + Summary: + Set the Message RAM Configuration. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. + Application must allocate buffer from non-cached + contiguous memory and buffer size must be + CAN0_MESSAGE_RAM_CONFIG_SIZE + + Returns: + None +*/ +/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ +void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) +{ + uint32_t offset = 0U; + uint32_t msgRAMConfigBaseAddr = (uint32_t)msgRAMConfigBaseAddress; + + (void) memset(msgRAMConfigBaseAddress, 0x00, CAN0_MESSAGE_RAM_CONFIG_SIZE); + + /* Set CAN CCCR Init for Message RAM Configuration */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + can0Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; + offset = CAN0_RX_FIFO0_SIZE; + /* Receive FIFO 0 Configuration Register */ + CAN0_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | + CAN_RXF0C_F0SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO0Address); + + can0Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_RX_FIFO1_SIZE; + /* Receive FIFO 1 Configuration Register */ + CAN0_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | + CAN_RXF1C_F1SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO1Address); + + can0Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_TX_FIFO_BUFFER_SIZE; + /* Transmit Buffer/FIFO Configuration Register */ + CAN0_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | + CAN_TXBC_TBSA((uint32_t)can0Obj.msgRAMConfig.txBuffersAddress); + + can0Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_TX_EVENT_FIFO_SIZE; + /* Transmit Event FIFO Configuration Register */ + CAN0_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | + CAN_TXEFC_EFSA((uint32_t)can0Obj.msgRAMConfig.txEventFIFOAddress); + + + /* Reference offset variable once to remove warning about the variable not being used after increment */ + (void)offset; + + /* Complete Message RAM Configuration by clearing CAN CCCR Init */ + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for configuration complete */ + } +} +/* MISRAC 2012 deviation block end for Rule 11.3*/ + + + + +void CAN0_SleepModeEnter(void) +{ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) + { + /* Wait for clock stop request to complete */ + } +} + +void CAN0_SleepModeExit(void) +{ + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) + { + /* Wait for no clock stop */ + } + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } +} + +bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + uint32_t numOfTimeQuanta; + uint8_t tseg1; + float temp1; + float temp2; + + if ((setup != NULL) && (bitTiming != NULL)) + { + if (setup->nominalBitTimingSet == true) + { + numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) + { + if (setup->nominalSamplePoint < 50.0f) + { + setup->nominalSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; + bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; + bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; + bitTiming->nominalBitTimingSet = true; + status = true; + } + else + { + bitTiming->nominalBitTimingSet = false; + } + } + if (setup->dataBitTimingSet == true) + { + numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->dataBitRate * ((uint32_t)setup->dataPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 49U)) + { + if (setup->dataSamplePoint < 50.0f) + { + setup->dataSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->dataSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->dataBitTiming.dataTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->dataBitTiming.dataTimeSegment1 = tseg1 - 2U; + bitTiming->dataBitTiming.dataSJW = bitTiming->dataBitTiming.dataTimeSegment2; + bitTiming->dataBitTiming.dataPrescaler = setup->dataPrescaler; + bitTiming->dataBitTimingSet = true; + status = true; + } + else + { + bitTiming->dataBitTimingSet = false; + status = false; + } + } + } + + return status; +} + +bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + bool nominalBitTimingSet = false; + bool dataBitTimingSet = false; + + if ((bitTiming->nominalBitTimingSet == true) + && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) + && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) + && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) + && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) + { + nominalBitTimingSet = true; + } + + if ((bitTiming->dataBitTimingSet == true) + && ((bitTiming->dataBitTiming.dataTimeSegment1 >= 0x1U) && (bitTiming->dataBitTiming.dataTimeSegment1 <= 0x1FU)) + && (bitTiming->dataBitTiming.dataTimeSegment2 <= 0xFU) + && (bitTiming->dataBitTiming.dataPrescaler <= 0x1FU) + && (bitTiming->dataBitTiming.dataSJW <= 0xFU)) + { + dataBitTimingSet = true; + } + + if ((nominalBitTimingSet == true) || (dataBitTimingSet == true)) + { + /* Start CAN initialization */ + CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + if (dataBitTimingSet == true) + { + /* Set Data Bit Timing and Prescaler Register */ + CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(bitTiming->dataBitTiming.dataTimeSegment2) | CAN_DBTP_DTSEG1(bitTiming->dataBitTiming.dataTimeSegment1) | CAN_DBTP_DBRP(bitTiming->dataBitTiming.dataPrescaler) | CAN_DBTP_DSJW(bitTiming->dataBitTiming.dataSJW); + } + if (nominalBitTimingSet == true) + { + /* Set Nominal Bit timing and Prescaler Register */ + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); + } + + /* Set the operation mode */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; + + + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + status = true; + } + return status; +} + + +// ***************************************************************************** +/* Function: + void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0TxFifoCallbackObj.callback = callback; + can0TxFifoCallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_EVENT_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0TxEventFifoCallbackObj.callback = callback; + can0TxEventFifoCallbackObj.context = contextHandle; + + } +} + + +// ***************************************************************************** +/* Function: + void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO Number + + callback - A pointer to a function with a calling signature defined + by the CAN_RX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0RxFifoCallbackObj[rxFifoNum].callback = callback; + can0RxFifoCallbackObj[rxFifoNum].context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0CallbackObj.callback = callback; + can0CallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN0_InterruptHandler(void) + + Summary: + CAN0 Peripheral Interrupt Handler. + + Description: + This function is CAN0 Peripheral Interrupt Handler and will + called on every CAN0 interrupt. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Remarks: + The function is called as peripheral instance's interrupt handler if the + instance interrupt is enabled. If peripheral instance's interrupt is not + enabled user need to call it from the main while loop of the application. +*/ +void __attribute__((used)) CAN0_InterruptHandler(void) +{ + uint8_t numberOfMessage = 0; + uint8_t numberOfTxEvent = 0; + + uint32_t ir = CAN0_REGS->CAN_IR; + + /* Additional temporary variable used to prevent MISRA violations (Rule 13.x) */ + uintptr_t context; + + if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) + { + CAN0_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); + if (can0CallbackObj.callback != NULL) + { + context = can0CallbackObj.context; + can0CallbackObj.callback(ir, context); + } + } + /* New Message in Rx FIFO 0 */ + if ((ir & CAN_IR_RF0N_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_RF0N_Msk; + + numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); + + if (can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) + { + context = can0RxFifoCallbackObj[CAN_RX_FIFO_0].context; + can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, context); + } + } + /* New Message in Rx FIFO 1 */ + if ((ir & CAN_IR_RF1N_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_RF1N_Msk; + + numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); + + if (can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) + { + context = can0RxFifoCallbackObj[CAN_RX_FIFO_1].context; + can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, context); + } + } + + /* TX FIFO is empty */ + if ((ir & CAN_IR_TFE_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_TFE_Msk; + if (can0TxFifoCallbackObj.callback != NULL) + { + context = can0TxFifoCallbackObj.context; + can0TxFifoCallbackObj.callback(context); + } + } + /* Tx Event FIFO new entry */ + if ((ir & CAN_IR_TEFN_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_TEFN_Msk; + + numberOfTxEvent = (uint8_t)(CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); + + if (can0TxEventFifoCallbackObj.callback != NULL) + { + context = can0TxEventFifoCallbackObj.context; + can0TxEventFifoCallbackObj.callback(numberOfTxEvent, context); + } + } +} + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h new file mode 100644 index 00000000..63404486 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h @@ -0,0 +1,123 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_can0.h + + Summary: + CAN PLIB interface declarations. + + Description: + The CAN plib provides a simple interface to manage the CAN modules on + Microchip microcontrollers. This file defines the interface declarations + for the CAN plib. + + Remarks: + None. + +*******************************************************************************/ +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END + +#ifndef PLIB_CAN0_H +#define PLIB_CAN0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +/* + * This section lists the other files that are included in this file. + */ +#include +#include + +#include "device.h" +#include "plib_can_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +#define CAN0_CLOCK_FREQUENCY 48000000U + +/* CAN0 Message RAM Configuration Size */ +#define CAN0_RX_FIFO0_ELEMENT_SIZE 16U +#define CAN0_RX_FIFO0_SIZE 16U +#define CAN0_RX_FIFO1_ELEMENT_SIZE 16U +#define CAN0_RX_FIFO1_SIZE 16U +#define CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE 16U +#define CAN0_TX_FIFO_BUFFER_SIZE 16U +#define CAN0_TX_EVENT_FIFO_SIZE 8U + +/* CAN0_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver + for allocating buffer from non-cached contiguous memory */ +#define CAN0_MESSAGE_RAM_CONFIG_SIZE 56U + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +void CAN0_Initialize(void); +bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); +uint8_t CAN0_TxFifoFreeLevelGet(void); +bool CAN0_TxBufferIsBusy(uint8_t bufferNumber); +bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); +bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); +CAN_ERROR CAN0_ErrorGet(void); +void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); +void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); +void CAN0_SleepModeEnter(void); +void CAN0_SleepModeExit(void); +bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); +bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming); +void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif +// DOM-IGNORE-END + +#endif // PLIB_CAN0_H + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h new file mode 100644 index 00000000..b5f9f963 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h @@ -0,0 +1,668 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_can_common.h + + Summary + CAN peripheral library interface. + + Description + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_CAN_COMMON_H +#define PLIB_CAN_COMMON_H + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + + // ***************************************************************************** +/* CAN Transfer Errors + + Summary: + CAN Transfer Error macros. + + Description: + Helper macros to identify CAN errors. + + Remarks: + None. +*/ + +#define CAN_ERROR_NONE 0x0U +#define CAN_ERROR_LEC_STUFF 0x1U +#define CAN_ERROR_LEC_FORM 0x2U +#define CAN_ERROR_LEC_ACK 0x3U +#define CAN_ERROR_LEC_BIT1 0x4U +#define CAN_ERROR_LEC_BIT0 0x5U +#define CAN_ERROR_LEC_CRC 0x6U +#define CAN_ERROR_LEC_NC 0x7U +#define CAN_ERROR_PASSIVE 0x20U +#define CAN_ERROR_WARNING_STATUS 0x40U +#define CAN_ERROR_BUS_OFF 0x80U +#define CAN_ERROR_DLEC_STUFF 0x100U +#define CAN_ERROR_DLEC_FORM 0x200U +#define CAN_ERROR_DLEC_ACK 0x300U +#define CAN_ERROR_DLEC_BIT1 0x400U +#define CAN_ERROR_DLEC_BIT0 0x500U +#define CAN_ERROR_DLEC_CRC 0x600U +#define CAN_ERROR_DLEC_NC 0x700U +#define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U +#define CAN_ERROR_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* CAN Rx FIFO Number + + Summary: + CAN Rx FIFO Number. + + Description: + This data type defines CAN Rx FIFO number for Rx FIFO0 and FIFO1. + + Remarks: + None. +*/ +typedef enum +{ + CAN_RX_FIFO_0 = 0U, + CAN_RX_FIFO_1 +} CAN_RX_FIFO_NUM; + +// ***************************************************************************** +/* CAN Interrupt Mask + + Summary: + CAN Interrupt Mask. + + Description: + This data type defines the CAN Interrupt sources number. + + Remarks: + None. +*/ +typedef enum +{ + CAN_INTERRUPT_RF0N_MASK = (1UL << 0U), + CAN_INTERRUPT_RF0W_MASK = (1UL << 1U), + CAN_INTERRUPT_RF0F_MASK = (1UL << 2U), + CAN_INTERRUPT_RF0L_MASK = (1UL << 3U), + CAN_INTERRUPT_RF1N_MASK = (1UL << 4U), + CAN_INTERRUPT_RF1W_MASK = (1UL << 5U), + CAN_INTERRUPT_RF1F_MASK = (1UL << 6U), + CAN_INTERRUPT_RF1L_MASK = (1UL << 7U), + CAN_INTERRUPT_HPM_MASK = (1UL << 8U), + CAN_INTERRUPT_TC_MASK = (1UL << 9U), + CAN_INTERRUPT_TCF_MASK = (1UL << 10U), + CAN_INTERRUPT_TFE_MASK = (1UL << 11U), + CAN_INTERRUPT_TEFN_MASK = (1UL << 12U), + CAN_INTERRUPT_TEFW_MASK = (1UL << 13U), + CAN_INTERRUPT_TEFF_MASK = (1UL << 14U), + CAN_INTERRUPT_TEFL_MASK = (1UL << 15U), + CAN_INTERRUPT_TSW_MASK = (1UL << 16U), + CAN_INTERRUPT_MRAF_MASK = (1UL << 17U), + CAN_INTERRUPT_TOO_MASK = (1UL << 18U), + CAN_INTERRUPT_DRX_MASK = (1UL << 19U), + CAN_INTERRUPT_ELO_MASK = (1UL << 22U), + CAN_INTERRUPT_EP_MASK = (1UL << 23U), + CAN_INTERRUPT_EW_MASK = (1UL << 24U), + CAN_INTERRUPT_BO_MASK = (1UL << 25U), + CAN_INTERRUPT_WDI_MASK = (1UL << 26U), + CAN_INTERRUPT_PEA_MASK = (1UL << 27U), + CAN_INTERRUPT_PED_MASK = (1UL << 28U), + CAN_INTERRUPT_ARA_MASK = (1UL << 29U) +}CAN_INTERRUPT_MASK; + +// ***************************************************************************** +/* CAN Transfer Error + + Summary: + CAN Transfer Error data type. + + Description: + This data type defines the CAN Transfer Error. + + Remarks: + None. +*/ +typedef uint32_t CAN_ERROR; + +// ***************************************************************************** +/* CAN Tx FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_FIFO_CALLBACK) (uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN TX/RX Buffers Callback + + Summary: + CAN Callback Function Pointer for TX/RX Buffers. + + Description: + This data type defines the CAN Callback Function Pointer for TX/RX Buffers. + + Remarks: + None. +*/ +typedef void (*CAN_TXRX_BUFFERS_CALLBACK) (uint8_t bufferNumber, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx Event FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx Event FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_EVENT_FIFO_CALLBACK) (uint8_t numberOfTxEvent, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback + + Summary: + CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Description: + This data type defines the CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Remarks: + None. +*/ +typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Callback + + Summary: + CAN Callback Function Pointer. + + Description: + This data type defines the CAN Callback Function Pointer. + + Remarks: + None. +*/ +typedef void (*CAN_CALLBACK) (uint32_t interruptStatus, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Message RAM Configuration + + Summary: + CAN Message RAM Configuration structure. + + Description: + This data structure defines the CAN Message RAM Base address for Rx FIFO0, + Rx FIFO1, Rx Buffers, Tx Buffers/FIFO, Tx Event FIFO, Standard Message ID Filter and + Extended Message ID Filter configuration. + + Remarks: + None. +*/ +typedef struct +{ + /* Rx FIFO0 base address */ + can_rxf0e_registers_t *rxFIFO0Address; + + /* Rx FIFO1 base address */ + can_rxf1e_registers_t *rxFIFO1Address; + + /* Rx Buffer base address */ + can_rxbe_registers_t *rxBuffersAddress; + + /* Tx Buffers/FIFO base address */ + can_txbe_registers_t *txBuffersAddress; + + /* Tx Event FIFO base address */ + can_txefe_registers_t *txEventFIFOAddress; + + /* Standard Message ID Filter base address */ + can_sidfe_registers_t *stdMsgIDFilterAddress; + + /* Extended Message ID Filter base address */ + can_xidfe_registers_t *extMsgIDFilterAddress; +} CAN_MSG_RAM_CONFIG; + +// ***************************************************************************** +/* CAN Rx Buffer and FIFO Element + + Summary: + CAN Rx Buffer and FIFO Element Structure. + + Description: + This data structure defines CAN Rx Buffer and FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Rx Timestamp */ + unsigned int rxts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :2; + /* Filter Index */ + unsigned int fidx:7; + /* Accepted Non-matching Frame */ + unsigned int anmf:1; + + /* Data field */ + uint8_t data[8]; + +} CAN_RX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Buffer Element + + Summary: + CAN Tx Buffer Element Structure. + + Description: + This data structure defines CAN Tx Buffer Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Reserved */ + unsigned int :16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :1; + /* Event FIFO Control */ + unsigned int efc:1; + /* Message Marker */ + unsigned int mm:8; + + /* Data field */ + uint8_t data[8]; + +} CAN_TX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Event FIFO Element + + Summary: + CAN Tx Event FIFO Element Structure. + + Description: + This data structure defines CAN Tx Event FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Tx Timestamp */ + unsigned int txts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switch */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Event Type */ + unsigned int et:2; + /* Message Marker */ + unsigned int mm:8; + +} CAN_TX_EVENT_FIFO; + +// ***************************************************************************** +/* CAN Nominal Bit Timing Parameters + + Summary: + CAN Nominal Bit Timing Parameter structure. + + Description: + This data structure defines Nominal Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal Time segment after sample point */ + uint8_t nominalTimeSegment2; + + /* Nominal Time segment before sample point */ + uint8_t nominalTimeSegment1; + + /* Nominal Baud Rate Prescaler */ + uint16_t nominalPrescaler; + + /* Nominal Syncronization Jump Width */ + uint8_t nominalSJW; + +} CAN_NOMINAL_BIT_TIMING; + +// ***************************************************************************** +/* CAN Data Bit Timing Parameters + + Summary: + CAN Data Bit Timing Parameter structure. + + Description: + This data structure defines Data Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Data Time segment after sample point */ + uint8_t dataTimeSegment2; + + /* Data Time segment before sample point */ + uint8_t dataTimeSegment1; + + /* Data Baud Rate Prescaler */ + uint8_t dataPrescaler; + + /* Data Syncronization Jump Width */ + uint8_t dataSJW; + +} CAN_DATA_BIT_TIMING; + +// ***************************************************************************** +/* CAN Bit Timing Parameters + + Summary: + CAN Bit Timing Parameter structure. + + Description: + This data structure defines Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal bit timing set flag */ + bool nominalBitTimingSet; + + /* Nominal bit timing parameters */ + CAN_NOMINAL_BIT_TIMING nominalBitTiming; + + /* Data bit timing set flag */ + bool dataBitTimingSet; + + /* Data bit timing parameters */ + CAN_DATA_BIT_TIMING dataBitTiming; +} CAN_BIT_TIMING; + +// ***************************************************************************** +/* CAN Bit Timing Setup + + Summary: + CAN Bit Timing Setup structure. + + Description: + This data structure defines Bit Timing Setup parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal bit timing set flag */ + bool nominalBitTimingSet; + + /* Nominal bit rate */ + uint32_t nominalBitRate; + + /* Nominal Sample Point */ + float nominalSamplePoint; + + /* Nominal Baud Rate Prescaler */ + uint16_t nominalPrescaler; + + /* Data bit timing set flag */ + bool dataBitTimingSet; + + /* Data bit rate */ + uint32_t dataBitRate; + + /* Data Sample Point */ + float dataSamplePoint; + + /* Data Baud Rate Prescaler */ + uint8_t dataPrescaler; + +} CAN_BIT_TIMING_SETUP; + +// ***************************************************************************** +/* CAN Tx FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx/Rx Buffers Callback Object + + Summary: + CAN transfer event callback structure for Tx/Rx Buffers. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TXRX_BUFFERS_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TXRX_BUFFERS_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx Event FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_EVENT_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_EVENT_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback Object + + Summary: + CAN transfer event callback structure for Rx FIFO0/FIFO1. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_RX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_RX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Callback Object + + Summary: + CAN interrupt status callback structure. + + Description: + This data structure stores interrupt status callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* CAN Interrupt Status Callback */ + CAN_CALLBACK callback; + + /* CAN Interrupt Status Callback Context */ + uintptr_t context; +} CAN_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN PLib Instance Object + + Summary: + CAN PLib Object structure. + + Description: + This data structure defines the CAN PLib Instance Object. + + Remarks: + None. +*/ +typedef struct +{ + /* Message RAM Configuration */ + CAN_MSG_RAM_CONFIG msgRAMConfig; + +} CAN_OBJ; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif //PLIB_CAN_COMMON_H +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c new file mode 100644 index 00000000..35258b3e --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c @@ -0,0 +1,148 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.c + + Summary: + CLOCK PLIB Implementation File. + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_clock.h" +#include "device.h" +#include "interrupts.h" + + + + +static void OSCCTRL_Initialize(void) +{ + uint32_t calibValue = (uint32_t)(((*(uint64_t*)0x00806020UL) >> 19 ) & 0x3fffffUL); + OSCCTRL_REGS->OSCCTRL_CAL48M = calibValue; + + + /* Selection of the Division Value */ + OSCCTRL_REGS->OSCCTRL_OSC48MDIV = (uint8_t)OSCCTRL_OSC48MDIV_DIV(0UL); + + while((OSCCTRL_REGS->OSCCTRL_OSC48MSYNCBUSY & OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) == OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) + { + /* Waiting for the synchronization */ + } + + while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_OSC48MRDY_Msk) != OSCCTRL_STATUS_OSC48MRDY_Msk) + { + /* Waiting for the OSC48M Ready state */ + } + OSCCTRL_REGS->OSCCTRL_OSC48MCTRL |= OSCCTRL_OSC48MCTRL_ONDEMAND_Msk; + +} + +static void OSC32KCTRL_Initialize(void) +{ + OSC32KCTRL_REGS->OSC32KCTRL_OSC32K = 0x0UL; + + OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0UL); +} + + + +static void GCLK0_Initialize(void) +{ + + GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1UL) | GCLK_GENCTRL_SRC(6UL) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL0_Msk) == GCLK_SYNCBUSY_GENCTRL0_Msk) + { + /* wait for the Generator 0 synchronization */ + } +} + +void CLOCK_Initialize (void) +{ + /* Function to Initialize the Oscillators */ + OSCCTRL_Initialize(); + + /* Function to Initialize the 32KHz Oscillators */ + OSC32KCTRL_Initialize(); + + GCLK0_Initialize(); + + + /* Selection of the Generator and write Lock for SERCOM1_CORE */ + GCLK_REGS->GCLK_PCHCTRL[20] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[20] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM4_CORE */ + GCLK_REGS->GCLK_PCHCTRL[23] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[23] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for CAN0 */ + GCLK_REGS->GCLK_PCHCTRL[26] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[26] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for ADC0 */ + GCLK_REGS->GCLK_PCHCTRL[33] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[33] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for ADC1 */ + GCLK_REGS->GCLK_PCHCTRL[34] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[34] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Configure the AHB Bridge Clocks */ + MCLK_REGS->MCLK_AHBMASK = 0x1dffU; + + + + /* Configure the APBC Bridge Clocks */ + MCLK_REGS->MCLK_APBCMASK = 0x60024U; + + +} + + + diff --git a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.h b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.h new file mode 100644 index 00000000..71d6690a --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.h @@ -0,0 +1,143 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.h + + Summary: + CLOCK PLIB Header File. + + Description: + The Clock PLIB initializes all the oscillators based on the + requirements. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_CLOCK_H +#define PLIB_CLOCK_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void CLOCK_Initialize (void); + + Summary: + Initializes all the modules related to the system clock. + + Description: + This function initializes the clock as defined by the MHC and Clock Manager + selections. The function will configure the NVM Flash Wait states based on + the configured CPU operational frequency. It will then configure the + oscillators. + + For each of the clock sources (External Oscillator, Digital Phase Locked + Loop, Internal 48MHz Oscillator, External 32KHz oscillator and the Internal + 32KHz oscillator) enabled in MHC, the function will configure the clock + settings and will then wait till the clock is ready. In case of DPLL, the + function will wait till a lock is obtained. + + The function will then configure the Generic clock generators based on MHC + configurations. If a Generic Clock is enabled in MHC, this will be enabled + in the CLOCK_Initialize() function. The function will apply the CPU clock + divider and will wait for the Main Clock module to get ready. If the Main + Clock to the Peripheral APB and AHB interfaces was enabled in MHC, these + will be enabled in the CLOCK_Initialize() function. If the Peripheral Clock + Channels were enabled in MHC, these will be enabled in the + CLOCK_Initialize() function. + + The peripheral AHB and APB main clock and peripheral channel clocks will be + enabled when the peripheral specific initialize functions are called. This + will override the setting in MHC. The Generic Clock Generator source for + desired peripheral channel must be configured in MHC. + + Precondition: + MHC GUI should be configured with the right values. Incorrect configuration + of the Clock will result in incorrect peripheral behavior or a non + functional device. + + Parameters: + None. + + Returns: + None. + + Example: + + CLOCK_Initialize(); + + + Remarks: + This function should be called before calling other Clock library functions. +*/ + +void CLOCK_Initialize (void); + + + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_CLOCK_H */ + diff --git a/bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.c b/bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.c new file mode 100644 index 00000000..0876df57 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.c @@ -0,0 +1,52 @@ +/******************************************************************************* + EVSYS Peripheral Library + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.c + + Summary: + EVSYS Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_evsys.h" +#include "interrupts.h" + + +void EVSYS_Initialize( void ) +{ /*Event Channel User Configuration*/ + + +} + + + diff --git a/bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.h b/bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.h new file mode 100644 index 00000000..9ea8b02b --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/evsys/plib_evsys.h @@ -0,0 +1,68 @@ +/******************************************************************************* + Interface definition of EVSYS PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.h + + Summary: + Interface definition of the Event System Plib (EVSYS). + + Description: + This file defines the interface for the EVSYS Plib. + It allows user to setup event generators and users. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef EVSYS_H // Guards against multiple inclusion +#define EVSYS_H + +#include "device.h" +#include +#include + +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface +// ***************************************************************************** +// ***************************************************************************** + + + +/***************************** EVSYS API *******************************/ +void EVSYS_Initialize( void ); + +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif + +#endif diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c new file mode 100644 index 00000000..da38ec0f --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c @@ -0,0 +1,121 @@ +/******************************************************************************* + NVIC PLIB Implementation + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.c + + Summary: + NVIC PLIB Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "device.h" +#include "plib_nvic.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVIC Implementation +// ***************************************************************************** +// ***************************************************************************** + +void NVIC_Initialize( void ) +{ + + /* Enable NVIC Controller */ + __DMB(); + __enable_irq(); + + /* Enable the interrupt sources and configure the priorities as configured + * from within the "Interrupt Manager" of MHC. */ + NVIC_SetPriority(SERCOM1_IRQn, 3); + NVIC_EnableIRQ(SERCOM1_IRQn); + NVIC_SetPriority(CAN0_IRQn, 3); + NVIC_EnableIRQ(CAN0_IRQn); + + + + +} + +void NVIC_INT_Enable( void ) +{ + __DMB(); + __enable_irq(); +} + +bool NVIC_INT_Disable( void ) +{ + bool processorStatus = (__get_PRIMASK() == 0U); + + __disable_irq(); + __DMB(); + + return processorStatus; +} + +void NVIC_INT_Restore( bool state ) +{ + if( state == true ) + { + __DMB(); + __enable_irq(); + } + else + { + __disable_irq(); + __DMB(); + } +} + +bool NVIC_INT_SourceDisable( IRQn_Type source ) +{ + bool processorStatus; + bool intSrcStatus; + + processorStatus = NVIC_INT_Disable(); + intSrcStatus = (NVIC_GetEnableIRQ(source) != 0U); + NVIC_DisableIRQ( source ); + NVIC_INT_Restore( processorStatus ); + + /* return the source status */ + return intSrcStatus; +} + +void NVIC_INT_SourceRestore( IRQn_Type source, bool status ) +{ + if( status ) { + NVIC_EnableIRQ( source ); + } + + return; +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.h b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.h new file mode 100644 index 00000000..6d36bd14 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.h @@ -0,0 +1,72 @@ +/******************************************************************************* + NVIC PLIB Header + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.h + + Summary: + NVIC PLIB Header File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_NVIC_H +#define PLIB_NVIC_H + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + + +/***************************** NVIC Inline *******************************/ + +void NVIC_Initialize( void ); +void NVIC_INT_Enable( void ); +bool NVIC_INT_Disable( void ); +void NVIC_INT_Restore( bool state ); +bool NVIC_INT_SourceDisable( IRQn_Type source ); +void NVIC_INT_SourceRestore( IRQn_Type source, bool status ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END +#endif // PLIB_NVIC_H diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c b/bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c new file mode 100644 index 00000000..36679253 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -0,0 +1,260 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.c + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include "interrupts.h" +#include "plib_nvmctrl.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVMCTRL Implementation +// ***************************************************************************** +// ***************************************************************************** + + +void NVMCTRL_Initialize(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY | NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS | NVMCTRL_CTRLB_RWS(2UL) | NVMCTRL_CTRLB_MANW_Msk; +} + +void NVMCTRL_CacheInvalidate(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_INVALL | NVMCTRL_CTRLA_CMDEX_KEY); +} +bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t *paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* Writing 32-bit words in the given address */ + for ( i = 0U; i < (NVMCTRL_RWWEEPROM_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEWP | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_RWWEEPROM_RowErase( uint32_t address ) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEER | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t *paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + return true; +} + +bool NVMCTRL_PageBufferCommit( const uint32_t address) +{ + uint16_t command = NVMCTRL_CTRLA_CMD_WP_Val; + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + if (address >= NVMCTRL_RWWEEPROM_START_ADDRESS) + { + command = NVMCTRL_CTRLA_CMD_RWWEEWP; + } + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(command | NVMCTRL_CTRLA_CMDEX_KEY); + + + return true; +} + +bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_WP_Val | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_RowErase( uint32_t address ) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_ER_Val | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + bool pagewrite_val = false; + + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= ((NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE) - NVMCTRL_USERROW_PAGESIZE))) + { + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_USERROW_PAGESIZE/4U); i++) + { + *paddress = data[i]; + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_WAP_Val | NVMCTRL_CTRLA_CMDEX_KEY; + + + pagewrite_val = true; + } + + return pagewrite_val; +} + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ) +{ + bool rowerase = false; + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= (NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE))) + { + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_EAR_Val | NVMCTRL_CTRLA_CMDEX_KEY; + + + rowerase = true; + } + + return rowerase; +} + +NVMCTRL_ERROR NVMCTRL_ErrorGet( void ) +{ + uint16_t nvm_error; + + /* Get the error bits set */ + nvm_error = (NVMCTRL_REGS->NVMCTRL_STATUS & (NVMCTRL_STATUS_NVME_Msk | NVMCTRL_STATUS_LOCKE_Msk | NVMCTRL_STATUS_PROGE_Msk)); + + /* Clear the error bits in both STATUS and INTFLAG register */ + NVMCTRL_REGS->NVMCTRL_STATUS |= nvm_error; + + NVMCTRL_REGS->NVMCTRL_INTFLAG = NVMCTRL_INTFLAG_ERROR_Msk; + + return ((NVMCTRL_ERROR) nvm_error); +} + +bool NVMCTRL_IsBusy(void) +{ + return ((NVMCTRL_REGS->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_READY_Msk)!= NVMCTRL_INTFLAG_READY_Msk); +} + +void NVMCTRL_RegionLock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_LR_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} + +void NVMCTRL_RegionUnlock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_UR_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} + +void NVMCTRL_SecurityBitSet(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_SSB_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h b/bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h new file mode 100644 index 00000000..365c2866 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h @@ -0,0 +1,137 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.h + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_NVMCTRL_H +#define PLIB_NVMCTRL_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + +#define NVMCTRL_FLASH_START_ADDRESS (0x00000000U) +#define NVMCTRL_FLASH_PAGESIZE (64U) +#define NVMCTRL_FLASH_ROWSIZE (256U) + +#define NVMCTRL_EMULATED_EEPROM_START_ADDRESS (0x40000U) +#define NVMCTRL_EMULATED_EEPROM_PAGESIZE (64U) +#define NVMCTRL_EMULATED_EEPROM_SIZE (0U) + +#define NVMCTRL_RWWEEPROM_START_ADDRESS (0x00400000U) +#define NVMCTRL_RWWEEPROM_SIZE (0x2000U) +#define NVMCTRL_RWWEEPROM_PAGESIZE (64U) +#define NVMCTRL_RWWEEPROM_ROWSIZE (256U) + +#define NVMCTRL_USERROW_START_ADDRESS (0x00804000U) +#define NVMCTRL_USERROW_SIZE (0x100U) +#define NVMCTRL_USERROW_PAGESIZE (64U) + +#define NVMCTRL_ERROR_NONE 0x0U +#define NVMCTRL_ERROR_PROG 0x4U +#define NVMCTRL_ERROR_LOCK 0x8U +#define NVMCTRL_ERROR_NVM 0x10U + +typedef uint16_t NVMCTRL_ERROR; + + +void NVMCTRL_Initialize(void); + +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ); + + +bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address); + +bool NVMCTRL_PageBufferCommit( const uint32_t address); + + +bool NVMCTRL_RowErase( uint32_t address ); + +bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_RWWEEPROM_RowErase ( uint32_t address ); + +NVMCTRL_ERROR NVMCTRL_ErrorGet( void ); + +bool NVMCTRL_IsBusy( void ); + +void NVMCTRL_RegionLock (uint32_t address); + +void NVMCTRL_RegionUnlock (uint32_t address); + +void NVMCTRL_SecurityBitSet(void); + + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ); + +void NVMCTRL_CacheInvalidate ( void ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END +#endif // PLIB_NVMCTRL_H diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c new file mode 100644 index 00000000..53c22749 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c @@ -0,0 +1,309 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.c + + Summary: + Interface definition of PORT PLIB + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_port.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_IN); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value) +{ + /* Write the desired value */ + ((port_group_registers_t*)group)->PORT_OUT = (((port_group_registers_t*)group)->PORT_OUT & (~mask)) | (mask & value); +} + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_OUT); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTCLR = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTTGL = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRCLR = mask; + + for(uint32_t i = 0U; i < 32U; i++) + { + if((mask & ((uint32_t)1U << i)) != 0U) + { + ((port_group_registers_t*)group)->PORT_PINCFG[i] |= PORT_PINCFG_INEN_Msk; + } + } +} + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) +{ + uint32_t periph_func = (uint32_t) function; + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + uint32_t pinmux_val = (uint32_t)((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)]; + + /* For odd pins */ + if (0U != (pin_num & 0x01U)) + { + pinmux_val = (pinmux_val & ~0xF0U) | (periph_func << 4); + } + else + { + pinmux_val = (pinmux_val & ~0x0FU) | periph_func; + } + ((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)] = (uint8_t)pinmux_val; + + /* Enable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] |= (uint8_t)PORT_PINCFG_PMUXEN_Msk; +} + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinGPIOConfig(PORT_PIN pin) +{ + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + + /* Disable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h new file mode 100644 index 00000000..e8fcb4d1 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h @@ -0,0 +1,999 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.h + + Summary: + PORT PLIB Header File + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_PORT_H +#define PLIB_PORT_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data types and constants +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PORT Group + + Summary: + Identifies the port groups available on the device. + + Description: + These macros identifies all the ports groups that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the preprocessor macros as these may vary between devices. + + Port groups shown here are the ones available on the selected device. Not + all ports groups are implemented. Refer to the device specific datasheet + for more details. The MHC will generate these macros with the port + groups that are available on the device. +*/ + +/* Group 0 */ +#define PORT_GROUP_0 (PORT_BASE_ADDRESS + (0U * 0x80U)) + +/* Group 1 */ +#define PORT_GROUP_1 (PORT_BASE_ADDRESS + (1U * 0x80U)) + + +/* Helper macros to get port information from the pin */ +#define GET_PORT_GROUP(pin) ((PORT_GROUP)(PORT_BASE_ADDRESS + (0x80U * (((uint32_t)pin) >> 5U)))) +#define GET_PIN_MASK(pin) (((uint32_t)(0x1U)) << (((uint32_t)pin) & 0x1FU)) + +/* Named type for port group */ +typedef uint32_t PORT_GROUP; + + +typedef enum +{ +PERIPHERAL_FUNCTION_A = 0x0, +PERIPHERAL_FUNCTION_B = 0x1, +PERIPHERAL_FUNCTION_C = 0x2, +PERIPHERAL_FUNCTION_D = 0x3, +PERIPHERAL_FUNCTION_E = 0x4, +PERIPHERAL_FUNCTION_F = 0x5, +PERIPHERAL_FUNCTION_G = 0x6, +PERIPHERAL_FUNCTION_H = 0x7, +PERIPHERAL_FUNCTION_I = 0x8, + +}PERIPHERAL_FUNCTION; + +// ***************************************************************************** +/* PORT Pins + + Summary: + Identifies the available Ports pins. + + Description: + This enumeration identifies all the ports pins that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the enumeration constants as these may vary between devices. + + Port pins shown here are the ones available on the selected device. Not + all ports pins within a port group are implemented. Refer to the device + specific datasheet for more details. +*/ + +typedef enum +{ + /* PA00 pin */ + PORT_PIN_PA00 = 0U, + + /* PA01 pin */ + PORT_PIN_PA01 = 1U, + + /* PA02 pin */ + PORT_PIN_PA02 = 2U, + + /* PA03 pin */ + PORT_PIN_PA03 = 3U, + + /* PA04 pin */ + PORT_PIN_PA04 = 4U, + + /* PA05 pin */ + PORT_PIN_PA05 = 5U, + + /* PA06 pin */ + PORT_PIN_PA06 = 6U, + + /* PA07 pin */ + PORT_PIN_PA07 = 7U, + + /* PA08 pin */ + PORT_PIN_PA08 = 8U, + + /* PA09 pin */ + PORT_PIN_PA09 = 9U, + + /* PA10 pin */ + PORT_PIN_PA10 = 10U, + + /* PA11 pin */ + PORT_PIN_PA11 = 11U, + + /* PA12 pin */ + PORT_PIN_PA12 = 12U, + + /* PA13 pin */ + PORT_PIN_PA13 = 13U, + + /* PA14 pin */ + PORT_PIN_PA14 = 14U, + + /* PA15 pin */ + PORT_PIN_PA15 = 15U, + + /* PA16 pin */ + PORT_PIN_PA16 = 16U, + + /* PA17 pin */ + PORT_PIN_PA17 = 17U, + + /* PA18 pin */ + PORT_PIN_PA18 = 18U, + + /* PA19 pin */ + PORT_PIN_PA19 = 19U, + + /* PA20 pin */ + PORT_PIN_PA20 = 20U, + + /* PA21 pin */ + PORT_PIN_PA21 = 21U, + + /* PA22 pin */ + PORT_PIN_PA22 = 22U, + + /* PA23 pin */ + PORT_PIN_PA23 = 23U, + + /* PA24 pin */ + PORT_PIN_PA24 = 24U, + + /* PA25 pin */ + PORT_PIN_PA25 = 25U, + + /* PA27 pin */ + PORT_PIN_PA27 = 27U, + + /* PA28 pin */ + PORT_PIN_PA28 = 28U, + + /* PA30 pin */ + PORT_PIN_PA30 = 30U, + + /* PA31 pin */ + PORT_PIN_PA31 = 31U, + + /* PB00 pin */ + PORT_PIN_PB00 = 32U, + + /* PB01 pin */ + PORT_PIN_PB01 = 33U, + + /* PB02 pin */ + PORT_PIN_PB02 = 34U, + + /* PB03 pin */ + PORT_PIN_PB03 = 35U, + + /* PB04 pin */ + PORT_PIN_PB04 = 36U, + + /* PB05 pin */ + PORT_PIN_PB05 = 37U, + + /* PB06 pin */ + PORT_PIN_PB06 = 38U, + + /* PB07 pin */ + PORT_PIN_PB07 = 39U, + + /* PB08 pin */ + PORT_PIN_PB08 = 40U, + + /* PB09 pin */ + PORT_PIN_PB09 = 41U, + + /* PB10 pin */ + PORT_PIN_PB10 = 42U, + + /* PB11 pin */ + PORT_PIN_PB11 = 43U, + + /* PB12 pin */ + PORT_PIN_PB12 = 44U, + + /* PB13 pin */ + PORT_PIN_PB13 = 45U, + + /* PB14 pin */ + PORT_PIN_PB14 = 46U, + + /* PB15 pin */ + PORT_PIN_PB15 = 47U, + + /* PB16 pin */ + PORT_PIN_PB16 = 48U, + + /* PB17 pin */ + PORT_PIN_PB17 = 49U, + + /* PB22 pin */ + PORT_PIN_PB22 = 54U, + + /* PB23 pin */ + PORT_PIN_PB23 = 55U, + + /* PB30 pin */ + PORT_PIN_PB30 = 62U, + + /* PB31 pin */ + PORT_PIN_PB31 = 63U, + + /* This element should not be used in any of the PORT APIs. + * It will be used by other modules or application to denote that none of + * the PORT Pin is used */ + PORT_PIN_NONE = 65535U, + +} PORT_PIN; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Generated API based on pin configurations done in Pin Manager +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on multiple pins of a group +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the hardware state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_Read(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the output state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_GroupLatchRead(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + mask - A 32 bit value in which positions of 0s and 1s decide + which IO pins of the selected port group will be written. + 1's - Will write to corresponding IO pins. + 0's - Will remain unchanged. + + value - Value which has to be written/driven on the I/O + lines of the selected port for which mask bits are '1'. + Values for the corresponding mask bit '0' will be ignored. + Refer to the function description for effect on pins + which are not configured for output. + + Returns: + None. + + Example: + + + PORT_GroupWrite(PORT_GROUP_C, 0x0F, 0xF563D453); + + + + Remarks: + None. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 1. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupSet(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 1 on this pin will cause the pull + up to be enabled. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 0. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupClear(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will be toggled. If the + value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupToggle(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. Driving a logic 1 on this pin will cause the pull up to + be enabled. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + input. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupInputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + output. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupOutputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + None +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function); + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + None +*/ +void PORT_PinGPIOConfig(PORT_PIN pin); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on one pin at a time +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void PORT_PinWrite(PORT_PIN pin, bool value) + + Summary: + Writes the specified value to the selected pin. + + Description: + This function writes/drives the "value" on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called once. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + value - value to be written on the selected pin. + true = set pin to high (1). + false = clear pin to low (0). + + Returns: + None. + + Example: + + + bool value = true; + PORT_PinWrite(PORT_PIN_PB3, value); + + + + Remarks: + Calling this function with an input pin with the pull-up/pull-down feature + enabled will affect the pull-up/pull-down configuration. If the value is + false, the pull-down will be enabled. If the value is true, the pull-up will + be enabled. +*/ + +static inline void PORT_PinWrite(PORT_PIN pin, bool value) +{ + PORT_GroupWrite(GET_PORT_GROUP(pin), + GET_PIN_MASK(pin), + (value ? GET_PIN_MASK(pin) : 0U)); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinRead(PORT_PIN pin) + + Summary: + Read the selected pin value. + + Description: + This function reads the present state at the selected input pin. The + function can also be called to read the value of an output pin if input + sampling on the output pin is enabled in MHC. If input synchronization on + the pin is disabled in MHC, the function will cause a 2 PORT Clock cycles + delay. Enabling the synchronization eliminates the delay but will increase + power consumption. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + pin - the port pin whose state needs to be read. + + Returns: + true - the state at the pin is a logic high. + false - the state at the pin is a logic low. + + Example: + + + bool value; + value = PORT_PinRead(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline bool PORT_PinRead(PORT_PIN pin) +{ + return ((PORT_GroupRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinLatchRead(PORT_PIN pin) + + Summary: + Read the value driven on the selected pin. + + Description: + This function reads the data driven on the selected I/O line/pin. The + function does not sample the state of the hardware pin. It only returns the + value that is written to output register. Refer to the PORT_PinRead() + function if the state of the output pin needs to be read. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + true - the present value in the output latch is a logic high. + false - the present value in the output latch is a logic low. + + Example: + + + bool value; + value = PORT_PinLatchRead(PORT_PIN_PB3); + + + + Remarks: + To read actual pin value, PIN_Read API should be used. +*/ + +static inline bool PORT_PinLatchRead(PORT_PIN pin) +{ + return ((PORT_GroupLatchRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinToggle(PORT_PIN pin) + + Summary: + Toggles the selected pin. + + Description: + This function toggles/inverts the present value on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinToggle(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinToggle(PORT_PIN pin) +{ + PORT_GroupToggle(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinSet(PORT_PIN pin) + + Summary: + Sets the selected pin. + + Description: + This function drives a logic 1 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinSet(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinSet(PORT_PIN pin) +{ + PORT_GroupSet(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinClear(PORT_PIN pin) + + Summary: + Clears the selected pin. + + Description: + This function drives a logic 0 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinClear(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinClear(PORT_PIN pin) +{ + PORT_GroupClear(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinInputEnable(PORT_PIN pin) + + Summary: + Configures the selected IO pin as input. + + Description: + This function configures the selected IO pin as input. This function + override the MHC input output pin settings. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinInputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinInputEnable(PORT_PIN pin) +{ + PORT_GroupInputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinOutputEnable(PORT_PIN pin) + + Summary: + Enables selected IO pin as output. + + Description: + This function enables selected IO pin as output. Calling this function will + override the MHC input output pin configuration. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinOutputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinOutputEnable(PORT_PIN pin) +{ + PORT_GroupOutputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +} + +#endif +// DOM-IGNORE-END +#endif // PLIB_PORT_H diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c new file mode 100644 index 00000000..6774f2e5 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c @@ -0,0 +1,680 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_sercom1_i2c.c + + Summary: + SERCOM I2C PLIB Implementation file + + Description: + This file defines the interface to the SERCOM I2C peripheral library. + This library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "interrupts.h" +#include "plib_sercom1_i2c_master.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + + +#define SERCOM1_I2CM_SPEED_HZ 100000 + +/* SERCOM1 I2C baud value */ +#define SERCOM1_I2CM_BAUD_VALUE (0xE8U) + + +static volatile SERCOM_I2C_OBJ sercom1I2CObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM1 I2C Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM1_I2C_Initialize(void) +{ + /* Reset the module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable smart mode */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Baud rate - Master Baud Rate*/ + SERCOM1_REGS->I2CM.SERCOM_BAUD = SERCOM1_I2CM_BAUD_VALUE; + + /* Set Operation Mode (Master), SDA Hold time, run in stand by and i2c master enable */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | SERCOM_I2CM_CTRLA_SDAHOLD_75NS | SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE | SERCOM_I2CM_CTRLA_SCLSM(0UL) | SERCOM_I2CM_CTRLA_ENABLE_Msk ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initial Bus State: IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize the SERCOM1 PLib Object */ + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Enable all Interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; +} + +static bool SERCOM1_I2C_CalculateBaudValue(uint32_t srcClkFreq, uint32_t i2cClkSpeed, uint32_t* baudVal) +{ + uint32_t baudValue = 0U; + float fSrcClkFreq = (float)srcClkFreq; + float fI2cClkSpeed = (float)i2cClkSpeed; + float fBaudValue = 0.0f; + + /* Reference clock frequency must be atleast two times the baud rate */ + if (srcClkFreq < (2U * i2cClkSpeed)) + { + return false; + } + + if (i2cClkSpeed <= 1000000U) + { + /* Standard, FM and FM+ baud calculation */ + fBaudValue = (fSrcClkFreq / fI2cClkSpeed) - ((fSrcClkFreq * (100.0f / 1000000000.0f)) + 10.0f); + baudValue = (uint32_t)fBaudValue; + } + else + { + return false; + } + if (i2cClkSpeed <= 400000U) + { + /* For I2C clock speed upto 400 kHz, the value of BAUD<7:0> determines both SCL_L and SCL_H with SCL_L = SCL_H */ + if (baudValue > (0xFFU * 2U)) + { + /* Set baud rate to the minimum possible value */ + baudValue = 0xFFU; + } + else if (baudValue <= 1U) + { + /* Baud value cannot be 0. Set baud rate to maximum possible value */ + baudValue = 1U; + } + else + { + baudValue /= 2U; + } + } + else + { + /* To maintain the ratio of SCL_L:SCL_H to 2:1, the max value of BAUD_LOW<15:8>:BAUD<7:0> can be 0xFF:0x7F. Hence BAUD_LOW + BAUD can not exceed 255+127 = 382 */ + if (baudValue >= 382U) + { + /* Set baud rate to the minimum possible value while maintaining SCL_L:SCL_H to 2:1 */ + baudValue = (0xFFUL << 8U) | (0x7FU); + } + else if (baudValue <= 3U) + { + /* Baud value cannot be 0. Set baud rate to maximum possible value while maintaining SCL_L:SCL_H to 2:1 */ + baudValue = (2UL << 8U) | 1U; + } + else + { + /* For Fm+ mode, I2C SCL_L:SCL_H to 2:1 */ + baudValue = ((((baudValue * 2U)/3U) << 8U) | (baudValue/3U)); + } + } + *baudVal = baudValue; + return true; +} + +bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ) +{ + uint32_t baudValue; + uint32_t i2cClkSpeed; + uint32_t i2cSpeedMode = 0; + + if (setup == NULL) + { + return false; + } + + i2cClkSpeed = setup->clkSpeed; + + if( srcClkFreq == 0U) + { + srcClkFreq = 48000000UL; + } + + if (SERCOM1_I2C_CalculateBaudValue(srcClkFreq, i2cClkSpeed, &baudValue) == false) + { + return false; + } + + if (i2cClkSpeed > 400000U) + { + i2cSpeedMode = 1U; + } + + /* Disable the I2C before changing the I2C clock speed */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Baud rate - Master Baud Rate*/ + SERCOM1_REGS->I2CM.SERCOM_BAUD = baudValue; + + SERCOM1_REGS->I2CM.SERCOM_CTRLA = ((SERCOM1_REGS->I2CM.SERCOM_CTRLA & ~SERCOM_I2CM_CTRLA_SPEED_Msk) | (SERCOM_I2CM_CTRLA_SPEED(i2cSpeedMode))); + + /* Re-enable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + return true; +} + +void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle) +{ + sercom1I2CObj.callback = callback; + + sercom1I2CObj.context = contextHandle; +} + + +static void SERCOM1_I2C_SendAddress(uint16_t address, bool dir) +{ + /* If operation is I2C read */ + if(dir) + { + /*

*/ + + /* Next state will be to read data */ + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; + } + else + { + /*

*/ + + /* Next state will be to write data */ + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_WRITE; + } + + + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)address << 1U) | (dir ? 1UL :0UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + +} + +static void SERCOM1_I2C_InitiateTransfer(uint16_t address, bool dir) +{ + sercom1I2CObj.writeCount = 0U; + sercom1I2CObj.readCount = 0U; + + /* Clear all flags */ + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Smart mode enabled with SCLSM = 0, - ACK is set to send while receiving the data */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB &= ~SERCOM_I2CM_CTRLB_ACKACT_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + SERCOM1_I2C_SendAddress(address, dir); +} + +static bool SERCOM1_I2C_XferSetup( + uint16_t address, + uint8_t* wrData, + uint32_t wrLength, + uint8_t* rdData, + uint32_t rdLength, + bool dir, + bool isHighSpeed +) +{ + /* Check for ongoing transfer */ + if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) + { + return false; + } + + sercom1I2CObj.address = address; + sercom1I2CObj.readBuffer = rdData; + sercom1I2CObj.readSize = rdLength; + sercom1I2CObj.writeBuffer = wrData; + sercom1I2CObj.writeSize = wrLength; + sercom1I2CObj.transferDir = dir; + sercom1I2CObj.isHighSpeed = isHighSpeed; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + + SERCOM1_I2C_InitiateTransfer(address, dir); + + return true; +} + +bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength) +{ + return SERCOM1_I2C_XferSetup(address, NULL, 0, rdData, rdLength, true, false); +} + +bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength) +{ + return SERCOM1_I2C_XferSetup(address, wrData, wrLength, NULL, 0, false, false); +} + +bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength) +{ + return SERCOM1_I2C_XferSetup(address, wrData, wrLength, rdData, rdLength, false, false); +} + + +bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound) +{ + uint8_t* pDevList = (uint8_t*)pDevicesList; + uint8_t nDevFound = 0; + + /* Check for ongoing transfer */ + if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) + { + return false; + } + + if ((pDevicesList == NULL) || (nDevicesFound == NULL)) + { + return false; + } + + *nDevicesFound = 0; + + /* Clear all flags */ + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Disable all interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENCLR = (uint8_t)SERCOM_I2CM_INTENCLR_Msk; + + for (uint16_t dev_addr = start_addr; dev_addr <= end_addr; dev_addr++) + { + while(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) + { + /* Wait for the bus to become IDLE */ + } + + /* Put the 7-bit device address on the bus with WR bit */ + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)dev_addr << 1U); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + while ((SERCOM1_REGS->I2CM.SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_MB_Msk) == 0U) + { + /* Wait for the address transfer to complete */ + } + + if ((SERCOM1_REGS->I2CM.SERCOM_STATUS & (SERCOM_I2CM_STATUS_ARBLOST_Msk | SERCOM_I2CM_STATUS_BUSERR_Msk | SERCOM_I2CM_STATUS_RXNACK_Msk)) == 0U) + { + /* No error and device responded with an ACK. Add the device to the list of found devices. */ + pDevList[nDevFound] = (uint8_t)dev_addr; + + nDevFound += 1U; + } + + /* Issue stop condition */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } + + *nDevicesFound = nDevFound; + + /* Re-enable all interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; + + return true; +} + +bool SERCOM1_I2C_IsBusy(void) +{ + bool isBusy = true; + if((sercom1I2CObj.state == SERCOM_I2C_STATE_IDLE)) + { + if(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) + { + isBusy = false; + } + } + return isBusy; +} + +SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void) +{ + return sercom1I2CObj.error; +} + +void SERCOM1_I2C_TransferAbort( void ) +{ + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + // Reset the plib to IDLE state + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Disable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Re-enable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void __attribute__((used)) SERCOM1_I2C_InterruptHandler(void) +{ + if(SERCOM1_REGS->I2CM.SERCOM_INTENSET != 0U) + { + uintptr_t context = sercom1I2CObj.context; + + /* Checks if the arbitration lost in multi-master scenario */ + if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_ARBLOST_Msk) == SERCOM_I2CM_STATUS_ARBLOST_Msk) + { + /* Set Error status */ + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; + + } + /* Check for Bus Error during transmission */ + else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSERR_Msk) == SERCOM_I2CM_STATUS_BUSERR_Msk) + { + /* Set Error status */ + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; + } + /* Checks slave acknowledge for address or data */ + else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_RXNACK_Msk) == SERCOM_I2CM_STATUS_RXNACK_Msk) + { + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NAK; + } + else + { + switch(sercom1I2CObj.state) + { + case SERCOM_I2C_REINITIATE_TRANSFER: + + if (sercom1I2CObj.writeSize != 0U) + { + /* Initiate Write transfer */ + SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, false); + } + else + { + /* Initiate Read transfer */ + SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, true); + } + + break; + + + case SERCOM_I2C_STATE_IDLE: + + break; + + + + case SERCOM_I2C_STATE_TRANSFER_WRITE: + { + size_t writeCount = sercom1I2CObj.writeCount; + + if (writeCount == (sercom1I2CObj.writeSize)) + { + if(sercom1I2CObj.readSize != 0U) + { + + /* Write 7bit address with direction (ADDR.ADDR[0]) equal to 1*/ + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)(sercom1I2CObj.address) << 1U) | (uint32_t)I2C_TRANSFER_READ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; + + } + else + { + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; + } + } + /* Write next byte */ + else + { + SERCOM1_REGS->I2CM.SERCOM_DATA = sercom1I2CObj.writeBuffer[writeCount]; + writeCount++; + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + sercom1I2CObj.writeCount = writeCount; + } + } + + break; + + case SERCOM_I2C_STATE_TRANSFER_READ: + { + size_t readCount = sercom1I2CObj.readCount; + + + if(readCount == (sercom1I2CObj.readSize - 1U)) + { + /* Set NACK and send stop condition to the slave from master */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_ACKACT_Msk | SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; + } + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Read the received data */ + sercom1I2CObj.readBuffer[readCount] = (uint8_t) SERCOM1_REGS->I2CM.SERCOM_DATA; + readCount++; + + sercom1I2CObj.readCount = readCount; + } + + break; + + default: + + /* Do nothing */ + break; + } + } + + /* Error Status */ + if(sercom1I2CObj.state == SERCOM_I2C_STATE_ERROR) + { + /* Reset the PLib objects and Interrupts */ + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Generate STOP condition */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + if (sercom1I2CObj.callback != NULL) + { + sercom1I2CObj.callback(context); + } + } + /* Transfer Complete */ + else if(sercom1I2CObj.state == SERCOM_I2C_STATE_TRANSFER_DONE) + { + /* Reset the PLib objects and interrupts */ + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Wait for the NAK and STOP bit to be transmitted out and I2C state machine to rest in IDLE state */ + while((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U)) + { + /* Do nothing */ + } + + if(sercom1I2CObj.callback != NULL) + { + sercom1I2CObj.callback(context); + } + + } + else + { + /* Do nothing */ + } + } + + return; +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h new file mode 100644 index 00000000..d20fd0e2 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h @@ -0,0 +1,104 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Instance Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_sercom1_i2c.h + + Summary: + SERCOM I2C PLIB Header file + + Description: + This file defines the interface to the SERCOM I2C peripheral library. This + library provides access to and control of the associated peripheral + instance. +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM1_I2C_H +#define PLIB_SERCOM1_I2C_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_sercom_i2c_master_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +/* + * The following functions make up the methods (set of possible operations) of + * this interface. + */ + +void SERCOM1_I2C_Initialize(void); + +bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength); + +bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength); + +bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength); + +bool SERCOM1_I2C_IsBusy(void); + +SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void); + +void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle); + +bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ); + + +void SERCOM1_I2C_TransferAbort( void ); + +bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_SERCOM1_I2C_H */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h new file mode 100644 index 00000000..904a768b --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h @@ -0,0 +1,260 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Instance Header File + + Company + Microchip Technology Inc. + + File Name + plib_sercom_i2c_master.h + + Summary + SERCOM I2C peripheral library interface. + + Description + This file defines the interface to the SERCOM I2C peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_I2C_MASTER_H +#define PLIB_SERCOM_I2C_MASTER_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SERCOM I2C Transfer type + + Summary: + List of transfer direction. + + Description: + This enum defines the I2C transfer direction. + + Remarks: + None. +*/ + +enum +{ + I2C_TRANSFER_WRITE = 0, + I2C_TRANSFER_READ = 1, +}; + +// ***************************************************************************** +/* SERCOM I2C Error. + + Summary: + Defines the possible errors that the SERCOM I2C peripheral can generate. + + Description: + This enum defines the possible error the SERCOM I2C peripheral can generate. + An error of this type is returned by the SERCOMx_I2C_ErrorGet() function. + + Remarks: + None. +*/ + +typedef enum +{ + /* No error has occurred. */ + SERCOM_I2C_ERROR_NONE, + + /* A bus transaction was NAK'ed */ + SERCOM_I2C_ERROR_NAK, + + /* A bus error has occurred. */ + SERCOM_I2C_ERROR_BUS, + +} SERCOM_I2C_ERROR; + +// ***************************************************************************** +/* SERCOM I2C State. + + Summary: + SERCOM I2C PLib Task State. + + Description: + This data type defines the SERCOM I2C PLib Task State. + + Remarks: + None. +*/ + +typedef enum +{ + /* SERCOM PLib Task Error State */ + SERCOM_I2C_STATE_ERROR = -1, + + /* SERCOM PLib Task Idle State */ + SERCOM_I2C_STATE_IDLE, + + /* SERCOM PLib Task Address Send State */ + SERCOM_I2C_STATE_ADDR_SEND, + + SERCOM_I2C_REINITIATE_TRANSFER, + /* SERCOM PLib Task Read Transfer State */ + SERCOM_I2C_STATE_TRANSFER_READ, + + /* SERCOM PLib Task Write Transfer State */ + SERCOM_I2C_STATE_TRANSFER_WRITE, + + /* SERCOM PLib Task High Speed Slave Address Send State */ + SERCOM_I2C_STATE_TRANSFER_ADDR_HS, + + /* SERCOM PLib Task Transfer Done State */ + SERCOM_I2C_STATE_TRANSFER_DONE, + +} SERCOM_I2C_STATE; + +// ***************************************************************************** +/* SERCOM I2C Callback + + Summary: + SERCOM I2C Callback Function Pointer. + + Description: + This data type defines the SERCOM I2C Callback Function Pointer. + + Remarks: + None. +*/ + +typedef void (*SERCOM_I2C_CALLBACK) +( + /*Transfer context*/ + uintptr_t contextHandle + +); + +// ***************************************************************************** +/* SERCOM I2C PLib Instance Object + + Summary: + SERCOM I2C PLib Object structure. + + Description: + This data structure defines the SERCOM I2C PLib Instance Object. + + Remarks: + None. +*/ + +typedef struct +{ + bool isHighSpeed; + + bool txMasterCode; + + bool transferDir; + + uint16_t address; + + uint8_t masterCode; + + uint8_t* writeBuffer; + + uint8_t* readBuffer; + + size_t writeSize; + + size_t readSize; + + size_t writeCount; + + size_t readCount; + + /* State */ + SERCOM_I2C_STATE state; + + /* Transfer status */ + SERCOM_I2C_ERROR error; + + /* Transfer Event Callback */ + SERCOM_I2C_CALLBACK callback; + + /* Transfer context */ + uintptr_t context; + +} SERCOM_I2C_OBJ; + +// ***************************************************************************** +/* Transaction Request Block + + Summary: + Transaction Request Block Structure. + + Description: + This data structure defines the Transaction Request Block. + + Remarks: + None. +*/ + +typedef struct +{ + /* SERCOM I2C Clock Speed */ + uint32_t clkSpeed; + +} SERCOM_I2C_TRANSFER_SETUP; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_SERCOM_I2C_MASTER_H */ \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c new file mode 100644 index 00000000..7cd533a7 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c @@ -0,0 +1,454 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom4_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom4_usart.h" +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM4 USART baud value for 115200 Hz baud rate */ +#define SERCOM4_USART_INT_BAUD_VALUE (63019UL) + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM4 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM4_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM4_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM4_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM4_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM4_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + + + + + +uint32_t SERCOM4_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM4_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM4_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = (SERCOM4_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM4_REGS->USART_INT.SERCOM_CTRLB = (SERCOM4_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = (SERCOM4_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM4_REGS->USART_INT.SERCOM_CTRLB = (SERCOM4_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM4_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + SERCOM4_USART_ErrorClear(); + } + + return errorStatus; +} + +void SERCOM4_USART_Enable( void ) +{ + if((SERCOM4_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM4_USART_Disable( void ) +{ + if((SERCOM4_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM4_USART_TransmitterEnable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM4_USART_TransmitterDisable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM4_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint8_t *pu8Data = (uint8_t*)buffer; + uint16_t *pu16Data = (uint16_t*)buffer; + uint32_t u32Index = 0U; + + if(buffer != NULL) + { + /* Blocks while buffer is being transferred */ + while(u32Index < size) + { + /* Check if USART is ready for new data */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk) == 0U) + { + /* Do nothing */ + } + + /* Write data to USART module */ + if (((SERCOM4_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM4_REGS->USART_INT.SERCOM_DATA = pu8Data[u32Index]; + } + else + { + /* 9-bit mode */ + SERCOM4_REGS->USART_INT.SERCOM_DATA = pu16Data[u32Index]; + } + + /* Increment index */ + u32Index++; + } + writeStatus = true; + } + + return writeStatus; +} + + +bool SERCOM4_USART_TransmitterIsReady( void ) +{ + bool transmitterStatus = false; + + if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) + { + transmitterStatus = true; + } + + return transmitterStatus; +} + +void SERCOM4_USART_WriteByte( int data ) +{ + /* Check if USART is ready for new data */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == 0U) + { + /* Do nothing */ + } + + SERCOM4_REGS->USART_INT.SERCOM_DATA = (uint16_t)data; +} + +bool SERCOM4_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM4_USART_ReceiverEnable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM4_USART_ReceiverDisable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM4_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + uint8_t* pu8Data = (uint8_t*)buffer; + uint16_t *pu16Data = (uint16_t*)buffer; + uint32_t u32Index = 0U; + USART_ERROR errorStatus = USART_ERROR_NONE; + + if(buffer != NULL) + { + + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM4_USART_ErrorClear(); + + while(u32Index < size) + { + /* Check if USART has new data */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == 0U) + { + /* Do nothing */ + } + + errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + break; + } + + if (((SERCOM4_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + pu8Data[u32Index] = (uint8_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; + } + else + { + /* 9-bit mode */ + pu16Data[u32Index] = (uint16_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; + } + + /* Increment index */ + u32Index++; + } + + if(size == u32Index) + { + readStatus = true; + } + } + + return readStatus; +} + +bool SERCOM4_USART_ReceiverIsReady( void ) +{ + bool receiverStatus = false; + + if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + receiverStatus = true; + } + + return receiverStatus; +} + +int SERCOM4_USART_ReadByte( void ) +{ + return (int)SERCOM4_REGS->USART_INT.SERCOM_DATA; +} + + + + + diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h new file mode 100644 index 00000000..bc21fb11 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h @@ -0,0 +1,115 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom4_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM4_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM4_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM4_USART_Initialize( void ); + +bool SERCOM4_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM4_USART_Enable( void ); + +void SERCOM4_USART_Disable( void ); + +void SERCOM4_USART_TransmitterEnable( void ); + +void SERCOM4_USART_TransmitterDisable( void ); + +bool SERCOM4_USART_Write( void *buffer, const size_t size ); + +bool SERCOM4_USART_TransmitComplete( void ); + + +bool SERCOM4_USART_TransmitterIsReady( void ); + +void SERCOM4_USART_WriteByte( int data ); + + +void SERCOM4_USART_ReceiverEnable( void ); + +void SERCOM4_USART_ReceiverDisable( void ); + +bool SERCOM4_USART_Read( void *buffer, const size_t size ); + +bool SERCOM4_USART_ReceiverIsReady( void ); + +int SERCOM4_USART_ReadByte( void ); + +USART_ERROR SERCOM4_USART_ErrorGet( void ); + +uint32_t SERCOM4_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM4_USART_H diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h new file mode 100644 index 00000000..ab6321c6 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h @@ -0,0 +1,405 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchronous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom_usart_common.h + + Summary + Data Type definition of the USART Peripheral Interface Plib. + + Description + This file defines the Data Types for the USART Plib. + + Remarks: + None. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_USART_COMMON_H // Guards against multiple inclusion +#define PLIB_SERCOM_USART_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* USART Error convenience macros */ +// ***************************************************************************** +// ***************************************************************************** + /* Error status when no error has occurred */ +#define USART_ERROR_NONE 0U + + /* Error status when parity error has occurred */ +#define USART_ERROR_PARITY SERCOM_USART_INT_STATUS_PERR_Msk + + /* Error status when framing error has occurred */ +#define USART_ERROR_FRAMING SERCOM_USART_INT_STATUS_FERR_Msk + + /* Error status when overrun error has occurred */ +#define USART_ERROR_OVERRUN SERCOM_USART_INT_STATUS_BUFOVF_Msk + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* USART Errors + + Summary: + Defines the data type for the USART peripheral errors. + + Description: + This may be used to check the type of error occurred with the USART + peripheral during error status. + + Remarks: + None. +*/ + +typedef uint16_t USART_ERROR; + +// ***************************************************************************** +/* USART DATA + + Summary: + Defines the data type for the USART peripheral data. + + Description: + This may be used to check the type of data with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_DATA_5_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT, + USART_DATA_6_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT, + USART_DATA_7_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT, + USART_DATA_8_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT, + USART_DATA_9_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT, + + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_DATA_INVALID = 0xFFFFFFFFU + +} USART_DATA; + +// ***************************************************************************** +/* USART PARITY + + Summary: + Defines the data type for the USART peripheral parity. + + Description: + This may be used to check the type of parity with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_PARITY_EVEN = SERCOM_USART_INT_CTRLB_PMODE_EVEN, + + USART_PARITY_ODD = SERCOM_USART_INT_CTRLB_PMODE_ODD, + + /* This enum is defined to set frame format only + * This value won't be written to register + */ + USART_PARITY_NONE = 0x2, + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_PARITY_INVALID = 0xFFFFFFFFU + +} USART_PARITY; + +// ***************************************************************************** +/* USART STOP + + Summary: + Defines the data type for the USART peripheral stop bits. + + Description: + This may be used to check the type of stop bits with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_STOP_0_BIT = SERCOM_USART_INT_CTRLB_SBMODE_1_BIT, + USART_STOP_1_BIT = SERCOM_USART_INT_CTRLB_SBMODE_2_BIT, + + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_STOP_INVALID = 0xFFFFFFFFU + +} USART_STOP; + +// ***************************************************************************** +/* USART LIN Command + + Summary: + Defines the data type for the USART peripheral LIN Command. + + Description: + This may be used to set the USART LIN Master mode command. + + Remarks: + None. +*/ + +typedef enum +{ + USART_LIN_MASTER_CMD_NONE = SERCOM_USART_INT_CTRLB_LINCMD_NONE, + + USART_LIN_MASTER_CMD_SOFTWARE_CONTROLLED = SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD, + + USART_LIN_MASTER_CMD_AUTO_TRANSMIT = SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD + +} USART_LIN_MASTER_CMD; + +// ***************************************************************************** +/* USART Serial Configuration + + Summary: + Defines the data type for the USART serial configurations. + + Description: + This may be used to set the serial configurations for USART. + + Remarks: + None. +*/ + +typedef struct +{ + uint32_t baudRate; + + USART_PARITY parity; + + USART_DATA dataWidth; + + USART_STOP stopBits; + +} USART_SERIAL_SETUP; + +// ***************************************************************************** +/* Callback Function Pointer + + Summary: + Defines the data type and function signature for the USART peripheral + callback function. + + Description: + This data type defines the function signature for the USART peripheral + callback function. The USART peripheral will call back the client's + function with this signature when the USART buffer event has occurred. + + Remarks: + None. +*/ + +typedef void (*SERCOM_USART_CALLBACK)( uintptr_t context ); + +// ***************************************************************************** +/* SERCOM USART Object + + Summary: + Defines the data type for the data structures used for + peripheral operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + void * txBuffer; + + size_t txSize; + + size_t txProcessedSize; + + SERCOM_USART_CALLBACK txCallback; + + uintptr_t txContext; + + bool txBusyStatus; + + void * rxBuffer; + + size_t rxSize; + + size_t rxProcessedSize; + + SERCOM_USART_CALLBACK rxCallback; + + uintptr_t rxContext; + + bool rxBusyStatus; + + USART_ERROR errorStatus; + +} SERCOM_USART_OBJECT; + + +typedef enum +{ + /* Threshold number of bytes are available in the receive ring buffer */ + SERCOM_USART_EVENT_READ_THRESHOLD_REACHED = 0, + + /* Receive ring buffer is full. Application must read the data out to avoid missing data on the next RX interrupt. */ + SERCOM_USART_EVENT_READ_BUFFER_FULL, + + /* USART error. Application must call the SERCOMx_USART_ErrorGet API to get the type of error and clear the error. */ + SERCOM_USART_EVENT_READ_ERROR, + + /* Threshold number of free space is available in the transmit ring buffer */ + SERCOM_USART_EVENT_WRITE_THRESHOLD_REACHED, + + /* Recevie break signal is detected */ + SERCOM_USART_EVENT_BREAK_SIGNAL_DETECTED, +}SERCOM_USART_EVENT; + +// ***************************************************************************** +/* Callback Function Pointer + + Summary: + Defines the data type and function signature for the USART peripheral + callback function. + + Description: + This data type defines the function signature for the USART peripheral + callback function. The USART peripheral will call back the client's + function with this signature when the USART buffer event has occurred. + + Remarks: + None. +*/ + +typedef void (*SERCOM_USART_RING_BUFFER_CALLBACK)(SERCOM_USART_EVENT event, uintptr_t context ); + +// ***************************************************************************** +/* SERCOM USART Ring Buffer Object + + Summary: + Defines the data type for the data structures used for + peripheral operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + SERCOM_USART_RING_BUFFER_CALLBACK wrCallback; + + uintptr_t wrContext; + + uint32_t wrInIndex; + + uint32_t wrOutIndex; + + uint32_t wrBufferSize; + + bool isWrNotificationEnabled; + + uint32_t wrThreshold; + + bool isWrNotifyPersistently; + + SERCOM_USART_RING_BUFFER_CALLBACK rdCallback; + + uintptr_t rdContext; + + uint32_t rdInIndex; + + uint32_t rdOutIndex; + + uint32_t rdBufferSize; + + bool isRdNotificationEnabled; + + uint32_t rdThreshold; + + bool isRdNotifyPersistently; + + USART_ERROR errorStatus; + +} SERCOM_USART_RING_BUFFER_OBJECT; + +// ***************************************************************************** +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM_USART_COMMON_H diff --git a/bms/bms/bms_config/src/config/default/startup_xc32.c b/bms/bms/bms_config/src/config/default/startup_xc32.c new file mode 100644 index 00000000..d9430dd5 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/startup_xc32.c @@ -0,0 +1,145 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include "device.h" +#include "interrupts.h" + +/* + * The MPLAB X Simulator does not yet support simulation of programming the + * GPNVM bits yet. We can remove this once it supports the FRDY bit. + */ + /* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.1 deviated 1 time. Deviation record ID - H3_MISRAC_2012_R_21_1_DR_1 */ +#ifdef __MPLAB_DEBUGGER_SIMULATOR +#define __XC32_SKIP_STARTUP_GPNVM_WAIT +#endif +/* MISRAC 2012 deviation block end */ + +/* + * This startup code relies on features that are specific to the MPLAB XC32 + * toolchain. Do not use it with other toolchains. + */ +#ifndef __XC32 +#warning This startup code is intended for use with the MPLAB XC32 Compiler only. +#endif + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated 5 times. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 6 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ + +/* array initialization function */ +extern void __attribute__((long_call)) __libc_init_array(void); + +/* Optional application-provided functions */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_bootstrap(void); + +/* Reserved for use by the MPLAB XC32 Compiler */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_bootstrap(void); + +/* Linker defined variables */ +extern uint32_t __svectors; +#if defined (__REINIT_STACK_POINTER) +extern uint32_t _stack; +#endif + +/* MISRAC 2012 deviation block end */ + + +extern int main(void); + + + +/* Brief default application function used as a weak reference */ +extern void Dummy_App_Func(void); +void __attribute__((optimize("-O1"),long_call))Dummy_App_Func(void) +{ + /* Do nothing */ + return; +} + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void __attribute__((optimize("-O1"), section(".text.Reset_Handler"), long_call, noreturn)) Reset_Handler(void) +{ +#ifdef SCB_VTOR_TBLOFF_Msk + uint32_t *pSrc; +#endif + +#if defined (__REINIT_STACK_POINTER) + /* Initialize SP from linker-defined _stack symbol. */ + __set_MSP((uint32_t)&_stack); + +#ifdef SCB_VTOR_TBLOFF_Msk + /* Buy stack for locals */ + __asm__ volatile ("sub sp, sp, #8" : : : "sp"); +#endif + __asm__ volatile ("add r7, sp, #0" : : : "r7"); +#endif + + /* Call the optional application-provided _on_reset() function. */ + _on_reset(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_reset(); + + /* Initialize data after TCM is enabled. + * Data initialization from the XC32 .dinit template */ + __pic32c_data_initialization(); + + +# ifdef SCB_VTOR_TBLOFF_Msk + /* Set the vector-table base address in FLASH */ + pSrc = (uint32_t *) & __svectors; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); +# endif /* SCB_VTOR_TBLOFF_Msk */ + + /* Initialize the C library */ + __libc_init_array(); + + /* Call the optional application-provided _on_bootstrap() function. */ + _on_bootstrap(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_bootstrap(); + + /* Branch to application's main function */ + (void)main(); + +#if (defined(__DEBUG) || defined(__DEBUG_D)) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + + while (true) + { + /* Infinite loop */ + } +} diff --git a/bms/bms/bms_config/src/config/default/stdio/xc32_monitor.c b/bms/bms/bms_config/src/config/default/stdio/xc32_monitor.c new file mode 100644 index 00000000..64afa35a --- /dev/null +++ b/bms/bms/bms_config/src/config/default/stdio/xc32_monitor.c @@ -0,0 +1,73 @@ +/******************************************************************************* + Debug Console Source file + + Company: + Microchip Technology Inc. + + File Name: + xc32_monitor.c + + Summary: + debug console Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +#include +#include "definitions.h" + +extern int read(int handle, void *buffer, unsigned int len); +extern int write(int handle, void * buffer, size_t count); + + +int read(int handle, void *buffer, unsigned int len) +{ + int nChars = 0; + bool success = false; + if ((handle == 0) && (len > 0U)) + { + do + { + success = SERCOM4_USART_Read(buffer, 1); + }while( !success); + nChars = 1; + } + return nChars; +} + +int write(int handle, void * buffer, size_t count) +{ + bool success = false; + if (handle == 1) + { + do + { + success = SERCOM4_USART_Write(buffer, count); + }while( !success); + } + return (int)count; +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/toolchain_specifics.h b/bms/bms/bms_config/src/config/default/toolchain_specifics.h new file mode 100644 index 00000000..96407a4e --- /dev/null +++ b/bms/bms/bms_config/src/config/default/toolchain_specifics.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef TOOLCHAIN_SPECIFICS_H +#define TOOLCHAIN_SPECIFICS_H + +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +#pragma GCC diagnostic push +#ifndef __cplusplus + #pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#include "cmsis_compiler.h" +#pragma GCC diagnostic pop + +#include + +#define NO_INIT __attribute__((section(".no_init"))) +#define SECTION(a) __attribute__((__section__(a))) + +#define CACHE_LINE_SIZE (4u) +#define CACHE_ALIGN + +#define CACHE_ALIGNED_SIZE_GET(size) ((size) + ((((size) % (CACHE_LINE_SIZE))!= 0U)? ((CACHE_LINE_SIZE) - ((size) % (CACHE_LINE_SIZE))) : (0U))) + +#ifndef FORMAT_ATTRIBUTE + #define FORMAT_ATTRIBUTE(archetype, string_index, first_to_check) __attribute__ ((format (archetype, string_index, first_to_check))) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // end of header + diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c new file mode 100644 index 00000000..fa0edee2 --- /dev/null +++ b/bms/bms/bms_config/src/main.c @@ -0,0 +1,57 @@ +/******************************************************************************* + Main Source File + + Company: + Microchip Technology Inc. + + File Name: + main.c + + Summary: + This file contains the "main" function for a project. + + Description: + This file contains the "main" function for a project. The + "main" function calls the "SYS_Initialize" function to initialize the state + machines of all modules in the system + *******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Main Entry Point +// ***************************************************************************** +// ***************************************************************************** + +int main ( void ) +{ + /* Initialize all modules */ + SYS_Initialize ( NULL ); + + while ( true ) + { + /* Maintain state machines of all polled MPLAB Harmony modules. */ + SYS_Tasks ( ); + } + + /* Execution should not come here during normal operation */ + + return ( EXIT_FAILURE ); +} + + +/******************************************************************************* + End of File +*/ + diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ac.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ac.h new file mode 100644 index 00000000..1f81f59a --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ac.h @@ -0,0 +1,490 @@ +/* + * Component description for AC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_AC_COMPONENT_H_ +#define _SAMC21_AC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _UINT8_(0x00) /* (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _UINT8_(0) /* (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_UINT8_(0x1) << AC_CTRLA_SWRST_Pos) /* (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & (_UINT8_(value) << AC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AC_CTRLA register */ +#define AC_CTRLA_ENABLE_Pos _UINT8_(1) /* (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << AC_CTRLA_ENABLE_Pos) /* (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & (_UINT8_(value) << AC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_CTRLA register */ +#define AC_CTRLA_Msk _UINT8_(0x03) /* (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _UINT8_(0x00) /* (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _UINT8_(0) /* (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_UINT8_(0x1) << AC_CTRLB_START0_Pos) /* (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & (_UINT8_(value) << AC_CTRLB_START0_Pos)) /* Assigment of value for START0 in the AC_CTRLB register */ +#define AC_CTRLB_START1_Pos _UINT8_(1) /* (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_UINT8_(0x1) << AC_CTRLB_START1_Pos) /* (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & (_UINT8_(value) << AC_CTRLB_START1_Pos)) /* Assigment of value for START1 in the AC_CTRLB register */ +#define AC_CTRLB_START2_Pos _UINT8_(2) /* (AC_CTRLB) Comparator 2 Start Comparison Position */ +#define AC_CTRLB_START2_Msk (_UINT8_(0x1) << AC_CTRLB_START2_Pos) /* (AC_CTRLB) Comparator 2 Start Comparison Mask */ +#define AC_CTRLB_START2(value) (AC_CTRLB_START2_Msk & (_UINT8_(value) << AC_CTRLB_START2_Pos)) /* Assigment of value for START2 in the AC_CTRLB register */ +#define AC_CTRLB_START3_Pos _UINT8_(3) /* (AC_CTRLB) Comparator 3 Start Comparison Position */ +#define AC_CTRLB_START3_Msk (_UINT8_(0x1) << AC_CTRLB_START3_Pos) /* (AC_CTRLB) Comparator 3 Start Comparison Mask */ +#define AC_CTRLB_START3(value) (AC_CTRLB_START3_Msk & (_UINT8_(value) << AC_CTRLB_START3_Pos)) /* Assigment of value for START3 in the AC_CTRLB register */ +#define AC_CTRLB_Msk _UINT8_(0x0F) /* (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _UINT8_(0) /* (AC_CTRLB Position) Comparator 3 Start Comparison */ +#define AC_CTRLB_START_Msk (_UINT8_(0xF) << AC_CTRLB_START_Pos) /* (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & (_UINT8_(value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _UINT16_(0) /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO0_Pos) /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assigment of value for COMPEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO1_Pos _UINT16_(1) /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO1_Pos) /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assigment of value for COMPEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO2_Pos _UINT16_(2) /* (AC_EVCTRL) Comparator 2 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO2_Pos) /* (AC_EVCTRL) Comparator 2 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO2(value) (AC_EVCTRL_COMPEO2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO2_Pos)) /* Assigment of value for COMPEO2 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO3_Pos _UINT16_(3) /* (AC_EVCTRL) Comparator 3 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO3_Pos) /* (AC_EVCTRL) Comparator 3 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO3(value) (AC_EVCTRL_COMPEO3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO3_Pos)) /* Assigment of value for COMPEO3 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO0_Pos _UINT16_(4) /* (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO0_Pos) /* (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assigment of value for WINEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO1_Pos _UINT16_(5) /* (AC_EVCTRL) Window 1 Event Output Enable Position */ +#define AC_EVCTRL_WINEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO1_Pos) /* (AC_EVCTRL) Window 1 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO1(value) (AC_EVCTRL_WINEO1_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO1_Pos)) /* Assigment of value for WINEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI0_Pos _UINT16_(8) /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI0_Pos) /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assigment of value for COMPEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI1_Pos _UINT16_(9) /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI1_Pos) /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assigment of value for COMPEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI2_Pos _UINT16_(10) /* (AC_EVCTRL) Comparator 2 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI2_Pos) /* (AC_EVCTRL) Comparator 2 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI2(value) (AC_EVCTRL_COMPEI2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI2_Pos)) /* Assigment of value for COMPEI2 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI3_Pos _UINT16_(11) /* (AC_EVCTRL) Comparator 3 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI3_Pos) /* (AC_EVCTRL) Comparator 3 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI3(value) (AC_EVCTRL_COMPEI3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI3_Pos)) /* Assigment of value for COMPEI3 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI0_Pos _UINT16_(12) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI0_Pos) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assigment of value for INVEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI1_Pos _UINT16_(13) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI1_Pos) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assigment of value for INVEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI2_Pos _UINT16_(14) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI2_Pos) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI2(value) (AC_EVCTRL_INVEI2_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI2_Pos)) /* Assigment of value for INVEI2 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI3_Pos _UINT16_(15) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI3_Pos) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI3(value) (AC_EVCTRL_INVEI3_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI3_Pos)) /* Assigment of value for INVEI3 in the AC_EVCTRL register */ +#define AC_EVCTRL_Msk _UINT16_(0xFF3F) /* (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _UINT16_(0) /* (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEO_Pos) /* (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _UINT16_(4) /* (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_UINT16_(0x3) << AC_EVCTRL_WINEO_Pos) /* (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _UINT16_(8) /* (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEI_Pos) /* (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _UINT16_(12) /* (AC_EVCTRL Position) Comparator 3 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_UINT16_(0xF) << AC_EVCTRL_INVEI_Pos) /* (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _UINT8_(0) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP0_Pos) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & (_UINT8_(value) << AC_INTENCLR_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP1_Pos _UINT8_(1) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP1_Pos) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & (_UINT8_(value) << AC_INTENCLR_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP2_Pos _UINT8_(2) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Position */ +#define AC_INTENCLR_COMP2_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP2_Pos) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP2(value) (AC_INTENCLR_COMP2_Msk & (_UINT8_(value) << AC_INTENCLR_COMP2_Pos)) /* Assigment of value for COMP2 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP3_Pos _UINT8_(3) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Position */ +#define AC_INTENCLR_COMP3_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP3_Pos) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP3(value) (AC_INTENCLR_COMP3_Msk & (_UINT8_(value) << AC_INTENCLR_COMP3_Pos)) /* Assigment of value for COMP3 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN0_Pos _UINT8_(4) /* (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN0_Pos) /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & (_UINT8_(value) << AC_INTENCLR_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN1_Pos _UINT8_(5) /* (AC_INTENCLR) Window 1 Interrupt Enable Position */ +#define AC_INTENCLR_WIN1_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN1_Pos) /* (AC_INTENCLR) Window 1 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN1(value) (AC_INTENCLR_WIN1_Msk & (_UINT8_(value) << AC_INTENCLR_WIN1_Pos)) /* Assigment of value for WIN1 in the AC_INTENCLR register */ +#define AC_INTENCLR_Msk _UINT8_(0x3F) /* (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _UINT8_(0) /* (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_UINT8_(0xF) << AC_INTENCLR_COMP_Pos) /* (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & (_UINT8_(value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _UINT8_(4) /* (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_UINT8_(0x3) << AC_INTENCLR_WIN_Pos) /* (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & (_UINT8_(value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _UINT8_(0x00) /* (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _UINT8_(0) /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_UINT8_(0x1) << AC_INTENSET_COMP0_Pos) /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & (_UINT8_(value) << AC_INTENSET_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENSET register */ +#define AC_INTENSET_COMP1_Pos _UINT8_(1) /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_UINT8_(0x1) << AC_INTENSET_COMP1_Pos) /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & (_UINT8_(value) << AC_INTENSET_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENSET register */ +#define AC_INTENSET_COMP2_Pos _UINT8_(2) /* (AC_INTENSET) Comparator 2 Interrupt Enable Position */ +#define AC_INTENSET_COMP2_Msk (_UINT8_(0x1) << AC_INTENSET_COMP2_Pos) /* (AC_INTENSET) Comparator 2 Interrupt Enable Mask */ +#define AC_INTENSET_COMP2(value) (AC_INTENSET_COMP2_Msk & (_UINT8_(value) << AC_INTENSET_COMP2_Pos)) /* Assigment of value for COMP2 in the AC_INTENSET register */ +#define AC_INTENSET_COMP3_Pos _UINT8_(3) /* (AC_INTENSET) Comparator 3 Interrupt Enable Position */ +#define AC_INTENSET_COMP3_Msk (_UINT8_(0x1) << AC_INTENSET_COMP3_Pos) /* (AC_INTENSET) Comparator 3 Interrupt Enable Mask */ +#define AC_INTENSET_COMP3(value) (AC_INTENSET_COMP3_Msk & (_UINT8_(value) << AC_INTENSET_COMP3_Pos)) /* Assigment of value for COMP3 in the AC_INTENSET register */ +#define AC_INTENSET_WIN0_Pos _UINT8_(4) /* (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_UINT8_(0x1) << AC_INTENSET_WIN0_Pos) /* (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & (_UINT8_(value) << AC_INTENSET_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENSET register */ +#define AC_INTENSET_WIN1_Pos _UINT8_(5) /* (AC_INTENSET) Window 1 Interrupt Enable Position */ +#define AC_INTENSET_WIN1_Msk (_UINT8_(0x1) << AC_INTENSET_WIN1_Pos) /* (AC_INTENSET) Window 1 Interrupt Enable Mask */ +#define AC_INTENSET_WIN1(value) (AC_INTENSET_WIN1_Msk & (_UINT8_(value) << AC_INTENSET_WIN1_Pos)) /* Assigment of value for WIN1 in the AC_INTENSET register */ +#define AC_INTENSET_Msk _UINT8_(0x3F) /* (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _UINT8_(0) /* (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_UINT8_(0xF) << AC_INTENSET_COMP_Pos) /* (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & (_UINT8_(value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _UINT8_(4) /* (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_UINT8_(0x3) << AC_INTENSET_WIN_Pos) /* (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & (_UINT8_(value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _UINT8_(0) /* (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP0_Pos) /* (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & (_UINT8_(value) << AC_INTFLAG_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP1_Pos _UINT8_(1) /* (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP1_Pos) /* (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & (_UINT8_(value) << AC_INTFLAG_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP2_Pos _UINT8_(2) /* (AC_INTFLAG) Comparator 2 Position */ +#define AC_INTFLAG_COMP2_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP2_Pos) /* (AC_INTFLAG) Comparator 2 Mask */ +#define AC_INTFLAG_COMP2(value) (AC_INTFLAG_COMP2_Msk & (_UINT8_(value) << AC_INTFLAG_COMP2_Pos)) /* Assigment of value for COMP2 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP3_Pos _UINT8_(3) /* (AC_INTFLAG) Comparator 3 Position */ +#define AC_INTFLAG_COMP3_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP3_Pos) /* (AC_INTFLAG) Comparator 3 Mask */ +#define AC_INTFLAG_COMP3(value) (AC_INTFLAG_COMP3_Msk & (_UINT8_(value) << AC_INTFLAG_COMP3_Pos)) /* Assigment of value for COMP3 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN0_Pos _UINT8_(4) /* (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN0_Pos) /* (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & (_UINT8_(value) << AC_INTFLAG_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN1_Pos _UINT8_(5) /* (AC_INTFLAG) Window 1 Position */ +#define AC_INTFLAG_WIN1_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN1_Pos) /* (AC_INTFLAG) Window 1 Mask */ +#define AC_INTFLAG_WIN1(value) (AC_INTFLAG_WIN1_Msk & (_UINT8_(value) << AC_INTFLAG_WIN1_Pos)) /* Assigment of value for WIN1 in the AC_INTFLAG register */ +#define AC_INTFLAG_Msk _UINT8_(0x3F) /* (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _UINT8_(0) /* (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_UINT8_(0xF) << AC_INTFLAG_COMP_Pos) /* (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & (_UINT8_(value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _UINT8_(4) /* (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_UINT8_(0x3) << AC_INTFLAG_WIN_Pos) /* (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & (_UINT8_(value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _UINT8_(0x00) /* (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _UINT8_(0) /* (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_UINT8_(0x1) << AC_STATUSA_STATE0_Pos) /* (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & (_UINT8_(value) << AC_STATUSA_STATE0_Pos)) /* Assigment of value for STATE0 in the AC_STATUSA register */ +#define AC_STATUSA_STATE1_Pos _UINT8_(1) /* (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_UINT8_(0x1) << AC_STATUSA_STATE1_Pos) /* (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & (_UINT8_(value) << AC_STATUSA_STATE1_Pos)) /* Assigment of value for STATE1 in the AC_STATUSA register */ +#define AC_STATUSA_STATE2_Pos _UINT8_(2) /* (AC_STATUSA) Comparator 2 Current State Position */ +#define AC_STATUSA_STATE2_Msk (_UINT8_(0x1) << AC_STATUSA_STATE2_Pos) /* (AC_STATUSA) Comparator 2 Current State Mask */ +#define AC_STATUSA_STATE2(value) (AC_STATUSA_STATE2_Msk & (_UINT8_(value) << AC_STATUSA_STATE2_Pos)) /* Assigment of value for STATE2 in the AC_STATUSA register */ +#define AC_STATUSA_STATE3_Pos _UINT8_(3) /* (AC_STATUSA) Comparator 3 Current State Position */ +#define AC_STATUSA_STATE3_Msk (_UINT8_(0x1) << AC_STATUSA_STATE3_Pos) /* (AC_STATUSA) Comparator 3 Current State Mask */ +#define AC_STATUSA_STATE3(value) (AC_STATUSA_STATE3_Msk & (_UINT8_(value) << AC_STATUSA_STATE3_Pos)) /* Assigment of value for STATE3 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_Pos _UINT8_(4) /* (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assigment of value for WSTATE0 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_WSTATE1_Pos _UINT8_(6) /* (AC_STATUSA) Window 1 Current State Position */ +#define AC_STATUSA_WSTATE1_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Window 1 Current State Mask */ +#define AC_STATUSA_WSTATE1(value) (AC_STATUSA_WSTATE1_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE1_Pos)) /* Assigment of value for WSTATE1 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE1_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE1_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE1_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE1_ABOVE (AC_STATUSA_WSTATE1_ABOVE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE1_INSIDE (AC_STATUSA_WSTATE1_INSIDE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE1_BELOW (AC_STATUSA_WSTATE1_BELOW_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _UINT8_(0xFF) /* (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _UINT8_(0) /* (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_UINT8_(0xF) << AC_STATUSA_STATE_Pos) /* (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & (_UINT8_(value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _UINT8_(0x00) /* (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _UINT8_(0) /* (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_UINT8_(0x1) << AC_STATUSB_READY0_Pos) /* (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & (_UINT8_(value) << AC_STATUSB_READY0_Pos)) /* Assigment of value for READY0 in the AC_STATUSB register */ +#define AC_STATUSB_READY1_Pos _UINT8_(1) /* (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_UINT8_(0x1) << AC_STATUSB_READY1_Pos) /* (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & (_UINT8_(value) << AC_STATUSB_READY1_Pos)) /* Assigment of value for READY1 in the AC_STATUSB register */ +#define AC_STATUSB_READY2_Pos _UINT8_(2) /* (AC_STATUSB) Comparator 2 Ready Position */ +#define AC_STATUSB_READY2_Msk (_UINT8_(0x1) << AC_STATUSB_READY2_Pos) /* (AC_STATUSB) Comparator 2 Ready Mask */ +#define AC_STATUSB_READY2(value) (AC_STATUSB_READY2_Msk & (_UINT8_(value) << AC_STATUSB_READY2_Pos)) /* Assigment of value for READY2 in the AC_STATUSB register */ +#define AC_STATUSB_READY3_Pos _UINT8_(3) /* (AC_STATUSB) Comparator 3 Ready Position */ +#define AC_STATUSB_READY3_Msk (_UINT8_(0x1) << AC_STATUSB_READY3_Pos) /* (AC_STATUSB) Comparator 3 Ready Mask */ +#define AC_STATUSB_READY3(value) (AC_STATUSB_READY3_Msk & (_UINT8_(value) << AC_STATUSB_READY3_Pos)) /* Assigment of value for READY3 in the AC_STATUSB register */ +#define AC_STATUSB_Msk _UINT8_(0x0F) /* (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _UINT8_(0) /* (AC_STATUSB Position) Comparator 3 Ready */ +#define AC_STATUSB_READY_Msk (_UINT8_(0xF) << AC_STATUSB_READY_Pos) /* (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & (_UINT8_(value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /* (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AC_DBGCTRL register */ +#define AC_DBGCTRL_Msk _UINT8_(0x01) /* (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _UINT8_(0x00) /* (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _UINT8_(0) /* (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN0_Pos) /* (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & (_UINT8_(value) << AC_WINCTRL_WEN0_Pos)) /* Assigment of value for WEN0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_Pos _UINT8_(1) /* (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL0_Pos)) /* Assigment of value for WINTSEL0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_WEN1_Pos _UINT8_(4) /* (AC_WINCTRL) Window 1 Mode Enable Position */ +#define AC_WINCTRL_WEN1_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN1_Pos) /* (AC_WINCTRL) Window 1 Mode Enable Mask */ +#define AC_WINCTRL_WEN1(value) (AC_WINCTRL_WEN1_Msk & (_UINT8_(value) << AC_WINCTRL_WEN1_Pos)) /* Assigment of value for WEN1 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL1_Pos _UINT8_(5) /* (AC_WINCTRL) Window 1 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL1_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Window 1 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL1(value) (AC_WINCTRL_WINTSEL1_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL1_Pos)) /* Assigment of value for WINTSEL1 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL1_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL1_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL1_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL1_ABOVE (AC_WINCTRL_WINTSEL1_ABOVE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL1_INSIDE (AC_WINCTRL_WINTSEL1_INSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL1_BELOW (AC_WINCTRL_WINTSEL1_BELOW_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE (AC_WINCTRL_WINTSEL1_OUTSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _UINT8_(0x77) /* (AC_WINCTRL) Register Mask */ + + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _UINT8_(0x00) /* (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _UINT8_(0) /* (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_UINT8_(0x3F) << AC_SCALER_VALUE_Pos) /* (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & (_UINT8_(value) << AC_SCALER_VALUE_Pos)) /* Assigment of value for VALUE in the AC_SCALER register */ +#define AC_SCALER_Msk _UINT8_(0x3F) /* (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _UINT32_(0x00) /* (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _UINT32_(1) /* (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos) /* (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SINGLE_Pos _UINT32_(2) /* (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos) /* (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assigment of value for SINGLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_Pos _UINT32_(3) /* (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assigment of value for INTSEL in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _UINT32_(0x0) /* (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _UINT32_(0x1) /* (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _UINT32_(0x2) /* (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _UINT32_(0x3) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _UINT32_(6) /* (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /* (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_Pos _UINT32_(8) /* (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _UINT32_(0x4) /* (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _UINT32_(0x5) /* (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _UINT32_(0x6) /* (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _UINT32_(0x7) /* (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _UINT32_(12) /* (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXPOS_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _UINT32_(0x4) /* (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _UINT32_(15) /* (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos) /* (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assigment of value for SWAP in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_Pos _UINT32_(16) /* (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_UINT32_(0x3) << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assigment of value for SPEED in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_LOW_Val _UINT32_(0x0) /* (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _UINT32_(0x3) /* (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Low speed Position */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _UINT32_(19) /* (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_UINT32_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /* (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & (_UINT32_(value) << AC_COMPCTRL_HYSTEN_Pos)) /* Assigment of value for HYSTEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_Pos _UINT32_(24) /* (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assigment of value for FLEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _UINT32_(0x1) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _UINT32_(0x2) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _UINT32_(28) /* (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assigment of value for OUT in the AC_COMPCTRL register */ +#define AC_COMPCTRL_OUT_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _UINT32_(0x1) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _UINT32_(0x2) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _UINT32_(0x370BF75E) /* (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_WINCTRL_Pos _UINT32_(2) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) /* Assigment of value for WINCTRL in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL0_Pos _UINT32_(3) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assigment of value for COMPCTRL0 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL1_Pos _UINT32_(4) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assigment of value for COMPCTRL1 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL2_Pos _UINT32_(5) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL2_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL2_Pos) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL2(value) (AC_SYNCBUSY_COMPCTRL2_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL2_Pos)) /* Assigment of value for COMPCTRL2 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL3_Pos _UINT32_(6) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL3_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL3_Pos) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL3(value) (AC_SYNCBUSY_COMPCTRL3_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL3_Pos)) /* Assigment of value for COMPCTRL3 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_Msk _UINT32_(0x0000007F) /* (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _UINT32_(3) /* (AC_SYNCBUSY Position) COMPCTRL 3 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_UINT32_(0xF) << AC_SYNCBUSY_COMPCTRL_Pos) /* (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/** \brief AC register offsets definitions */ +#define AC_CTRLA_REG_OFST _UINT32_(0x00) /* (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST _UINT32_(0x01) /* (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST _UINT32_(0x02) /* (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST _UINT32_(0x04) /* (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST _UINT32_(0x05) /* (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST _UINT32_(0x06) /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST _UINT32_(0x07) /* (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST _UINT32_(0x08) /* (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST _UINT32_(0x0A) /* (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST _UINT32_(0x0C) /* (AC_SCALER) Scaler n Offset */ +#define AC_SCALER0_REG_OFST _UINT32_(0x0C) /* (AC_SCALER0) Scaler n Offset */ +#define AC_SCALER1_REG_OFST _UINT32_(0x0D) /* (AC_SCALER1) Scaler n Offset */ +#define AC_SCALER2_REG_OFST _UINT32_(0x0E) /* (AC_SCALER2) Scaler n Offset */ +#define AC_SCALER3_REG_OFST _UINT32_(0x0F) /* (AC_SCALER3) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_COMPCTRL0_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL0) Comparator Control n Offset */ +#define AC_COMPCTRL1_REG_OFST _UINT32_(0x14) /* (AC_COMPCTRL1) Comparator Control n Offset */ +#define AC_COMPCTRL2_REG_OFST _UINT32_(0x18) /* (AC_COMPCTRL2) Comparator Control n Offset */ +#define AC_COMPCTRL3_REG_OFST _UINT32_(0x1C) /* (AC_COMPCTRL3) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (AC_SYNCBUSY) Synchronization Busy Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[4]; /**< Offset: 0x0C (R/W 8) Scaler n */ + __IO uint32_t AC_COMPCTRL[4]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_AC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/adc.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/adc.h new file mode 100644 index 00000000..418bc316 --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/adc.h @@ -0,0 +1,523 @@ +/* + * Component description for ADC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_ADC_COMPONENT_H_ +#define _SAMC21_ADC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _UINT8_(0) /* (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_UINT8_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT8_(value) << ADC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_CTRLA register */ +#define ADC_CTRLA_ENABLE_Pos _UINT8_(1) /* (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT8_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_CTRLA register */ +#define ADC_CTRLA_SLAVEEN_Pos _UINT8_(5) /* (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_UINT8_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT8_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assigment of value for SLAVEEN in the ADC_CTRLA register */ +#define ADC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (ADC_CTRLA) Run During Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run During Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the ADC_CTRLA register */ +#define ADC_CTRLA_ONDEMAND_Pos _UINT8_(7) /* (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_UINT8_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT8_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the ADC_CTRLA register */ +#define ADC_CTRLA_Msk _UINT8_(0xE3) /* (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_PRESCALER_Pos _UINT8_(0) /* (ADC_CTRLB) Prescaler Configuration Position */ +#define ADC_CTRLB_PRESCALER_Msk (_UINT8_(0x7) << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Prescaler Configuration Mask */ +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & (_UINT8_(value) << ADC_CTRLB_PRESCALER_Pos)) /* Assigment of value for PRESCALER in the ADC_CTRLB register */ +#define ADC_CTRLB_PRESCALER_DIV2_Val _UINT8_(0x0) /* (ADC_CTRLB) Peripheral clock / 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _UINT8_(0x1) /* (ADC_CTRLB) Peripheral clock / 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _UINT8_(0x2) /* (ADC_CTRLB) Peripheral clock / 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _UINT8_(0x3) /* (ADC_CTRLB) Peripheral clock / 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _UINT8_(0x4) /* (ADC_CTRLB) Peripheral clock / 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _UINT8_(0x5) /* (ADC_CTRLB) Peripheral clock / 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _UINT8_(0x6) /* (ADC_CTRLB) Peripheral clock / 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _UINT8_(0x7) /* (ADC_CTRLB) Peripheral clock / 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 2 Position */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 4 Position */ +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 8 Position */ +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 16 Position */ +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 32 Position */ +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 64 Position */ +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 128 Position */ +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 256 Position */ +#define ADC_CTRLB_Msk _UINT8_(0x07) /* (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assigment of value for REFSEL in the ADC_REFCTRL register */ +#define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x1) /* (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x3) /* (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_DAC_Val _UINT8_(0x4) /* (ADC_REFCTRL) DAC */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _UINT8_(0x5) /* (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/1.6 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference Position */ +#define ADC_REFCTRL_REFSEL_DAC (ADC_REFCTRL_REFSEL_DAC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) DAC Position */ +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assigment of value for REFCOMP in the ADC_REFCTRL register */ +#define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assigment of value for FLUSHEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assigment of value for STARTEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assigment of value for FLUSHINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assigment of value for STARTINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assigment of value for RESRDYEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assigment of value for WINMONEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENCLR register */ +#define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENCLR register */ +#define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENCLR register */ +#define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENSET register */ +#define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENSET register */ +#define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENSET register */ +#define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTFLAG register */ +#define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTFLAG register */ +#define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTFLAG register */ +#define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) ( R/ 8) Sequence Status -------- */ +#define ADC_SEQSTATUS_RESETVALUE _UINT8_(0x00) /* (ADC_SEQSTATUS) Sequence Status Reset Value */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos _UINT8_(0) /* (ADC_SEQSTATUS) Sequence State Position */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_UINT8_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) /* (ADC_SEQSTATUS) Sequence State Mask */ +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQSTATE_Pos)) /* Assigment of value for SEQSTATE in the ADC_SEQSTATUS register */ +#define ADC_SEQSTATUS_SEQBUSY_Pos _UINT8_(7) /* (ADC_SEQSTATUS) Sequence Busy Position */ +#define ADC_SEQSTATUS_SEQBUSY_Msk (_UINT8_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) /* (ADC_SEQSTATUS) Sequence Busy Mask */ +#define ADC_SEQSTATUS_SEQBUSY(value) (ADC_SEQSTATUS_SEQBUSY_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQBUSY_Pos)) /* Assigment of value for SEQBUSY in the ADC_SEQSTATUS register */ +#define ADC_SEQSTATUS_Msk _UINT8_(0x9F) /* (ADC_SEQSTATUS) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _UINT16_(0x1C) /* (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_Msk _UINT16_(0x1F1F) /* (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#define ADC_CTRLC_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLC) Control C Reset Value */ + +#define ADC_CTRLC_DIFFMODE_Pos _UINT16_(0) /* (ADC_CTRLC) Differential Mode Position */ +#define ADC_CTRLC_DIFFMODE_Msk (_UINT16_(0x1) << ADC_CTRLC_DIFFMODE_Pos) /* (ADC_CTRLC) Differential Mode Mask */ +#define ADC_CTRLC_DIFFMODE(value) (ADC_CTRLC_DIFFMODE_Msk & (_UINT16_(value) << ADC_CTRLC_DIFFMODE_Pos)) /* Assigment of value for DIFFMODE in the ADC_CTRLC register */ +#define ADC_CTRLC_LEFTADJ_Pos _UINT16_(1) /* (ADC_CTRLC) Left-Adjusted Result Position */ +#define ADC_CTRLC_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLC_LEFTADJ_Pos) /* (ADC_CTRLC) Left-Adjusted Result Mask */ +#define ADC_CTRLC_LEFTADJ(value) (ADC_CTRLC_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLC_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the ADC_CTRLC register */ +#define ADC_CTRLC_FREERUN_Pos _UINT16_(2) /* (ADC_CTRLC) Free Running Mode Position */ +#define ADC_CTRLC_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLC_FREERUN_Pos) /* (ADC_CTRLC) Free Running Mode Mask */ +#define ADC_CTRLC_FREERUN(value) (ADC_CTRLC_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLC_FREERUN_Pos)) /* Assigment of value for FREERUN in the ADC_CTRLC register */ +#define ADC_CTRLC_CORREN_Pos _UINT16_(3) /* (ADC_CTRLC) Digital Correction Logic Enable Position */ +#define ADC_CTRLC_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLC_CORREN_Pos) /* (ADC_CTRLC) Digital Correction Logic Enable Mask */ +#define ADC_CTRLC_CORREN(value) (ADC_CTRLC_CORREN_Msk & (_UINT16_(value) << ADC_CTRLC_CORREN_Pos)) /* Assigment of value for CORREN in the ADC_CTRLC register */ +#define ADC_CTRLC_RESSEL_Pos _UINT16_(4) /* (ADC_CTRLC) Conversion Result Resolution Position */ +#define ADC_CTRLC_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) Conversion Result Resolution Mask */ +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLC_RESSEL_Pos)) /* Assigment of value for RESSEL in the ADC_CTRLC register */ +#define ADC_CTRLC_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLC) 12-bit */ +#define ADC_CTRLC_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLC) 16-bit averaging mode */ +#define ADC_CTRLC_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLC) 10-bit */ +#define ADC_CTRLC_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLC) 8-bit */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 12-bit Position */ +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 16-bit averaging mode Position */ +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 10-bit Position */ +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 8-bit Position */ +#define ADC_CTRLC_R2R_Pos _UINT16_(7) /* (ADC_CTRLC) Rail-to-Rail mode enable Position */ +#define ADC_CTRLC_R2R_Msk (_UINT16_(0x1) << ADC_CTRLC_R2R_Pos) /* (ADC_CTRLC) Rail-to-Rail mode enable Mask */ +#define ADC_CTRLC_R2R(value) (ADC_CTRLC_R2R_Msk & (_UINT16_(value) << ADC_CTRLC_R2R_Pos)) /* Assigment of value for R2R in the ADC_CTRLC register */ +#define ADC_CTRLC_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLC) Window Monitor Mode Position */ +#define ADC_CTRLC_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) Window Monitor Mode Mask */ +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLC_WINMODE_Pos)) /* Assigment of value for WINMODE in the ADC_CTRLC register */ +#define ADC_CTRLC_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) No window mode (default) Position */ +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT > WINLT Position */ +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT < WINUT Position */ +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLC_DUALSEL_Pos _UINT16_(12) /* (ADC_CTRLC) Dual Mode Trigger Selection Position */ +#define ADC_CTRLC_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLC_DUALSEL_Pos)) /* Assigment of value for DUALSEL in the ADC_CTRLC register */ +#define ADC_CTRLC_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLC_Msk _UINT16_(0x37BF) /* (ADC_CTRLC) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assigment of value for SAMPLENUM in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assigment of value for ADJRES in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assigment of value for SAMPLEN in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assigment of value for OFFCOMP in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_WINLT register */ +#define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_WINUT register */ +#define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_GAINCORR register */ +#define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_OFFSETCORR register */ +#define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assigment of value for FLUSH in the ADC_SWTRIG register */ +#define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assigment of value for START in the ADC_SWTRIG register */ +#define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the ADC_DBGCTRL register */ +#define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) ( R/ 16) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _UINT16_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _UINT16_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_ENABLE_Pos _UINT16_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT16_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT16_(2) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_CTRLC_Pos _UINT16_(3) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLC_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLC(value) (ADC_SYNCBUSY_CTRLC_Msk & (_UINT16_(value) << ADC_SYNCBUSY_CTRLC_Pos)) /* Assigment of value for CTRLC in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_AVGCTRL_Pos _UINT16_(4) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT16_(5) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINLT_Pos _UINT16_(6) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINUT_Pos _UINT16_(7) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_GAINCORR_Pos _UINT16_(8) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT16_(9) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SWTRIG_Pos _UINT16_(10) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assigment of value for SWTRIG in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_Msk _UINT16_(0x07FF) /* (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x24) ( R/ 16) Result -------- */ +#define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Reset Value */ + +#define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Value Position */ +#define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the ADC_RESULT register */ +#define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ + + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#define ADC_SEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_SEQCTRL) Sequence Control Reset Value */ + +#define ADC_SEQCTRL_SEQEN_Pos _UINT32_(0) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Position */ +#define ADC_SEQCTRL_SEQEN_Msk (_UINT32_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Mask */ +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & (_UINT32_(value) << ADC_SEQCTRL_SEQEN_Pos)) /* Assigment of value for SEQEN in the ADC_SEQCTRL register */ +#define ADC_SEQCTRL_Msk _UINT32_(0xFFFFFFFF) /* (ADC_SEQCTRL) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assigment of value for BIASCOMP in the ADC_CALIB register */ +#define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assigment of value for BIASREFBUF in the ADC_CALIB register */ +#define ADC_CALIB_Msk _UINT16_(0x0707) /* (ADC_CALIB) Register Mask */ + + +/** \brief ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ +#define ADC_CTRLB_REG_OFST _UINT32_(0x01) /* (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST _UINT32_(0x02) /* (ADC_REFCTRL) Reference Control Offset */ +#define ADC_EVCTRL_REG_OFST _UINT32_(0x03) /* (ADC_EVCTRL) Event Control Offset */ +#define ADC_INTENCLR_REG_OFST _UINT32_(0x04) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST _UINT32_(0x05) /* (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST _UINT32_(0x06) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_SEQSTATUS_REG_OFST _UINT32_(0x07) /* (ADC_SEQSTATUS) Sequence Status Offset */ +#define ADC_INPUTCTRL_REG_OFST _UINT32_(0x08) /* (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLC_REG_OFST _UINT32_(0x0A) /* (ADC_CTRLC) Control C Offset */ +#define ADC_AVGCTRL_REG_OFST _UINT32_(0x0C) /* (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0D) /* (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST _UINT32_(0x0E) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST _UINT32_(0x10) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST _UINT32_(0x12) /* (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST _UINT32_(0x14) /* (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST _UINT32_(0x18) /* (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_DBGCTRL_REG_OFST _UINT32_(0x1C) /* (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_RESULT_REG_OFST _UINT32_(0x24) /* (ADC_RESULT) Result Offset */ +#define ADC_SEQCTRL_REG_OFST _UINT32_(0x28) /* (ADC_SEQCTRL) Sequence Control Offset */ +#define ADC_CALIB_REG_OFST _UINT32_(0x2C) /* (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint8_t ADC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t ADC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t ADC_REFCTRL; /**< Offset: 0x02 (R/W 8) Reference Control */ + __IO uint8_t ADC_EVCTRL; /**< Offset: 0x03 (R/W 8) Event Control */ + __IO uint8_t ADC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_SEQSTATUS; /**< Offset: 0x07 (R/ 8) Sequence Status */ + __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x08 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLC; /**< Offset: 0x0A (R/W 16) Control C */ + __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0C (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0D (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /**< Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /**< Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /**< Offset: 0x12 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x14 (R/W 16) Offset Correction */ + __I uint8_t Reserved1[0x02]; + __IO uint8_t ADC_SWTRIG; /**< Offset: 0x18 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x03]; + __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x1C (R/W 8) Debug Control */ + __I uint8_t Reserved3[0x03]; + __I uint16_t ADC_SYNCBUSY; /**< Offset: 0x20 (R/ 16) Synchronization Busy */ + __I uint8_t Reserved4[0x02]; + __I uint16_t ADC_RESULT; /**< Offset: 0x24 (R/ 16) Result */ + __I uint8_t Reserved5[0x02]; + __IO uint32_t ADC_SEQCTRL; /**< Offset: 0x28 (R/W 32) Sequence Control */ + __IO uint16_t ADC_CALIB; /**< Offset: 0x2C (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_ADC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/can.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/can.h new file mode 100644 index 00000000..b95505e8 --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/can.h @@ -0,0 +1,2527 @@ +/* + * Component description for CAN + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_CAN_COMPONENT_H_ +#define _SAMC21_CAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CAN */ +/* ************************************************************************** */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ +#define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ +#define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ +#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ +#define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ +#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ +#define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ +#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ + + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ +#define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ +#define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ +#define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ +#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ +#define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ +#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ +#define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ +#define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ + + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ +#define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ +#define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ +#define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ +#define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ + + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ +#define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ +#define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ +#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ +#define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ +#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ +#define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ +#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ + + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ +#define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ +#define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ +#define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ +#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ +#define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ +#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ +#define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ + + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ +#define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ +#define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ +#define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ +#define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ + + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ +#define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ +#define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ +#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ +#define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ +#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ +#define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ +#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ + + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ +#define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ +#define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ +#define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ +#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ +#define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ +#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ +#define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ + + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ +#define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ +#define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ +#define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ +#define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ + + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ +#define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ +#define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ +#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ +#define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ +#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ +#define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ +#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ + + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ +#define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ +#define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ +#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ +#define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ +#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ +#define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ +#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assigment of value for EFC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ +#define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ + + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ +#define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ +#define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ +#define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ +#define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ + + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ +#define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ +#define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ +#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ +#define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ +#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ +#define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ +#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ + + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ +#define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assigment of value for TXTS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ +#define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ +#define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ +#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ +#define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ +#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ +#define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assigment of value for ET in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ +#define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ + + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ +#define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assigment of value for SFID2 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ +#define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assigment of value for SFID1 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assigment of value for SFEC in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ +#define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ +#define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assigment of value for SFT in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ +#define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ +#define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assigment of value for EFID1 in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assigment of value for EFEC in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ +#define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ +#define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assigment of value for EFID2 in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ +#define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assigment of value for EFT in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ + + +/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ +#define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ + +#define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ +#define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assigment of value for SUBSTEP in the CAN_CREL register */ +#define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ +#define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assigment of value for STEP in the CAN_CREL register */ +#define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ +#define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assigment of value for REL in the CAN_CREL register */ +#define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ + + +/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ +#define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ + +#define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ +#define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assigment of value for ETV in the CAN_ENDN register */ +#define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ + + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ + +#define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ +#define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assigment of value for QOS in the CAN_MRCFG register */ +#define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ +#define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ + + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ + +#define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ +#define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assigment of value for DSJW in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ +#define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assigment of value for DTSEG2 in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ +#define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assigment of value for DTSEG1 in the CAN_DBTP register */ +#define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ +#define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assigment of value for DBRP in the CAN_DBTP register */ +#define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ +#define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ +#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assigment of value for TDC in the CAN_DBTP register */ +#define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ + + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ + +#define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ +#define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ +#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assigment of value for LBCK in the CAN_TEST register */ +#define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ +#define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assigment of value for TX in the CAN_TEST register */ +#define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ +#define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ +#define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ +#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assigment of value for RX in the CAN_TEST register */ +#define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ + + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ + +#define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ +#define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assigment of value for WDC in the CAN_RWD register */ +#define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ +#define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assigment of value for WDV in the CAN_RWD register */ +#define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ + + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ + +#define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ +#define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ +#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assigment of value for INIT in the CAN_CCCR register */ +#define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ +#define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ +#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assigment of value for CCE in the CAN_CCCR register */ +#define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ +#define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ +#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assigment of value for ASM in the CAN_CCCR register */ +#define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ +#define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ +#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assigment of value for CSA in the CAN_CCCR register */ +#define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ +#define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ +#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assigment of value for CSR in the CAN_CCCR register */ +#define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ +#define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ +#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assigment of value for MON in the CAN_CCCR register */ +#define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ +#define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ +#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assigment of value for DAR in the CAN_CCCR register */ +#define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ +#define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ +#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assigment of value for TEST in the CAN_CCCR register */ +#define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ +#define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ +#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assigment of value for FDOE in the CAN_CCCR register */ +#define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ +#define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ +#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assigment of value for BRSE in the CAN_CCCR register */ +#define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ +#define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ +#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assigment of value for PXHD in the CAN_CCCR register */ +#define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ +#define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ +#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assigment of value for EFBI in the CAN_CCCR register */ +#define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ +#define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ +#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assigment of value for TXP in the CAN_CCCR register */ +#define CAN_CCCR_NISO_Pos _UINT32_(15) /* (CAN_CCCR) Non ISO Operation Position */ +#define CAN_CCCR_NISO_Msk (_UINT32_(0x1) << CAN_CCCR_NISO_Pos) /* (CAN_CCCR) Non ISO Operation Mask */ +#define CAN_CCCR_NISO(value) (CAN_CCCR_NISO_Msk & (_UINT32_(value) << CAN_CCCR_NISO_Pos)) /* Assigment of value for NISO in the CAN_CCCR register */ +#define CAN_CCCR_Msk _UINT32_(0x0000F3FF) /* (CAN_CCCR) Register Mask */ + + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ + +#define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ +#define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assigment of value for NTSEG2 in the CAN_NBTP register */ +#define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ +#define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assigment of value for NTSEG1 in the CAN_NBTP register */ +#define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ +#define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assigment of value for NBRP in the CAN_NBTP register */ +#define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ +#define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assigment of value for NSJW in the CAN_NBTP register */ +#define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ + + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ + +#define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ +#define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assigment of value for TSS in the CAN_TSCC register */ +#define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _UINT32_(0x2) /* (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) External timestamp counter value used Position */ +#define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ +#define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assigment of value for TCP in the CAN_TSCC register */ +#define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ + + +/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ +#define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ + +#define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ +#define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assigment of value for TSC in the CAN_TSCV register */ +#define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ + + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ + +#define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ +#define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ +#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assigment of value for ETOC in the CAN_TOCC register */ +#define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ +#define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assigment of value for TOS in the CAN_TOCC register */ +#define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ +#define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ +#define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assigment of value for TOP in the CAN_TOCC register */ +#define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ + + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ + +#define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ +#define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assigment of value for TOC in the CAN_TOCV register */ +#define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ + + +/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ +#define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ + +#define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ +#define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assigment of value for TEC in the CAN_ECR register */ +#define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ +#define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assigment of value for REC in the CAN_ECR register */ +#define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ +#define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ +#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assigment of value for RP in the CAN_ECR register */ +#define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ +#define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assigment of value for CEL in the CAN_ECR register */ +#define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ + + +/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ +#define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ + +#define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ +#define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assigment of value for LEC in the CAN_PSR register */ +#define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ +#define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assigment of value for ACT in the CAN_PSR register */ +#define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ +#define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ +#define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ +#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assigment of value for EP in the CAN_PSR register */ +#define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ +#define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ +#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assigment of value for EW in the CAN_PSR register */ +#define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ +#define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ +#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assigment of value for BO in the CAN_PSR register */ +#define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ +#define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assigment of value for DLEC in the CAN_PSR register */ +#define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ +#define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ +#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assigment of value for RESI in the CAN_PSR register */ +#define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ +#define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ +#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assigment of value for RBRS in the CAN_PSR register */ +#define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ +#define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ +#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assigment of value for RFDF in the CAN_PSR register */ +#define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ +#define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ +#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assigment of value for PXE in the CAN_PSR register */ +#define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ +#define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assigment of value for TDCV in the CAN_PSR register */ +#define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ + + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ + +#define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ +#define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assigment of value for TDCF in the CAN_TDCR register */ +#define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assigment of value for TDCO in the CAN_TDCR register */ +#define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ + + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ + +#define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ +#define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ +#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assigment of value for RF0N in the CAN_IR register */ +#define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ +#define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ +#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assigment of value for RF0W in the CAN_IR register */ +#define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ +#define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ +#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assigment of value for RF0F in the CAN_IR register */ +#define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ +#define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ +#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_IR register */ +#define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ +#define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ +#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assigment of value for RF1N in the CAN_IR register */ +#define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ +#define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ +#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assigment of value for RF1W in the CAN_IR register */ +#define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ +#define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ +#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assigment of value for RF1F in the CAN_IR register */ +#define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ +#define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ +#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_IR register */ +#define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ +#define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ +#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assigment of value for HPM in the CAN_IR register */ +#define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ +#define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ +#define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assigment of value for TC in the CAN_IR register */ +#define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ +#define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ +#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assigment of value for TCF in the CAN_IR register */ +#define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ +#define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ +#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assigment of value for TFE in the CAN_IR register */ +#define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ +#define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ +#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assigment of value for TEFN in the CAN_IR register */ +#define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ +#define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assigment of value for TEFW in the CAN_IR register */ +#define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ +#define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ +#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assigment of value for TEFF in the CAN_IR register */ +#define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ +#define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ +#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_IR register */ +#define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ +#define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ +#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assigment of value for TSW in the CAN_IR register */ +#define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ +#define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ +#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assigment of value for MRAF in the CAN_IR register */ +#define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ +#define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ +#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assigment of value for TOO in the CAN_IR register */ +#define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ +#define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ +#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assigment of value for DRX in the CAN_IR register */ +#define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ +#define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ +#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assigment of value for BEC in the CAN_IR register */ +#define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ +#define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ +#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assigment of value for BEU in the CAN_IR register */ +#define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ +#define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ +#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assigment of value for ELO in the CAN_IR register */ +#define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ +#define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ +#define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assigment of value for EP in the CAN_IR register */ +#define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ +#define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ +#define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assigment of value for EW in the CAN_IR register */ +#define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ +#define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ +#define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assigment of value for BO in the CAN_IR register */ +#define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ +#define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ +#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assigment of value for WDI in the CAN_IR register */ +#define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ +#define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ +#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assigment of value for PEA in the CAN_IR register */ +#define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ +#define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ +#define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assigment of value for PED in the CAN_IR register */ +#define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ +#define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ +#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assigment of value for ARA in the CAN_IR register */ +#define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ + + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ + +#define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ +#define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ +#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assigment of value for RF0NE in the CAN_IE register */ +#define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assigment of value for RF0WE in the CAN_IE register */ +#define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ +#define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ +#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assigment of value for RF0FE in the CAN_IE register */ +#define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assigment of value for RF0LE in the CAN_IE register */ +#define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ +#define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ +#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assigment of value for RF1NE in the CAN_IE register */ +#define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assigment of value for RF1WE in the CAN_IE register */ +#define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ +#define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ +#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assigment of value for RF1FE in the CAN_IE register */ +#define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assigment of value for RF1LE in the CAN_IE register */ +#define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ +#define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ +#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assigment of value for HPME in the CAN_IE register */ +#define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ +#define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ +#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assigment of value for TCE in the CAN_IE register */ +#define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assigment of value for TCFE in the CAN_IE register */ +#define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assigment of value for TFEE in the CAN_IE register */ +#define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assigment of value for TEFNE in the CAN_IE register */ +#define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assigment of value for TEFWE in the CAN_IE register */ +#define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assigment of value for TEFFE in the CAN_IE register */ +#define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ +#define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ +#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assigment of value for TEFLE in the CAN_IE register */ +#define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assigment of value for TSWE in the CAN_IE register */ +#define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assigment of value for MRAFE in the CAN_IE register */ +#define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ +#define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assigment of value for TOOE in the CAN_IE register */ +#define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ +#define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ +#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assigment of value for DRXE in the CAN_IE register */ +#define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ +#define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ +#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assigment of value for BECE in the CAN_IE register */ +#define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ +#define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ +#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assigment of value for BEUE in the CAN_IE register */ +#define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assigment of value for ELOE in the CAN_IE register */ +#define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ +#define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ +#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assigment of value for EPE in the CAN_IE register */ +#define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ +#define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ +#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assigment of value for EWE in the CAN_IE register */ +#define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ +#define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assigment of value for BOE in the CAN_IE register */ +#define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ +#define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ +#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assigment of value for WDIE in the CAN_IE register */ +#define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assigment of value for PEAE in the CAN_IE register */ +#define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ +#define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ +#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assigment of value for PEDE in the CAN_IE register */ +#define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ +#define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ +#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assigment of value for ARAE in the CAN_IE register */ +#define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ + + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ + +#define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ +#define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ +#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assigment of value for RF0NL in the CAN_ILS register */ +#define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assigment of value for RF0WL in the CAN_ILS register */ +#define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ +#define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ +#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assigment of value for RF0FL in the CAN_ILS register */ +#define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assigment of value for RF0LL in the CAN_ILS register */ +#define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ +#define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ +#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assigment of value for RF1NL in the CAN_ILS register */ +#define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assigment of value for RF1WL in the CAN_ILS register */ +#define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ +#define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ +#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assigment of value for RF1FL in the CAN_ILS register */ +#define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assigment of value for RF1LL in the CAN_ILS register */ +#define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ +#define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ +#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assigment of value for HPML in the CAN_ILS register */ +#define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ +#define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ +#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assigment of value for TCL in the CAN_ILS register */ +#define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assigment of value for TCFL in the CAN_ILS register */ +#define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assigment of value for TFEL in the CAN_ILS register */ +#define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assigment of value for TEFNL in the CAN_ILS register */ +#define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assigment of value for TEFWL in the CAN_ILS register */ +#define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assigment of value for TEFFL in the CAN_ILS register */ +#define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ +#define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ +#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assigment of value for TEFLL in the CAN_ILS register */ +#define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assigment of value for TSWL in the CAN_ILS register */ +#define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assigment of value for MRAFL in the CAN_ILS register */ +#define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ +#define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assigment of value for TOOL in the CAN_ILS register */ +#define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ +#define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ +#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assigment of value for DRXL in the CAN_ILS register */ +#define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ +#define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ +#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assigment of value for BECL in the CAN_ILS register */ +#define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ +#define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ +#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assigment of value for BEUL in the CAN_ILS register */ +#define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assigment of value for ELOL in the CAN_ILS register */ +#define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ +#define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ +#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assigment of value for EPL in the CAN_ILS register */ +#define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ +#define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ +#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assigment of value for EWL in the CAN_ILS register */ +#define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ +#define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assigment of value for BOL in the CAN_ILS register */ +#define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ +#define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ +#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assigment of value for WDIL in the CAN_ILS register */ +#define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assigment of value for PEAL in the CAN_ILS register */ +#define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ +#define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ +#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assigment of value for PEDL in the CAN_ILS register */ +#define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ +#define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ +#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assigment of value for ARAL in the CAN_ILS register */ +#define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ + + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ + +#define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ +#define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ +#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assigment of value for EINT0 in the CAN_ILE register */ +#define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ +#define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ +#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assigment of value for EINT1 in the CAN_ILE register */ +#define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ + +#define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ +#define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ +#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ + +#define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ +#define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ +#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assigment of value for RRFE in the CAN_GFC register */ +#define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ +#define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ +#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assigment of value for RRFS in the CAN_GFC register */ +#define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ +#define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assigment of value for ANFE in the CAN_GFC register */ +#define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ +#define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assigment of value for ANFS in the CAN_GFC register */ +#define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ + + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ + +#define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ +#define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assigment of value for FLSSA in the CAN_SIDFC register */ +#define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ +#define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assigment of value for LSS in the CAN_SIDFC register */ +#define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ + + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ + +#define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ +#define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assigment of value for FLESA in the CAN_XIDFC register */ +#define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ +#define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assigment of value for LSE in the CAN_XIDFC register */ +#define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ + + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ + +#define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ +#define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assigment of value for EIDM in the CAN_XIDAM register */ +#define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ + + +/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ +#define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ + +#define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ +#define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assigment of value for BIDX in the CAN_HPMS register */ +#define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ +#define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assigment of value for MSI in the CAN_HPMS register */ +#define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ +#define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ +#define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_HPMS register */ +#define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ +#define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ +#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assigment of value for FLST in the CAN_HPMS register */ +#define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ + + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ + +#define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ +#define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ +#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assigment of value for ND0 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ +#define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ +#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assigment of value for ND1 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ +#define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ +#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assigment of value for ND2 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ +#define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ +#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assigment of value for ND3 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ +#define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ +#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assigment of value for ND4 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ +#define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ +#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assigment of value for ND5 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ +#define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ +#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assigment of value for ND6 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ +#define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ +#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assigment of value for ND7 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ +#define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ +#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assigment of value for ND8 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ +#define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ +#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assigment of value for ND9 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ +#define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ +#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assigment of value for ND10 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ +#define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ +#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assigment of value for ND11 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ +#define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ +#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assigment of value for ND12 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ +#define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ +#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assigment of value for ND13 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ +#define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ +#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assigment of value for ND14 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ +#define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ +#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assigment of value for ND15 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ +#define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ +#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assigment of value for ND16 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ +#define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ +#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assigment of value for ND17 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ +#define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ +#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assigment of value for ND18 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ +#define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ +#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assigment of value for ND19 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ +#define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ +#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assigment of value for ND20 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ +#define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ +#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assigment of value for ND21 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ +#define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ +#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assigment of value for ND22 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ +#define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ +#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assigment of value for ND23 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ +#define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ +#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assigment of value for ND24 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ +#define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ +#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assigment of value for ND25 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ +#define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ +#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assigment of value for ND26 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ +#define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ +#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assigment of value for ND27 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ +#define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ +#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assigment of value for ND28 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ +#define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ +#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assigment of value for ND29 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ +#define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ +#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assigment of value for ND30 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ +#define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ +#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assigment of value for ND31 in the CAN_NDAT1 register */ +#define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ + +#define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ +#define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ +#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ + +#define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ +#define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ +#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assigment of value for ND32 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ +#define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ +#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assigment of value for ND33 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ +#define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ +#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assigment of value for ND34 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ +#define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ +#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assigment of value for ND35 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ +#define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ +#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assigment of value for ND36 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ +#define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ +#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assigment of value for ND37 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ +#define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ +#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assigment of value for ND38 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ +#define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ +#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assigment of value for ND39 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ +#define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ +#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assigment of value for ND40 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ +#define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ +#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assigment of value for ND41 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ +#define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ +#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assigment of value for ND42 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ +#define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ +#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assigment of value for ND43 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ +#define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ +#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assigment of value for ND44 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ +#define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ +#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assigment of value for ND45 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ +#define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ +#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assigment of value for ND46 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ +#define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ +#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assigment of value for ND47 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ +#define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ +#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assigment of value for ND48 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ +#define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ +#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assigment of value for ND49 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ +#define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ +#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assigment of value for ND50 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ +#define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ +#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assigment of value for ND51 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ +#define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ +#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assigment of value for ND52 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ +#define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ +#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assigment of value for ND53 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ +#define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ +#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assigment of value for ND54 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ +#define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ +#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assigment of value for ND55 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ +#define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ +#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assigment of value for ND56 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ +#define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ +#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assigment of value for ND57 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ +#define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ +#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assigment of value for ND58 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ +#define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ +#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assigment of value for ND59 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ +#define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ +#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assigment of value for ND60 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ +#define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ +#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assigment of value for ND61 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ +#define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ +#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assigment of value for ND62 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ +#define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ +#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assigment of value for ND63 in the CAN_NDAT2 register */ +#define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ + +#define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ +#define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ +#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ + +#define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ +#define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assigment of value for F0SA in the CAN_RXF0C register */ +#define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ +#define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assigment of value for F0S in the CAN_RXF0C register */ +#define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ +#define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assigment of value for F0WM in the CAN_RXF0C register */ +#define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ +#define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assigment of value for F0OM in the CAN_RXF0C register */ +#define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ + + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ +#define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ + +#define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ +#define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assigment of value for F0FL in the CAN_RXF0S register */ +#define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ +#define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assigment of value for F0GI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ +#define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assigment of value for F0PI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ +#define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ +#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assigment of value for F0F in the CAN_RXF0S register */ +#define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ +#define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ +#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_RXF0S register */ +#define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ + + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ + +#define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ +#define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assigment of value for F0AI in the CAN_RXF0A register */ +#define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ + + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ + +#define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ +#define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assigment of value for RBSA in the CAN_RXBC register */ +#define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ + + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ + +#define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ +#define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assigment of value for F1SA in the CAN_RXF1C register */ +#define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ +#define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assigment of value for F1S in the CAN_RXF1C register */ +#define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ +#define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assigment of value for F1WM in the CAN_RXF1C register */ +#define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ +#define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assigment of value for F1OM in the CAN_RXF1C register */ +#define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ + + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ +#define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ + +#define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ +#define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assigment of value for F1FL in the CAN_RXF1S register */ +#define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ +#define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assigment of value for F1GI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ +#define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assigment of value for F1PI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ +#define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ +#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assigment of value for F1F in the CAN_RXF1S register */ +#define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ +#define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ +#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ +#define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assigment of value for DMS in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ +#define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ + + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ + +#define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ +#define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assigment of value for F1AI in the CAN_RXF1A register */ +#define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ + + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ + +#define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ +#define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assigment of value for F0DS in the CAN_RXESC register */ +#define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ +#define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assigment of value for F1DS in the CAN_RXESC register */ +#define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ +#define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assigment of value for RBDS in the CAN_RXESC register */ +#define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ + + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ + +#define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ +#define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assigment of value for TBSA in the CAN_TXBC register */ +#define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assigment of value for NDTB in the CAN_TXBC register */ +#define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ +#define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assigment of value for TFQS in the CAN_TXBC register */ +#define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ +#define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assigment of value for TFQM in the CAN_TXBC register */ +#define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ + + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ +#define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ + +#define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ +#define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assigment of value for TFFL in the CAN_TXFQS register */ +#define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ +#define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assigment of value for TFGI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assigment of value for TFQPI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ +#define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assigment of value for TFQF in the CAN_TXFQS register */ +#define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ + + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ + +#define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ +#define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assigment of value for TBDS in the CAN_TXESC register */ +#define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ +#define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ + + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ +#define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ + +#define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ +#define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ +#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assigment of value for TRP0 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ +#define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ +#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assigment of value for TRP1 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ +#define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ +#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assigment of value for TRP2 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ +#define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ +#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assigment of value for TRP3 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ +#define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ +#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assigment of value for TRP4 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ +#define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ +#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assigment of value for TRP5 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ +#define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ +#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assigment of value for TRP6 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ +#define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ +#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assigment of value for TRP7 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ +#define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ +#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assigment of value for TRP8 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ +#define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ +#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assigment of value for TRP9 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ +#define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ +#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assigment of value for TRP10 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ +#define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ +#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assigment of value for TRP11 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ +#define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ +#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assigment of value for TRP12 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ +#define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ +#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assigment of value for TRP13 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ +#define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ +#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assigment of value for TRP14 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ +#define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ +#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assigment of value for TRP15 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ +#define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ +#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assigment of value for TRP16 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ +#define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ +#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assigment of value for TRP17 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ +#define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ +#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assigment of value for TRP18 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ +#define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ +#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assigment of value for TRP19 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ +#define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ +#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assigment of value for TRP20 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ +#define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ +#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assigment of value for TRP21 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ +#define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ +#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assigment of value for TRP22 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ +#define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ +#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assigment of value for TRP23 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ +#define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ +#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assigment of value for TRP24 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ +#define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ +#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assigment of value for TRP25 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ +#define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ +#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assigment of value for TRP26 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ +#define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ +#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assigment of value for TRP27 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ +#define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ +#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assigment of value for TRP28 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ +#define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ +#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assigment of value for TRP29 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ +#define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ +#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assigment of value for TRP30 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ +#define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ +#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assigment of value for TRP31 in the CAN_TXBRP register */ +#define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ + +#define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ +#define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ +#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ + +#define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ +#define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ +#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assigment of value for AR0 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ +#define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ +#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assigment of value for AR1 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ +#define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ +#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assigment of value for AR2 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ +#define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ +#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assigment of value for AR3 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ +#define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ +#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assigment of value for AR4 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ +#define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ +#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assigment of value for AR5 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ +#define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ +#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assigment of value for AR6 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ +#define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ +#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assigment of value for AR7 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ +#define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ +#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assigment of value for AR8 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ +#define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ +#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assigment of value for AR9 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ +#define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ +#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assigment of value for AR10 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ +#define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ +#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assigment of value for AR11 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ +#define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ +#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assigment of value for AR12 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ +#define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ +#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assigment of value for AR13 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ +#define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ +#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assigment of value for AR14 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ +#define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ +#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assigment of value for AR15 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ +#define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ +#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assigment of value for AR16 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ +#define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ +#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assigment of value for AR17 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ +#define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ +#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assigment of value for AR18 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ +#define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ +#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assigment of value for AR19 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ +#define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ +#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assigment of value for AR20 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ +#define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ +#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assigment of value for AR21 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ +#define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ +#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assigment of value for AR22 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ +#define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ +#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assigment of value for AR23 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ +#define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ +#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assigment of value for AR24 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ +#define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ +#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assigment of value for AR25 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ +#define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ +#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assigment of value for AR26 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ +#define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ +#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assigment of value for AR27 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ +#define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ +#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assigment of value for AR28 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ +#define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ +#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assigment of value for AR29 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ +#define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ +#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assigment of value for AR30 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ +#define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ +#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assigment of value for AR31 in the CAN_TXBAR register */ +#define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ + +#define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ +#define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ +#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ + +#define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ +#define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ +#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assigment of value for CR0 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ +#define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ +#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assigment of value for CR1 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ +#define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ +#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assigment of value for CR2 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ +#define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ +#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assigment of value for CR3 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ +#define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ +#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assigment of value for CR4 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ +#define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ +#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assigment of value for CR5 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ +#define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ +#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assigment of value for CR6 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ +#define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ +#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assigment of value for CR7 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ +#define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ +#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assigment of value for CR8 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ +#define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ +#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assigment of value for CR9 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ +#define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ +#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assigment of value for CR10 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ +#define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ +#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assigment of value for CR11 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ +#define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ +#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assigment of value for CR12 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ +#define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ +#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assigment of value for CR13 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ +#define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ +#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assigment of value for CR14 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ +#define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ +#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assigment of value for CR15 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ +#define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ +#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assigment of value for CR16 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ +#define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ +#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assigment of value for CR17 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ +#define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ +#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assigment of value for CR18 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ +#define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ +#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assigment of value for CR19 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ +#define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ +#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assigment of value for CR20 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ +#define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ +#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assigment of value for CR21 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ +#define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ +#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assigment of value for CR22 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ +#define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ +#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assigment of value for CR23 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ +#define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ +#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assigment of value for CR24 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ +#define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ +#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assigment of value for CR25 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ +#define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ +#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assigment of value for CR26 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ +#define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ +#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assigment of value for CR27 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ +#define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ +#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assigment of value for CR28 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ +#define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ +#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assigment of value for CR29 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ +#define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ +#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assigment of value for CR30 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ +#define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ +#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assigment of value for CR31 in the CAN_TXBCR register */ +#define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ + +#define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ +#define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ +#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ +#define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ + +#define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ +#define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ +#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assigment of value for TO0 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ +#define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ +#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assigment of value for TO1 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ +#define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ +#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assigment of value for TO2 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ +#define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ +#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assigment of value for TO3 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ +#define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ +#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assigment of value for TO4 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ +#define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ +#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assigment of value for TO5 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ +#define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ +#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assigment of value for TO6 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ +#define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ +#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assigment of value for TO7 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ +#define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ +#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assigment of value for TO8 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ +#define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ +#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assigment of value for TO9 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ +#define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ +#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assigment of value for TO10 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ +#define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ +#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assigment of value for TO11 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ +#define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ +#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assigment of value for TO12 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ +#define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ +#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assigment of value for TO13 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ +#define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ +#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assigment of value for TO14 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ +#define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ +#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assigment of value for TO15 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ +#define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ +#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assigment of value for TO16 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ +#define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ +#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assigment of value for TO17 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ +#define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ +#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assigment of value for TO18 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ +#define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ +#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assigment of value for TO19 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ +#define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ +#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assigment of value for TO20 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ +#define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ +#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assigment of value for TO21 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ +#define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ +#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assigment of value for TO22 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ +#define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ +#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assigment of value for TO23 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ +#define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ +#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assigment of value for TO24 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ +#define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ +#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assigment of value for TO25 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ +#define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ +#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assigment of value for TO26 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ +#define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ +#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assigment of value for TO27 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ +#define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ +#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assigment of value for TO28 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ +#define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ +#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assigment of value for TO29 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ +#define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ +#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assigment of value for TO30 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ +#define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ +#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assigment of value for TO31 in the CAN_TXBTO register */ +#define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ + +#define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ +#define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ +#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ +#define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ + +#define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ +#define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ +#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assigment of value for CF0 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ +#define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ +#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assigment of value for CF1 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ +#define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ +#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assigment of value for CF2 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ +#define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ +#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assigment of value for CF3 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ +#define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ +#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assigment of value for CF4 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ +#define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ +#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assigment of value for CF5 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ +#define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ +#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assigment of value for CF6 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ +#define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ +#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assigment of value for CF7 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ +#define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ +#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assigment of value for CF8 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ +#define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ +#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assigment of value for CF9 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ +#define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ +#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assigment of value for CF10 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ +#define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ +#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assigment of value for CF11 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ +#define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ +#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assigment of value for CF12 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ +#define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ +#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assigment of value for CF13 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ +#define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ +#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assigment of value for CF14 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ +#define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ +#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assigment of value for CF15 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ +#define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ +#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assigment of value for CF16 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ +#define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ +#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assigment of value for CF17 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ +#define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ +#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assigment of value for CF18 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ +#define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ +#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assigment of value for CF19 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ +#define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ +#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assigment of value for CF20 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ +#define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ +#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assigment of value for CF21 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ +#define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ +#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assigment of value for CF22 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ +#define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ +#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assigment of value for CF23 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ +#define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ +#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assigment of value for CF24 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ +#define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ +#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assigment of value for CF25 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ +#define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ +#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assigment of value for CF26 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ +#define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ +#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assigment of value for CF27 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ +#define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ +#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assigment of value for CF28 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ +#define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ +#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assigment of value for CF29 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ +#define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ +#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assigment of value for CF30 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ +#define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ +#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assigment of value for CF31 in the CAN_TXBCF register */ +#define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ + +#define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ +#define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ +#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ + +#define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ +#define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ +#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assigment of value for TIE0 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ +#define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ +#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assigment of value for TIE1 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ +#define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ +#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assigment of value for TIE2 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ +#define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ +#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assigment of value for TIE3 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ +#define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ +#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assigment of value for TIE4 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ +#define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ +#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assigment of value for TIE5 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ +#define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ +#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assigment of value for TIE6 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ +#define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ +#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assigment of value for TIE7 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ +#define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ +#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assigment of value for TIE8 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ +#define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ +#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assigment of value for TIE9 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ +#define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ +#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assigment of value for TIE10 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ +#define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ +#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assigment of value for TIE11 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ +#define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ +#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assigment of value for TIE12 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ +#define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ +#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assigment of value for TIE13 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ +#define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ +#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assigment of value for TIE14 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ +#define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ +#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assigment of value for TIE15 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ +#define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ +#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assigment of value for TIE16 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ +#define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ +#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assigment of value for TIE17 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ +#define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ +#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assigment of value for TIE18 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ +#define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ +#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assigment of value for TIE19 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ +#define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ +#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assigment of value for TIE20 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ +#define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ +#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assigment of value for TIE21 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ +#define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ +#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assigment of value for TIE22 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ +#define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ +#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assigment of value for TIE23 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ +#define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ +#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assigment of value for TIE24 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ +#define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ +#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assigment of value for TIE25 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ +#define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ +#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assigment of value for TIE26 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ +#define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ +#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assigment of value for TIE27 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ +#define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ +#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assigment of value for TIE28 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ +#define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ +#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assigment of value for TIE29 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ +#define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ +#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assigment of value for TIE30 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ +#define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ +#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assigment of value for TIE31 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ + +#define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ +#define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ +#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ + +#define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ +#define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ +#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assigment of value for CFIE0 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ +#define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ +#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assigment of value for CFIE1 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ +#define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ +#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assigment of value for CFIE2 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ +#define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ +#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assigment of value for CFIE3 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ +#define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ +#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assigment of value for CFIE4 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ +#define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ +#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assigment of value for CFIE5 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ +#define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ +#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assigment of value for CFIE6 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ +#define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ +#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assigment of value for CFIE7 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ +#define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ +#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assigment of value for CFIE8 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ +#define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ +#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assigment of value for CFIE9 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ +#define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ +#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assigment of value for CFIE10 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ +#define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ +#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assigment of value for CFIE11 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ +#define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ +#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assigment of value for CFIE12 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ +#define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ +#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assigment of value for CFIE13 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ +#define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ +#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assigment of value for CFIE14 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ +#define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ +#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assigment of value for CFIE15 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ +#define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ +#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assigment of value for CFIE16 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ +#define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ +#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assigment of value for CFIE17 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ +#define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ +#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assigment of value for CFIE18 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ +#define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ +#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assigment of value for CFIE19 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ +#define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ +#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assigment of value for CFIE20 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ +#define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ +#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assigment of value for CFIE21 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ +#define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ +#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assigment of value for CFIE22 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ +#define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ +#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assigment of value for CFIE23 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ +#define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ +#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assigment of value for CFIE24 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ +#define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ +#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assigment of value for CFIE25 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ +#define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ +#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assigment of value for CFIE26 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ +#define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ +#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assigment of value for CFIE27 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ +#define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ +#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assigment of value for CFIE28 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ +#define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ +#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assigment of value for CFIE29 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ +#define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ +#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assigment of value for CFIE30 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ +#define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ +#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assigment of value for CFIE31 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ + +#define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ +#define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ +#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ + +#define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ +#define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assigment of value for EFSA in the CAN_TXEFC register */ +#define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ +#define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assigment of value for EFS in the CAN_TXEFC register */ +#define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ +#define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assigment of value for EFWM in the CAN_TXEFC register */ +#define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ + + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ +#define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ + +#define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ +#define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assigment of value for EFFL in the CAN_TXEFS register */ +#define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ +#define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assigment of value for EFGI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ +#define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assigment of value for EFPI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ +#define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ +#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assigment of value for EFF in the CAN_TXEFS register */ +#define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_TXEFS register */ +#define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ + + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ + +#define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assigment of value for EFAI in the CAN_TXEFA register */ +#define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ + + +/** \brief CAN register offsets definitions */ +#define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ +#define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ +#define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ +#define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ +#define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ +#define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ +#define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ +#define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ +#define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ +#define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ +#define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ +#define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ +#define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ +#define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ +#define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ +#define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ +#define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ +#define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ +#define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ +#define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ +#define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ +#define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ +#define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ +#define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ +#define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ +#define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ +#define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ +#define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ +#define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ +#define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ +#define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ +#define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ +#define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ +#define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ +#define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ +#define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ +#define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ +#define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ +#define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ +#define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ +#define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ +#define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ +#define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ +#define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ +#define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ +#define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ +#define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t CAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t CAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t CAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} can_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t CAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t CAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t CAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} can_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t CAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t CAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t CAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} can_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t CAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t CAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t CAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} can_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t CAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t CAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} can_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t CAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} can_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t CAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t CAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} can_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN register API structure */ +typedef struct +{ /* Control Area Network */ + __I uint32_t CAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release */ + __I uint32_t CAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian */ + __IO uint32_t CAN_MRCFG; /**< Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO uint32_t CAN_DBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO uint32_t CAN_TEST; /**< Offset: 0x10 (R/W 32) Test */ + __IO uint32_t CAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO uint32_t CAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control */ + __IO uint32_t CAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO uint32_t CAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I uint32_t CAN_TSCV; /**< Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO uint32_t CAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO uint32_t CAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value */ + __I uint8_t Reserved1[0x10]; + __I uint32_t CAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter */ + __I uint32_t CAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status */ + __IO uint32_t CAN_TDCR; /**< Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t CAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt */ + __IO uint32_t CAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO uint32_t CAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO uint32_t CAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t CAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO uint32_t CAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO uint32_t CAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t CAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I uint32_t CAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO uint32_t CAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 */ + __IO uint32_t CAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 */ + __IO uint32_t CAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I uint32_t CAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO uint32_t CAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO uint32_t CAN_RXBC; /**< Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO uint32_t CAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I uint32_t CAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO uint32_t CAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO uint32_t CAN_RXESC; /**< Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t CAN_TXBC; /**< Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I uint32_t CAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO uint32_t CAN_TXESC; /**< Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I uint32_t CAN_TXBRP; /**< Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO uint32_t CAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO uint32_t CAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I uint32_t CAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I uint32_t CAN_TXBCF; /**< Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO uint32_t CAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t CAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t CAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I uint32_t CAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO uint32_t CAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} can_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_CAN_COMPONENT_H_ */ diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ccl.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ccl.h new file mode 100644 index 00000000..74bf2c33 --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/ccl.h @@ -0,0 +1,217 @@ +/* + * Component description for CCL + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_CCL_COMPONENT_H_ +#define _SAMC21_CCL_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CCL_CTRL register */ +#define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_CTRL register */ +#define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the CCL_CTRL register */ +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assigment of value for SEQSEL in the CCL_SEQCTRL register */ +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assigment of value for FILTSEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assigment of value for EDGESEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assigment of value for INSEL0 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assigment of value for INSEL1 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assigment of value for INSEL2 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assigment of value for LUTEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assigment of value for LUTEO in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assigment of value for TRUTH in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ + + +/** \brief CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ +#define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ +#define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ +#define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ +#define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ +#define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_CCL_COMPONENT_H_ */ diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dac.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dac.h new file mode 100644 index 00000000..49599db0 --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dac.h @@ -0,0 +1,216 @@ +/* + * Component description for DAC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_DAC_COMPONENT_H_ +#define _SAMC21_DAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_CTRLA register */ +#define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable Position */ +#define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_CTRLA register */ +#define DAC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (DAC_CTRLA) Run in Standby Position */ +#define DAC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) /* (DAC_CTRLA) Run in Standby Mask */ +#define DAC_CTRLA_RUNSTDBY(value) (DAC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << DAC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the DAC_CTRLA register */ +#define DAC_CTRLA_Msk _UINT8_(0x43) /* (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_EOEN_Pos _UINT8_(0) /* (DAC_CTRLB) External Output Enable Position */ +#define DAC_CTRLB_EOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_EOEN_Pos) /* (DAC_CTRLB) External Output Enable Mask */ +#define DAC_CTRLB_EOEN(value) (DAC_CTRLB_EOEN_Msk & (_UINT8_(value) << DAC_CTRLB_EOEN_Pos)) /* Assigment of value for EOEN in the DAC_CTRLB register */ +#define DAC_CTRLB_IOEN_Pos _UINT8_(1) /* (DAC_CTRLB) Internal Output Enable Position */ +#define DAC_CTRLB_IOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_IOEN_Pos) /* (DAC_CTRLB) Internal Output Enable Mask */ +#define DAC_CTRLB_IOEN(value) (DAC_CTRLB_IOEN_Msk & (_UINT8_(value) << DAC_CTRLB_IOEN_Pos)) /* Assigment of value for IOEN in the DAC_CTRLB register */ +#define DAC_CTRLB_LEFTADJ_Pos _UINT8_(2) /* (DAC_CTRLB) Left Adjusted Data Position */ +#define DAC_CTRLB_LEFTADJ_Msk (_UINT8_(0x1) << DAC_CTRLB_LEFTADJ_Pos) /* (DAC_CTRLB) Left Adjusted Data Mask */ +#define DAC_CTRLB_LEFTADJ(value) (DAC_CTRLB_LEFTADJ_Msk & (_UINT8_(value) << DAC_CTRLB_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the DAC_CTRLB register */ +#define DAC_CTRLB_VPD_Pos _UINT8_(3) /* (DAC_CTRLB) Voltage Pump Disable Position */ +#define DAC_CTRLB_VPD_Msk (_UINT8_(0x1) << DAC_CTRLB_VPD_Pos) /* (DAC_CTRLB) Voltage Pump Disable Mask */ +#define DAC_CTRLB_VPD(value) (DAC_CTRLB_VPD_Msk & (_UINT8_(value) << DAC_CTRLB_VPD_Pos)) /* Assigment of value for VPD in the DAC_CTRLB register */ +#define DAC_CTRLB_DITHER_Pos _UINT8_(5) /* (DAC_CTRLB) Dither Enable Position */ +#define DAC_CTRLB_DITHER_Msk (_UINT8_(0x1) << DAC_CTRLB_DITHER_Pos) /* (DAC_CTRLB) Dither Enable Mask */ +#define DAC_CTRLB_DITHER(value) (DAC_CTRLB_DITHER_Msk & (_UINT8_(value) << DAC_CTRLB_DITHER_Pos)) /* Assigment of value for DITHER in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_Pos _UINT8_(6) /* (DAC_CTRLB) Reference Selection Position */ +#define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assigment of value for REFSEL in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_INT1V_Val _UINT8_(0x0) /* (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _UINT8_(0x1) /* (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal 1.0V reference Position */ +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) AVCC Position */ +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference Position */ +#define DAC_CTRLB_Msk _UINT8_(0xEF) /* (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input Position */ +#define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL) Start Conversion Event Input Mask */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) /* Assigment of value for STARTEI in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(1) /* (DAC_EVCTRL) Data Buffer Empty Event Output Position */ +#define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output Mask */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) /* Assigment of value for EMPTYEO in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI_Pos _UINT8_(2) /* (DAC_EVCTRL) Invert Event Input Position */ +#define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL) Invert Event Input Mask */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the DAC_EVCTRL register */ +#define DAC_EVCTRL_Msk _UINT8_(0x07) /* (DAC_EVCTRL) Register Mask */ + + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR) Underrun Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) /* Assigment of value for UNDERRUN in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY_Pos _UINT8_(1) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) /* Assigment of value for EMPTY in the DAC_INTENCLR register */ +#define DAC_INTENCLR_Msk _UINT8_(0x03) /* (DAC_INTENCLR) Register Mask */ + + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET) Underrun Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) /* Assigment of value for UNDERRUN in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY_Pos _UINT8_(1) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) /* Assigment of value for EMPTY in the DAC_INTENSET register */ +#define DAC_INTENSET_Msk _UINT8_(0x03) /* (DAC_INTENSET) Register Mask */ + + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG) Underrun Position */ +#define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG) Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) /* Assigment of value for UNDERRUN in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY_Pos _UINT8_(1) /* (DAC_INTFLAG) Data Buffer Empty Position */ +#define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG) Data Buffer Empty Mask */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) /* Assigment of value for EMPTY in the DAC_INTFLAG register */ +#define DAC_INTFLAG_Msk _UINT8_(0x03) /* (DAC_INTFLAG) Register Mask */ + + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS) Ready Position */ +#define DAC_STATUS_READY_Msk (_UINT8_(0x1) << DAC_STATUS_READY_Pos) /* (DAC_STATUS) Ready Mask */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) /* Assigment of value for READY in the DAC_STATUS register */ +#define DAC_STATUS_Msk _UINT8_(0x01) /* (DAC_STATUS) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */ +#define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) Data Reset Value */ + +#define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) Data value to be converted Position */ +#define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) Data value to be converted Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assigment of value for DATA in the DAC_DATA register */ +#define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assigment of value for DATABUF in the DAC_DATABUF register */ +#define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) Enable Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) Enable Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data Position */ +#define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY) Data Mask */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) /* Assigment of value for DATA in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data Buffer Position */ +#define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY) Data Buffer Mask */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) /* Assigment of value for DATABUF in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_Msk _UINT32_(0x0000000F) /* (DAC_SYNCBUSY) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the DAC_DBGCTRL register */ +#define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ + + +/** \brief DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ +#define DAC_DATA_REG_OFST _UINT32_(0x08) /* (DAC_DATA) Data Offset */ +#define DAC_DATABUF_REG_OFST _UINT32_(0x0C) /* (DAC_DATABUF) Data Buffer Offset */ +#define DAC_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DBGCTRL_REG_OFST _UINT32_(0x14) /* (DAC_DBGCTRL) Debug Control Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DAC register API structure */ +typedef struct +{ /* Digital Analog Converter */ + __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ + __O uint16_t DAC_DATA; /**< Offset: 0x08 ( /W 16) Data */ + __I uint8_t Reserved2[0x02]; + __O uint16_t DAC_DATABUF; /**< Offset: 0x0C ( /W 16) Data Buffer */ + __I uint8_t Reserved3[0x02]; + __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Busy */ + __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x14 (R/W 8) Debug Control */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_DAC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/divas.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/divas.h new file mode 100644 index 00000000..84bf6983 --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/divas.h @@ -0,0 +1,126 @@ +/* + * Component description for DIVAS + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_DIVAS_COMPONENT_H_ +#define _SAMC21_DIVAS_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DIVAS */ +/* ************************************************************************** */ + +/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */ +#define DIVAS_CTRLA_RESETVALUE _UINT8_(0x00) /* (DIVAS_CTRLA) Control Reset Value */ + +#define DIVAS_CTRLA_SIGNED_Pos _UINT8_(0) /* (DIVAS_CTRLA) Signed Position */ +#define DIVAS_CTRLA_SIGNED_Msk (_UINT8_(0x1) << DIVAS_CTRLA_SIGNED_Pos) /* (DIVAS_CTRLA) Signed Mask */ +#define DIVAS_CTRLA_SIGNED(value) (DIVAS_CTRLA_SIGNED_Msk & (_UINT8_(value) << DIVAS_CTRLA_SIGNED_Pos)) /* Assigment of value for SIGNED in the DIVAS_CTRLA register */ +#define DIVAS_CTRLA_DLZ_Pos _UINT8_(1) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Position */ +#define DIVAS_CTRLA_DLZ_Msk (_UINT8_(0x1) << DIVAS_CTRLA_DLZ_Pos) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Mask */ +#define DIVAS_CTRLA_DLZ(value) (DIVAS_CTRLA_DLZ_Msk & (_UINT8_(value) << DIVAS_CTRLA_DLZ_Pos)) /* Assigment of value for DLZ in the DIVAS_CTRLA register */ +#define DIVAS_CTRLA_Msk _UINT8_(0x03) /* (DIVAS_CTRLA) Register Mask */ + + +/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */ +#define DIVAS_STATUS_RESETVALUE _UINT8_(0x00) /* (DIVAS_STATUS) Status Reset Value */ + +#define DIVAS_STATUS_BUSY_Pos _UINT8_(0) /* (DIVAS_STATUS) DIVAS Accelerator Busy Position */ +#define DIVAS_STATUS_BUSY_Msk (_UINT8_(0x1) << DIVAS_STATUS_BUSY_Pos) /* (DIVAS_STATUS) DIVAS Accelerator Busy Mask */ +#define DIVAS_STATUS_BUSY(value) (DIVAS_STATUS_BUSY_Msk & (_UINT8_(value) << DIVAS_STATUS_BUSY_Pos)) /* Assigment of value for BUSY in the DIVAS_STATUS register */ +#define DIVAS_STATUS_DBZ_Pos _UINT8_(1) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Position */ +#define DIVAS_STATUS_DBZ_Msk (_UINT8_(0x1) << DIVAS_STATUS_DBZ_Pos) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Mask */ +#define DIVAS_STATUS_DBZ(value) (DIVAS_STATUS_DBZ_Msk & (_UINT8_(value) << DIVAS_STATUS_DBZ_Pos)) /* Assigment of value for DBZ in the DIVAS_STATUS register */ +#define DIVAS_STATUS_Msk _UINT8_(0x03) /* (DIVAS_STATUS) Register Mask */ + + +/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */ +#define DIVAS_DIVIDEND_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVIDEND) Dividend Reset Value */ + +#define DIVAS_DIVIDEND_DIVIDEND_Pos _UINT32_(0) /* (DIVAS_DIVIDEND) DIVIDEND Position */ +#define DIVAS_DIVIDEND_DIVIDEND_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos) /* (DIVAS_DIVIDEND) DIVIDEND Mask */ +#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & (_UINT32_(value) << DIVAS_DIVIDEND_DIVIDEND_Pos)) /* Assigment of value for DIVIDEND in the DIVAS_DIVIDEND register */ +#define DIVAS_DIVIDEND_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVIDEND) Register Mask */ + + +/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */ +#define DIVAS_DIVISOR_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVISOR) Divisor Reset Value */ + +#define DIVAS_DIVISOR_DIVISOR_Pos _UINT32_(0) /* (DIVAS_DIVISOR) DIVISOR Position */ +#define DIVAS_DIVISOR_DIVISOR_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos) /* (DIVAS_DIVISOR) DIVISOR Mask */ +#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & (_UINT32_(value) << DIVAS_DIVISOR_DIVISOR_Pos)) /* Assigment of value for DIVISOR in the DIVAS_DIVISOR register */ +#define DIVAS_DIVISOR_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVISOR) Register Mask */ + + +/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) ( R/ 32) Result -------- */ +#define DIVAS_RESULT_RESETVALUE _UINT32_(0x00) /* (DIVAS_RESULT) Result Reset Value */ + +#define DIVAS_RESULT_RESULT_Pos _UINT32_(0) /* (DIVAS_RESULT) RESULT Position */ +#define DIVAS_RESULT_RESULT_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos) /* (DIVAS_RESULT) RESULT Mask */ +#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & (_UINT32_(value) << DIVAS_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the DIVAS_RESULT register */ +#define DIVAS_RESULT_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_RESULT) Register Mask */ + + +/* -------- DIVAS_REM : (DIVAS Offset: 0x14) ( R/ 32) Remainder -------- */ +#define DIVAS_REM_RESETVALUE _UINT32_(0x00) /* (DIVAS_REM) Remainder Reset Value */ + +#define DIVAS_REM_REM_Pos _UINT32_(0) /* (DIVAS_REM) REM Position */ +#define DIVAS_REM_REM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_REM_REM_Pos) /* (DIVAS_REM) REM Mask */ +#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & (_UINT32_(value) << DIVAS_REM_REM_Pos)) /* Assigment of value for REM in the DIVAS_REM register */ +#define DIVAS_REM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_REM) Register Mask */ + + +/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */ +#define DIVAS_SQRNUM_RESETVALUE _UINT32_(0x00) /* (DIVAS_SQRNUM) Square Root Input Reset Value */ + +#define DIVAS_SQRNUM_SQRNUM_Pos _UINT32_(0) /* (DIVAS_SQRNUM) Square Root Input Position */ +#define DIVAS_SQRNUM_SQRNUM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos) /* (DIVAS_SQRNUM) Square Root Input Mask */ +#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & (_UINT32_(value) << DIVAS_SQRNUM_SQRNUM_Pos)) /* Assigment of value for SQRNUM in the DIVAS_SQRNUM register */ +#define DIVAS_SQRNUM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_SQRNUM) Register Mask */ + + +/** \brief DIVAS register offsets definitions */ +#define DIVAS_CTRLA_REG_OFST _UINT32_(0x00) /* (DIVAS_CTRLA) Control Offset */ +#define DIVAS_STATUS_REG_OFST _UINT32_(0x04) /* (DIVAS_STATUS) Status Offset */ +#define DIVAS_DIVIDEND_REG_OFST _UINT32_(0x08) /* (DIVAS_DIVIDEND) Dividend Offset */ +#define DIVAS_DIVISOR_REG_OFST _UINT32_(0x0C) /* (DIVAS_DIVISOR) Divisor Offset */ +#define DIVAS_RESULT_REG_OFST _UINT32_(0x10) /* (DIVAS_RESULT) Result Offset */ +#define DIVAS_REM_REG_OFST _UINT32_(0x14) /* (DIVAS_REM) Remainder Offset */ +#define DIVAS_SQRNUM_REG_OFST _UINT32_(0x18) /* (DIVAS_SQRNUM) Square Root Input Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DIVAS register API structure */ +typedef struct +{ /* Divide and Square Root Accelerator */ + __IO uint8_t DIVAS_CTRLA; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t DIVAS_STATUS; /**< Offset: 0x04 (R/W 8) Status */ + __I uint8_t Reserved2[0x03]; + __IO uint32_t DIVAS_DIVIDEND; /**< Offset: 0x08 (R/W 32) Dividend */ + __IO uint32_t DIVAS_DIVISOR; /**< Offset: 0x0C (R/W 32) Divisor */ + __I uint32_t DIVAS_RESULT; /**< Offset: 0x10 (R/ 32) Result */ + __I uint32_t DIVAS_REM; /**< Offset: 0x14 (R/ 32) Remainder */ + __IO uint32_t DIVAS_SQRNUM; /**< Offset: 0x18 (R/W 32) Square Root Input */ +} divas_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_DIVAS_COMPONENT_H_ */ diff --git a/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dmac.h b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dmac.h new file mode 100644 index 00000000..924dc654 --- /dev/null +++ b/bms/bms/bms_config/src/packs/ATSAMC21J18A_DFP/component/dmac.h @@ -0,0 +1,882 @@ +/* + * Component description for DMAC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_DMAC_COMPONENT_H_ +#define _SAMC21_DMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _UINT16_(0x00) /* (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _UINT16_(0) /* (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos) /* (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assigment of value for VALID in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_Pos _UINT16_(1) /* (DMAC_BTCTRL) Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assigment of value for EVOSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when block transfer complete Position */ +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when beat transfer complete Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _UINT16_(3) /* (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assigment of value for BLOCKACT in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _UINT16_(0x2) /* (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _UINT16_(8) /* (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assigment of value for BEATSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _UINT16_(0x1) /* (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _UINT16_(0x2) /* (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _UINT16_(10) /* (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /* (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assigment of value for SRCINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_DSTINC_Pos _UINT16_(11) /* (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assigment of value for DSTINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_Pos _UINT16_(12) /* (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assigment of value for STEPSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_DST_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _UINT16_(13) /* (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assigment of value for STEPSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSIZE_X1_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M0PLUS Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAMC21J18A specific Interrupt Numbers ***********************************/ + MCLK_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (MCLK) */ + OSCCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSC32KCTRL) */ + PAC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (PAC) */ + SUPC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (SUPC) */ + WDT_IRQn = 1, /* 1 Watchdog Timer (WDT) */ + RTC_IRQn = 2, /* 2 Real-Time Counter (RTC) */ + EIC_IRQn = 3, /* 3 External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /* 4 Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /* 5 Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /* 6 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /* 7 Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /* 8 Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /* 9 Serial Communication Interface (SERCOM0) */ + SERCOM1_IRQn = 10, /* 10 Serial Communication Interface (SERCOM1) */ + SERCOM2_IRQn = 11, /* 11 Serial Communication Interface (SERCOM2) */ + SERCOM3_IRQn = 12, /* 12 Serial Communication Interface (SERCOM3) */ + SERCOM4_IRQn = 13, /* 13 Serial Communication Interface (SERCOM4) */ + SERCOM5_IRQn = 14, /* 14 Serial Communication Interface (SERCOM5) */ + CAN0_IRQn = 15, /* 15 Control Area Network (CAN0) */ + CAN1_IRQn = 16, /* 16 Control Area Network (CAN1) */ + TCC0_IRQn = 17, /* 17 Timer Counter Control (TCC0) */ + TCC1_IRQn = 18, /* 18 Timer Counter Control (TCC1) */ + TCC2_IRQn = 19, /* 19 Timer Counter Control (TCC2) */ + TC0_IRQn = 20, /* 20 Basic Timer Counter (TC0) */ + TC1_IRQn = 21, /* 21 Basic Timer Counter (TC1) */ + TC2_IRQn = 22, /* 22 Basic Timer Counter (TC2) */ + TC3_IRQn = 23, /* 23 Basic Timer Counter (TC3) */ + TC4_IRQn = 24, /* 24 Basic Timer Counter (TC4) */ + ADC0_IRQn = 25, /* 25 Analog Digital Converter (ADC0) */ + ADC1_IRQn = 26, /* 26 Analog Digital Converter (ADC1) */ + AC_IRQn = 27, /* 27 Analog Comparators (AC) */ + DAC_IRQn = 28, /* 28 Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /* 30 Peripheral Touch Controller (PTC) */ + + PERIPH_MAX_IRQn = 30 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M0PLUS handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pvReservedC12; + void* pvReservedC11; + void* pvReservedC10; + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pvReservedC4; + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt (MCLK OSCCTRL OSC32KCTRL PAC SUPC) */ + void* pfnWDT_Handler; /* 1 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 2 Real-Time Counter (RTC) */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 4 Frequency Meter (FREQM) */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor (TSENS) */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_Handler; /* 8 Event System Interface (EVSYS) */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface (SERCOM5) */ + void* pfnCAN0_Handler; /* 15 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 16 Control Area Network (CAN1) */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control (TCC0) */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control (TCC1) */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control (TCC2) */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter (TC4) */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter (ADC0) */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 27 Analog Comparators (AC) */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter (DAC) */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller (PTC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M0PLUS exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M0PLUS Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001 /* Cortex-M0+ Core Revision */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm0plus.h" +#if defined USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J18A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/ptc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /* Power Manager (PM) */ +#define ID_MCLK ( 2) /* Main Clock (MCLK) */ +#define ID_RSTC ( 3) /* Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /* Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /* Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /* Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /* Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /* External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /* Frequency Meter (FREQM) */ +#define ID_TSENS ( 12) /* Temperature Sensor (TSENS) */ +#define ID_PORT ( 32) /* Port Module (PORT) */ +#define ID_DSU ( 33) /* Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /* Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC ( 35) /* Direct Memory Access Controller (DMAC) */ +#define ID_MTB ( 36) /* Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS ( 37) /* HSB Matrix (HMATRIXHS) */ +#define ID_EVSYS ( 64) /* Event System Interface (EVSYS) */ +#define ID_SERCOM0 ( 65) /* Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 66) /* Serial Communication Interface (SERCOM1) */ +#define ID_SERCOM2 ( 67) /* Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 68) /* Serial Communication Interface (SERCOM3) */ +#define ID_SERCOM4 ( 69) /* Serial Communication Interface (SERCOM4) */ +#define ID_SERCOM5 ( 70) /* Serial Communication Interface (SERCOM5) */ +#define ID_CAN0 ( 71) /* Control Area Network (CAN0) */ +#define ID_CAN1 ( 72) /* Control Area Network (CAN1) */ +#define ID_TCC0 ( 73) /* Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 74) /* Timer Counter Control (TCC1) */ +#define ID_TCC2 ( 75) /* Timer Counter Control (TCC2) */ +#define ID_TC0 ( 76) /* Basic Timer Counter (TC0) */ +#define ID_TC1 ( 77) /* Basic Timer Counter (TC1) */ +#define ID_TC2 ( 78) /* Basic Timer Counter (TC2) */ +#define ID_TC3 ( 79) /* Basic Timer Counter (TC3) */ +#define ID_TC4 ( 80) /* Basic Timer Counter (TC4) */ +#define ID_ADC0 ( 81) /* Analog Digital Converter (ADC0) */ +#define ID_ADC1 ( 82) /* Analog Digital Converter (ADC1) */ +#define ID_SDADC ( 83) /* Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC ( 84) /* Analog Comparators (AC) */ +#define ID_DAC ( 85) /* Digital Analog Converter (DAC) */ +#define ID_PTC ( 86) /* Peripheral Touch Controller (PTC) */ +#define ID_CCL ( 87) /* Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_MAX ( 87) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42005000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x42004400) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x42004800) /* ADC1 Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42001c00) /* CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42002000) /* CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42005c00) /* CCL Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x42005400) /* DAC Registers Address */ +#define DIVAS_REGS ((divas_registers_t*)0x48000000) /* DIVAS Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x41006000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x42000000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define HMATRIXHS_REGS ((hmatrixb_registers_t*)0x4100a000) /* HMATRIXHS Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define MTB_REGS ((mtb_registers_t*)0x41008000) /* MTB Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define OTP5_FUSES_REGS ((fuses_otp5_fuses_registers_t*)0x00806020) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00806030) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41000000) /* PORT Registers Address */ +#define PORT_IOBUS_REGS ((port_registers_t*)0x60000000) /* PORT Registers Address */ +#define PTC_REGS ((ptc_registers_t*)0x42005800) /* PTC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDADC_REGS ((sdadc_registers_t*)0x42004c00) /* SDADC Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x42000400) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x42000800) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x42000c00) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x42001000) /* SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x42001400) /* SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x42001800) /* SERCOM5 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x42003000) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x42003400) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x42003800) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x42003c00) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42004000) /* TC4 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x42002400) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x42002800) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42002c00) /* TCC2 Registers Address */ +#define TSENS_REGS ((tsens_registers_t*)0x40003000) /* TSENS Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42005000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x42004400) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x42004800) /* ADC1 Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42001c00) /* CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UINT32_(0x42002000) /* CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42005c00) /* CCL Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x42005400) /* DAC Base Address */ +#define DIVAS_BASE_ADDRESS _UINT32_(0x48000000) /* DIVAS Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x41006000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x42000000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define HMATRIXHS_BASE_ADDRESS _UINT32_(0x4100a000) /* HMATRIXHS Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define MTB_BASE_ADDRESS _UINT32_(0x41008000) /* MTB Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define OTP5_FUSES_BASE_ADDRESS _UINT32_(0x00806020) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00806030) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41000000) /* PORT Base Address */ +#define PORT_IOBUS_BASE_ADDRESS _UINT32_(0x60000000) /* PORT Base Address */ +#define PTC_BASE_ADDRESS _UINT32_(0x42005800) /* PTC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDADC_BASE_ADDRESS _UINT32_(0x42004c00) /* SDADC Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x42000400) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x42000800) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x42000c00) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x42001000) /* SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UINT32_(0x42001400) /* SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UINT32_(0x42001800) /* SERCOM5 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x42003000) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x42003400) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x42003800) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x42003c00) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42004000) /* TC4 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x42002400) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x42002800) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42002c00) /* TCC2 Base Address */ +#define TSENS_BASE_ADDRESS _UINT32_(0x40003000) /* TSENS Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#include "pio/samc21j18a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 64) +#define FLASH_NB_OF_PAGES _UINT32_( 4096) + +#define OTP5_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ +#define USER_PAGE_SIZE _UINT32_(0x00000100) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 64) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 4) + +#define RWW_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: flash */ +#define RWW_PAGE_SIZE _UINT32_( 64) +#define RWW_NB_OF_PAGES _UINT32_( 128) + +#define HSRAM_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004000) /* 16kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00010000) /* 64kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: io */ +#define DIVAS_SIZE _UINT32_(0x00000020) /* 0kB Memory segment type: io */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define PERIPHERALS_SIZE _UINT32_(0x20000000) /* 524288kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define OTP5_ADDR _UINT32_(0x00806020) /* OTP5 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00806030) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define RWW_ADDR _UINT32_(0x00400000) /* RWW base address (type: flash)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define DIVAS_ADDR _UINT32_(0x48000000) /* DIVAS base address (type: io)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ +#define PERIPHERALS_ADDR _UINT32_(0x40000000) /* PERIPHERALS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAMC21J18A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X11010500) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAMC21J18A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL 1 /* ID for OSCCTRL event generator XOSC_FAIL */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_CMP_0 3 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 4 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_OVF 5 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_RTC_PER_0 6 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 7 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 8 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 9 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 10 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 11 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 12 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 13 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_0 14 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 15 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 16 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 17 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 18 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 19 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 20 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 21 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 22 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 23 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 24 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 25 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 26 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 27 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 28 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 29 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_TSENS_WINMON 30 /* ID for TSENS event generator WINMON */ +#define EVENT_ID_GEN_DMAC_CH_0 31 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 32 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 33 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 34 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_TCC0_OVF 35 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 36 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 37 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 38 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 39 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 40 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 41 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC1_OVF 42 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 43 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 44 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 45 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 46 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_OVF 47 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 48 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 49 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 50 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 51 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 52 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 53 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 54 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 55 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 56 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 57 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 58 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 59 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 60 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 61 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 62 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 63 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 64 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 65 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 66 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 67 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 68 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 69 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 70 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_SDADC_RESRDY 71 /* ID for SDADC event generator RESRDY */ +#define EVENT_ID_GEN_SDADC_WINMON 72 /* ID for SDADC event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 73 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 74 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_COMP_2 75 /* ID for AC event generator COMP_2 */ +#define EVENT_ID_GEN_AC_COMP_3 76 /* ID for AC event generator COMP_3 */ +#define EVENT_ID_GEN_AC_WIN_0 77 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_AC_WIN_1 78 /* ID for AC event generator WIN_1 */ +#define EVENT_ID_GEN_DAC_EMPTY 79 /* ID for DAC event generator EMPTY */ +#define EVENT_ID_GEN_PTC_EOC 80 /* ID for PTC event generator EOC */ +#define EVENT_ID_GEN_PTC_WIN_COMP 81 /* ID for PTC event generator WIN_COMP */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 82 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 83 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 84 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 85 /* ID for CCL event generator LUTOUT_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 86 /* ID for PAC event generator ACCERR */ + +/* ************************************************************************** */ +/* Event User IDs for SAMC21J18A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_TSENS_START 0 /* ID for TSENS event user START */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_TCC0_EV_0 9 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 10 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 11 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 12 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 13 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 14 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC1_EV_0 15 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 16 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 17 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 18 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC2_EV_0 19 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 20 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 21 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 22 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 23 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 24 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 25 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 26 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 27 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_ADC0_START 28 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 29 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 30 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 31 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_SDADC_START 32 /* ID for SDADC event user START */ +#define EVENT_ID_USER_SDADC_FLUSH 33 /* ID for SDADC event user FLUSH */ +#define EVENT_ID_USER_AC_SOC_0 34 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 35 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_AC_SOC_2 36 /* ID for AC event user SOC_2 */ +#define EVENT_ID_USER_AC_SOC_3 37 /* ID for AC event user SOC_3 */ +#define EVENT_ID_USER_DAC_START 38 /* ID for DAC event user START */ +#define EVENT_ID_USER_CCL_LUTIN_0 40 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 41 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 42 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 43 /* ID for CCL event user LUTIN_3 */ +#define EVENT_ID_USER_MTB_START 45 /* ID for MTB event user START */ +#define EVENT_ID_USER_MTB_STOP 46 /* ID for MTB event user STOP */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAMC21J18A_H_ */ + diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000..9f4c4d77 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000..a2ad65fb --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000..74bc4a2d --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..6edd5096 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000..21a2c711 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000..045aaf19 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000..407b94ba --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000..6addcbb7 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000..ed961aa4 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000..3b268177 --- /dev/null +++ b/bms/bms/bms_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bms/bms/main.c b/bms/bms/main.c deleted file mode 100644 index 7d073795..00000000 --- a/bms/bms/main.c +++ /dev/null @@ -1,12 +0,0 @@ -/** - * @file main.c - * @author alihs - * @date 2025-10-05 - * @brief Main function - */ -int main(){ - - // Add your code here and press Ctrl + Shift + B to build - - return 0; -} From a7e06ef7cdd5ee66a56b5bcdc888edf7bdbcb925 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Wed, 15 Oct 2025 15:59:42 +0200 Subject: [PATCH 03/30] feat: add safety features including current monitoring and killswitch --- .../bms_config_default/components/can0.yml | 10 + .../bms_config_default/components/can1.yml | 202 ++++++++++++++++++ .../bms_config_default/components/core.yml | 60 +++++- .../bms_config_default/components/stdio.yml | 2 +- .../mcc/bms_config_default/mcc-config.mc4 | 1 + .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- .../config/default/peripheral/adc/plib_adc0.c | 4 +- bms/bms/bms_config/src/main.c | 5 + bms/bms/bms_config/src/safety/current.c | 77 +++++++ bms/bms/bms_config/src/safety/current.h | 16 ++ bms/bms/bms_config/src/safety/killswitch.c | 0 bms/bms/bms_config/src/safety/killswitch.h | 0 bms/bms/bms_config/src/safety/temperature.c | 0 bms/bms/bms_config/src/safety/temperature.h | 0 bms/bms/bms_config/src/safety/voltage.c | 0 bms/bms/bms_config/src/safety/voltage.h | 0 16 files changed, 368 insertions(+), 11 deletions(-) create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/can1.yml create mode 100644 bms/bms/bms_config/src/safety/current.c create mode 100644 bms/bms/bms_config/src/safety/current.h create mode 100644 bms/bms/bms_config/src/safety/killswitch.c create mode 100644 bms/bms/bms_config/src/safety/killswitch.h create mode 100644 bms/bms/bms_config/src/safety/temperature.c create mode 100644 bms/bms/bms_config/src/safety/temperature.h create mode 100644 bms/bms/bms_config/src/safety/voltage.c create mode 100644 bms/bms/bms_config/src/safety/voltage.h diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml index b66d0283..75139367 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml @@ -334,4 +334,14 @@ data: type: User type: Values type: Integer + NOMINAL_BITRATE: + attributes: + id: NOMINAL_BITRATE + children: + - children: + - attributes: + value: '500' + type: User + type: Values + type: Integer userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml new file mode 100644 index 00000000..667f40c0 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml @@ -0,0 +1,202 @@ +configVersion: 1.0.0 +componentName: can1 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: can1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: can1 + x: '196' + y: '146' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + AUTO_DATA_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_DATA_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + CALCULATED_DATA_BITRATE: + attributes: + id: CALCULATED_DATA_BITRATE + children: + - children: + - attributes: + id: can1 + value: '500' + type: Dynamic + type: Values + type: Integer + CALCULATED_DATA_ERRORRATE: + attributes: + id: CALCULATED_DATA_ERRORRATE + children: + - children: + - attributes: + id: can1 + value: '0.000' + type: Dynamic + type: Values + type: String + CAN_OPMODE: + attributes: + id: CAN_OPMODE + children: + - children: + - attributes: + value: CAN FD + type: User + type: Values + type: Combo + DATA_SAMPLE_POINT: + attributes: + id: DATA_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: can1 + value: '96.875' + type: Dynamic + type: Values + type: Float + DATA_TIME_QUANTA_PERIOD: + attributes: + id: DATA_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can1 + value: '62.500' + type: Dynamic + type: Values + type: String + DBTP_DBRP: + attributes: + id: DBTP_DBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: can1 + value: '2' + type: Dynamic + type: Values + type: Integer + DBTP_DSJW: + attributes: + id: DBTP_DSJW + children: + - children: + - attributes: + id: can1 + value: '1' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG1: + attributes: + id: DBTP_DTSEG1 + children: + - children: + - attributes: + id: can1 + value: '30' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG2: + attributes: + id: DBTP_DTSEG2 + children: + - children: + - attributes: + id: can1 + value: '1' + type: Dynamic + type: Values + type: Integer + DBTP_TOTAL_TIME_QUANTA: + attributes: + id: DBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can1 + value: '32' + type: Dynamic + type: Values + type: Integer + INTERRUPT_MODE: + attributes: + id: INTERRUPT_MODE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + instHeaderFile: + attributes: + id: instHeaderFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_interrupt.h.ftl + type: String + type: Attributes + type: File + sourceFile: + attributes: + id: sourceFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_interrupt.c.ftl + type: String + type: Attributes + type: File + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index eefe1ac3..bb1854cc 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -167,7 +167,7 @@ data: - children: - attributes: id: core - value: '0x1dff' + value: '0x1fff' type: Dynamic type: Values type: String @@ -343,7 +343,7 @@ data: - children: - attributes: id: core - value: '0' + value: '48000000' type: Dynamic type: Values type: Integer @@ -354,7 +354,7 @@ data: - children: - attributes: id: core - value: '0' + value: '48000000' type: Dynamic type: Values type: Integer @@ -365,7 +365,7 @@ data: - children: - attributes: id: core - value: 'false' + value: 'true' type: Dynamic type: Values type: Boolean @@ -453,7 +453,7 @@ data: - children: - attributes: id: core - value: 'true' + value: 'false' type: Dynamic type: Values type: Boolean @@ -464,7 +464,7 @@ data: - children: - attributes: id: core - value: 'false' + value: 'true' type: Dynamic type: Values type: Boolean @@ -475,7 +475,7 @@ data: - children: - attributes: id: core - value: CAN1_Handler + value: CAN1_InterruptHandler type: Dynamic type: Values type: String @@ -486,7 +486,7 @@ data: - children: - attributes: id: core - value: 'false' + value: 'true' type: Dynamic type: Values type: Boolean @@ -732,6 +732,50 @@ data: type: Dynamic type: Values type: String + CAN1_CLOCK_ENABLE: + attributes: + id: CAN1_CLOCK_ENABLE + children: + - children: + - attributes: + id: can1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_INTERRUPT_ENABLE: + attributes: + id: CAN1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: can1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_INTERRUPT_HANDLER: + attributes: + id: CAN1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: can1 + value: CAN1_InterruptHandler + type: Dynamic + type: Values + type: String + CAN1_INTERRUPT_HANDLER_LOCK: + attributes: + id: CAN1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: can1 + value: 'true' + type: Dynamic + type: Values + type: Boolean userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml b/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml index fe6cfec9..bf922231 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml @@ -45,7 +45,7 @@ data: - attributes: id: stdio x: '307' - y: '350' + y: '339' type: ElementPosition type: ElementPositions type: ComponentGraph diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index b34a641e..aac4e0a1 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -9,6 +9,7 @@ modules: - adc0 - adc1 - can0 +- can1 - cmsis - core - dfp diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index 8548790a..bd5d7700 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2025-10-09T17:41:06.423+02:00[Europe/Oslo] +creation_date: 2025-10-10T14:27:55.811+02:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c index 1f7f4eb5..5b38d23d 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc0.c @@ -177,7 +177,7 @@ void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) ADC0_REGS->ADC_WINUT = high_threshold; while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) { - /* Wait for Synchronization */ + /* Wait for Synchronization */ } while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) { @@ -226,3 +226,5 @@ bool ADC0_ConversionStatusGet( void ) } return status; } + + diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index fa0edee2..a57b3ad8 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -26,6 +26,10 @@ #include // Defines true #include // Defines EXIT_FAILURE #include "definitions.h" // SYS function prototypes +#include "peripheral/adc/plib_adc0.h" + + + // ***************************************************************************** @@ -45,6 +49,7 @@ int main ( void ) SYS_Tasks ( ); } + /* Execution should not come here during normal operation */ return ( EXIT_FAILURE ); diff --git a/bms/bms/bms_config/src/safety/current.c b/bms/bms/bms_config/src/safety/current.c new file mode 100644 index 00000000..66c50ad8 --- /dev/null +++ b/bms/bms/bms_config/src/safety/current.c @@ -0,0 +1,77 @@ +#include "current.h" +#include "definitions.h" +#include "peripheral/adc/plib_adc0.h" +#include "samc21j18a.h" +#include +#include + + +static int current_flags = 0; +uint16_t adc_read_channel(uint8_t channel) +{ + // 1. Select ADC input (MUXPOS) + ADC0_REGS->ADC_INPUTCTRL = ADC_INPUTCTRL_MUXPOS(channel); + while (ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk); + + // 2. Start conversion + ADC0_REGS->ADC_SWTRIG |= ADC_SWTRIG_START_Msk; + + // 3. Wait for conversion to complete + while ((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) == 0); + + // 4. Read result + uint16_t result = ADC0_REGS->ADC_RESULT; + + // 5. Clear the RESRDY flag (write 1 to clear) + ADC0_REGS->ADC_INTFLAG = ADC_INTFLAG_RESRDY_Msk; + + return result; +} + + + +//static float read_current_amps(void){} + + +void current_init(){ + + ADC0_Initialize(); + ADC0_Enable(); + ADC0_ChannelSelect(ADC_POSINPUT_AIN0, ADC_NEGINPUT_GND); + ADC0_ConversionStart(); + + + +} + + + +void current_check(){ + + if (ADC0_REGS->ADC_RESULT > CURRENT_THRESHOLD_A){ + + + + current_flags++;} + + +} + + + + +void check_raise_flags(void){ + //check if current sense flags are raised + //if raised, take action + if (current_flags>5){ + //raise system fault + + } +} + + + + +//raise flags logic if current is out of range +//fault handling logic +//current limiting logic diff --git a/bms/bms/bms_config/src/safety/current.h b/bms/bms/bms_config/src/safety/current.h new file mode 100644 index 00000000..1942156b --- /dev/null +++ b/bms/bms/bms_config/src/safety/current.h @@ -0,0 +1,16 @@ + +#include "definitions.h" +#include "peripheral/adc/plib_adc0.h" +#include + + +#define CURRENT_THRESHOLD_A 25 +#define SENSOR_SENSITIVITY_V_A 0.04 +#define SENSOR_OFFSET_V 1.65 + + + +void current_init(void); +void current_check(void); +void current_raise_flags(void); + diff --git a/bms/bms/bms_config/src/safety/killswitch.c b/bms/bms/bms_config/src/safety/killswitch.c new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config/src/safety/killswitch.h b/bms/bms/bms_config/src/safety/killswitch.h new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config/src/safety/temperature.c b/bms/bms/bms_config/src/safety/temperature.c new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config/src/safety/temperature.h b/bms/bms/bms_config/src/safety/temperature.h new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config/src/safety/voltage.c b/bms/bms/bms_config/src/safety/voltage.c new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config/src/safety/voltage.h b/bms/bms/bms_config/src/safety/voltage.h new file mode 100644 index 00000000..e69de29b From c0a0af3f8d8851785aa34bee564188a50e57acc7 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Wed, 22 Oct 2025 16:06:04 +0200 Subject: [PATCH 04/30] feat: implement BQ76942 driver and update initialization sequences --- .../bms_config_default/components/core.yml | 123 ++- .../bms_config_default/components/sercom0.yml | 322 +++++++ .../mcc/bms_config_default/mcc-config.mc4 | 23 +- .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- .../mcc/mcc-manifest-generated-success.yml | 2 +- .../src/config/default/definitions.h | 8 +- .../default/harmony-manifest-success.yml | 2 +- .../src/config/default/initialization.c | 10 +- .../src/config/default/interrupts.c | 8 +- .../src/config/default/interrupts.h | 2 + .../default/peripheral/adc/plib_adc_common.h | 2 +- .../config/default/peripheral/can/plib_can1.c | 911 ++++++++++++++++++ .../config/default/peripheral/can/plib_can1.h | 123 +++ .../default/peripheral/clock/plib_clock.c | 18 +- .../default/peripheral/nvic/plib_nvic.c | 4 + .../i2c_master/plib_sercom1_i2c_master.c | 4 +- .../spi_master/plib_sercom0_spi_master.c | 622 ++++++++++++ .../spi_master/plib_sercom0_spi_master.h | 624 ++++++++++++ .../plib_sercom_spi_master_common.h | 296 ++++++ .../bms_config/src/ic_bms/bms_afe_driver.c | 76 ++ .../bms_config/src/ic_bms/bms_afe_driver.h | 8 + bms/bms/bms_config/src/safety/current.c | 1 + 22 files changed, 3166 insertions(+), 25 deletions(-) create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml create mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h create mode 100644 bms/bms/bms_config/src/ic_bms/bms_afe_driver.c create mode 100644 bms/bms/bms_config/src/ic_bms/bms_afe_driver.h diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index bb1854cc..7aaa156c 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -178,7 +178,7 @@ data: - children: - attributes: id: core - value: '0x60024' + value: '0x60026' type: Dynamic type: Values type: String @@ -776,6 +776,127 @@ data: type: Dynamic type: Values type: Boolean + SERCOM0_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM0_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_FREQ: + attributes: + id: GCLK_ID_19_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_CHEN: + attributes: + id: GCLK_ID_19_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM0_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_ENABLE: + attributes: + id: NVIC_9_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER_LOCK: + attributes: + id: NVIC_9_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER: + attributes: + id: NVIC_9_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_INTERRUPT_HANDLER: + attributes: + id: SERCOM0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom0 + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml new file mode 100644 index 00000000..675a9975 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml @@ -0,0 +1,322 @@ +configVersion: 1.0.0 +componentName: sercom0 +coreVersion: 5.8.2 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom0 + x: '538' + y: '152' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom0 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SERCOM_SPIM_COMMON_HEADER: + attributes: + id: SERCOM_SPIM_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_HEADER: + attributes: + id: SERCOM_SPIM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_SOURCE: + attributes: + id: SERCOM_SPIM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '23' + type: Dynamic + type: Values + type: Integer + SPI_CLOCK_PHASE: + attributes: + id: SPI_CLOCK_PHASE + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SPI_DIPO: + attributes: + id: SPI_DIPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom0 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom0 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom0 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index aac4e0a1..86afd346 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -15,6 +15,7 @@ modules: - dfp - evsys - nvmctrl +- sercom0 - sercom1 - sercom4 - stdio @@ -22,7 +23,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/ATSAMC21J18A.ld hash: 3fc7dbb63ae72ecd9b52572e4dd84ed79cbd37feb6064cb6d4df6fca301d09af - file: ../src/config/default/definitions.h - hash: e95b77e439bb3e6f7617af8bf65118cfa46b3979eaa08ed9c7773ee22a8f3d4b + hash: 5c3b223526d2cb5ed3468dda6a1fe34df911ac1c46135acf8d4f73b28eadab9b - file: ../src/config/default/device.h hash: e539bb402fa4783d95ccf06235458b2e1fe01207c83c0e046a853e0385d0b6f4 - file: ../src/config/default/device_cache.h @@ -32,11 +33,11 @@ generatedFileHashHistoryMap: - file: ../src/config/default/exceptions.c hash: 42f9da2668e04ccb3473d45b149683a00f80072c6883c7918d6ce93997cd6987 - file: ../src/config/default/initialization.c - hash: 84d3e4b57326e3a0bff8237bc317e4a32557a444cb2874c2298be46616b502e6 + hash: 377b659de8dd37b4b694a4a0f88359507d3c6536d908fae6f55a5644c8d7aee6 - file: ../src/config/default/interrupts.c - hash: ed7b4c0a70155ac9cdb7fe60b822c074c9f7ef45504bf3a448dc9c8b86bf0b2d + hash: b334b6f53c28ee3dba860dd2edd4a121b9526d6f4f96067a92960fa67c5ace92 - file: ../src/config/default/interrupts.h - hash: cd5790e206c937d36c78fbd349a75a7a31e1e7244733766dc46b428ade8467cb + hash: 8bd51246b301b4f479b766a82de6995ae32c86486b464b0328593e157052eda8 - file: ../src/config/default/libc_syscalls.c hash: 88bb2e34c939601b5b7ad076556e3ee0fcedf388436b8cddb6d6fd3e9d07472f - file: ../src/config/default/peripheral/adc/plib_adc0.c @@ -53,10 +54,14 @@ generatedFileHashHistoryMap: hash: 7f0eea33ffe3942f00d645cc9590cbeb93e3aacf764aa27d47528f8200877f0f - file: ../src/config/default/peripheral/can/plib_can0.h hash: 82effa7ee26a29add640e0239848f8265bf69247e1c29d24fa8b05ed853de21e +- file: ../src/config/default/peripheral/can/plib_can1.c + hash: f405307acbc691f6d286c022386f428d7d5b48ee9ba68563ab62744b2478330a +- file: ../src/config/default/peripheral/can/plib_can1.h + hash: 3237de4a4f656f996a4b3c449dbd14e23be7ee0885790c1853b2c1990d714413 - file: ../src/config/default/peripheral/can/plib_can_common.h hash: e0e3b54f69be9d8811bbe507f91daa443ae7bff5dc724ac51baebc160097b2d6 - file: ../src/config/default/peripheral/clock/plib_clock.c - hash: 43a11aa99441b76a84454322731605622ea578c327ed25c0d5411298c0ac9b86 + hash: f25fa3a02969658149292d7db24592b04413717fb07310ded817f7d1c31bd12b - file: ../src/config/default/peripheral/clock/plib_clock.h hash: 01c269741541514e997ef61546f4dbb0e23f66e27c6a957162557f13b4638baf - file: ../src/config/default/peripheral/evsys/plib_evsys.c @@ -64,7 +69,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/evsys/plib_evsys.h hash: f7d08eb8162f271ce1db384c082586a6624e506aa7f502c64c4ab5a1aadac47d - file: ../src/config/default/peripheral/nvic/plib_nvic.c - hash: e30586eae9669af9d0edddd329e98129dee11ef34037ecdfd54d454cbadfefd5 + hash: 0d3ba62c35d242212df5ddc0dae9cadcc8462b3b4c49a6ae2cbcfb2a60fe5f73 - file: ../src/config/default/peripheral/nvic/plib_nvic.h hash: 9936ac782115af41003255283fa2f603f4ff2212d16275b7c80ea8d067a9e208 - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -81,6 +86,12 @@ generatedFileHashHistoryMap: hash: 989b307a02a3932781c3120222b4624c5536e6cda1a1d70259e230a8f60c5ed4 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h hash: f167b04b3c6a0f83fe41b7b6f810cbf0a48b8ca7d5a747b76463dd53d3c1a2a2 +- file: ../src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c + hash: 46b45fe236f74221755882245969cd1b2c83c66cb8a02b32eee89cf66be70f06 +- file: ../src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h + hash: 8e1550559a741d9ace2e6fb145ac015c8457aa417c877996855b73238051babb +- file: ../src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h + hash: 06e3c7813e1608b5008e3c8955569f9cff04bef321a34c35421f7979368a4ada - file: ../src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c hash: 880e9248b3e4b6517183810b77c56edaf08e4e99a993c52ccfa39fc83819f920 - file: ../src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index bd5d7700..2a809904 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2025-10-10T14:27:55.811+02:00[Europe/Oslo] +creation_date: 2025-10-22T14:14:56.067+02:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml index fbab818a..67bb2f81 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2025-10-09T17:41:06.334+02:00[Europe/Oslo] +creation_date: 2025-10-22T14:14:34.229+02:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/config/default/definitions.h b/bms/bms/bms_config/src/config/default/definitions.h index 3e0cb6ea..eeba27c2 100644 --- a/bms/bms/bms_config/src/config/default/definitions.h +++ b/bms/bms/bms_config/src/config/default/definitions.h @@ -52,13 +52,15 @@ #include "peripheral/nvmctrl/plib_nvmctrl.h" #include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" #include "peripheral/evsys/plib_evsys.h" -#include "peripheral/adc/plib_adc0.h" +#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" +#include "peripheral/can/plib_can1.h" #include "peripheral/port/plib_port.h" #include "peripheral/clock/plib_clock.h" #include "peripheral/nvic/plib_nvic.h" -#include "peripheral/adc/plib_adc1.h" -#include "peripheral/can/plib_can0.h" #include "peripheral/sercom/usart/plib_sercom4_usart.h" +#include "peripheral/can/plib_can0.h" +#include "peripheral/adc/plib_adc0.h" +#include "peripheral/adc/plib_adc1.h" // DOM-IGNORE-BEGIN #ifdef __cplusplus // Provide C++ Compatibility diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml index 24fec660..76572352 100644 --- a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -4,7 +4,7 @@ project: bms_config_default -creation_date: 2025-10-09T17:41:06.372+02:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +creation_date: 2025-10-22T14:14:34.243+02:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime operating_system: Linux mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] mcc_version: v5.6.2 diff --git a/bms/bms/bms_config/src/config/default/initialization.c b/bms/bms/bms_config/src/config/default/initialization.c index 1759e1f1..52f622d3 100644 --- a/bms/bms/bms_config/src/config/default/initialization.c +++ b/bms/bms/bms_config/src/config/default/initialization.c @@ -171,14 +171,18 @@ void SYS_Initialize ( void* data ) EVSYS_Initialize(); + SERCOM0_SPI_Initialize(); - ADC0_Initialize(); + CAN1_Initialize(); + + SERCOM4_USART_Initialize(); - ADC1_Initialize(); CAN0_Initialize(); - SERCOM4_USART_Initialize(); + ADC0_Initialize(); + + ADC1_Initialize(); NVIC_Initialize(); diff --git a/bms/bms/bms_config/src/config/default/interrupts.c b/bms/bms/bms_config/src/config/default/interrupts.c index adda0b21..11668af1 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.c +++ b/bms/bms/bms_config/src/config/default/interrupts.c @@ -75,7 +75,7 @@ void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(vo } /* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 8.6 deviated 32 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 30 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ /* Device vectors list dummy definition*/ extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); @@ -89,12 +89,10 @@ extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dumm extern void NVMCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void DMAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void EVSYS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void SERCOM0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SERCOM2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SERCOM3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SERCOM4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SERCOM5_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void CAN1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TCC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TCC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TCC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); @@ -138,14 +136,14 @@ const H3DeviceVectors exception_table= .pfnNVMCTRL_Handler = NVMCTRL_Handler, .pfnDMAC_Handler = DMAC_Handler, .pfnEVSYS_Handler = EVSYS_Handler, - .pfnSERCOM0_Handler = SERCOM0_Handler, + .pfnSERCOM0_Handler = SERCOM0_SPI_InterruptHandler, .pfnSERCOM1_Handler = SERCOM1_I2C_InterruptHandler, .pfnSERCOM2_Handler = SERCOM2_Handler, .pfnSERCOM3_Handler = SERCOM3_Handler, .pfnSERCOM4_Handler = SERCOM4_Handler, .pfnSERCOM5_Handler = SERCOM5_Handler, .pfnCAN0_Handler = CAN0_InterruptHandler, - .pfnCAN1_Handler = CAN1_Handler, + .pfnCAN1_Handler = CAN1_InterruptHandler, .pfnTCC0_Handler = TCC0_Handler, .pfnTCC1_Handler = TCC1_Handler, .pfnTCC2_Handler = TCC2_Handler, diff --git a/bms/bms/bms_config/src/config/default/interrupts.h b/bms/bms/bms_config/src/config/default/interrupts.h index 336ef6ce..9206fa21 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.h +++ b/bms/bms/bms_config/src/config/default/interrupts.h @@ -59,8 +59,10 @@ void Reset_Handler (void); void NonMaskableInt_Handler (void); void HardFault_Handler (void); +void SERCOM0_SPI_InterruptHandler (void); void SERCOM1_I2C_InterruptHandler (void); void CAN0_InterruptHandler (void); +void CAN1_InterruptHandler (void); diff --git a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h index 0d449e87..c1dfe852 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h +++ b/bms/bms/bms_config/src/config/default/peripheral/adc/plib_adc_common.h @@ -91,7 +91,7 @@ typedef enum ADC_POSINPUT_AIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, ADC_POSINPUT_AIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, ADC_POSINPUT_AIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, - ADC_POSINPUT_AIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, + ADC_POSINPUT_AIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, ADC_POSINPUT_AIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, ADC_POSINPUT_AIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, ADC_POSINPUT_AIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c new file mode 100644 index 00000000..3b043bb7 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c @@ -0,0 +1,911 @@ +/******************************************************************************* + Controller Area Network (CAN) Peripheral Library Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_can1.c + + Summary: + CAN peripheral library interface. + + Description: + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Header Includes +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include "interrupts.h" +#include "plib_can1.h" + +// ***************************************************************************** +// ***************************************************************************** +// Global Data +// ***************************************************************************** +// ***************************************************************************** +#define CAN_STD_ID_Msk 0x7FFU + +static volatile CAN_TX_FIFO_CALLBACK_OBJ can1TxFifoCallbackObj; +static volatile CAN_TX_EVENT_FIFO_CALLBACK_OBJ can1TxEventFifoCallbackObj; +static volatile CAN_RX_FIFO_CALLBACK_OBJ can1RxFifoCallbackObj[2]; +static volatile CAN_CALLBACK_OBJ can1CallbackObj; +static volatile CAN_OBJ can1Obj; + +static inline void CAN1_ZeroInitialize(volatile void* pData, size_t dataSize) +{ + volatile uint8_t* data = (volatile uint8_t*)pData; + for (uint32_t index = 0; index < dataSize; index++) + { + data[index] = 0U; + } +} + +// ***************************************************************************** +// ***************************************************************************** +// CAN1 PLib Interface Routines +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void CAN1_Initialize(void) + + Summary: + Initializes given instance of the CAN peripheral. + + Precondition: + None. + + Parameters: + None. + + Returns: + None +*/ +void CAN1_Initialize(void) +{ + /* Start CAN initialization */ + CAN1_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + /* Set Data Bit Timing and Prescaler Register */ + CAN1_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(0UL) | CAN_DBTP_DTSEG1(29UL) | CAN_DBTP_DBRP(2UL) | CAN_DBTP_DSJW(0UL); + + /* Set Nominal Bit timing and Prescaler Register */ + CAN1_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(23UL) | CAN_NBTP_NTSEG1(70UL) | CAN_NBTP_NBRP(0UL) | CAN_NBTP_NSJW(23UL); + + /* Receive Buffer / FIFO Element Size Configuration Register */ + CAN1_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(0UL) | CAN_RXESC_F1DS(0UL); + /* Transmit Buffer/FIFO Element Size Configuration Register */ + CAN1_REGS->CAN_TXESC = CAN_TXESC_TBDS(0UL); + + /* Global Filter Configuration Register */ + CAN1_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; + + /* Set the operation mode */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; + + + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Select interrupt line */ + CAN1_REGS->CAN_ILS = 0x0U; + + /* Enable interrupt line */ + CAN1_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; + + /* Enable CAN interrupts */ + CAN1_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk + | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk + | CAN_IE_TFEE_Msk + | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk + | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk + | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk + + | CAN_IE_MRAFE_Msk; + + CAN1_ZeroInitialize(&can1Obj.msgRAMConfig, sizeof(CAN_MSG_RAM_CONFIG)); +} + + +// ***************************************************************************** +/* Function: + bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) + + Summary: + Transmit multiple messages into CAN bus from Tx FIFO. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfMessage - Total number of message. + txBuffer - Pointer to Tx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) +{ + uint8_t *txFifo = NULL; + uint8_t *txBuf = (uint8_t *)txBuffer; + uint32_t bufferNumber = 0U; + uint8_t tfqpi = 0U; + uint8_t count = 0U; + bool transmitFifo_event = false; + + if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) + { + tfqpi = (uint8_t)((CAN1_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + + for (count = 0U; count < numberOfMessage; count++) + { + txFifo = (uint8_t *)((uint8_t*)can1Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE)); + + (void) memcpy(txFifo, txBuf, CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE); + + txBuf += CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE; + bufferNumber |= (1UL << tfqpi); + tfqpi++; + if (tfqpi == 1U) + { + tfqpi = 0U; + } + } + + __DSB(); + + /* Set Transmission request */ + CAN1_REGS->CAN_TXBAR = bufferNumber; + + transmitFifo_event = true; + } + return transmitFifo_event; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN1_TxFifoFreeLevelGet(void) + + Summary: + Returns Tx FIFO Free Level. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Tx FIFO Free Level. +*/ +uint8_t CAN1_TxFifoFreeLevelGet(void) +{ + return (uint8_t)(CAN1_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); +} + +// ***************************************************************************** +/* Function: + bool CAN1_TxBufferIsBusy(uint8_t bufferNumber) + + Summary: + Check if Transmission request is pending for the specific Tx buffer. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + true - Transmission request is pending. + false - Transmission request is not pending. +*/ +bool CAN1_TxBufferIsBusy(uint8_t bufferNumber) +{ + return ((CAN1_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); +} + +// ***************************************************************************** +/* Function: + bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) + + Summary: + Read Tx Event FIFO for the transmitted messages. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfTxEvent - Total number of Tx Event + txEventFifo - Pointer to Tx Event FIFO + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) +{ + uint8_t txefgi = 0U; + uint8_t count = 0U; + uint8_t *txEvent = NULL; + uint8_t *txEvtFifo = (uint8_t *)txEventFifo; + bool txFifo_event = false; + + if (txEventFifo != NULL) + { + /* Read data from the Rx FIFO0 */ + txefgi = (uint8_t)((CAN1_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); + for (count = 0U; count < numberOfTxEvent; count++) + { + txEvent = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); + + (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); + + if ((count + 1U) == numberOfTxEvent) + { + break; + } + txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); + txefgi++; + if (txefgi == 1U) + { + txefgi = 0U; + } + } + + /* Ack the Tx Event FIFO position */ + CAN1_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); + + txFifo_event = true; + } + return txFifo_event; +} + + +// ***************************************************************************** +/* Function: + bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) + + Summary: + Read messages from Rx FIFO0/FIFO1. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO number + numberOfMessage - Total number of message + rxBuffer - Pointer to Rx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) +{ + uint8_t rxgi = 0U; + uint8_t count = 0U; + uint8_t *rxFifo = NULL; + uint8_t *rxBuf = (uint8_t *)rxBuffer; + bool status = false; + + if (rxBuffer != NULL) + { + switch (rxFifoNum) + { + case CAN_RX_FIFO_0: + /* Read data from the Rx FIFO0 */ + rxgi = (uint8_t)((CAN1_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN1_RX_FIFO0_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN1_RX_FIFO0_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN1_RX_FIFO0_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + + /* Ack the fifo position */ + CAN1_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); + + status = true; + break; + case CAN_RX_FIFO_1: + /* Read data from the Rx FIFO1 */ + rxgi = (uint8_t)((CAN1_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN1_RX_FIFO1_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN1_RX_FIFO1_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN1_RX_FIFO1_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + /* Ack the fifo position */ + CAN1_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); + + status = true; + break; + default: + /* Do nothing */ + break; + } + } + return status; +} + +// ***************************************************************************** +/* Function: + CAN_ERROR CAN1_ErrorGet(void) + + Summary: + Returns the error during transfer. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Error during transfer. +*/ +CAN_ERROR CAN1_ErrorGet(void) +{ + CAN_ERROR error; + uint32_t errorStatus = CAN1_REGS->CAN_PSR; + + error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) + | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); + + if ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + } + + return error; +} + +// ***************************************************************************** +/* Function: + void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) + + Summary: + Returns the transmit and receive error count during transfer. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + txErrorCount - Transmit Error Count to be received + rxErrorCount - Receive Error Count to be received + + Returns: + None. +*/ +void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) +{ + *txErrorCount = (uint8_t)(CAN1_REGS->CAN_ECR & CAN_ECR_TEC_Msk); + *rxErrorCount = (uint8_t)((CAN1_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); +} + +// ***************************************************************************** +/* Function: + void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) + + Summary: + Set the Message RAM Configuration. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. + Application must allocate buffer from non-cached + contiguous memory and buffer size must be + CAN1_MESSAGE_RAM_CONFIG_SIZE + + Returns: + None +*/ +/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ +void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) +{ + uint32_t offset = 0U; + uint32_t msgRAMConfigBaseAddr = (uint32_t)msgRAMConfigBaseAddress; + + (void) memset(msgRAMConfigBaseAddress, 0x00, CAN1_MESSAGE_RAM_CONFIG_SIZE); + + /* Set CAN CCCR Init for Message RAM Configuration */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + can1Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; + offset = CAN1_RX_FIFO0_SIZE; + /* Receive FIFO 0 Configuration Register */ + CAN1_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | + CAN_RXF0C_F0SA((uint32_t)can1Obj.msgRAMConfig.rxFIFO0Address); + + can1Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN1_RX_FIFO1_SIZE; + /* Receive FIFO 1 Configuration Register */ + CAN1_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | + CAN_RXF1C_F1SA((uint32_t)can1Obj.msgRAMConfig.rxFIFO1Address); + + can1Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN1_TX_FIFO_BUFFER_SIZE; + /* Transmit Buffer/FIFO Configuration Register */ + CAN1_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | + CAN_TXBC_TBSA((uint32_t)can1Obj.msgRAMConfig.txBuffersAddress); + + can1Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN1_TX_EVENT_FIFO_SIZE; + /* Transmit Event FIFO Configuration Register */ + CAN1_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | + CAN_TXEFC_EFSA((uint32_t)can1Obj.msgRAMConfig.txEventFIFOAddress); + + + /* Reference offset variable once to remove warning about the variable not being used after increment */ + (void)offset; + + /* Complete Message RAM Configuration by clearing CAN CCCR Init */ + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for configuration complete */ + } +} +/* MISRAC 2012 deviation block end for Rule 11.3*/ + + + + +void CAN1_SleepModeEnter(void) +{ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) + { + /* Wait for clock stop request to complete */ + } +} + +void CAN1_SleepModeExit(void) +{ + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) + { + /* Wait for no clock stop */ + } + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } +} + +bool CAN1_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + uint32_t numOfTimeQuanta; + uint8_t tseg1; + float temp1; + float temp2; + + if ((setup != NULL) && (bitTiming != NULL)) + { + if (setup->nominalBitTimingSet == true) + { + numOfTimeQuanta = CAN1_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) + { + if (setup->nominalSamplePoint < 50.0f) + { + setup->nominalSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; + bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; + bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; + bitTiming->nominalBitTimingSet = true; + status = true; + } + else + { + bitTiming->nominalBitTimingSet = false; + } + } + if (setup->dataBitTimingSet == true) + { + numOfTimeQuanta = CAN1_CLOCK_FREQUENCY / (setup->dataBitRate * ((uint32_t)setup->dataPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 49U)) + { + if (setup->dataSamplePoint < 50.0f) + { + setup->dataSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->dataSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->dataBitTiming.dataTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->dataBitTiming.dataTimeSegment1 = tseg1 - 2U; + bitTiming->dataBitTiming.dataSJW = bitTiming->dataBitTiming.dataTimeSegment2; + bitTiming->dataBitTiming.dataPrescaler = setup->dataPrescaler; + bitTiming->dataBitTimingSet = true; + status = true; + } + else + { + bitTiming->dataBitTimingSet = false; + status = false; + } + } + } + + return status; +} + +bool CAN1_BitTimingSet(CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + bool nominalBitTimingSet = false; + bool dataBitTimingSet = false; + + if ((bitTiming->nominalBitTimingSet == true) + && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) + && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) + && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) + && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) + { + nominalBitTimingSet = true; + } + + if ((bitTiming->dataBitTimingSet == true) + && ((bitTiming->dataBitTiming.dataTimeSegment1 >= 0x1U) && (bitTiming->dataBitTiming.dataTimeSegment1 <= 0x1FU)) + && (bitTiming->dataBitTiming.dataTimeSegment2 <= 0xFU) + && (bitTiming->dataBitTiming.dataPrescaler <= 0x1FU) + && (bitTiming->dataBitTiming.dataSJW <= 0xFU)) + { + dataBitTimingSet = true; + } + + if ((nominalBitTimingSet == true) || (dataBitTimingSet == true)) + { + /* Start CAN initialization */ + CAN1_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + if (dataBitTimingSet == true) + { + /* Set Data Bit Timing and Prescaler Register */ + CAN1_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(bitTiming->dataBitTiming.dataTimeSegment2) | CAN_DBTP_DTSEG1(bitTiming->dataBitTiming.dataTimeSegment1) | CAN_DBTP_DBRP(bitTiming->dataBitTiming.dataPrescaler) | CAN_DBTP_DSJW(bitTiming->dataBitTiming.dataSJW); + } + if (nominalBitTimingSet == true) + { + /* Set Nominal Bit timing and Prescaler Register */ + CAN1_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); + } + + /* Set the operation mode */ + CAN1_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; + + + CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + status = true; + } + return status; +} + + +// ***************************************************************************** +/* Function: + void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1TxFifoCallbackObj.callback = callback; + can1TxFifoCallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_EVENT_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1TxEventFifoCallbackObj.callback = callback; + can1TxEventFifoCallbackObj.context = contextHandle; + + } +} + + +// ***************************************************************************** +/* Function: + void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO Number + + callback - A pointer to a function with a calling signature defined + by the CAN_RX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1RxFifoCallbackObj[rxFifoNum].callback = callback; + can1RxFifoCallbackObj[rxFifoNum].context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN1_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can1CallbackObj.callback = callback; + can1CallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN1_InterruptHandler(void) + + Summary: + CAN1 Peripheral Interrupt Handler. + + Description: + This function is CAN1 Peripheral Interrupt Handler and will + called on every CAN1 interrupt. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Remarks: + The function is called as peripheral instance's interrupt handler if the + instance interrupt is enabled. If peripheral instance's interrupt is not + enabled user need to call it from the main while loop of the application. +*/ +void __attribute__((used)) CAN1_InterruptHandler(void) +{ + uint8_t numberOfMessage = 0; + uint8_t numberOfTxEvent = 0; + + uint32_t ir = CAN1_REGS->CAN_IR; + + /* Additional temporary variable used to prevent MISRA violations (Rule 13.x) */ + uintptr_t context; + + if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) + { + CAN1_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); + if (can1CallbackObj.callback != NULL) + { + context = can1CallbackObj.context; + can1CallbackObj.callback(ir, context); + } + } + /* New Message in Rx FIFO 0 */ + if ((ir & CAN_IR_RF0N_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_RF0N_Msk; + + numberOfMessage = (uint8_t)(CAN1_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); + + if (can1RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) + { + context = can1RxFifoCallbackObj[CAN_RX_FIFO_0].context; + can1RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, context); + } + } + /* New Message in Rx FIFO 1 */ + if ((ir & CAN_IR_RF1N_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_RF1N_Msk; + + numberOfMessage = (uint8_t)(CAN1_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); + + if (can1RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) + { + context = can1RxFifoCallbackObj[CAN_RX_FIFO_1].context; + can1RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, context); + } + } + + /* TX FIFO is empty */ + if ((ir & CAN_IR_TFE_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_TFE_Msk; + if (can1TxFifoCallbackObj.callback != NULL) + { + context = can1TxFifoCallbackObj.context; + can1TxFifoCallbackObj.callback(context); + } + } + /* Tx Event FIFO new entry */ + if ((ir & CAN_IR_TEFN_Msk) != 0U) + { + CAN1_REGS->CAN_IR = CAN_IR_TEFN_Msk; + + numberOfTxEvent = (uint8_t)(CAN1_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); + + if (can1TxEventFifoCallbackObj.callback != NULL) + { + context = can1TxEventFifoCallbackObj.context; + can1TxEventFifoCallbackObj.callback(numberOfTxEvent, context); + } + } +} + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h new file mode 100644 index 00000000..144bacf5 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h @@ -0,0 +1,123 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_can1.h + + Summary: + CAN PLIB interface declarations. + + Description: + The CAN plib provides a simple interface to manage the CAN modules on + Microchip microcontrollers. This file defines the interface declarations + for the CAN plib. + + Remarks: + None. + +*******************************************************************************/ +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END + +#ifndef PLIB_CAN1_H +#define PLIB_CAN1_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +/* + * This section lists the other files that are included in this file. + */ +#include +#include + +#include "device.h" +#include "plib_can_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +#define CAN1_CLOCK_FREQUENCY 48000000U + +/* CAN1 Message RAM Configuration Size */ +#define CAN1_RX_FIFO0_ELEMENT_SIZE 16U +#define CAN1_RX_FIFO0_SIZE 16U +#define CAN1_RX_FIFO1_ELEMENT_SIZE 16U +#define CAN1_RX_FIFO1_SIZE 16U +#define CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE 16U +#define CAN1_TX_FIFO_BUFFER_SIZE 16U +#define CAN1_TX_EVENT_FIFO_SIZE 8U + +/* CAN1_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver + for allocating buffer from non-cached contiguous memory */ +#define CAN1_MESSAGE_RAM_CONFIG_SIZE 56U + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +void CAN1_Initialize(void); +bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); +uint8_t CAN1_TxFifoFreeLevelGet(void); +bool CAN1_TxBufferIsBusy(uint8_t bufferNumber); +bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); +bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); +CAN_ERROR CAN1_ErrorGet(void); +void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); +void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); +void CAN1_SleepModeEnter(void); +void CAN1_SleepModeExit(void); +bool CAN1_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); +bool CAN1_BitTimingSet(CAN_BIT_TIMING *bitTiming); +void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif +// DOM-IGNORE-END + +#endif // PLIB_CAN1_H + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c index 35258b3e..d5277453 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c +++ b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c @@ -98,6 +98,13 @@ void CLOCK_Initialize (void) GCLK0_Initialize(); + /* Selection of the Generator and write Lock for SERCOM0_CORE */ + GCLK_REGS->GCLK_PCHCTRL[19] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[19] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } /* Selection of the Generator and write Lock for SERCOM1_CORE */ GCLK_REGS->GCLK_PCHCTRL[20] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; @@ -119,6 +126,13 @@ void CLOCK_Initialize (void) { /* Wait for synchronization */ } + /* Selection of the Generator and write Lock for CAN1 */ + GCLK_REGS->GCLK_PCHCTRL[27] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[27] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } /* Selection of the Generator and write Lock for ADC0 */ GCLK_REGS->GCLK_PCHCTRL[33] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; @@ -134,12 +148,12 @@ void CLOCK_Initialize (void) /* Wait for synchronization */ } /* Configure the AHB Bridge Clocks */ - MCLK_REGS->MCLK_AHBMASK = 0x1dffU; + MCLK_REGS->MCLK_AHBMASK = 0x1fffU; /* Configure the APBC Bridge Clocks */ - MCLK_REGS->MCLK_APBCMASK = 0x60024U; + MCLK_REGS->MCLK_APBCMASK = 0x60026U; } diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c index da38ec0f..c6c35377 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c +++ b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c @@ -57,10 +57,14 @@ void NVIC_Initialize( void ) /* Enable the interrupt sources and configure the priorities as configured * from within the "Interrupt Manager" of MHC. */ + NVIC_SetPriority(SERCOM0_IRQn, 3); + NVIC_EnableIRQ(SERCOM0_IRQn); NVIC_SetPriority(SERCOM1_IRQn, 3); NVIC_EnableIRQ(SERCOM1_IRQn); NVIC_SetPriority(CAN0_IRQn, 3); NVIC_EnableIRQ(CAN0_IRQn); + NVIC_SetPriority(CAN1_IRQn, 3); + NVIC_EnableIRQ(CAN1_IRQn); diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c index 6774f2e5..f462e518 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c @@ -105,6 +105,7 @@ void SERCOM1_I2C_Initialize(void) { /* Do nothing */ } + /* Initial Bus State: IDLE */ SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); @@ -351,12 +352,13 @@ bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength) return SERCOM1_I2C_XferSetup(address, wrData, wrLength, NULL, 0, false, false); } + + bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength) { return SERCOM1_I2C_XferSetup(address, wrData, wrLength, rdData, rdLength, false, false); } - bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound) { uint8_t* pDevList = (uint8_t*)pDevicesList; diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c new file mode 100644 index 00000000..f3ba5875 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c @@ -0,0 +1,622 @@ +/******************************************************************************* + SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE(SERCOM0_SPI) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_spi_master.c + + Summary + SERCOM0_SPI Master PLIB Implementation File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_sercom0_spi_master.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: MACROS Definitions +// ***************************************************************************** +// ***************************************************************************** + + +/* SERCOM0 clk freq value for the baud calculation */ +#define SERCOM0_Frequency (48000000UL) + +/* SERCOM0 SPI baud value for 1000000 Hz baud rate */ +#define SERCOM0_SPIM_BAUD_VALUE (23UL) + +/*Global object to save SPI Exchange related data */ +static volatile SPI_OBJECT sercom0SPIObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM0_SPI Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_Initialize(void); + + Summary: + Initializes instance SERCOM0 of the SERCOM module operating in SPI mode. + + Description: + This function initializes instance SERCOM0 of SERCOM module operating in SPI mode. + This function should be called before any other library function. The SERCOM + module will be configured as per the MHC settings. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_Initialize(void) +{ + /* Instantiate the SERCOM0 SPI object */ + sercom0SPIObj.callback = NULL ; + sercom0SPIObj.transferIsBusy = false ; + sercom0SPIObj.txSize = 0U; + sercom0SPIObj.rxSize = 0U; + + /* Selection of the Character Size and Receiver Enable */ + SERCOM0_REGS->SPIM.SERCOM_CTRLB = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT | SERCOM_SPIM_CTRLB_RXEN_Msk ; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Selection of the Baud Value */ + SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)SERCOM_SPIM_BAUD_BAUD(SERCOM0_SPIM_BAUD_VALUE); + + /* Configure Data Out Pin Out , Master Mode, + * Data In and Pin Out,Data Order and Standby mode if configured + * and Selection of the Clock Phase and Polarity and Enable the SPI Module + */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA = SERCOM_SPIM_CTRLA_MODE_SPI_MASTER | SERCOM_SPIM_CTRLA_DOPO_PAD0 | SERCOM_SPIM_CTRLA_DIPO_PAD3 | SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW | SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE | SERCOM_SPIM_CTRLA_DORD_MSB | SERCOM_SPIM_CTRLA_ENABLE_Msk ; + + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, + uint32_t spiSourceClock); + + Summary: + Configure SERCOM SPI operational parameters at run time. + + Description: + This function allows the application to change the SERCOM SPI operational + parameter at run time. The application can thus override the MHC defined + configuration for these parameters. The parameter are specified via the + SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter + should be initialized to the desired value. + + The application may feel need to call this function in situation where + multiple SPI slaves, each with different operation parameters, are connected + to one SPI master. This function can thus be used to setup the SPI Master to + meet the communication needs of the slave. + + Calling this function will affect any ongoing communication. The application + must thus ensure that there is no on-going communication on the SPI before + calling this function. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock) +{ + uint32_t baudValue = 0U; + + bool statusValue = false; + + if(spiSourceClock == 0U) + { + /* Fetch Master Clock Frequency directly */ + spiSourceClock = SERCOM0_Frequency; + } + + /* Disable the SPI Module */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_ENABLE_Msk); + + /* Disabling SPI module, also clears the TXC (Transmit Complete) bit to 0. TXC = 0 means transfer is not complete (busy). + As a result, calling SERCOM0_SPI_IsBusy() after a call to SERCOM0_SPI_TransferSetup() always returns busy. + Since, application must call the SERCOM0_SPI_TransferSetup() API only after ensuring that no transfer is in progress, + it is safe to clear the rxSize and txSize to 0, so as to let the SERCOM0_SPI_IsBusy() return false (not busy). + */ + sercom0SPIObj.rxSize = 0; + sercom0SPIObj.txSize = 0; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + if(setup != NULL) + { + if (setup->clockFrequency <= spiSourceClock/2U) + { + baudValue = (spiSourceClock/(2U*(setup->clockFrequency))) - 1U; + + /* Set the lowest possible baud */ + if (baudValue >= 255U) + { + baudValue = 255U; + } + + /* Selection of the Clock Polarity and Clock Phase */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_CPOL_Msk | SERCOM_SPIM_CTRLA_CPHA_Msk); + SERCOM0_REGS->SPIM.SERCOM_CTRLA |= (uint32_t)setup->clockPolarity | (uint32_t)setup->clockPhase; + + /* Selection of the Baud Value */ + SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)baudValue; + + /* Selection of the Character Size */ + SERCOM0_REGS->SPIM.SERCOM_CTRLB &= ~SERCOM_SPIM_CTRLB_CHSIZE_Msk; + SERCOM0_REGS->SPIM.SERCOM_CTRLB |= (uint32_t)setup->dataBits; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + statusValue = true; + } + } + + /* Enabling the SPI Module */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA |= SERCOM_SPIM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + return statusValue; +} + + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, + uintptr_t context); + + Summary: + Allows application to register callback with PLIB. + + Description: + This function allows application to register an event handling function + for the PLIB to call back when requested data exchange operation has + completed or any error has occurred. + The callback should be registered before the client performs exchange + operation. + At any point if application wants to stop the callback, it can use this + function with "callBack" value as NULL. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context ) +{ + sercom0SPIObj.callback = callBack; + + sercom0SPIObj.context = context; +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsBusy(void); + + Summary: + Returns transfer status of SERCOM SERCOM0SPI. + + Description: + This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The + application can use the function to check if SERCOM SERCOM0SPI module is busy + before calling any of the data transfer functions. The library does not + allow a data transfer operation if another transfer operation is already in + progress. + + This function can be used as an alternative to the callback function when + the library is operating interrupt mode. The allow the application to + implement a synchronous interface to the library. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_IsBusy(void) +{ + bool isBusy = false; + size_t txSize = sercom0SPIObj.txSize; + bool transferIsBusy = sercom0SPIObj.transferIsBusy; + + if ((sercom0SPIObj.rxSize == 0U) && (txSize == 0U)) + { + /* This means no transfer has been requested yet; hence SPI is not busy. */ + isBusy = false; + } + else + { + /* if transmit is not complete or if the state flag is not set, SPI is busy */ + isBusy = (((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U) || transferIsBusy); + } + return isBusy; +} + +bool SERCOM0_SPI_IsTransmitterBusy(void) +{ + return ((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U)? true : false; +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize + void* pReceiveData, size_t rxSize); + + Summary: + Write and Read data on SERCOM SERCOM0 SPI peripheral. + + Description: + This function transmits "txSize" number of bytes and receives "rxSize" + number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is + transmitted and received data is saved in the location pointed by + pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" + data units towards completion. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit and receive buffer are ownerd by the library until the data + transfer is complete and should not be modified by the application till the + transfer is complete. Only one transfer is allowed at any time. The + Application can use a callback function or a polling function to check for + completion of the transfer. If a callback is required, this should be + registered prior to calling the SERCOM0_SPI_WriteRead() function. The + application can use the SERCOM0_SPI_IsBusy() to poll for completion. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize) +{ + bool isRequestAccepted = false; + uint32_t dummyData = 0U; + size_t txSz; + + if (sercom0SPIObj.transferIsBusy == false) + { + /* Verify the request */ + if(((txSize > 0U) && (pTransmitData != NULL)) || ((rxSize > 0U) && (pReceiveData != NULL))) + { + if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_9) + { + /* For 9-bit transmission, the txSize and rxSize must be an even number. */ + if(((txSize > 0U) && ((txSize & 0x01U) != 0U)) || ((rxSize > 0U) && ((rxSize & 0x01U) != 0U))) + { + return isRequestAccepted; + } + } + + isRequestAccepted = true; + sercom0SPIObj.txBuffer = pTransmitData; + sercom0SPIObj.rxBuffer = pReceiveData; + sercom0SPIObj.rxCount = 0U; + sercom0SPIObj.txCount = 0U; + sercom0SPIObj.dummySize = 0U; + + if(pTransmitData != NULL) + { + sercom0SPIObj.txSize = txSize; + } + else + { + sercom0SPIObj.txSize = 0U; + } + + if(pReceiveData != NULL) + { + sercom0SPIObj.rxSize = rxSize; + } + else + { + sercom0SPIObj.rxSize = 0U; + } + + sercom0SPIObj.transferIsBusy = true; + + /* Flush out any unread data in SPI read buffer */ + while((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) + { + dummyData = SERCOM0_REGS->SPIM.SERCOM_DATA; + (void)dummyData; + } + + SERCOM0_REGS->SPIM.SERCOM_STATUS |= SERCOM_SPIM_STATUS_BUFOVF_Msk; + + SERCOM0_REGS->SPIM.SERCOM_INTFLAG |= (uint8_t)SERCOM_SPIM_INTFLAG_ERROR_Msk; + + txSz = sercom0SPIObj.txSize; + + if(sercom0SPIObj.rxSize > txSz) + { + sercom0SPIObj.dummySize = sercom0SPIObj.rxSize - txSz; + } + + /* Start the first write here itself, rest will happen in ISR context */ + if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_8) + { + if(sercom0SPIObj.txCount < txSz) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint8_t*)sercom0SPIObj.txBuffer); + + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + else + { + sercom0SPIObj.txSize >>= 1U; + sercom0SPIObj.dummySize >>= 1U; + sercom0SPIObj.rxSize >>= 1U; + + txSz = sercom0SPIObj.txSize; + + if(sercom0SPIObj.txCount < txSz) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint16_t*)sercom0SPIObj.txBuffer) & SERCOM_SPIM_DATA_Msk; + + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU & SERCOM_SPIM_DATA_Msk; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + + if(rxSize > 0U) + { + /* Enable ReceiveComplete */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_RXC_Msk; + } + else + { + /* Enable the DataRegisterEmpty */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; + } + } + } + + return isRequestAccepted; +} + +bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize) +{ + return SERCOM0_SPI_WriteRead(pTransmitData, txSize, NULL, 0U); +} + +bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize) +{ + return SERCOM0_SPI_WriteRead(NULL, 0U, pReceiveData, rxSize); +} + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_InterruptHandler(void); + + Summary: + Handler that handles the SPI interrupts + + Description: + This Function is called from the handler to handle the exchange based on the + Interrupts. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void __attribute__((used)) SERCOM0_SPI_InterruptHandler(void) +{ + uint32_t dataBits = 0U; + uint32_t receivedData = 0U; + static bool isLastByteTransferInProgress = false; + uintptr_t context = sercom0SPIObj.context; + + if(SERCOM0_REGS->SPIM.SERCOM_INTENSET != 0U) + { + dataBits = SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk; + + size_t rxCount = sercom0SPIObj.rxCount; + size_t txCount = sercom0SPIObj.txCount; + size_t txSize = sercom0SPIObj.txSize; + + if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) + { + receivedData = SERCOM0_REGS->SPIM.SERCOM_DATA; + + if(rxCount < sercom0SPIObj.rxSize) + { + if(dataBits == (uint32_t)SPI_DATA_BITS_8) + { + ((uint8_t*)sercom0SPIObj.rxBuffer)[rxCount] = (uint8_t)receivedData; + rxCount++; + } + else + { + ((uint16_t*)sercom0SPIObj.rxBuffer)[rxCount] = (uint16_t)receivedData; + rxCount++; + } + } + } + + /* If there are more words to be transmitted, then transmit them here and keep track of the count */ + if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_DRE_Msk) == SERCOM_SPIM_INTFLAG_DRE_Msk) + { + /* Disable the DRE interrupt. This will be enabled back if more than + * one byte is pending to be transmitted */ + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_DRE_Msk; + + if(dataBits == (uint32_t)SPI_DATA_BITS_8) + { + if(txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint8_t*)sercom0SPIObj.txBuffer)[txCount]; + txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + else + { + if(txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint16_t*)sercom0SPIObj.txBuffer)[txCount]; + txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + + if((sercom0SPIObj.dummySize == 0U) && (txCount == txSize)) + { + /* At higher baud rates, the data in the shift register can be + * shifted out and TXC flag can get set resulting in a + * callback been given to the application with the SPI interrupt + * pending with the application. This will then result in the + * interrupt handler being called again with nothing to transmit. + * To avoid this, a software flag is set, but + * the TXC interrupt is not enabled until the very end. + */ + + isLastByteTransferInProgress = true; + } + else if(rxCount == sercom0SPIObj.rxSize) + { + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; + + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_RXC_Msk; + } + else + { + /* Do nothing */ + } + } + + sercom0SPIObj.rxCount = rxCount; + sercom0SPIObj.txCount = txCount; + + if(((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == SERCOM_SPIM_INTFLAG_TXC_Msk) && (isLastByteTransferInProgress == true)) + { + if(rxCount == sercom0SPIObj.rxSize) + { + sercom0SPIObj.transferIsBusy = false; + + /* Disable the Data Register empty and Receive Complete Interrupt flags */ + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)(SERCOM_SPIM_INTENCLR_DRE_Msk | SERCOM_SPIM_INTENCLR_RXC_Msk | SERCOM_SPIM_INTENSET_TXC_Msk); + + isLastByteTransferInProgress = false; + + if(sercom0SPIObj.callback != NULL) + { + sercom0SPIObj.callback(context); + } + } + } + + if(isLastByteTransferInProgress == true) + { + /* For the last byte transfer, the DRE interrupt is already disabled. + * Enable TXC interrupt to ensure no data is present in the shift + * register before application callback is called. + */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_TXC_Msk; + } + } +} diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h new file mode 100644 index 00000000..ac5d988c --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h @@ -0,0 +1,624 @@ +/******************************************************************************* + SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE (SERCOM0_SPI ) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_spi_master.h + + Summary + SERCOM0_SPI Master PLIB Header File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM0_SPI_MASTER_H // Guards against multiple inclusion +#define PLIB_SERCOM0_SPI_MASTER_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_sercom_spi_master_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_Initialize (void); + + Summary: + Initializes instance SERCOM0 operating in SPI mode. + + Description: + This function initializes instance SERCOM0 operating in SPI mode. + This function should be called before any other library function. The SERCOM + module will be configured as per the MHC settings. + + Precondition: + MCC GUI should be configured with the right values. The Generic Clock + configuration and the SERCOM Peripheral Clock channel should have been + configured in the clock manager GUI.The function will itself enable the + required peripheral clock channel and main clock. + + Parameters: + None. + + Returns: + None. + + Example: + + SERCOM0_SPI_Initialize(); + + + Remarks: + This function must be called once before any other SPI function is called. +*/ + +void SERCOM0_SPI_Initialize (void); + + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, + uint32_t spiSourceClock); + + Summary: + Configure SERCOM SPI operational parameters at run time. + + Description: + This function allows the application to change the SERCOM SPI operational + parameter at run time. The application can thus override the MHC defined + configuration for these parameters. The parameter are specified via the + SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter + should be initialized to the desired value. + + The application may feel need to call this function in situation where + multiple SPI slaves, each with different operation paramertes, are connected + to one SPI master. This function can thus be used to setup the SPI Master to + meet the communication needs of the slave. + + Calling this function will affect any ongoing communication. The application + must thus ensure that there is no on-going communication on the SPI before + calling this function. + + Precondition: + SERCOM SERCOM0 SPI must first be initialized using SERCOM0_SPI_Initialize(). + + Parameters : + setup - pointer to the data structure of type SPI_TRANSFER_SETUP containing + the operation parameters. Each operation parameter must be specified even if + the parameter does not need to change. + + spiSourceClock - Current value of GCLK frequency feeding the SERCOM0 core. + + Returns: + true - setup was successful. + + false - if spiSourceClock and spi clock frequencies are such that resultant + baud value is out of the possible range. + + Example: Assuming 20 MHz as peripheral Master clock frequency + + SPI_TRANSFER_SETUP setup; + setup.clockFrequency = 1000000; + setup.clockPhase = SPI_CLOCK_PHASE_TRAILING_EDGE; + setup.clockPolarity = SPI_CLOCK_POLARITY_IDLE_LOW; + setup.dataBits = SPI_DATA_BITS_8; + + if (SERCOM0_SPI_TransferSetup (&setup, 20000000) == false) + { + this means setup could not be done, debug the reason. + } + + + + Remarks: + The application would need to call this function only if the operational + parameter need to be different than the ones configured in MHC. +*/ + +bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock); + + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize + void* pReceiveData, size_t rxSize); + + Summary: + Write and Read data on SERCOM SERCOM0 SPI peripheral. + + Description: + This function transmits "txSize" number of bytes and receives "rxSize" + number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is + transmitted and received data is saved in the location pointed by + pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" + data units towards completion. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit and receive buffer are ownerd by the library until the data + transfer is complete and should not be modified by the application till the + transfer is complete. Only one transfer is allowed at any time. The + Application can use a callback function or a polling function to check for + completion of the transfer. If a callback is required, this should be + registered prior to calling the SERCOM0_SPI_WriteRead() function. The + application can use the SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. If the + peripheral instance has been configured for Interrupt mode and transfer + completion status needs to be communicated back to application via callback, + a callback should have been registered using SERCOM0_SPI_CallbackRegister() + function. + + Parameters: + pTransmitData - Pointer to the data which has to be transmitted. In a case + where only data reception is required, this pointer can be set to NULL. If + the module is configured for 9 bit data length, the data should be right + aligned in a 16 bit memory location. The size of this buffer should be + txSize. + + txSize - Number of bytes to be transmitted. For 9 but data length, a count + of 1 counts 2 bytes. This value can be different from rxSize. + + pReceiveData - Pointer to the location where the received data has to be + stored. It is user's responsibility to ensure that this location has + sufficient memory to store rxSize amount of data. In a case where only data + transmission is required, this pointer can be set to NULL. If the module is + configured for 9 bit data length, received data will be right aligned and + will be stored in a 16 bit memory location. + + rxSize - Number of bytes to be received. This value can be different from + txSize. For 9 bit data length, a size count of 1 indicates 2 bytes required + to store 9 bits of data. + + Returns: + true - If configured for Non-interrupt mode, the function has recevied and + transmitted the requested number of bytes. If configured for Interrupt mode, + the request was accepted successfully and will be processed in the + interrupt. + + false - If both pTransmitData and pReceiveData are NULL, or if both txSize + and rxSize are 0 or if txSize is non-zero but the pTransmitData is set to + NULL or rxSize is non-zero but pReceiveData is NULL. In Interrupt mode, the + function returns false if there is an on-going data transfer at the time of + calling the function. + + Example: + + + The following code snippet shows an example using the + SERCOM0_SPI_WriteRead() function in interrupt mode operation using the + callback function. + + uint8_t txBuffer[4]; + uint8_t rxBuffer[10]; + size_t txSize = 4; + size_t rxSize = 10; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + The following code snippet shows non-interrupt or blocking mode + operation. + + uint8_t txBuffer[4]; + uint8_t rxBuffer[10]; + size_t txSize = 4; + size_t rxSize = 10; + + SERCOM0_SPI_Initialize(); + + This function call will block. + SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize); + + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); + + Summary: + Writes data to SERCOM SERCOM0 SPI peripheral. + + Description: + This function writes "txSize" number of bytes on SERCOM SERCOM0 SPI module. Data + pointed by pTransmitData is transmitted. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit buffer is ownerd by the library until the data transfer is + complete and should not be modified by the application till the transfer is + complete. Only one transfer is allowed at any time. The application can use + a callback function or a polling function to check for completion of the + transfer. If a callback is required, this should be registered prior to + calling the SERCOM0_SPI_WriteRead() function. The application can use the + SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the + peripheral instance has been configured in Interrupt mode and + transfer completion status needs to be communicated back to application via + callback. + + Parameters: + pTransmitData - Pointer to the buffer containing the data which has to be + transmitted. For 9 bit mode, data should be right aligned in the 16 bit + memory location. In "Interrupt Mode", this buffer should not be modified + after calling the function and before the callback function has been called + or the SERCOM0_SPI_IsBusy() function returns false. + + txSize - Number of bytes to be transmitted. For 9 bit mode, 2 bytes make up + a count of 1. + + Returns: + true - If configured for Non-interrupt mode, the function has transmitted + the requested number of bytes. If configured for Interrupt mode, the request + was accepted successfully and will be processed in the interrupt. + + false - If pTransmitData is NULL. In Interrupt mode, the function will + additionally return false if there is an on-going data transfer at the time + of calling the function. + + Example: + + uint8_t txBuffer[4]; + size_t txSize = 4; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_Write(&txBuffer, txSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + + + Remarks: + None. + +*/ + +bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); + + Summary: + Reads data on the SERCOM SERCOM0 SPI peripheral. + + Description: + This function reads "rxSize" number of bytes on SERCOM SERCOM0 SPI module. The + received data is stored in the buffer pointed by pReceiveData. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + receiving "rxSize" number of bytes. This indicates that the operation has + been completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + receive buffer is ownerd by the library until the data transfer is + complete and should not be modified by the application till the transfer is + complete. Only one transfer is allowed at any time. The application can use + a callback function or a polling function to check for completion of the + transfer. If a callback is required, this should be registered prior to + calling the SERCOM0_SPI_WriteRead() function. The application can use the + SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the + peripheral instance has been configured in Interrupt mode and + transfer completion status needs to be communicated back to application via + callback. + + Parameters: + pReceiveData - Pointer to the buffer where the received data will be stored. + For 9 bit mode, data should be right aligned in the 16 bit memory location. + In "Interrupt Mode", this buffer should not be modified after calling the + function and before the callback function has been called or the + SERCOM0_SPI_IsBusy() function returns false. + + rxSize - Number of bytes to be received. For 9 bit mode, 2 bytes make up a + count of 1. + + Returns: + true - If configured for Non-interrupt mode, the function has received the + requested number of bytes. If configured for Interrupt mode, the request was + accepted successfully and will be processed in the interrupt. + + false - If pReceiveData is NULL. In Interrupt mode, the function will + additionally return false if there is an on-going data transfer at the time + of calling the function. + + Example: + + uint8_t rxBuffer[10]; + size_t rxSize = 10; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_Read(&rxBuffer, rxSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, + uintptr_t context); + + Summary: + Allows application to register callback with PLIB. + + Description: + This function allows application to register an event handling function + for the PLIB to call back when requested data exchange operation has + completed or any error has occurred. + The callback should be registered before the client performs exchange + operation. + At any point if application wants to stop the callback, it can use this + function with "callBack" value as NULL. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Parameters: + callBack - Pointer to the event handler function implemented by the + user . + + context - The value of parameter will be passed back to the application + unchanged, when the callBack function is called. It can + be used to identify any application specific data object that + identifies the instance of the client module (for example, + it may be a pointer to the client module's state structure). + + Returns: + None. + + Example: + + uint8_t txBuffer[10]; + uint8_t rxBuffer[10]; + size_t txSize = 10; + size_t rxSize = 10; + + SERCOM0_SPI_Initialize(); + + SERCOM0_SPI_CallbackRegister(&APP_SPICallBack, (uintptr_t)NULL); + + if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize )) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + void APP_SPICallBack(uintptr_t contextHandle) + { + Exchange was completed without error, do something else. + } + + + Remarks: + If the client does not want to be notified when the queued operation + has completed, it does not need to register a callback. +*/ + +void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsBusy (void); + + Summary: + Returns transfer status of SERCOM SERCOM0SPI. + + Description: + This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The + application can use the function to check if SERCOM SERCOM0SPI module is busy + before calling any of the data transfer functions. The library does not + allow a data transfer operation if another transfer operation is already in + progress. This function returns true when the SPI PLIB software state machine is idle and + all the bytes are transmitted out on the bus (shift register is empty). + + This function can be used as an alternative to the callback function when + the library is operating interrupt mode. The allow the application to + implement a synchronous interface to the library. + + Precondition: + The SERCOM0_SPI_Initialize() should have been called once. The module should + have been configured for interrupt mode operation in MHC. + + Parameters: + None. + + Returns: + true - Transfer is still in progress + false - Transfer is completed or no transfer is currently in progress. + + Example: + + The following code example demonstrates the use of the + SERCOM0_SPI_IsBusy() function. This example shows a blocking while + loop. The function can also be called periodically. + + uint8_t dataBuffer[20]; + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_Write(dataBuffer, 20); + + while (SERCOM0_SPI_IsBusy() == true) + { + Wait here till the transfer is done. + } + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_IsBusy (void); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsTransmitterBusy (void); + + Summary: + Returns hardware transfer status of the SPI transmit shift register + + Description: + This function returns the hardware status of the transmit shift register. + The status is returned true after all the bytes have been shifted out on the + SPI bus. This function should be used when using DMA with SPI PLIB to make + sure that all the bytes have been transmitted out on the bus. For SPI + transfers without DMA, the SERCOM0_SPI_IsBusy() API must be used. + + Precondition: + The SERCOM0_SPI_Initialize() should have been called once. + + Parameters: + None. + + Returns: + true - Data is being shifted out on the SPI bus + false - All the data bytes have been shifted out on the SPI bus + + Example: + + + + + Remarks: + None. +*/ +bool SERCOM0_SPI_IsTransmitterBusy(void); + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_SERCOM0_SPI_MASTER_H */ \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h new file mode 100644 index 00000000..fcdc9dc8 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h @@ -0,0 +1,296 @@ +/******************************************************************************* + SERCOM_SPI(SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom_spi_master_common.h + + Summary + SERCOM_SPI PLIB Master Local Header File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_SPI_MASTER_COMMON_H // Guards against multiple inclusion +#define PLIB_SERCOM_SPI_MASTER_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI Clock Phase + + Summary: + Identifies SPI Clock Phase Options + + Description: + This enumeration identifies possible SPI Clock Phase Options. + + Remarks: + None. +*/ + +typedef enum +{ + SPI_CLOCK_PHASE_LEADING_EDGE = SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE, + SPI_CLOCK_PHASE_TRAILING_EDGE = SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE, + + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_CLOCK_PHASE_INVALID = 0xFFFFFFFFU + +} SPI_CLOCK_PHASE; + +// ***************************************************************************** +/* SPI Clock Polarity + + Summary: + Identifies SPI Clock Polarity Options + + Description: + This enumeration identifies possible SPI Clock Polarity Options. + + Remarks: + None. +*/ + +typedef enum +{ + SPI_CLOCK_POLARITY_IDLE_LOW = SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW, + SPI_CLOCK_POLARITY_IDLE_HIGH = SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH, + + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_CLOCK_POLARITY_INVALID = 0xFFFFFFFFU + +} SPI_CLOCK_POLARITY; + +// ***************************************************************************** +/* SPI Data Bits + + Summary: + Identifies SPI bits per transfer + + Description: + This enumeration identifies number of bits per SPI transfer. + + Remarks: + For 9 bit mode, data should be right aligned in the 16 bit + memory location. +*/ + +typedef enum +{ + SPI_DATA_BITS_8 = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT, + SPI_DATA_BITS_9 = SERCOM_SPIM_CTRLB_CHSIZE_9_BIT, + + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_DATA_BITS_INVALID = 0xFFFFFFFFU + +} SPI_DATA_BITS; + +// ***************************************************************************** +/* SPI Transfer Setup Parameters + + Summary: + Identifies the setup parameters which can be changed dynamically. + + Description + This structure identifies the possible setup parameters for SPI + which can be changed dynamically if needed. + + Remarks: + None. +*/ + +typedef struct +{ + /* Baud Rate or clock frequency */ + uint32_t clockFrequency; + + /* Clock Phase */ + SPI_CLOCK_PHASE clockPhase; + + /* Clock Polarity */ + SPI_CLOCK_POLARITY clockPolarity; + + /* Number of bits per transfer */ + SPI_DATA_BITS dataBits; + +} SPI_TRANSFER_SETUP; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI CallBack Function Pointer + + Summary: + Pointer to a SPI Call back function. + + Description: + This data type defines the required function signature for the + SPI event handling callback function. Application must register + a pointer to an event handling function whose function signature (parameter + and return value types) match the types specified by this function pointer + in order to receive event calls back from the PLIB. + + The parameters and return values are described here and a partial example + implementation is provided. + + Parameters: + context - Value identifying the context of the application that + registered the event handling function + + Returns: + None. + + Example: + + + SPI1_CallbackRegister(&APP_SPICallBack, NULL); + void APP_SPICallBack(uintptr_t contextHandle) + { + if( SPI_ERROR_NONE == SPI1_ErrorGet()) + { + Exchange was completed without error, do something else now. + } + } + + + Remarks: + The context parameter contains the a handle to the client context, + provided at the time the event handling function was registered using the + SPIx_CallbackRegister function. This context handle value is + passed back to the client as the "context" parameter. It can be any value + (such as a pointer to the client's data) necessary to identify the client + context or instance of the client that made the data exchange + request. + + The event handler function executes in the PLIB's interrupt context. It is + recommended of the application to not perform process intensive or blocking + operations with in this function. +*/ + +typedef void (*SERCOM_SPI_CALLBACK)(uintptr_t context); + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local: **** Local SPI Object**** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI Object + + Summary: + Defines the data type for the data structures used for peripheral + operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + /* Pointer to the transmitter buffer */ + void * txBuffer; + + /* Pointer to the received buffer */ + void * rxBuffer; + + size_t txSize; + + size_t rxSize; + + size_t dummySize; + + /* Size of the receive processed exchange size */ + size_t rxCount; + + /* Size of the transmit processed exchange size */ + size_t txCount; + + /* Exchange busy status of the SPI */ + bool transferIsBusy; + + /* SPI Event handler */ + SERCOM_SPI_CALLBACK callback; + + /* Context */ + uintptr_t context; + + uint32_t status; + +} SPI_OBJECT; + +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif + +#endif //PLIB_SERCOM_SPI_MASTER_COMMON_H \ No newline at end of file diff --git a/bms/bms/bms_config/src/ic_bms/bms_afe_driver.c b/bms/bms/bms_config/src/ic_bms/bms_afe_driver.c new file mode 100644 index 00000000..b98d1d65 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/bms_afe_driver.c @@ -0,0 +1,76 @@ +#include +#include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" +#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" +#include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" +#include "definitions.h" + + + + + +#define BQ_CS_GROUP (0U) +#define BQ_CS_MASK (1UL << 18) + +static inline void BQ_CS_Low(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; } +static inline void BQ_CS_High(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; } + + +//SPI + set CS high +void BQ76942_Init(void) +{ + // init SPI + SERCOM0_SPI_Initialize(); + + // configure CS pin as output and set HIGH (inactive) + PORT_REGS->GROUP[BQ_CS_GROUP].PORT_DIRSET = BQ_CS_MASK; + PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; +} + +bool Spi_2B(uint8_t tx0, uint8_t tx1, uint8_t *rx0, uint8_t *rx1) +{ + uint8_t tx[2] = { tx0, tx1 }; + uint8_t rx[2] = { 0, 0 }; + + + //wait while prev transfer is ongoing + + if (SERCOM0_SPI_IsBusy()) + return false; + + BQ_CS_Low(); + bool ok = SERCOM0_SPI_WriteRead(tx, 2U, rx, 2U); + BQ_CS_High(); + + if (!ok) + return false; + + if (rx0) *rx0 = rx[0]; + if (rx1) *rx1 = rx[1]; + + return true; +} + +bool WriteReg(uint8_t regAddr, uint8_t value) +{ + /* First byte: MSB=1 to indicate WRITE, lower 7 bits = register address */ + uint8_t tx[2]; + tx[0] = (uint8_t)(0x80 | (regAddr & 0x7F)); /* W flag + address */ + tx[1] = value; + + /* (optional) ensure no active transfer */ + if (SERCOM0_SPI_IsBusy()) + return false; + + /* CS low -> transfer -> CS high */ + PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; + bool ok = SERCOM0_SPI_Write(tx, 2U); + PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; + + return ok; +} + + + + + + diff --git a/bms/bms/bms_config/src/ic_bms/bms_afe_driver.h b/bms/bms/bms_config/src/ic_bms/bms_afe_driver.h new file mode 100644 index 00000000..fc6206c5 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/bms_afe_driver.h @@ -0,0 +1,8 @@ +#ifndef BQ76942_H +#define BQ76942_H + +/* Minimal driver: only SPI+CS bring-up */ +void BQ76942_Init(void); +bool S(void); + +#endif /* BQ76942_H */ diff --git a/bms/bms/bms_config/src/safety/current.c b/bms/bms/bms_config/src/safety/current.c index 66c50ad8..5ce0f86b 100644 --- a/bms/bms/bms_config/src/safety/current.c +++ b/bms/bms/bms_config/src/safety/current.c @@ -7,6 +7,7 @@ static int current_flags = 0; + uint16_t adc_read_channel(uint8_t channel) { // 1. Select ADC input (MUXPOS) From 53e829fabe37cb9578cf9405c0e75923073b7275 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 23 Oct 2025 18:03:04 +0200 Subject: [PATCH 05/30] feat: add BQ76942 SPI driver implementation --- bms/bms/bms_config/src/ic_bms/BQ769x2Header.h | 409 ++++++++ .../bms_config/src/ic_bms/bms_afe_driver.h | 8 - .../ic_bms/{bms_afe_driver.c => bms_spi.c} | 0 bms/bms/bms_config/src/ic_bms/bms_spi.h | 42 + .../bms_config/src/ic_bms/main_STM32_SPI.c | 955 ++++++++++++++++++ 5 files changed, 1406 insertions(+), 8 deletions(-) create mode 100644 bms/bms/bms_config/src/ic_bms/BQ769x2Header.h delete mode 100644 bms/bms/bms_config/src/ic_bms/bms_afe_driver.h rename bms/bms/bms_config/src/ic_bms/{bms_afe_driver.c => bms_spi.c} (100%) create mode 100644 bms/bms/bms_config/src/ic_bms/bms_spi.h create mode 100644 bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c diff --git a/bms/bms/bms_config/src/ic_bms/BQ769x2Header.h b/bms/bms/bms_config/src/ic_bms/BQ769x2Header.h new file mode 100644 index 00000000..fe82dbf3 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/BQ769x2Header.h @@ -0,0 +1,409 @@ +//BQ769x2 General Program Header File + +//Data Memory registers Name in TRM +#define Cell1Gain 0x9180 //Calibration:Voltage:Cell 1 Gain +#define Cell2Gain 0x9182 //Calibration:Voltage:Cell 2 Gain +#define Cell3Gain 0x9184 //Calibration:Voltage:Cell 3 Gain +#define Cell4Gain 0x9186 //Calibration:Voltage:Cell 4 Gain +#define Cell5Gain 0x9188 //Calibration:Voltage:Cell 5 Gain +#define Cell6Gain 0x918A //Calibration:Voltage:Cell 6 Gain +#define Cell7Gain 0x918C //Calibration:Voltage:Cell 7 Gain +#define Cell8Gain 0x918E //Calibration:Voltage:Cell 8 Gain +#define Cell9Gain 0x9190 //Calibration:Voltage:Cell 9 Gain +#define Cell10Gain 0x9192 //Calibration:Voltage:Cell 10 Gain +#define Cell11Gain 0x9194 //Calibration:Voltage:Cell 11 Gain +#define Cell12Gain 0x9196 //Calibration:Voltage:Cell 12 Gain +#define Cell13Gain 0x9198 //Calibration:Voltage:Cell 13 Gain +#define Cell14Gain 0x919A //Calibration:Voltage:Cell 14 Gain +#define Cell15Gain 0x919C //Calibration:Voltage:Cell 15 Gain +#define Cell16Gain 0x919E //Calibration:Voltage:Cell 16 Gain +#define PackGain 0x91A0 //Calibration:Voltage:Pack Gain +#define TOSGain 0x91A2 //Calibration:Voltage:TOS Gain +#define LDGain 0x91A4 //Calibration:Voltage:LD Gain +#define ADCGain 0x91A6 //Calibration:Voltage:ADC Gain +#define CCGain 0x91A8 //Calibration:Current:CC Gain +#define CapacityGain 0x91AC //Calibration:Current:Capacity Gain +#define VcellOffset 0x91B0 //Calibration:Vcell Offset:Vcell Offset +#define VdivOffset 0x91B2 //Calibration:V Divider Offset:Vdiv Offset +#define CoulombCounterOffsetSamples 0x91C6 //Calibration:Current Offset:Coulomb Counter Offset Samples +#define BoardOffset 0x91C8 //Calibration:Current Offset:Board Offset +#define InternalTempOffset 0x91CA //Calibration:Temperature:Internal Temp Offset +#define CFETOFFTempOffset 0x91CB //Calibration:Temperature:CFETOFF Temp Offset +#define DFETOFFTempOffset 0x91CC //Calibration:Temperature:DFETOFF Temp Offset +#define ALERTTempOffset 0x91CD //Calibration:Temperature:ALERT Temp Offset +#define TS1TempOffset 0x91CE //Calibration:Temperature:TS1 Temp Offset +#define TS2TempOffset 0x91CF //Calibration:Temperature:TS2 Temp Offset +#define TS3TempOffset 0x91D0 //Calibration:Temperature:TS3 Temp Offset +#define HDQTempOffset 0x91D1 //Calibration:Temperature:HDQ Temp Offset +#define DCHGTempOffset 0x91D2 //Calibration:Temperature:DCHG Temp Offset +#define DDSGTempOffset 0x91D3 //Calibration:Temperature:DDSG Temp Offset +#define IntGain 0x91E2 //Calibration:Internal Temp Model:Int Gain +#define Intbaseoffset 0x91E4 //Calibration:Internal Temp Model:Int base offset +#define IntMaximumAD 0x91E6 //Calibration:Internal Temp Model:Int Maximum AD +#define IntMaximumTemp 0x91E8 //Calibration:Internal Temp Model:Int Maximum Temp +#define T18kCoeffa1 0x91EA //Calibration:18K Temperature Model:Coeff a1 +#define T18kCoeffa2 0x91EC //Calibration:18K Temperature Model:Coeff a2 +#define T18kCoeffa3 0x91EE //Calibration:18K Temperature Model:Coeff a3 +#define T18kCoeffa4 0x91F0 //Calibration:18K Temperature Model:Coeff a4 +#define T18kCoeffa5 0x91F2 //Calibration:18K Temperature Model:Coeff a5 +#define T18kCoeffb1 0x91F4 //Calibration:18K Temperature Model:Coeff b1 +#define T18kCoeffb2 0x91F6 //Calibration:18K Temperature Model:Coeff b2 +#define T18kCoeffb3 0x91F8 //Calibration:18K Temperature Model:Coeff b3 +#define T18kCoeffb4 0x91FA //Calibration:18K Temperature Model:Coeff b4 +#define T18kAdc0 0x91FE //Calibration:18K Temperature Model:Adc0 +#define T180kCoeffa1 0x9200 //Calibration:180K Temperature Model:Coeff a1 +#define T180kCoeffa2 0x9202 //Calibration:180K Temperature Model:Coeff a2 +#define T180kCoeffa3 0x9204 //Calibration:180K Temperature Model:Coeff a3 +#define T180kCoeffa4 0x9206 //Calibration:180K Temperature Model:Coeff a4 +#define T180kCoeffa5 0x9208 //Calibration:180K Temperature Model:Coeff a5 +#define T180kCoeffb1 0x920A //Calibration:180K Temperature Model:Coeff b1 +#define T180kCoeffb2 0x920C //Calibration:180K Temperature Model:Coeff b2 +#define T180kCoeffb3 0x920E //Calibration:180K Temperature Model:Coeff b3 +#define T180kCoeffb4 0x9210 //Calibration:180K Temperature Model:Coeff b4 +#define T180kAdc0 0x9214 //Calibration:180K Temperature Model:Adc0 +#define CustomCoeffa1 0x9216 //Calibration:Custom Temperature Model:Coeff a1 +#define CustomCoeffa2 0x9218 //Calibration:Custom Temperature Model:Coeff a2 +#define CustomCoeffa3 0x921A //Calibration:Custom Temperature Model:Coeff a3 +#define CustomCoeffa4 0x921C //Calibration:Custom Temperature Model:Coeff a4 +#define CustomCoeffa5 0x921E //Calibration:Custom Temperature Model:Coeff a5 +#define CustomCoeffb1 0x9220 //Calibration:Custom Temperature Model:Coeff b1 +#define CustomCoeffb2 0x9222 //Calibration:Custom Temperature Model:Coeff b2 +#define CustomCoeffb3 0x9224 //Calibration:Custom Temperature Model:Coeff b3 +#define CustomCoeffb4 0x9226 //Calibration:Custom Temperature Model:Coeff b4 +#define CustomRc0 0x9228 //Calibration:Custom Temperature Model:Rc0 +#define CustomAdc0 0x922A //Calibration:Custom Temperature Model:Adc0 +#define CoulombCounterDeadband 0x922D //Calibration:Current Deadband:Coulomb Counter Deadband +#define CUVThresholdOverride 0x91D4 //Calibration:CUV:CUV Threshold Override +#define COVThresholdOverride 0x91D6 //Calibration:COV:COV Threshold Override +#define MinBlowFuseVoltage 0x9231 //Settings:Fuse:Min Blow Fuse Voltage +#define FuseBlowTimeout 0x9233 //Settings:Fuse:Fuse Blow Timeout +#define PowerConfig 0x9234 //Settings:Configuration:Power Config +#define REG12Config 0x9236 //Settings:Configuration:REG12 Config +#define REG0Config 0x9237 //Settings:Configuration:REG0 Config +#define HWDRegulatorOptions 0x9238 //Settings:Configuration:HWD Regulator Options +#define CommType 0x9239 //Settings:Configuration:Comm Type +#define I2CAddress 0x923A //Settings:Configuration:I2C Address +#define SPIConfiguration 0x923C //Settings:Configuration:SPI Configuration +#define CommIdleTime 0x923D //Settings:Configuration:Comm Idle Time +#define CFETOFFPinConfig 0x92FA //Settings:Configuration:CFETOFF Pin Config +#define DFETOFFPinConfig 0x92FB //Settings:Configuration:DFETOFF Pin Config +#define ALERTPinConfig 0x92FC //Settings:Configuration:ALERT Pin Config +#define TS1Config 0x92FD //Settings:Configuration:TS1 Config +#define TS2Config 0x92FE //Settings:Configuration:TS2 Config +#define TS3Config 0x92FF //Settings:Configuration:TS3 Config +#define HDQPinConfig 0x9300 //Settings:Configuration:HDQ Pin Config +#define DCHGPinConfig 0x9301 //Settings:Configuration:DCHG Pin Config +#define DDSGPinConfig 0x9302 //Settings:Configuration:DDSG Pin Config +#define DAConfiguration 0x9303 //Settings:Configuration:DA Configuration +#define VCellMode 0x9304 //Settings:Configuration:Vcell Mode +#define CC3Samples 0x9307 //Settings:Configuration:CC3 Samples +#define ProtectionConfiguration 0x925F //Settings:Protection:Protection Configuration +#define EnabledProtectionsA 0x9261 //Settings:Protection:Enabled Protections A +#define EnabledProtectionsB 0x9262 //Settings:Protection:Enabled Protections B +#define EnabledProtectionsC 0x9263 //Settings:Protection:Enabled Protections C +#define CHGFETProtectionsA 0x9265 //Settings:Protection:CHG FET Protections A +#define CHGFETProtectionsB 0x9266 //Settings:Protection:CHG FET Protections B +#define CHGFETProtectionsC 0x9267 //Settings:Protection:CHG FET Protections C +#define DSGFETProtectionsA 0x9269 //Settings:Protection:DSG FET Protections A +#define DSGFETProtectionsB 0x926A //Settings:Protection:DSG FET Protections B +#define DSGFETProtectionsC 0x926B //Settings:Protection:DSG FET Protections C +#define BodyDiodeThreshold 0x9273 //Settings:Protection:Body Diode Threshold +#define DefaultAlarmMask 0x926D //Settings:Alarm:Default Alarm Mask +#define SFAlertMaskA 0x926F //Settings:Alarm:SF Alert Mask A +#define SFAlertMaskB 0x9270 //Settings:Alarm:SF Alert Mask B +#define SFAlertMaskC 0x9271 //Settings:Alarm:SF Alert Mask C +#define PFAlertMaskA 0x92C4 //Settings:Alarm:PF Alert Mask A +#define PFAlertMaskB 0x92C5 //Settings:Alarm:PF Alert Mask B +#define PFAlertMaskC 0x92C6 //Settings:Alarm:PF Alert Mask C +#define PFAlertMaskD 0x92C7 //Settings:Alarm:PF Alert Mask D +#define EnabledPFA 0x92C0 //Settings:Permanent Failure:Enabled PF A +#define EnabledPFB 0x92C1 //Settings:Permanent Failure:Enabled PF B +#define EnabledPFC 0x92C2 //Settings:Permanent Failure:Enabled PF C +#define EnabledPFD 0x92C3 //Settings:Permanent Failure:Enabled PF D +#define FETOptions 0x9308 //Settings:FET:FET Options +#define ChgPumpControl 0x9309 //Settings:FET:Chg Pump Control +#define PrechargeStartVoltage 0x930A //Settings:FET:Precharge Start Voltage +#define PrechargeStopVoltage 0x930C //Settings:FET:Precharge Stop Voltage +#define PredischargeTimeout 0x930E //Settings:FET:Predischarge Timeout +#define PredischargeStopDelta 0x930F //Settings:FET:Predischarge Stop Delta +#define DsgCurrentThreshold 0x9310 //Settings:Current Thresholds:Dsg Current Threshold +#define ChgCurrentThreshold 0x9312 //Settings:Current Thresholds:Chg Current Threshold +#define CheckTime 0x9314 //Settings:Cell Open-Wire:Check Time +#define Cell1Interconnect 0x9315 //Settings:Interconnect Resistances:Cell 1 Interconnect +#define Cell2Interconnect 0x9317 //Settings:Interconnect Resistances:Cell 2 Interconnect +#define Cell3Interconnect 0x9319 //Settings:Interconnect Resistances:Cell 3 Interconnect +#define Cell4Interconnect 0x931B //Settings:Interconnect Resistances:Cell 4 Interconnect +#define Cell5Interconnect 0x931D //Settings:Interconnect Resistances:Cell 5 Interconnect +#define Cell6Interconnect 0x931F //Settings:Interconnect Resistances:Cell 6 Interconnect +#define Cell7Interconnect 0x9321 //Settings:Interconnect Resistances:Cell 7 Interconnect +#define Cell8Interconnect 0x9323 //Settings:Interconnect Resistances:Cell 8 Interconnect +#define Cell9Interconnect 0x9325 //Settings:Interconnect Resistances:Cell 9 Interconnect +#define Cell10Interconnect 0x9327 //Settings:Interconnect Resistances:Cell 10 Interconnect +#define Cell11Interconnect 0x9329 //Settings:Interconnect Resistances:Cell 11 Interconnect +#define Cell12Interconnect 0x932B //Settings:Interconnect Resistances:Cell 12 Interconnect +#define Cell13Interconnect 0x932D //Settings:Interconnect Resistances:Cell 13 Interconnect +#define Cell14Interconnect 0x932F //Settings:Interconnect Resistances:Cell 14 Interconnect +#define Cell15Interconnect 0x9331 //Settings:Interconnect Resistances:Cell 15 Interconnect +#define Cell16Interconnect 0x9333 //Settings:Interconnect Resistances:Cell 16 Interconnect +#define MfgStatusInit 0x9343 //Settings:Manufacturing:Mfg Status Init +#define BalancingConfiguration 0x9335 //Settings:Cell Balancing Config:Balancing Configuration +#define MinCellTemp 0x9336 //Settings:Cell Balancing Config:Min Cell Temp +#define MaxCellTemp 0x9337 //Settings:Cell Balancing Config:Max Cell Temp +#define MaxInternalTemp 0x9338 //Settings:Cell Balancing Config:Max Internal Temp +#define CellBalanceInterval 0x9339 //Settings:Cell Balancing Config:Cell Balance Interval +#define CellBalanceMaxCells 0x933A //Settings:Cell Balancing Config:Cell Balance Max Cells +#define CellBalanceMinCellVCharge 0x933B //Settings:Cell Balancing Config:Cell Balance Min Cell V (Charge) +#define CellBalanceMinDeltaCharge 0x933D //Settings:Cell Balancing Config:Cell Balance Min Delta (Charge) +#define CellBalanceStopDeltaCharge 0x933E //Settings:Cell Balancing Config:Cell Balance Stop Delta (Charge) +#define CellBalanceMinCellVRelax 0x933F //Settings:Cell Balancing Config:Cell Balance Min Cell V (Relax) +#define CellBalanceMinDeltaRelax 0x9341 //Settings:Cell Balancing Config:Cell Balance Min Delta (Relax) +#define CellBalanceStopDeltaRelax 0x9342 //Settings:Cell Balancing Config:Cell Balance Stop Delta (Relax) +#define ShutdownCellVoltage 0x923F //Power:Shutdown:Shutdown Cell Voltage +#define ShutdownStackVoltage 0x9241 //Power:Shutdown:Shutdown Stack Voltage +#define LowVShutdownDelay 0x9243 //Power:Shutdown:Low V Shutdown Delay +#define ShutdownTemperature 0x9244 //Power:Shutdown:Shutdown Temperature +#define ShutdownTemperatureDelay 0x9245 //Power:Shutdown:Shutdown Temperature Delay +#define FETOffDelay 0x9252 //Power:Shutdown:FET Off Delay +#define ShutdownCommandDelay 0x9253 //Power:Shutdown:Shutdown Command Delay +#define AutoShutdownTime 0x9254 //Power:Shutdown:Auto Shutdown Time +#define RAMFailShutdownTime 0x9255 //Power:Shutdown:RAM Fail Shutdown Time +#define SleepCurrent 0x9248 //Power:Sleep:Sleep Current +#define VoltageTime 0x924A //Power:Sleep:Voltage Time +#define WakeComparatorCurrent 0x924B //Power:Sleep:Wake Comparator Current +#define SleepHysteresisTime 0x924D //Power:Sleep:Sleep Hysteresis Time +#define SleepChargerVoltageThreshold 0x924E //Power:Sleep:Sleep Charger Voltage Threshold +#define SleepChargerPACKTOSDelta 0x9250 //Power:Sleep:Sleep Charger PACK-TOS Delta +#define ConfigRAMSignature 0x91E0 //System Data:Integrity:Config RAM Signature +#define CUVThreshold 0x9275 //Protections:CUV:Threshold +#define CUVDelay 0x9276 //Protections:CUV:Delay +#define CUVRecoveryHysteresis 0x927B //Protections:CUV:Recovery Hysteresis +#define COVThreshold 0x9278 //Protections:COV:Threshold +#define COVDelay 0x9279 //Protections:COV:Delay +#define COVRecoveryHysteresis 0x927C //Protections:COV:Recovery Hysteresis +#define COVLLatchLimit 0x927D //Protections:COVL:Latch Limit +#define COVLCounterDecDelay 0x927E //Protections:COVL:Counter Dec Delay +#define COVLRecoveryTime 0x927F //Protections:COVL:Recovery Time +#define OCCThreshold 0x9280 //Protections:OCC:Threshold +#define OCCDelay 0x9281 //Protections:OCC:Delay +#define OCCRecoveryThreshold 0x9288 //Protections:OCC:Recovery Threshold +#define OCCPACKTOSDelta 0x92B0 //Protections:OCC:PACK-TOS Delta +#define OCD1Threshold 0x9282 //Protections:OCD1:Threshold +#define OCD1Delay 0x9283 //Protections:OCD1:Delay +#define OCD2Threshold 0x9284 //Protections:OCD2:Threshold +#define OCD2Delay 0x9285 //Protections:OCD2:Delay +#define SCDThreshold 0x9286 //Protections:SCD:Threshold +#define SCDDelay 0x9287 //Protections:SCD:Delay +#define SCDRecoveryTime 0x9294 //Protections:SCD:Recovery Time +#define OCD3Threshold 0x928A //Protections:OCD3:Threshold +#define OCD3Delay 0x928C //Protections:OCD3:Delay +#define OCDRecoveryThreshold 0x928D //Protections:OCD:Recovery Threshold +#define OCDLLatchLimit 0x928F //Protections:OCDL:Latch Limit +#define OCDLCounterDecDelay 0x9290 //Protections:OCDL:Counter Dec Delay +#define OCDLRecoveryTime 0x9291 //Protections:OCDL:Recovery Time +#define OCDLRecoveryThreshold 0x9292 //Protections:OCDL:Recovery Threshold +#define SCDLLatchLimit 0x9295 //Protections:SCDL:Latch Limit +#define SCDLCounterDecDelay 0x9296 //Protections:SCDL:Counter Dec Delay +#define SCDLRecoveryTime 0x9297 //Protections:SCDL:Recovery Time +#define SCDLRecoveryThreshold 0x9298 //Protections:SCDL:Recovery Threshold +#define OTCThreshold 0x929A //Protections:OTC:Threshold +#define OTCDelay 0x920B //Protections:OTC:Delay +#define OTCRecovery 0x929C //Protections:OTC:Recovery +#define OTDThreshold 0x929D //Protections:OTD:Threshold +#define OTDDelay 0x929E //Protections:OTD:Delay +#define OTDRecovery 0x929F //Protections:OTD:Recovery +#define OTFThreshold 0x92A0 //Protections:OTF:Threshold +#define OTFDelay 0x92A1 //Protections:OTF:Delay +#define OTFRecovery 0x92A2 //Protections:OTF:Recovery +#define OTINTThreshold 0x92A3 //Protections:OTINT:Threshold +#define OTINTDelay 0x92A4 //Protections:OTINT:Delay +#define OTINTRecovery 0x92A5 //Protections:OTINT:Recovery +#define UTCThreshold 0x92A6 //Protections:UTC:Threshold +#define UTCDelay 0x92A7 //Protections:UTC:Delay +#define UTCRecovery 0x92A8 //Protections:UTC:Recovery +#define UTDThreshold 0x92A9 //Protections:UTD:Threshold +#define UTDDelay 0x92AA //Protections:UTD:Delay +#define UTDRecovery 0x92AB //Protections:UTD:Recovery +#define UTINTThreshold 0x92AC //Protections:UTINT:Threshold +#define UTINTDelay 0x92AD //Protections:UTINT:Delay +#define UTINTRecovery 0x92AE //Protections:UTINT:Recovery +#define ProtectionsRecoveryTime 0x92AF //Protections:Recovery:Time +#define HWDDelay 0x92B2 //Protections:HWD:Delay +#define LoadDetectActiveTime 0x92B4 //Protections:Load Detect:Active Time +#define LoadDetectRetryDelay 0x92B5 //Protections:Load Detect:Retry Delay +#define LoadDetectTimeout 0x92B6 //Protections:Load Detect:Timeout +#define PTOChargeThreshold 0x92BA //Protections:PTO:Charge Threshold +#define PTODelay 0x92BC //Protections:PTO:Delay +#define PTOReset 0x92BE //Protections:PTO:Reset +#define CUDEPThreshold 0x92C8 //Permanent Fail:CUDEP:Threshold +#define CUDEPDelay 0x92CA //Permanent Fail:CUDEP:Delay +#define SUVThreshold 0x92CB //Permanent Fail:SUV:Threshold +#define SUVDelay 0x92CD //Permanent Fail:SUV:Delay +#define SOVThreshold 0x92CE //Permanent Fail:SOV:Threshold +#define SOVDelay 0x92D0 //Permanent Fail:SOV:Delay +#define TOSSThreshold 0x92D1 //Permanent Fail:TOS:Threshold +#define TOSSDelay 0x92D3 //Permanent Fail:TOS:Delay +#define SOCCThreshold 0x92D4 //Permanent Fail:SOCC:Threshold +#define SOCCDelay 0x92D6 //Permanent Fail:SOCC:Delay +#define SOCDThreshold 0x92D7 //Permanent Fail:SOCD:Threshold +#define SOCDDelay 0x92D9 //Permanent Fail:SOCD:Delay +#define SOTThreshold 0x92DA //Permanent Fail:SOT:Threshold +#define SOTDelay 0x92DB //Permanent Fail:SOT:Delay +#define SOTFThreshold 0x92DC //Permanent Fail:SOTF:Threshold +#define SOTFDelay 0x92DD //Permanent Fail:SOTF:Delay +#define VIMRCheckVoltage 0x92DE //Permanent Fail:VIMR:Check Voltage +#define VIMRMaxRelaxCurrent 0x92E0 //Permanent Fail:VIMR:Max Relax Current +#define VIMRThreshold 0x92E2 //Permanent Fail:VIMR:Threshold +#define VIMRDelay 0x92E4 //Permanent Fail:VIMR:Delay +#define VIMRRelaxMinDuration 0x92E5 //Permanent Fail:VIMR:Relax Min Duration +#define VIMACheckVoltage 0x92E7 //Permanent Fail:VIMA:Check Voltage +#define VIMAMinActiveCurrent 0x92E9 //Permanent Fail:VIMA:Min Active Current +#define VIMAThreshold 0x92EB //Permanent Fail:VIMA:Threshold +#define VIMADelay 0x92ED //Permanent Fail:VIMA:Delay +#define CFETFOFFThreshold 0x92EE //Permanent Fail:CFETF:OFF Threshold +#define CFETFOFFDelay 0x92F0 //Permanent Fail:CFETF:OFF Delay +#define DFETFOFFThreshold 0x92F1 //Permanent Fail:DFETF:OFF Threshold +#define DFETFOFFDelay 0x92F3 //Permanent Fail:DFETF:OFF Delay +#define VSSFFailThreshold 0x92F4 //Permanent Fail:VSSF:Fail Threshold +#define VSSFDelay 0x92F6 //Permanent Fail:VSSF:Delay +#define PF2LVLDelay 0x92F7 //Permanent Fail:2LVL:Delay +#define LFOFDelay 0x92F8 //Permanent Fail:LFOF:Delay +#define HWMXDelay 0x92F9 //Permanent Fail:HWMX:Delay +#define SecuritySettings 0x9256 //Security:Settings:Security Settings +#define UnsealKeyStep1 0x9257 //Security:Keys:Unseal Key Step 1 +#define UnsealKeyStep2 0x9259 //Security:Keys:Unseal Key Step 2 +#define FullAccessKeyStep1 0x925B //Security:Keys:Full Access Key Step 1 +#define FullAccessKeyStep2 0x925D //Security:Keys:Full Access Key Step 2 + +//Direct Commands +#define ControlStatus 0x00 +#define SafetyAlertA 0x02 +#define SafetyStatusA 0x03 +#define SafetyAlertB 0x04 +#define SafetyStatusB 0x05 +#define SafetyAlertC 0x06 +#define SafetyStatusC 0x07 +#define PFAlertA 0x0A +#define PFStatusA 0x0B +#define PFAlertB 0x0C +#define PFStatusB 0x0D +#define PFAlertC 0x0E +#define PFStatusC 0x0F +#define PFAlertD 0x10 +#define PFStatusD 0x11 +#define BatteryStatus 0x12 +#define Cell1Voltage 0x14 +#define Cell2Voltage 0x16 +#define Cell3Voltage 0x18 +#define Cell4Voltage 0x1A +#define Cell5Voltage 0x1C +#define Cell6Voltage 0x1E +#define Cell7Voltage 0x20 +#define Cell8Voltage 0x22 +#define Cell9Voltage 0x24 +#define Cell10Voltage 0x26 +#define Cell11Voltage 0x28 +#define Cell12Voltage 0x2A +#define Cell13Voltage 0x2C +#define Cell14Voltage 0x2E +#define Cell15Voltage 0x30 +#define Cell16Voltage 0x32 +#define StackVoltage 0x34 +#define PACKPinVoltage 0x36 +#define LDPinVoltage 0x38 +#define CC2Current 0x3A +#define AlarmStatus 0x62 +#define AlarmRawStatus 0x64 +#define AlarmEnable 0x66 +#define IntTemperature 0x68 +#define CFETOFFTemperature 0x6A +#define DFETOFFTemperature 0x6C +#define ALERTTemperature 0x6E +#define TS1Temperature 0x70 +#define TS2Temperature 0x72 +#define TS3Temperature 0x74 +#define HDQTemperature 0x76 +#define DCHGTemperature 0x78 +#define DDSGTemperature 0x7A +#define FETStatus 0x7F + +//Subcommands +#define DEVICE_NUMBER 0x0001 +#define FW_VERSION 0x0002 +#define HW_VERSION 0x0003 +#define IROM_SIG 0x0004 +#define STATIC_CFG_SIG 0x0005 +#define PREV_MACWRITE 0x0007 +#define DROM_SIG 0x0009 +#define SECURITY_KEYS 0x0035 +#define SAVED_PF_STATUS 0x0053 +#define MANUFACTURINGSTATUS 0x0057 +#define MANU_DATA 0x0070 +#define DASTATUS1 0x0071 +#define DASTATUS2 0x0072 +#define DASTATUS3 0x0073 +#define DASTATUS4 0x0074 +#define DASTATUS5 0x0075 +#define DASTATUS6 0x0076 +#define DASTATUS7 0x0077 +#define CUV_SNAPSHOT 0x0080 +#define COV_SNAPSHOT 0X0081 +#define CB_ACTIVE_CELLS 0x0083 +#define CB_SET_LVL 0x0084 +#define CBSTATUS1 0x0085 +#define CBSTATUS2 0x0086 +#define CBSTATUS3 0x0087 +#define FET_CONTROL 0x0097 +#define REG12_CONTROL 0x0098 +#define OTP_WR_CHECK 0x00A0 +#define OTP_WRITE 0x00A1 +#define READ_CAL1 0xF081 +#define CAL_CUV 0xF090 +#define CAL_COV 0xF091 + +// Command Only Subcommands +#define EXIT_DEEPSLEEP 0x000E +#define DEEPSLEEP 0x000F +#define SHUTDOWN 0x0010 +#define BQ769x2_RESET 0x0012 //"RESET" in documentation +#define PDSGTEST 0x001C +#define FUSE_TOGGLE 0x001D +#define PCHGTEST 0x001E +#define CHGTEST 0x001F +#define DSGTEST 0x0020 +#define FET_ENABLE 0x0022 +#define PF_ENABLE 0x0024 +#define PF_RESET 0x0029 +#define SEAL 0x0030 +#define RESET_PASSQ 0x0082 +#define PTO_RECOVER 0x008A +#define SET_CFGUPDATE 0x0090 +#define EXIT_CFGUPDATE 0x0092 +#define DSG_PDSG_OFF 0x0093 +#define CHG_PCHG_OFF 0x0094 +#define ALL_FETS_OFF 0x0095 +#define ALL_FETS_ON 0x0096 +#define SLEEP_ENABLE 0x0099 +#define SLEEP_DISABLE 0x009A +#define OCDL_RECOVER 0x009B +#define SCDL_RECOVER 0x009C +#define LOAD_DETECT_RESTART 0x009D +#define LOAD_DETECT_ON 0x009E +#define LOAD_DETECT_OFF 0x009F +#define CFETOFF_LO 0x2800 +#define DFETOFF_LO 0x2801 +#define ALERT_LO 0x2802 +#define HDQ_LO 0x2806 +#define DCHG_LO 0x2807 +#define DDSG_LO 0x2808 +#define CFETOFF_HI 0x2810 +#define DFETOFF_HI 0x2811 +#define ALERT_HI 0x2812 +#define HDQ_HI 0x2816 +#define DCHG_HI 0x2817 +#define DDSG_HI 0x2818 +#define PF_FORCE_A 0x2857 +#define PF_FORCE_B 0x29A3 +#define SWAP_COMM_MODE 0x29BC +#define SWAP_TO_I2C 0x29E7 +#define SWAP_TO_SPI 0x7C35 +#define SWAP_TO_HDQ 0x7C40 diff --git a/bms/bms/bms_config/src/ic_bms/bms_afe_driver.h b/bms/bms/bms_config/src/ic_bms/bms_afe_driver.h deleted file mode 100644 index fc6206c5..00000000 --- a/bms/bms/bms_config/src/ic_bms/bms_afe_driver.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef BQ76942_H -#define BQ76942_H - -/* Minimal driver: only SPI+CS bring-up */ -void BQ76942_Init(void); -bool S(void); - -#endif /* BQ76942_H */ diff --git a/bms/bms/bms_config/src/ic_bms/bms_afe_driver.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c similarity index 100% rename from bms/bms/bms_config/src/ic_bms/bms_afe_driver.c rename to bms/bms/bms_config/src/ic_bms/bms_spi.c diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h new file mode 100644 index 00000000..58ae4ddd --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -0,0 +1,42 @@ +#ifndef BQ76942_H +#define BQ76942_H + +#define BatteryStatus 0x12 + +#define Cell1Voltage 0x14 +#define Cell2Voltage 0x16 +#define Cell3Voltage 0x18 +#define Cell4Voltage 0x1A +#define Cell5Voltage 0x1C +#define Cell6Voltage 0x1E +/* +#define Cell7Voltage 0x20 +#define Cell8Voltage 0x22 +#define Cell9Voltage 0x24 +#define Cell10Voltage 0x26 +#define Cell11Voltage 0x28 +#define Cell12Voltage 0x2A +#define Cell13Voltage 0x2C +#define Cell14Voltage 0x2E +#define Cell15Voltage 0x30 +#define Cell16Voltage 0x32 + +*/ // 16 cell voltage readings avaliable + + +#define StackVoltage 0x34 + + +#define SWAP_COMM_MODE 0x29BC +#define SWAP_TO_SPI 0x7C35 +#define SWAP_TO_I2C 0x29E7 //maybe needed + +#define THERMISOR_TEMP 0x6A +#define INTERNAL_TEMP 0x68 + +/* Minimal driver: only SPI+CS bring-up */ +void BQ76942_Init(void); + + + +#endif /* BQ76942_H */ diff --git a/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c b/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c new file mode 100644 index 00000000..2c773123 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c @@ -0,0 +1,955 @@ +/* --COPYRIGHT--,BSD_EX + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*//* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + * (Non-USER sections generated from STM32CubeMX software) + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +// BQ76952EVM demo code for STM32 NUCLEO-F103RB + BQ76952EVM +// +// Connection description: The SCLK, MISO, MOSI, and CS pins are the only pin connections required between the +// NUCLEO board and the BQ76952EVM for this demo code. Also a ground connection should be made between the 2 boards. +// The ALERT, RST_SHUT, and DFETOFF pins are also configured on the MCU and can be used as shown. +// +// +// STM32 +// ----------------- +// | PB3 |---------- SCLK +// | | +// | PB4 |---------- MISO +// | | +// DFETOFF ---| PA8 PB5 |---------- MOSI +// | | +// RST_SHUT ---| PA9 PB6 |---------- CS +// | | +// ALERT ---| PA10 |--- Green LED +// | | + + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include "BQ769x2Header.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +#define DEV_ADDR 0x10 // BQ769x2 address is 0x10 including R/W bit or 0x8 as 7-bit address +#define CRC_Mode 0 // 0 for disabled, 1 for enabled +#define MAX_BUFFER_SIZE 10 +#define R 0 // Read; Used in DirectCommands and Subcommands functions +#define W 1 // Write; Used in DirectCommands and Subcommands functions +#define W2 2 // Write data with two bytes; Used in Subcommands function +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +SPI_HandleTypeDef hspi1; + +TIM_HandleTypeDef htim1; + +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ +uint8_t rxdata [2]; +uint8_t RX_data [2] = {0x00, 0x00}; // used in several functions to store data read from BQ769x2 +uint8_t RX_32Byte [32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + //used in Subcommands read function +// Global Variables for cell voltages, temperatures, Stack voltage, PACK Pin voltage, LD Pin voltage, CC2 current +uint16_t CellVoltage [16] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; +float Temperature [3] = {0,0,0}; +uint16_t Stack_Voltage = 0x00; +uint16_t Pack_Voltage = 0x00; +uint16_t LD_Voltage = 0x00; +uint16_t Pack_Current = 0x00; + +uint16_t AlarmBits = 0x00; +uint8_t value_SafetyStatusA; // Safety Status Register A +uint8_t value_SafetyStatusB; // Safety Status Register B +uint8_t value_SafetyStatusC; // Safety Status Register C +uint8_t value_PFStatusA; // Permanent Fail Status Register A +uint8_t value_PFStatusB; // Permanent Fail Status Register B +uint8_t value_PFStatusC; // Permanent Fail Status Register C +uint8_t FET_Status; // FET Status register contents - Shows states of FETs +uint16_t CB_ActiveCells; // Cell Balancing Active Cells + +uint8_t UV_Fault = 0; // under-voltage fault state +uint8_t OV_Fault = 0; // over-voltage fault state +uint8_t SCD_Fault = 0; // short-circuit fault state +uint8_t OCD_Fault = 0; // over-current fault state +uint8_t ProtectionsTriggered = 0; // Set to 1 if any protection triggers + +uint8_t LD_ON = 0; // Load Detect status bit +uint8_t DSG = 0; // discharge FET state +uint8_t CHG = 0; // charge FET state +uint8_t PCHG = 0; // pre-charge FET state +uint8_t PDSG = 0; // pre-discharge FET state + +uint32_t AccumulatedCharge_Int; // in BQ769x2_READPASSQ func +uint32_t AccumulatedCharge_Frac;// in BQ769x2_READPASSQ func +uint32_t AccumulatedCharge_Time;// in BQ769x2_READPASSQ func +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_SPI1_Init(void); +static void MX_USART2_UART_Init(void); +static void MX_TIM1_Init(void); +/* USER CODE BEGIN PFP */ +void delayUS(uint32_t us) { // Sets the delay in microseconds. + __HAL_TIM_SET_COUNTER(&htim1,0); // set the counter value a 0 + while (__HAL_TIM_GET_COUNTER(&htim1) < us); // wait for the counter to reach the us input in the parameter +} + +void CopyArray(uint8_t *source, uint8_t *dest, uint8_t count) +{ + uint8_t copyIndex = 0; + for (copyIndex = 0; copyIndex < count; copyIndex++) + { + dest[copyIndex] = source[copyIndex]; + } +} + +unsigned char Checksum(unsigned char *ptr, unsigned char len) +// Calculates the checksum when writing to a RAM register. The checksum is the inverse of the sum of the bytes. +{ + unsigned char i; + unsigned char checksum = 0; + + for(i=0; i 0)) { + delayUS(500); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); + HAL_SPI_TransmitReceive(&hspi1, TX_Buffer, rxdata, 2, 1); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); + if ((rxdata[0] == addr) & (rxdata[1] == reg_data[i])) + match = 1; + retries --; + } + match = 0; + addr += 1; + delayUS(500); + } +} + + +void SPI_ReadReg(uint8_t reg_addr, uint8_t *reg_data, uint8_t count) { + // SPI Read. Includes retries in case HFO has not started or if wait time is needed. See BQ76952 Software Development Guide for examples + uint8_t addr; + uint8_t TX_Buffer [MAX_BUFFER_SIZE] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; + unsigned int i; + unsigned int match; + unsigned int retries = 10; + + match = 0; + addr = reg_addr; + + for(i=0; i 0)) { + delayUS(500); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); + HAL_SPI_TransmitReceive(&hspi1, TX_Buffer, rxdata, 2, 1); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); + if (rxdata[0] == addr) { + match = 1; + reg_data[i] = rxdata[1]; + } + retries --; + } + match = 0; + addr += 1; + delayUS(500); + } +} + +void BQ769x2_SetRegister(uint16_t reg_addr, uint32_t reg_data, uint8_t datalen) +{ + uint8_t TX_Buffer[2] = {0x00, 0x00}; + uint8_t TX_RegData[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + //TX_RegData in little endian format + TX_RegData[0] = reg_addr & 0xff; + TX_RegData[1] = (reg_addr >> 8) & 0xff; + TX_RegData[2] = reg_data & 0xff; //1st byte of data + + switch(datalen) + { + case 1: //1 byte datalength + SPI_WriteReg(0x3E, TX_RegData, 3); + delayUS(2000); + TX_Buffer[0] = Checksum(TX_RegData, 3); + TX_Buffer[1] = 0x05; //combined length of register address and data + SPI_WriteReg(0x60, TX_Buffer, 2); // Write the checksum and length + delayUS(2000); + break; + case 2: //2 byte datalength + TX_RegData[3] = (reg_data >> 8) & 0xff; + SPI_WriteReg(0x3E, TX_RegData, 4); + delayUS(2000); + TX_Buffer[0] = Checksum(TX_RegData, 4); + TX_Buffer[1] = 0x06; //combined length of register address and data + SPI_WriteReg(0x60, TX_Buffer, 2); // Write the checksum and length + delayUS(2000); + break; + case 4: //4 byte datalength, Only used for CCGain and Capacity Gain + TX_RegData[3] = (reg_data >> 8) & 0xff; + TX_RegData[4] = (reg_data >> 16) & 0xff; + TX_RegData[5] = (reg_data >> 24) & 0xff; + SPI_WriteReg(0x3E, TX_RegData, 6); + delayUS(2000); + TX_Buffer[0] = Checksum(TX_RegData, 6); + TX_Buffer[1] = 0x08; //combined length of register address and data + SPI_WriteReg(0x60, TX_Buffer, 2); // Write the checksum and length + delayUS(2000); + break; + } +} + +void CommandSubcommands(uint16_t command) //For Command only Subcommands +// See the TRM or the BQ76952 header file for a full list of Command-only subcommands +{ //For DEEPSLEEP/SHUTDOWN subcommand you will need to call this function twice consecutively + + uint8_t TX_Reg[2] = {0x00, 0x00}; + + //TX_Reg in little endian format + TX_Reg[0] = command & 0xff; + TX_Reg[1] = (command >> 8) & 0xff; + + SPI_WriteReg(0x3E,TX_Reg,2); + delayUS(2000); +} + +void Subcommands(uint16_t command, uint16_t data, uint8_t type) +// See the TRM or the BQ76952 header file for a full list of Subcommands +{ + //security keys and Manu_data writes dont work with this function (reading these commands works) + //max readback size is 32 bytes i.e. DASTATUS, CUV/COV snapshot + uint8_t TX_Reg[4] = {0x00, 0x00, 0x00, 0x00}; + uint8_t TX_Buffer[2] = {0x00, 0x00}; + + //TX_Reg in little endian format + TX_Reg[0] = command & 0xff; + TX_Reg[1] = (command >> 8) & 0xff; + + if (type == R) {//read + SPI_WriteReg(0x3E,TX_Reg,2); + delayUS(2000); + SPI_ReadReg(0x40, RX_32Byte, 32); //RX_32Byte is a global variable + } + else if (type == W) { + //FET_Control, REG12_Control + TX_Reg[2] = data & 0xff; + SPI_WriteReg(0x3E,TX_Reg,3); + delayUS(1000); + TX_Buffer[0] = Checksum(TX_Reg, 3); + TX_Buffer[1] = 0x05; //combined length of registers address and data + SPI_WriteReg(0x60, TX_Buffer, 2); + delayUS(1000); + } + else if (type == W2){ //write data with 2 bytes + //CB_Active_Cells, CB_SET_LVL + TX_Reg[2] = data & 0xff; + TX_Reg[3] = (data >> 8) & 0xff; + SPI_WriteReg(0x3E,TX_Reg,4); + delayUS(1000); + TX_Buffer[0] = Checksum(TX_Reg, 4); + TX_Buffer[1] = 0x06; //combined length of registers address and data + SPI_WriteReg(0x60, TX_Buffer, 2); + delayUS(1000); + } +} + +void DirectCommands(uint8_t command, uint16_t data, uint8_t type) +// See the TRM or the BQ76952 header file for a full list of Direct Commands +{ //type: R = read, W = write + uint8_t TX_data[2] = {0x00, 0x00}; + + //little endian format + TX_data[0] = data & 0xff; + TX_data[1] = (data >> 8) & 0xff; + + if (type == R) {//Read + SPI_ReadReg(command, RX_data, 2); //RX_data is a global variable + delayUS(2000); + } + if (type == W) {//write + //Control_status, alarm_status, alarm_enable all 2 bytes long + SPI_WriteReg(command,TX_data,2); + delayUS(2000); + } +} + +void BQ769x2_Init() { + // Configures all parameters in device RAM + + // Enter CONFIGUPDATE mode (Subcommand 0x0090) - It is required to be in CONFIG_UPDATE mode to program the device RAM settings + // See TRM for full description of CONFIG_UPDATE mode + CommandSubcommands(SET_CFGUPDATE); + + // After entering CONFIG_UPDATE mode, RAM registers can be programmed. When programming RAM, checksum and length must also be + // programmed for the change to take effect. All of the RAM registers are described in detail in the BQ769x2 TRM. + // An easier way to find the descriptions is in the BQStudio Data Memory screen. When you move the mouse over the register name, + // a full description of the register and the bits will pop up on the screen. + + // 'Power Config' - 0x9234 = 0x2D80 + // Setting the DSLP_LDO bit allows the LDOs to remain active when the device goes into Deep Sleep mode + // Set wake speed bits to 00 for best performance + BQ769x2_SetRegister(PowerConfig, 0x2D80, 2); + + // 'REG0 Config' - set REG0_EN bit to enable pre-regulator + BQ769x2_SetRegister(REG0Config, 0x01, 1); + + // 'REG12 Config' - Enable REG1 with 3.3V output (0x0D for 3.3V, 0x0F for 5V) + BQ769x2_SetRegister(REG12Config, 0x0D, 1); + + // Set DFETOFF pin to control BOTH CHG and DSG FET - 0x92FB = 0x42 (set to 0x00 to disable) + BQ769x2_SetRegister(DFETOFFPinConfig, 0x42, 1); + + // Set up ALERT Pin - 0x92FC = 0x2A + // This configures the ALERT pin to drive high (REG1 voltage) when enabled. + // The ALERT pin can be used as an interrupt to the MCU when a protection has triggered or new measurements are available + BQ769x2_SetRegister(ALERTPinConfig, 0x2A, 1); + + // Set TS1 to measure Cell Temperature - 0x92FD = 0x07 + BQ769x2_SetRegister(TS1Config, 0x07, 1); + + // Set TS3 to measure FET Temperature - 0x92FF = 0x0F + BQ769x2_SetRegister(TS3Config, 0x0F, 1); + + // Set HDQ to measure Cell Temperature - 0x9300 = 0x07 + BQ769x2_SetRegister(HDQPinConfig, 0x00, 1); // No thermistor installed on EVM HDQ pin, so set to 0x00 + + // 'VCell Mode' - Enable 16 cells - 0x9304 = 0x0000; Writing 0x0000 sets the default of 16 cells + BQ769x2_SetRegister(VCellMode, 0x0000, 2); + + // Enable protections in 'Enabled Protections A' 0x9261 = 0xBC + // Enables SCD (short-circuit), OCD1 (over-current in discharge), OCC (over-current in charge), + // COV (over-voltage), CUV (under-voltage) + BQ769x2_SetRegister(EnabledProtectionsA, 0xBC, 1); + + // Enable all protections in 'Enabled Protections B' 0x9262 = 0xF7 + // Enables OTF (over-temperature FET), OTINT (internal over-temperature), OTD (over-temperature in discharge), + // OTC (over-temperature in charge), UTINT (internal under-temperature), UTD (under-temperature in discharge), UTC (under-temperature in charge) + BQ769x2_SetRegister(EnabledProtectionsB, 0xF7, 1); + + // 'Default Alarm Mask' - 0x..82 Enables the FullScan and ADScan bits, default value = 0xF800 + BQ769x2_SetRegister(DefaultAlarmMask, 0xF882, 2); + + // Set up Cell Balancing Configuration - 0x9335 = 0x03 - Automated balancing while in Relax or Charge modes + // Also see "Cell Balancing with BQ769x2 Battery Monitors" document on ti.com + BQ769x2_SetRegister(BalancingConfiguration, 0x03, 1); + + // Set up CUV (under-voltage) Threshold - 0x9275 = 0x31 (2479 mV) + // CUV Threshold is this value multiplied by 50.6mV + BQ769x2_SetRegister(CUVThreshold, 0x31, 1); + + // Set up COV (over-voltage) Threshold - 0x9278 = 0x55 (4301 mV) + // COV Threshold is this value multiplied by 50.6mV + BQ769x2_SetRegister(COVThreshold, 0x55, 1); + + // Set up OCC (over-current in charge) Threshold - 0x9280 = 0x05 (10 mV = 10A across 1mOhm sense resistor) Units in 2mV + BQ769x2_SetRegister(OCCThreshold, 0x05, 1); + + // Set up OCD1 Threshold - 0x9282 = 0x0A (20 mV = 20A across 1mOhm sense resistor) units of 2mV + BQ769x2_SetRegister(OCD1Threshold, 0x0A, 1); + + // Set up SCD Threshold - 0x9286 = 0x05 (100 mV = 100A across 1mOhm sense resistor) 0x05=100mV + BQ769x2_SetRegister(SCDThreshold, 0x05, 1); + + // Set up SCD Delay - 0x9287 = 0x03 (30 us) Enabled with a delay of (value - 1) * 15 µs; min value of 1 + BQ769x2_SetRegister(SCDDelay, 0x03, 1); + + // Set up SCDL Latch Limit to 1 to set SCD recovery only with load removal 0x9295 = 0x01 + // If this is not set, then SCD will recover based on time (SCD Recovery Time parameter). + BQ769x2_SetRegister(SCDLLatchLimit, 0x01, 1); + + // Exit CONFIGUPDATE mode - Subcommand 0x0092 + CommandSubcommands(EXIT_CFGUPDATE); +} + +// ********************************* FET Control Commands *************************************** + +void BQ769x2_BOTHOFF () { + // Disables all FETs using the DFETOFF (BOTHOFF) pin + // The DFETOFF pin on the BQ76952EVM should be connected to the MCU board to use this function + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); // DFETOFF pin (BOTHOFF) set high +} + +void BQ769x2_RESET_BOTHOFF () { + // Resets DFETOFF (BOTHOFF) pin + // The DFETOFF pin on the BQ76952EVM should be connected to the MCU board to use this function + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); // DFETOFF pin (BOTHOFF) set low +} + +void BQ769x2_ReadFETStatus() { + // Read FET Status to see which FETs are enabled + DirectCommands(FETStatus, 0x00, R); + FET_Status = (RX_data[1]*256 + RX_data[0]); + DSG = ((0x4 & RX_data[0])>>2);// discharge FET state + CHG = (0x1 & RX_data[0]);// charge FET state + PCHG = ((0x2 & RX_data[0])>>1);// pre-charge FET state + PDSG = ((0x8 & RX_data[0])>>3);// pre-discharge FET state +} + +// ********************************* End of FET Control Commands ********************************* + +// ********************************* BQ769x2 Power Commands ***************************************** + +void BQ769x2_ShutdownPin() { + // Puts the device into SHUTDOWN mode using the RST_SHUT pin + // The RST_SHUT pin on the BQ76952EVM should be connected to the MCU board to use this function + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET); // Sets RST_SHUT pin +} + +void BQ769x2_ReleaseShutdownPin() { + // Releases the RST_SHUT pin + // The RST_SHUT pin on the BQ76952EVM should be connected to the MCU board to use this function + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET); // Resets RST_SHUT pin +} + +// ********************************* End of BQ769x2 Power Commands ***************************************** + + +// ********************************* BQ769x2 Status and Fault Commands ***************************************** + +uint16_t BQ769x2_ReadAlarmStatus() { + // Read this register to find out why the ALERT pin was asserted + DirectCommands(AlarmStatus, 0x00, R); + return (RX_data[1]*256 + RX_data[0]); +} + +void BQ769x2_ReadSafetyStatus() { //good example functions + // Read Safety Status A/B/C and find which bits are set + // This shows which primary protections have been triggered + DirectCommands(SafetyStatusA, 0x00, R); + value_SafetyStatusA = (RX_data[1]*256 + RX_data[0]); + //Example Fault Flags + UV_Fault = ((0x4 & RX_data[0])>>2); + OV_Fault = ((0x8 & RX_data[0])>>3); + SCD_Fault = ((0x8 & RX_data[1])>>3); + OCD_Fault = ((0x2 & RX_data[1])>>1); + DirectCommands(SafetyStatusB, 0x00, R); + value_SafetyStatusB = (RX_data[1]*256 + RX_data[0]); + DirectCommands(SafetyStatusC, 0x00, R); + value_SafetyStatusC = (RX_data[1]*256 + RX_data[0]); + if ((value_SafetyStatusA + value_SafetyStatusB + value_SafetyStatusC) > 1) { + ProtectionsTriggered = 1; } + else { + ProtectionsTriggered = 0; } +} + +void BQ769x2_ReadPFStatus() { + // Read Permanent Fail Status A/B/C and find which bits are set + // This shows which permanent failures have been triggered + DirectCommands(PFStatusA, 0x00, R); + value_PFStatusA = (RX_data[1]*256 + RX_data[0]); + DirectCommands(PFStatusB, 0x00, R); + value_PFStatusB = (RX_data[1]*256 + RX_data[0]); + DirectCommands(PFStatusC, 0x00, R); + value_PFStatusC = (RX_data[1]*256 + RX_data[0]); +} + +// ********************************* End of BQ769x2 Status and Fault Commands ***************************************** + + +// ********************************* BQ769x2 Measurement Commands ***************************************** + + +uint16_t BQ769x2_ReadVoltage(uint8_t command) +// This function can be used to read a specific cell voltage or stack / pack / LD voltage +{ + //RX_data is global var + DirectCommands(command, 0x00, R); + if(command >= Cell1Voltage && command <= Cell16Voltage) {//Cells 1 through 16 (0x14 to 0x32) + return (RX_data[1]*256 + RX_data[0]); //voltage is reported in mV + } + else {//stack, Pack, LD + return 10 * (RX_data[1]*256 + RX_data[0]); //voltage is reported in 0.01V units + } + +} +void BQ769x2_ReadAllVoltages() +// Reads all cell voltages, Stack voltage, PACK pin voltage, and LD pin voltage +{ + int cellvoltageholder = Cell1Voltage; //Cell1Voltage is 0x14 + for (int x = 0; x < 16; x++){//Reads all cell voltages + CellVoltage[x] = BQ769x2_ReadVoltage(cellvoltageholder); + cellvoltageholder = cellvoltageholder + 2; + } + Stack_Voltage = BQ769x2_ReadVoltage(StackVoltage); + Pack_Voltage = BQ769x2_ReadVoltage(PACKPinVoltage); + LD_Voltage = BQ769x2_ReadVoltage(LDPinVoltage); +} + +uint16_t BQ769x2_ReadCurrent() +// Reads PACK current +{ + DirectCommands(CC2Current, 0x00, R); + return (RX_data[1]*256 + RX_data[0]); // current is reported in mA +} + +float BQ769x2_ReadTemperature(uint8_t command) +{ + DirectCommands(command, 0x00, R); + //RX_data is a global var + return (0.1 * (float)(RX_data[1]*256 + RX_data[0])) - 273.15; // converts from 0.1K to Celcius +} + +void BQ769x2_ReadPassQ(){ // Read Accumulated Charge and Time from DASTATUS6 + Subcommands(DASTATUS6, 0x00, R); + AccumulatedCharge_Int = ((RX_32Byte[3]<<24) + (RX_32Byte[2]<<16) + (RX_32Byte[1]<<8) + RX_32Byte[0]); //Bytes 0-3 + AccumulatedCharge_Frac = ((RX_32Byte[7]<<24) + (RX_32Byte[6]<<16) + (RX_32Byte[5]<<8) + RX_32Byte[4]); //Bytes 4-7 + AccumulatedCharge_Time = ((RX_32Byte[11]<<24) + (RX_32Byte[10]<<16) + (RX_32Byte[9]<<8) + RX_32Byte[8]); //Bytes 8-11 +} + +// ********************************* End of BQ769x2 Measurement Commands ***************************************** + + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_SPI1_Init(); + MX_USART2_UART_Init(); + MX_TIM1_Init(); + /* USER CODE BEGIN 2 */ + // Start timer + HAL_TIM_Base_Start(&htim1); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); // SPI_CS pin set high + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET); // RST_SHUT pin set low + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); // DFETOFF pin (BOTHOFF) set low + delayUS(10000); + + CommandSubcommands(BQ769x2_RESET); // Resets the BQ769x2 registers + delayUS(60000); + BQ769x2_Init(); // Configure all of the BQ769x2 register settings + delayUS(10000); + CommandSubcommands(FET_ENABLE); // Enable the CHG and DSG FETs + delayUS(10000); + CommandSubcommands(SLEEP_DISABLE); // Sleep mode is enabled by default. For this example, Sleep is disabled to + // demonstrate full-speed measurements in Normal mode. + + delayUS(60000); delayUS(60000); delayUS(60000); delayUS(60000); //wait to start measurements after FETs close + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + + //Reads Cell, Stack, Pack, LD Voltages, Pack Current and TS1/TS3 Temperatures in a loop + //This basic example polls the Alarm Status register to see if protections have triggered or new measurements are ready + //The ALERT pin can also be used as an interrupt to the microcontroller for fastest response time instead of polling + //In this example the LED on the microcontroller board will be turned on to indicate a protection has triggered and will + //be turned off if the protection condition has cleared. + + AlarmBits = BQ769x2_ReadAlarmStatus(); + if (AlarmBits & 0x80) { // Check if FULLSCAN is complete. If set, new measurements are available + BQ769x2_ReadAllVoltages(); + Pack_Current = BQ769x2_ReadCurrent(); + Temperature[0] = BQ769x2_ReadTemperature(TS1Temperature); + Temperature[1] = BQ769x2_ReadTemperature(TS3Temperature); + DirectCommands(AlarmStatus, 0x0080, W); // Clear the FULLSCAN bit + } + + if (AlarmBits & 0xC000) { // If Safety Status bits are showing in AlarmStatus register + BQ769x2_ReadSafetyStatus(); // Read the Safety Status registers to find which protections have triggered + if (ProtectionsTriggered & 1) { + HAL_GPIO_WritePin(GPIOA, LD2_Pin, GPIO_PIN_SET); }// Turn on the LED to indicate Protection has triggered + DirectCommands(AlarmStatus, 0xF800, W); // Clear the Safety Status Alarm bits. + } + else + { + if (ProtectionsTriggered & 1) { + BQ769x2_ReadSafetyStatus(); + if (!(ProtectionsTriggered & 1)) + { + HAL_GPIO_WritePin(GPIOA, LD2_Pin, GPIO_PIN_RESET); + } + } // Turn off the LED if Safety Status has cleared which means the protection condition is no longer present + } + delayUS(20000); // repeat loop every 20 ms + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL8; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_ENABLE; + hspi1.Init.CRCPolynomial = 7; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief TIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM1_Init(void) +{ + + /* USER CODE BEGIN TIM1_Init 0 */ + + /* USER CODE END TIM1_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM1_Init 1 */ + + /* USER CODE END TIM1_Init 1 */ + htim1.Instance = TIM1; + htim1.Init.Prescaler = 63; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.Period = 65535; + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim1.Init.RepetitionCounter = 0; + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM1_Init 2 */ + + /* USER CODE END TIM1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, LD2_Pin|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10, GPIO_PIN_RESET); + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : LD2_Pin PA8 PA9 PA10 */ + GPIO_InitStruct.Pin = LD2_Pin|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : PB6 */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From df9dd533e7cfbeb0f554667e8df7e70ef5c2e39b Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 26 Oct 2025 16:03:08 +0100 Subject: [PATCH 06/30] feat: Added R/W functions for Direct registers, subcommands, data memory --- bms/bms/bms_config/src/ic_bms/bms_spi.c | 202 +++++++++++++++++++++--- bms/bms/bms_config/src/ic_bms/bms_spi.h | 31 +++- 2 files changed, 211 insertions(+), 22 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index b98d1d65..08af8e4e 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -1,8 +1,11 @@ #include +#include +#include #include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" #include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" #include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" #include "definitions.h" +#include "bms_spi.h" @@ -11,9 +14,17 @@ #define BQ_CS_GROUP (0U) #define BQ_CS_MASK (1UL << 18) +#define R 0 // Read; Used in DirectCommands and Subcommands functions +#define W 1 // Write; Used in DirectCommands and Subcommands functions + + static inline void BQ_CS_Low(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; } static inline void BQ_CS_High(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; } +static inline void _delay(uint32_t cycles){ + + for (volatile uint32_t i=0; iGROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; } -bool Spi_2B(uint8_t tx0, uint8_t tx1, uint8_t *rx0, uint8_t *rx1) +bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) { - uint8_t tx[2] = { tx0, tx1 }; - uint8_t rx[2] = { 0, 0 }; - - - //wait while prev transfer is ongoing - if (SERCOM0_SPI_IsBusy()) return false; BQ_CS_Low(); - bool ok = SERCOM0_SPI_WriteRead(tx, 2U, rx, 2U); + bool ok = SERCOM0_SPI_WriteRead(tx, length, rx, length); BQ_CS_High(); - if (!ok) - return false; - - if (rx0) *rx0 = rx[0]; - if (rx1) *rx1 = rx[1]; + _delay(100); + - return true; + return ok; } + + + bool WriteReg(uint8_t regAddr, uint8_t value) { /* First byte: MSB=1 to indicate WRITE, lower 7 bits = register address */ @@ -57,20 +62,179 @@ bool WriteReg(uint8_t regAddr, uint8_t value) tx[0] = (uint8_t)(0x80 | (regAddr & 0x7F)); /* W flag + address */ tx[1] = value; - /* (optional) ensure no active transfer */ if (SERCOM0_SPI_IsBusy()) return false; - /* CS low -> transfer -> CS high */ - PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; - bool ok = SERCOM0_SPI_Write(tx, 2U); - PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; + BQ_CS_Low(); + bool ok = SERCOM0_SPI_Write(tx, 2U); + BQ_CS_High(); + + _delay(2000); + + return ok; +} + + +bool ReadReg(uint8_t regAddr, uint8_t *value) +{ + uint8_t tx[2] = { (regAddr & 0x7F), 0x00 }; + uint8_t rx[2] = { 0, 0 }; + + if (SERCOM0_SPI_IsBusy()) + return false; + + BQ_CS_Low(); + bool ok = SERCOM0_SPI_WriteRead(tx, 2U, rx, 2U); + BQ_CS_High(); + + if (ok) + *value = rx[1]; + + _delay(2000); + return ok; +} + +bool BQ_DirectRead(uint8_t command, uint8_t *data, uint8_t count) +{ + bool ok = true; + + for (uint8_t i = 0; i < count; i++) + { + if (!ReadReg(command + i, &data[i])) + { + ok = false; + break; + } + _delay(2000); // short pause between bytes + } + + return ok; +} + +bool BQ_DirectWrite(uint8_t command, const uint8_t *data, uint8_t count) +{ + bool ok = true; + + for (uint8_t i = 0; i < count; i++) + { + if (!WriteReg(command + i, data[i])) + { + ok = false; + break; + } + _delay(2000); // short pause between bytes + } + + return ok; +} + + +bool BQ_DirectCommand(uint8_t command, uint16_t *data, char type) +{ + uint8_t buf[2]; + bool ok = true; + + if (type == 'W') // Write + { + buf[0] = (*data) & 0xFF; // LSB first + buf[1] = (*data >> 8) & 0xFF; // MSB + ok = BQ_DirectWrite(command, buf, 2); + } + else if (type == 'R') // Read + { + ok = BQ_DirectRead(command, buf, 2); + *data = (uint16_t)(buf[0] | (buf[1] << 8)); // Little endian + } + + _delay(2000); // short pause between frames (~few hundred µs) + return ok; +} + +bool BQ_CommandOnly(uint16_t subcmd){ + + + uint8_t lsb=(uint8_t)(subcmd & 0xFF); + uint8_t msb=(uint8_t)((subcmd >> 8) & 0xFF); + + if (!WriteReg(0x3E, lsb)) + return false; + if (!WriteReg(0x3F, msb)) + return false; + _delay(20000); + +} +/* + example of BQ_commandOnly usage: + + Reset the BQ76942 + BQ_CommandOnly(RESET); +*/ +bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length) +{ + uint8_t lsb = (uint8_t)(subcmd & 0xFF); + uint8_t msb = (uint8_t)((subcmd >> 8) & 0xFF); + uint8_t check_lsb=0, check_msb=0; + bool ok = true; + + + if (!WriteReg(0x3E, lsb)) + return false; + if (!WriteReg(0x3F, msb)) + return false; + + do{ + ReadReg(0x3E, &check_lsb); + ReadReg(0x3F, &check_msb); + }while ((check_lsb != lsb) || (check_msb != msb)); + + for (uint8_t i=0; i32) + return false; + uint8_t lsb=(uint8_t)(subcmd & 0xFF); + uint8_t msb=(uint8_t)((subcmd >> 8) & 0xFF); + uint8_t checksum=0; + uint16_t sum = 0; + if (!WriteReg(0x3E, lsb)) + return false; + if (!WriteReg(0x3F, msb)) + return false; + + for (uint8_t i=0; i +#include + +//Direct Commands #define BatteryStatus 0x12 +#define StackVoltage 0x34 #define Cell1Voltage 0x14 #define Cell2Voltage 0x16 @@ -24,7 +30,7 @@ */ // 16 cell voltage readings avaliable -#define StackVoltage 0x34 + #define SWAP_COMM_MODE 0x29BC @@ -34,8 +40,27 @@ #define THERMISOR_TEMP 0x6A #define INTERNAL_TEMP 0x68 +//Command only (R) + +#define RESET 0x0012 +#define SHUTDOWN 0x0010 + + /* Minimal driver: only SPI+CS bring-up */ void BQ76942_Init(void); +bool WriteReg(uint8_t regAddr, uint8_t value); +bool ReadReg(uint8_t regAddr, uint8_t *value); +bool BQ_DirectCommand(uint8_t command, uint16_t *data, char type); +bool BQ_CommandOnly(uint16_t subcmd); +bool BQ_DirectRead(uint8_t command, uint8_t *data, uint8_t count); +bool BQ_DirectWrite(uint8_t command, const uint8_t *data, uint8_t count); +bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length); +bool BQ_WriteSubCommand(uint16_t subcmd, const uint8_t *data, uint8_t length) + + + + + From 65888c529f243e2dd72e1c3fb0ac0906f4d800d0 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Wed, 29 Oct 2025 15:55:21 +0100 Subject: [PATCH 07/30] Added over/under voltage threshold and timer configs --- bms/bms/bms_config/src/ic_bms/bms_spi.c | 61 ++++++++++++++++++------- bms/bms/bms_config/src/ic_bms/bms_spi.h | 26 ++++++++++- 2 files changed, 69 insertions(+), 18 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 08af8e4e..e136542d 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -3,21 +3,10 @@ #include #include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" #include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" -#include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" #include "definitions.h" #include "bms_spi.h" - - - -#define BQ_CS_GROUP (0U) -#define BQ_CS_MASK (1UL << 18) - -#define R 0 // Read; Used in DirectCommands and Subcommands functions -#define W 1 // Write; Used in DirectCommands and Subcommands functions - - static inline void BQ_CS_Low(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; } static inline void BQ_CS_High(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; } @@ -162,6 +151,8 @@ bool BQ_CommandOnly(uint16_t subcmd){ return false; _delay(20000); + return true; + } /* example of BQ_commandOnly usage: @@ -197,7 +188,7 @@ bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length) } } _delay(2000); - return ok; + return true; } bool BQ_WriteSubCommand(uint16_t subcmd, const uint8_t *data, uint8_t length) @@ -214,26 +205,62 @@ bool BQ_WriteSubCommand(uint16_t subcmd, const uint8_t *data, uint8_t length) return false; if (!WriteReg(0x3F, msb)) return false; - + for (uint8_t i=0; i 110) cov_val = 110; + BQ_WriteSubCommand(COV_THRESHOLD_ADDR, &cov_val, 1); + uint16_t cov_delay_ticks = (uint16_t)(COV_DELAY_MS / 3.3f + 0.5f); + uint8_t cov_delay_bytes[2] = { + (uint8_t)(cov_delay_ticks & 0xFF), + (uint8_t)((cov_delay_ticks >> 8) & 0xFF) + }; + BQ_WriteSubCommand(COV_DELAY_ADDR, cov_delay_bytes, 2); + + + uint8_t cuv_val = (uint8_t)(CUV_THRESHOLD_MV / 50.6f + 0.5f); + if (cuv_val < 20) cuv_val = 20; + if (cuv_val > 110) cuv_val = 110; + BQ_WriteSubCommand(CUV_THRESHOLD_ADDR, &cuv_val, 1); + + uint16_t cuv_delay_ticks = (uint16_t)(CUV_DELAY_MS / 3.3f + 0.5f); + uint8_t cuv_delay_bytes[2] = { + (uint8_t)(cuv_delay_ticks & 0xFF), + (uint8_t)((cuv_delay_ticks >> 8) & 0xFF) + }; + BQ_WriteSubCommand(CUV_DELAY_ADDR, cuv_delay_bytes, 2); + + + BQ_CommandOnly(EXIT_CONFIG_UPDATE); } + + diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index a7c0d8eb..eb3ba305 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -4,6 +4,8 @@ #include #include + + //Direct Commands #define BatteryStatus 0x12 @@ -29,7 +31,11 @@ */ // 16 cell voltage readings avaliable +#define BQ_CS_GROUP (0U) +#define BQ_CS_MASK (1UL << 18) +#define R 0 // Read; Used in DirectCommands and Subcommands functions +#define W 1 // Write; Used in DirectCommands and Subcommands functions @@ -45,6 +51,23 @@ #define RESET 0x0012 #define SHUTDOWN 0x0010 +// Thresholds and Delays values (TBC) + +#define COV_THRESHOLD_MV 4250 +#define COV_DELAY_MS 200 +#define CUV_THRESHOLD_MV 3000 +#define CUV_DELAY_MS 300 + +// Addresses +#define COV_THRESHOLD_ADDR 0x9278 +#define COV_DELAY_ADDR 0x9279 +#define CUV_THRESHOLD_ADDR 0x9275 +#define CUV_DELAY_ADDR 0x9276 + +//Config Mode +#define ENTER_CONFIG_UPDATE 0x0090 +#define EXIT_CONFIG_UPDATE 0x0092 + /* Minimal driver: only SPI+CS bring-up */ void BQ76942_Init(void); @@ -55,7 +78,8 @@ bool BQ_CommandOnly(uint16_t subcmd); bool BQ_DirectRead(uint8_t command, uint8_t *data, uint8_t count); bool BQ_DirectWrite(uint8_t command, const uint8_t *data, uint8_t count); bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length); -bool BQ_WriteSubCommand(uint16_t subcmd, const uint8_t *data, uint8_t length) +bool BQ_WriteSubCommand(uint16_t subcmd, const uint8_t *data, uint8_t length); +void BMS_SetProtectionThresholds(void); From f733e56fc2f351512cefad24aa738a998a2e1667 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 2 Nov 2025 10:26:05 +0100 Subject: [PATCH 08/30] feat: readme --- bms/bms/bms_config/src/ic_bms/README.md | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 bms/bms/bms_config/src/ic_bms/README.md diff --git a/bms/bms/bms_config/src/ic_bms/README.md b/bms/bms/bms_config/src/ic_bms/README.md new file mode 100644 index 00000000..847fe096 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/README.md @@ -0,0 +1,6 @@ +### BMS IC BQ76942 + + +## Datasheets: [Link Text] (#https://www.ti.com/lit/ug/sluuby1b/sluuby1b.pdf?ts=1761234036230&ref_url=https%253A%252F%252Fcopilot.microsoft.com%252F) + + From 15e5a9a00ffb284ab5449e0246c6a557c9f4c710 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 2 Nov 2025 10:51:13 +0100 Subject: [PATCH 09/30] feat: README --- bms/bms/bms_config/src/ic_bms/README.md | 67 ++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/README.md b/bms/bms/bms_config/src/ic_bms/README.md index 847fe096..9d46bfc5 100644 --- a/bms/bms/bms_config/src/ic_bms/README.md +++ b/bms/bms/bms_config/src/ic_bms/README.md @@ -1,6 +1,69 @@ -### BMS IC BQ76942 +âš¡ Battery Management System (BMS) — TI BQ76942 +Overview +The goal of this work is to implement and understand the Texas Instruments BQ76942 battery management IC for use in Vortex NTNU’s AUV power system. +The IC manages 3–10 lithium cells, providing voltage, current, and temperature protection as well as cell balancing and fault monitoring. -## Datasheets: [Link Text] (#https://www.ti.com/lit/ug/sluuby1b/sluuby1b.pdf?ts=1761234036230&ref_url=https%253A%252F%252Fcopilot.microsoft.com%252F) +[!NOTE] +All firmware is written in bare-metal C for the Microchip SAMC21 microcontroller. Communication between the MCU and the BQ76942 uses SPI. +🧠 What Has Been Done +1. IC Initialization & Configuration +Implemented routines to enter CONFIG_UPDATE mode for safe parameter editing. + +Wrote register configuration for: + +Overvoltage (COV) and Undervoltage (CUV) thresholds + +Discharge and Charge FET control + +Protections and alert handling + +[!TIP] +Using the TI register map, thresholds are calculated based on cell voltage divided by 50.6 mV per bit, giving accurate programmable limits. + +2. Power Mode Handling + +Verified the IC’s transition between: + +NORMAL → SLEEP → DEEPSLEEP → SHUTDOWN + +Implemented RST_SHUT pin behavior for controlled shutdown and wake-up. + +Discovered that configuration commands must be resent after SHUTDOWN, since register memory is cleared. + +3. Protection & Fault Behavior + +Explored COV/CUV protection activation logic and timing. + +Confirmed ALERT pin triggers correctly when thresholds are crossed. + +Observed autonomous recovery works after voltage returns to safe range. + +[!IMPORTANT] +The BQ76942 protection system runs independently from the host MCU, meaning faults are handled even if communication is lost. + +4. Communication & Command Structure + +Verified SPI protocol operation using the Direct Command and Subcommand interface. + +Implemented functions for: + +Sending command-only subcommands (e.g., RESET, SEAL, UNSEAL) + +Reading measurement registers (cell voltages, pack current, temperature) + +🔠Key Discoveries + +RST_SHUT pin: Can both reset and shut down the IC depending on logic level and pulse duration. + +Dual ADC design allows simultaneous current and voltage sampling for precise protection timing. + +REG1/REG2 LDOs can power external logic (3.3 V or 5 V), reducing component count. + +OTP memory stores permanent configuration — useful for final production calibration. + +[!NOTE] +The system now successfully reads live cell voltages, controls protection FETs, and reports alerts over SPI. +Next focus: integrate fault reporting over CAN and test full pack balancing. \ No newline at end of file From a739a6c439cca0f74fa6e2a3640e6263cd2f8636 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 2 Nov 2025 10:55:08 +0100 Subject: [PATCH 10/30] feat: README --- bms/bms/bms_config/src/ic_bms/README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/README.md b/bms/bms/bms_config/src/ic_bms/README.md index 9d46bfc5..bc849890 100644 --- a/bms/bms/bms_config/src/ic_bms/README.md +++ b/bms/bms/bms_config/src/ic_bms/README.md @@ -4,8 +4,8 @@ Overview The goal of this work is to implement and understand the Texas Instruments BQ76942 battery management IC for use in Vortex NTNU’s AUV power system. The IC manages 3–10 lithium cells, providing voltage, current, and temperature protection as well as cell balancing and fault monitoring. -[!NOTE] -All firmware is written in bare-metal C for the Microchip SAMC21 microcontroller. Communication between the MCU and the BQ76942 uses SPI. +> [!NOTE] +> All firmware is written in bare-metal C for the Microchip SAMC21 microcontroller. Communication between the MCU and the BQ76942 uses SPI. 🧠 What Has Been Done 1. IC Initialization & Configuration @@ -20,8 +20,8 @@ Discharge and Charge FET control Protections and alert handling -[!TIP] -Using the TI register map, thresholds are calculated based on cell voltage divided by 50.6 mV per bit, giving accurate programmable limits. +> [!TIP] +> Using the TI register map, thresholds are calculated based on cell voltage divided by 50.6 mV per bit, giving accurate programmable limits. 2. Power Mode Handling @@ -41,8 +41,8 @@ Confirmed ALERT pin triggers correctly when thresholds are crossed. Observed autonomous recovery works after voltage returns to safe range. -[!IMPORTANT] -The BQ76942 protection system runs independently from the host MCU, meaning faults are handled even if communication is lost. +> [!IMPORTANT] +> The BQ76942 protection system runs independently from the host MCU, meaning faults are handled even if communication is lost. 4. Communication & Command Structure @@ -64,6 +64,6 @@ REG1/REG2 LDOs can power external logic (3.3 V or 5 V), reducing component count OTP memory stores permanent configuration — useful for final production calibration. -[!NOTE] -The system now successfully reads live cell voltages, controls protection FETs, and reports alerts over SPI. +> [!NOTE] +> The system now successfully reads live cell voltages, controls protection FETs, and reports alerts over SPI. Next focus: integrate fault reporting over CAN and test full pack balancing. \ No newline at end of file From 23b7b86cbc0e41407257de4539a78594ad63b96c Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 2 Nov 2025 10:56:59 +0100 Subject: [PATCH 11/30] feat: README --- bms/{bms/bms_config/src/ic_bms => }/README.md | 0 bms/bms/README.md | 11 ----------- 2 files changed, 11 deletions(-) rename bms/{bms/bms_config/src/ic_bms => }/README.md (100%) delete mode 100644 bms/bms/README.md diff --git a/bms/bms/bms_config/src/ic_bms/README.md b/bms/README.md similarity index 100% rename from bms/bms/bms_config/src/ic_bms/README.md rename to bms/README.md diff --git a/bms/bms/README.md b/bms/bms/README.md deleted file mode 100644 index 40233c27..00000000 --- a/bms/bms/README.md +++ /dev/null @@ -1,11 +0,0 @@ - -# bms - -## Structure - -| Path | Purpose | -|------------------------|-- -| -| _build | Stores build artifacts, can be deleted | -| cmake | Generated [CMake](https://cmake.org/) files. May be deleted if user.cmake has not been added | -| .vscode | See [VSCode Settings](https://code.visualstudio.com/docs/getstarted/settings) | -| .vscode/bms.mplab.json | The MPLAB project file, should not be deleted | From c1427c1c29deca65ffe39ac979d1d045b37fcdfb Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 2 Nov 2025 16:21:17 +0100 Subject: [PATCH 12/30] feat: Started with main and added Batterystatus check --- bms/bms/bms_config/src/ic_bms/bms_spi.c | 38 +++++++++++-- bms/bms/bms_config/src/ic_bms/bms_spi.h | 22 ++++---- .../bms_config/src/ic_bms/main_STM32_SPI.c | 4 +- bms/bms/bms_config/src/main.c | 54 ++++++++++++++++++- 4 files changed, 102 insertions(+), 16 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index e136542d..5af2e844 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -5,6 +5,8 @@ #include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" #include "definitions.h" #include "bms_spi.h" +# + static inline void BQ_CS_Low(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; } @@ -135,10 +137,11 @@ bool BQ_DirectCommand(uint8_t command, uint16_t *data, char type) *data = (uint16_t)(buf[0] | (buf[1] << 8)); // Little endian } - _delay(2000); // short pause between frames (~few hundred µs) + _delay(2000); return ok; } + bool BQ_CommandOnly(uint16_t subcmd){ @@ -165,7 +168,7 @@ bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length) uint8_t lsb = (uint8_t)(subcmd & 0xFF); uint8_t msb = (uint8_t)((subcmd >> 8) & 0xFF); uint8_t check_lsb=0, check_msb=0; - bool ok = true; + if (!WriteReg(0x3E, lsb)) @@ -183,7 +186,7 @@ bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length) if(!ReadReg(0x40+i,&data[i])) { - ok=false; + false; break; } } @@ -260,6 +263,35 @@ void BMS_SetProtectionThresholds(void) BQ_CommandOnly(EXIT_CONFIG_UPDATE); } +void BMS_BATTERY_STATUS(void){ + + uint8_t fetReg=0; + + if(!BQ_DirectRead(FET_STATUS, &fetReg, 1)){ + printf("Failed to read FET status\n"); + return; + } + + bool chg_on = (fetReg & (1 << 0)); // CHG_FET bit + bool pchg_on = (fetReg & (1 << 1)); // PCHG_FET bit + bool dsg_on = (fetReg & (1 << 2)); // DSG_FET bit + + + if (pchg_on) + printf("Battery in precharge mode\n"); + else if (chg_on && !dsg_on) + printf("Battery is charging\n"); + else if (dsg_on && !chg_on) + printf("Battery is discharging\n"); + else if (!chg_on && !dsg_on) + printf("Battery is idle\n"); + else + printf("Both CHG_FET and DSG_FET ACTIVE (transition)\n"); + + + +} + diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index eb3ba305..c898daba 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -8,15 +8,17 @@ //Direct Commands -#define BatteryStatus 0x12 -#define StackVoltage 0x34 - -#define Cell1Voltage 0x14 -#define Cell2Voltage 0x16 -#define Cell3Voltage 0x18 -#define Cell4Voltage 0x1A -#define Cell5Voltage 0x1C -#define Cell6Voltage 0x1E +#define BATTERYSTATUS 0x12 +#define STACKVOLTAGE 0x34 + +#define CELL1VOLTAGE 0x14 +#define CELL2VOLTAGE 0x16 +#define CELL3VOLTAGE 0x18 +#define CELL4VOLTAGE 0x1A +#define CELL5VOLTAGE 0x1C +#define CELL6VOLTAGE 0x1E + + /* #define Cell7Voltage 0x20 #define Cell8Voltage 0x22 @@ -68,6 +70,8 @@ #define ENTER_CONFIG_UPDATE 0x0090 #define EXIT_CONFIG_UPDATE 0x0092 +#define FET_STATUS 0x7F + /* Minimal driver: only SPI+CS bring-up */ void BQ76942_Init(void); diff --git a/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c b/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c index 2c773123..52c59f00 100644 --- a/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c +++ b/bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c @@ -470,7 +470,7 @@ void BQ769x2_Init() { // Set up SCD Threshold - 0x9286 = 0x05 (100 mV = 100A across 1mOhm sense resistor) 0x05=100mV BQ769x2_SetRegister(SCDThreshold, 0x05, 1); - // Set up SCD Delay - 0x9287 = 0x03 (30 us) Enabled with a delay of (value - 1) * 15 µs; min value of 1 + // Set up SCD Delay - 0x9287 = 0x03 (30 us) Enabled with a delay of (value - 1) * 15 �s; min value of 1 BQ769x2_SetRegister(SCDDelay, 0x03, 1); // Set up SCDL Latch Limit to 1 to set SCD recovery only with load removal 0x9295 = 0x01 @@ -577,7 +577,7 @@ uint16_t BQ769x2_ReadVoltage(uint8_t command) if(command >= Cell1Voltage && command <= Cell16Voltage) {//Cells 1 through 16 (0x14 to 0x32) return (RX_data[1]*256 + RX_data[0]); //voltage is reported in mV } - else {//stack, Pack, LD + else {//stack, Pack, LDCommand return 10 * (RX_data[1]*256 + RX_data[0]); //voltage is reported in 0.01V units } diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index a57b3ad8..88dc9915 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -26,9 +26,9 @@ #include // Defines true #include // Defines EXIT_FAILURE #include "definitions.h" // SYS function prototypes -#include "peripheral/adc/plib_adc0.h" - +#include "ic_bms/bms_spi.h" +#include @@ -38,11 +38,61 @@ // ***************************************************************************** // ***************************************************************************** +static inline void _delay(uint32_t cycles){ + + for (volatile uint32_t i=0; i Date: Wed, 5 Nov 2025 11:09:25 +0100 Subject: [PATCH 13/30] Update README.md --- bms/README.md | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/bms/README.md b/bms/README.md index bc849890..22adde6e 100644 --- a/bms/README.md +++ b/bms/README.md @@ -1,13 +1,17 @@ -âš¡ Battery Management System (BMS) — TI BQ76942 +Battery Management System (BMS) — TI BQ76942 Overview +> [!NOTE] +> Pages about Direct commands and subcommands is on page (13-14) and Data Memory settings on page (125) in BQ-TI datasheet: +> https://www.ti.com/lit/ug/sluuby1b/sluuby1b.pdf?ts=1761234036230&ref_url=https%253A%252F%252Fcopilot.microsoft.com%252F + The goal of this work is to implement and understand the Texas Instruments BQ76942 battery management IC for use in Vortex NTNU’s AUV power system. The IC manages 3–10 lithium cells, providing voltage, current, and temperature protection as well as cell balancing and fault monitoring. > [!NOTE] > All firmware is written in bare-metal C for the Microchip SAMC21 microcontroller. Communication between the MCU and the BQ76942 uses SPI. -🧠 What Has Been Done +What Has Been Done 1. IC Initialization & Configuration Implemented routines to enter CONFIG_UPDATE mode for safe parameter editing. @@ -66,4 +70,4 @@ OTP memory stores permanent configuration — useful for final production calibr > [!NOTE] > The system now successfully reads live cell voltages, controls protection FETs, and reports alerts over SPI. -Next focus: integrate fault reporting over CAN and test full pack balancing. \ No newline at end of file +Next focus: integrate fault reporting over CAN and test full pack balancing. From ac81fa100c998bdff9f23b493d5792eea36332b1 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Wed, 5 Nov 2025 16:05:13 +0100 Subject: [PATCH 14/30] fixed BQ_Read/WriteSubCommand func, started changing to snake_case format --- bms/bms/bms_config/src/ic_bms/bms_spi.c | 104 ++++++++++++++++++++---- bms/bms/bms_config/src/ic_bms/bms_spi.h | 21 +++-- bms/bms/bms_config/src/main.c | 38 +-------- 3 files changed, 103 insertions(+), 60 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 5af2e844..2e897a54 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -16,6 +16,7 @@ static inline void _delay(uint32_t cycles){ for (volatile uint32_t i=0; i> 8); + uint8_t echo_l = 0xFF, echo_h = 0xFF; + + if (!WriteReg(0x3E, lsb)) + return false; + if (!WriteReg(0x3F, msb)) + return false; + + uint32_t tries = 0; + do{ + if (!ReadReg(0x3E,&echo_l)) + return false; + if (!ReadReg(0x3F,&echo_h)) + return false; + if (++tries > BQ_SUBCMD_MAX_POLLS) + return false; + } while ((echo_l == 0xFF && echo_h == 0xFF) || (echo_l != lsb) || (echo_h != msb)); + + uint8_t buf[34]; + for (uint8_t off = 0; off<=(0x61 - 0x40); off++){ + if(!ReadReg((uint8_t)(0x40 + off), &buf[off])) + return false; + } + + uint8_t len_total=buf[0x61-0x40]; + if(len_total < 4) + return false; + uint8_t buf_len = (uint8_t)(len_total - 4); + if (buf_len > 32) + buf_len = 32; + uint8_t to_copy = (buf_len < length) ? buf_len : length; + + for (uint8_t i=0; i> 8) & 0xFF); - uint8_t checksum=0; - uint16_t sum = 0; + if (!WriteReg(0x3E, lsb)) return false; if (!WriteReg(0x3F, msb)) return false; + uint8_t sum = (uint8_t)(lsb + msb); for (uint8_t i=0; i Date: Sun, 9 Nov 2025 11:36:01 +0100 Subject: [PATCH 15/30] Update README.md --- bms/README.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/bms/README.md b/bms/README.md index 22adde6e..da92b11a 100644 --- a/bms/README.md +++ b/bms/README.md @@ -6,7 +6,7 @@ Overview > https://www.ti.com/lit/ug/sluuby1b/sluuby1b.pdf?ts=1761234036230&ref_url=https%253A%252F%252Fcopilot.microsoft.com%252F The goal of this work is to implement and understand the Texas Instruments BQ76942 battery management IC for use in Vortex NTNU’s AUV power system. -The IC manages 3–10 lithium cells, providing voltage, current, and temperature protection as well as cell balancing and fault monitoring. +The IC manages various lithium cells, providing voltage, current, and temperature protection as well as cell balancing and fault monitoring. > [!NOTE] > All firmware is written in bare-metal C for the Microchip SAMC21 microcontroller. Communication between the MCU and the BQ76942 uses SPI. @@ -22,6 +22,10 @@ Overvoltage (COV) and Undervoltage (CUV) thresholds Discharge and Charge FET control +Battery Status + +Read cell voltages + Protections and alert handling > [!TIP] @@ -29,7 +33,7 @@ Protections and alert handling 2. Power Mode Handling -Verified the IC’s transition between: +Need to verify the IC’s transition between: NORMAL → SLEEP → DEEPSLEEP → SHUTDOWN From 5c9790c20f485696301795a4f60483157062658f Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Sun, 9 Nov 2025 16:09:44 +0100 Subject: [PATCH 16/30] feat: changed read/write reg function, fixed snake_case, started looking at ALERT --- bms/bms/bms_config/src/ic_bms/bms_spi.c | 271 +++++++++--------------- bms/bms/bms_config/src/ic_bms/bms_spi.h | 38 ++-- bms/bms/bms_config/src/main.c | 9 +- 3 files changed, 128 insertions(+), 190 deletions(-) diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 2e897a54..ab851f77 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -1,16 +1,17 @@ #include +#include #include #include #include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" #include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" #include "definitions.h" #include "bms_spi.h" -# -static inline void BQ_CS_Low(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTCLR = BQ_CS_MASK; } -static inline void BQ_CS_High(void) { PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; } + +static inline void bq_cs_low(void) { PORT_REGS->GROUP[bq_cs_group].PORT_OUTCLR = bq_cs_mask; } +static inline void bq_cs_high(void) { PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; } static inline void _delay(uint32_t cycles){ @@ -19,14 +20,14 @@ static inline void _delay(uint32_t cycles){ //SPI + set CS high -void BQ76942_Init(void) +void bq76942_init(void) { // init SPI SERCOM0_SPI_Initialize(); // configure CS pin as output and set HIGH (inactive) - PORT_REGS->GROUP[BQ_CS_GROUP].PORT_DIRSET = BQ_CS_MASK; - PORT_REGS->GROUP[BQ_CS_GROUP].PORT_OUTSET = BQ_CS_MASK; + PORT_REGS->GROUP[bq_cs_group].PORT_DIRSET = bq_cs_mask; + PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; } bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) @@ -34,94 +35,64 @@ bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) if (SERCOM0_SPI_IsBusy()) return false; - BQ_CS_Low(); + bq_cs_low(); bool ok = SERCOM0_SPI_WriteRead(tx, length, rx, length); - BQ_CS_High(); - - + bq_cs_high(); - return ok; } - - - -bool WriteReg(uint8_t regAddr, uint8_t value) +bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length) { - /* First byte: MSB=1 to indicate WRITE, lower 7 bits = register address */ - uint8_t tx[2]; - tx[0] = (uint8_t)(0x80 | (regAddr & 0x7F)); /* W flag + address */ - tx[1] = value; + if (SERCOM0_SPI_IsBusy()) return false; - BQ_CS_Low(); - bool ok = SERCOM0_SPI_Write(tx, 2U); - BQ_CS_High(); - + uint8_t tx[length + 1]; + tx[0] = 0x80 | (regAddr & 0x7F); // Write flag + address + memcpy(&tx[1], data, length); //(memcpy (dest, src, length)) + bq_cs_low(); + bool ok = SERCOM0_SPI_Write(tx,length +1); + bq_cs_high(); return ok; } -bool ReadReg(uint8_t regAddr, uint8_t *value) +bool read_reg(uint8_t regAddr, uint8_t *data, uint8_t length) { - uint8_t tx[2] = { (regAddr & 0x7F), 0x00 }; - uint8_t rx[2] = { 0, 0 }; - + if (SERCOM0_SPI_IsBusy()) return false; - BQ_CS_Low(); - bool ok = SERCOM0_SPI_WriteRead(tx, 2U, rx, 2U); - BQ_CS_High(); + uint8_t tx[length + 1]; + uint8_t rx[length + 1]; + tx[0] = (regAddr & 0x7F); + memset(&tx[1], 0x00, length); - if (ok) - *value = rx[1]; + bq_cs_low(); + bool ok = SERCOM0_SPI_WriteRead(tx, length+1, rx, length+1); + bq_cs_high(); - + if (ok) + memcpy(&tx[1],0x00,length); return ok; + } -bool BQ_DirectRead(uint8_t command, uint8_t *data, uint8_t count) +bool bq_direct_read(uint8_t command, uint8_t *data, uint8_t count) { - bool ok = true; - - for (uint8_t i = 0; i < count; i++) - { - if (!ReadReg(command + i, &data[i])) - { - ok = false; - break; - } - _delay(2000); // short pause between bytes - } - - return ok; + return read_reg(command,data,count); } -bool BQ_DirectWrite(uint8_t command, const uint8_t *data, uint8_t count) +bool bq_direct_write(uint8_t command, const uint8_t *data, uint8_t count) { - bool ok = true; - - for (uint8_t i = 0; i < count; i++) - { - if (!WriteReg(command + i, data[i])) - { - ok = false; - break; - } - _delay(2000); // short pause between bytes - } - - return ok; + return write_reg(command, data, count); } - -bool BQ_DirectCommand(uint8_t command, uint16_t *data, char type) +bool bq_direct_command(uint8_t command, uint16_t *data, char type) { uint8_t buf[2]; bool ok = true; @@ -130,34 +101,34 @@ bool BQ_DirectCommand(uint8_t command, uint16_t *data, char type) { buf[0] = (*data) & 0xFF; // LSB first buf[1] = (*data >> 8) & 0xFF; // MSB - ok = BQ_DirectWrite(command, buf, 2); + ok = bq_direct_write(command, buf, 2); } else if (type == 'R') // Read { - ok = BQ_DirectRead(command, buf, 2); - *data = (uint16_t)(buf[0] | (buf[1] << 8)); // Little endian + ok = bq_direct_read(command, buf, 2); + if (ok) + *data = (uint16_t)(buf[0] | (buf[1] << 8)); // Little endian } - _delay(2000); + return ok; } -bool BQ_CommandOnly(uint16_t subcmd){ +bool bq_command_only(uint16_t subcmd){ - uint8_t lsb=(uint8_t)(subcmd & 0xFF); - uint8_t msb=(uint8_t)((subcmd >> 8) & 0xFF); - - if (!WriteReg(0x3E, lsb)) - return false; - if (!WriteReg(0x3F, msb)) + // Send 0x3E/0x3F in one SPI frame (lead’s request) + uint8_t two[2] = { + (uint8_t)(subcmd & 0xFF), + (uint8_t)((subcmd >> 8) & 0xFF) + }; + if (!write_reg(0x3E, two, 2)) return false; - _delay(20000); - + return true; - } + /* example of BQ_commandOnly usage: @@ -165,158 +136,126 @@ bool BQ_CommandOnly(uint16_t subcmd){ BQ_CommandOnly(RESET); */ -/* -bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length) -{ - uint8_t lsb = (uint8_t)(subcmd & 0xFF); - uint8_t msb = (uint8_t)((subcmd >> 8) & 0xFF); - uint8_t check_lsb=0, check_msb=0; - - - - if (!WriteReg(0x3E, lsb)) - return false; - if (!WriteReg(0x3F, msb)) - return false; - - do{ - ReadReg(0x3E, &check_lsb); - ReadReg(0x3F, &check_msb); - }while ((check_lsb != lsb) || (check_msb != msb)); - - for (uint8_t i=0; i> 8); - uint8_t echo_l = 0xFF, echo_h = 0xFF; + if (length > 32) + length = 32; - if (!WriteReg(0x3E, lsb)) - return false; - if (!WriteReg(0x3F, msb)) + // Write subcommand (0x3E LSB, 0x3F MSB) in one frame + uint8_t sub[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) }; + if (!write_reg(0x3E, sub, 2)) return false; + // Poll for echo of 0x3E/0x3F (in as few frames as possible) + uint8_t echo[2] = {0xFF, 0xFF}; uint32_t tries = 0; - do{ - if (!ReadReg(0x3E,&echo_l)) - return false; - if (!ReadReg(0x3F,&echo_h)) + do { + if (!read_reg(0x3E, echo, 2)) return false; if (++tries > BQ_SUBCMD_MAX_POLLS) return false; - } while ((echo_l == 0xFF && echo_h == 0xFF) || (echo_l != lsb) || (echo_h != msb)); + } while ((echo[0] == 0xFF && echo[1] == 0xFF) || echo[0] != sub[0] || echo[1] != sub[1]); + // Read full buffer 0x40..0x61 (34 bytes) in one frame uint8_t buf[34]; - for (uint8_t off = 0; off<=(0x61 - 0x40); off++){ - if(!ReadReg((uint8_t)(0x40 + off), &buf[off])) - return false; - } + if (!read_reg(0x40, buf, sizeof(buf))) + return false; - uint8_t len_total=buf[0x61-0x40]; - if(len_total < 4) + uint8_t len_total = buf[0x61 - 0x40]; + if (len_total < 4) // must include 0x3E,0x3F,0x60,0x61 => 4 minimum return false; + uint8_t buf_len = (uint8_t)(len_total - 4); if (buf_len > 32) buf_len = 32; - uint8_t to_copy = (buf_len < length) ? buf_len : length; - for (uint8_t i=0; i32) + if (length > 32) return false; - uint8_t lsb=(uint8_t)(subcmd & 0xFF); - uint8_t msb=(uint8_t)((subcmd >> 8) & 0xFF); - - - if (!WriteReg(0x3E, lsb)) + // Subcommand in one frame + uint8_t sub[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) }; + if (!write_reg(0x3E, sub, 2)) return false; - if (!WriteReg(0x3F, msb)) + + // Write payload 0x40.. in one frame + if (length > 0 && !write_reg(0x40, data, length)) return false; - uint8_t sum = (uint8_t)(lsb + msb); - for (uint8_t i=0; i 110) cov_val = 110; - BQ_WriteSubCommand(COV_THRESHOLD_ADDR, &cov_val, 1); + bq_write_subcommand(COV_THRESHOLD_ADDR, &cov_val, 1); uint16_t cov_delay_ticks = (uint16_t)(COV_DELAY_MS / 3.3f + 0.5f); uint8_t cov_delay_bytes[2] = { (uint8_t)(cov_delay_ticks & 0xFF), (uint8_t)((cov_delay_ticks >> 8) & 0xFF) }; - BQ_WriteSubCommand(COV_DELAY_ADDR, cov_delay_bytes, 2); + bq_write_subcommand(COV_DELAY_ADDR, cov_delay_bytes, 2); uint8_t cuv_val = (uint8_t)(CUV_THRESHOLD_MV / 50.6f + 0.5f); if (cuv_val < 20) cuv_val = 20; if (cuv_val > 110) cuv_val = 110; - BQ_WriteSubCommand(CUV_THRESHOLD_ADDR, &cuv_val, 1); + bq_write_subcommand(CUV_THRESHOLD_ADDR, &cuv_val, 1); uint16_t cuv_delay_ticks = (uint16_t)(CUV_DELAY_MS / 3.3f + 0.5f); uint8_t cuv_delay_bytes[2] = { (uint8_t)(cuv_delay_ticks & 0xFF), (uint8_t)((cuv_delay_ticks >> 8) & 0xFF) }; - BQ_WriteSubCommand(CUV_DELAY_ADDR, cuv_delay_bytes, 2); + bq_write_subcommand(CUV_DELAY_ADDR, cuv_delay_bytes, 2); - BQ_CommandOnly(EXIT_CONFIG_UPDATE); + bq_command_only(EXIT_CONFIG_UPDATE); } -void BMS_BATTERY_STATUS(void){ +void bms_battery_status(void){ uint8_t fetReg=0; - if(!BQ_DirectRead(FET_STATUS, &fetReg, 1)){ + if(!bq_direct_read(FET_STATUS, &fetReg, 1)){ printf("Failed to read FET status\n"); return; } @@ -341,7 +280,7 @@ void BMS_BATTERY_STATUS(void){ } -void Read_Cells_1to6(){ +void read_cells_1to6(){ const uint8_t CellVoltageAddr[6]={CELL_1_VOLTAGE, CELL_2_VOLTAGE, CELL_3_VOLTAGE, CELL_4_VOLTAGE, CELL_5_VOLTAGE, CELL_6_VOLTAGE}; uint16_t raw = 0; @@ -349,7 +288,7 @@ void Read_Cells_1to6(){ uint8_t i = 0; for (i=0; i<6; i++){ - if (BQ_DirectCommand(CellVoltageAddr[i], &raw , R)) + if (bq_direct_command(CellVoltageAddr[i], &raw , R)) { voltage = raw*0.001f; // Convert mV to V printf("Cell %u Voltage: %.3f V\n", i+1, voltage); diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index 8f9d4215..c9a7cfc9 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -6,7 +6,7 @@ -//Direct Commands +//direct commands #define BATTERY_STATUS 0x12 #define STACK_VOLTAGE 0x34 @@ -33,11 +33,11 @@ */ // 16 cell voltage readings avaliable -#define BQ_CS_GROUP (0U) -#define BQ_CS_MASK (1UL << 18) +#define bq_cs_group (0U) +#define bq_cs_mask (1UL << 18) -#define R 0 // Read; Used in DirectCommands and Subcommands functions -#define W 1 // Write; Used in DirectCommands and Subcommands functions +#define R 0 // Read; Used in directcommands and Subcommands functions +#define W 1 // Write; Used in directcommands and Subcommands functions #define BQ_SUBCMD_MAX_POLLS 2000u @@ -48,7 +48,7 @@ #define THERMISOR_TEMP 0x6A #define INTERNAL_TEMP 0x68 -//Command only (R) +//command only (R) #define RESET 0x0012 #define SHUTDOWN 0x0010 @@ -75,18 +75,18 @@ /* Minimal driver: only SPI+CS bring-up */ -void BQ76942_Init(void); -bool WriteReg(uint8_t regAddr, uint8_t value); -bool ReadReg(uint8_t regAddr, uint8_t *value); -bool BQ_DirectCommand(uint8_t command, uint16_t *data, char type); -bool BQ_CommandOnly(uint16_t subcmd); -bool BQ_DirectRead(uint8_t command, uint8_t *data, uint8_t count); -bool BQ_DirectWrite(uint8_t command, const uint8_t *data, uint8_t count); -bool BQ_ReadSubCommand(uint16_t subcmd, uint8_t *data, uint8_t length); -bool BQ_WriteSubCommand(uint16_t subcmd, const uint8_t *data, uint8_t length); -void BMS_SetProtectionThresholds(void); -void BMS_BATTERY_STATUS(void); -void Read_Cells_1to6(void); +void bq76942_init(void); +bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length); +bool read_reg(uint8_t regAddr, uint8_t *data, uint8_t length); +bool bq_direct_command(uint8_t command, uint16_t *data, char type); +bool bq_command_only(uint16_t subcmd); +bool bq_direct_read(uint8_t command, uint8_t *data, uint8_t count); +bool bq_direct_write(uint8_t command, const uint8_t *data, uint8_t count); +bool bq_read_subcommand(uint16_t subcmd, uint8_t *data, uint8_t length); +bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length); +void bms_set_protection_threshold(void); +void bms_battery_status(void); +void read_cells_1to6(void); @@ -95,4 +95,4 @@ void Read_Cells_1to6(void); -#endif /* BQ76942_H */ +#endif /* bq76942_H */ diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 04254154..4394f6e9 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -50,11 +50,10 @@ int main ( void ) /* Initialize all modules */ SYS_Initialize ( NULL ); - BQ76942_Init(); - BMS_SetProtectionThresholds(); - - Read_Cells_1to6(); - BMS_BATTERY_STATUS(); + bq76942_init(); + bms_set_protection_threshold(); + read_cells_1to6(); + bms_battery_status(); _delay(10000); //wait 1 second From 92e2e6905d47f39581048dc02a31db6ce1ae945e Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Wed, 12 Nov 2025 15:54:53 +0100 Subject: [PATCH 17/30] feat: added CRC to write/read reg func, updated void bq76942_Init(void) --- bms/bms/bms_config/src/ic_bms/bms_spi.c | 121 ++- .../bms_config/src/ic_bms/main_STM32_SPI.c | 955 ------------------ bms/bms/bms_config/src/main.c | 3 +- 3 files changed, 96 insertions(+), 983 deletions(-) delete mode 100644 bms/bms/bms_config/src/ic_bms/main_STM32_SPI.c diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index ab851f77..8f4888a2 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -19,17 +19,26 @@ static inline void _delay(uint32_t cycles){ } -//SPI + set CS high -void bq76942_init(void) +void bq76942_Init(void) { - // init SPI - SERCOM0_SPI_Initialize(); - - // configure CS pin as output and set HIGH (inactive) + // --- Chip select pin setup --- PORT_REGS->GROUP[bq_cs_group].PORT_DIRSET = bq_cs_mask; - PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; + PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; // Set HIGH (inactive) + + // --- IC configuration sequence --- + bq_command_only(ENTER_CONFIG_UPDATE); + bms_set_protection_threshold(); + bq_command_only(EXIT_CONFIG_UPDATE); + + // Status check + uint8_t status = 0; + if (bq_direct_read(0x12, &status, 1)) + printf("BQ76942 communication OK\n"); + else + printf("BQ76942 communication failed\n"); } + bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) { if (SERCOM0_SPI_IsBusy()) @@ -42,49 +51,106 @@ bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) return ok; } +static uint8_t bq_crc8_calc(const uint8_t *data, uint8_t len) +{ + uint8_t crc = 0x00; // init + + for (uint8_t i = 0; i < len; i++) { + + crc ^= data[i]; // XOR in next byte + for (uint8_t b = 0; b < 8; b++) { + if (crc & 0x80) // test MSB + crc = (uint8_t)((crc << 1) ^ 0x07); + else + crc <<= 1; + } + } + return crc; +} + + bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length) { if (SERCOM0_SPI_IsBusy()) return false; + if (length == 0) + return true; - uint8_t tx[length + 1]; - tx[0] = 0x80 | (regAddr & 0x7F); // Write flag + address - memcpy(&tx[1], data, length); //(memcpy (dest, src, length)) - - bq_cs_low(); - bool ok = SERCOM0_SPI_Write(tx,length +1); - bq_cs_high(); + // Pack back-to-back 24-bit frames: [cmd, data_byte, crc] * length + uint8_t tx_bytes[3 * length]; + + for (uint8_t i=0;i
© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.
- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -// BQ76952EVM demo code for STM32 NUCLEO-F103RB + BQ76952EVM -// -// Connection description: The SCLK, MISO, MOSI, and CS pins are the only pin connections required between the -// NUCLEO board and the BQ76952EVM for this demo code. Also a ground connection should be made between the 2 boards. -// The ALERT, RST_SHUT, and DFETOFF pins are also configured on the MCU and can be used as shown. -// -// -// STM32 -// ----------------- -// | PB3 |---------- SCLK -// | | -// | PB4 |---------- MISO -// | | -// DFETOFF ---| PA8 PB5 |---------- MOSI -// | | -// RST_SHUT ---| PA9 PB6 |---------- CS -// | | -// ALERT ---| PA10 |--- Green LED -// | | - - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -#include -#include "BQ769x2Header.h" -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ -#define DEV_ADDR 0x10 // BQ769x2 address is 0x10 including R/W bit or 0x8 as 7-bit address -#define CRC_Mode 0 // 0 for disabled, 1 for enabled -#define MAX_BUFFER_SIZE 10 -#define R 0 // Read; Used in DirectCommands and Subcommands functions -#define W 1 // Write; Used in DirectCommands and Subcommands functions -#define W2 2 // Write data with two bytes; Used in Subcommands function -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -SPI_HandleTypeDef hspi1; - -TIM_HandleTypeDef htim1; - -UART_HandleTypeDef huart2; - -/* USER CODE BEGIN PV */ -uint8_t rxdata [2]; -uint8_t RX_data [2] = {0x00, 0x00}; // used in several functions to store data read from BQ769x2 -uint8_t RX_32Byte [32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - //used in Subcommands read function -// Global Variables for cell voltages, temperatures, Stack voltage, PACK Pin voltage, LD Pin voltage, CC2 current -uint16_t CellVoltage [16] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; -float Temperature [3] = {0,0,0}; -uint16_t Stack_Voltage = 0x00; -uint16_t Pack_Voltage = 0x00; -uint16_t LD_Voltage = 0x00; -uint16_t Pack_Current = 0x00; - -uint16_t AlarmBits = 0x00; -uint8_t value_SafetyStatusA; // Safety Status Register A -uint8_t value_SafetyStatusB; // Safety Status Register B -uint8_t value_SafetyStatusC; // Safety Status Register C -uint8_t value_PFStatusA; // Permanent Fail Status Register A -uint8_t value_PFStatusB; // Permanent Fail Status Register B -uint8_t value_PFStatusC; // Permanent Fail Status Register C -uint8_t FET_Status; // FET Status register contents - Shows states of FETs -uint16_t CB_ActiveCells; // Cell Balancing Active Cells - -uint8_t UV_Fault = 0; // under-voltage fault state -uint8_t OV_Fault = 0; // over-voltage fault state -uint8_t SCD_Fault = 0; // short-circuit fault state -uint8_t OCD_Fault = 0; // over-current fault state -uint8_t ProtectionsTriggered = 0; // Set to 1 if any protection triggers - -uint8_t LD_ON = 0; // Load Detect status bit -uint8_t DSG = 0; // discharge FET state -uint8_t CHG = 0; // charge FET state -uint8_t PCHG = 0; // pre-charge FET state -uint8_t PDSG = 0; // pre-discharge FET state - -uint32_t AccumulatedCharge_Int; // in BQ769x2_READPASSQ func -uint32_t AccumulatedCharge_Frac;// in BQ769x2_READPASSQ func -uint32_t AccumulatedCharge_Time;// in BQ769x2_READPASSQ func -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_SPI1_Init(void); -static void MX_USART2_UART_Init(void); -static void MX_TIM1_Init(void); -/* USER CODE BEGIN PFP */ -void delayUS(uint32_t us) { // Sets the delay in microseconds. - __HAL_TIM_SET_COUNTER(&htim1,0); // set the counter value a 0 - while (__HAL_TIM_GET_COUNTER(&htim1) < us); // wait for the counter to reach the us input in the parameter -} - -void CopyArray(uint8_t *source, uint8_t *dest, uint8_t count) -{ - uint8_t copyIndex = 0; - for (copyIndex = 0; copyIndex < count; copyIndex++) - { - dest[copyIndex] = source[copyIndex]; - } -} - -unsigned char Checksum(unsigned char *ptr, unsigned char len) -// Calculates the checksum when writing to a RAM register. The checksum is the inverse of the sum of the bytes. -{ - unsigned char i; - unsigned char checksum = 0; - - for(i=0; i 0)) { - delayUS(500); - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); - HAL_SPI_TransmitReceive(&hspi1, TX_Buffer, rxdata, 2, 1); - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); - if ((rxdata[0] == addr) & (rxdata[1] == reg_data[i])) - match = 1; - retries --; - } - match = 0; - addr += 1; - delayUS(500); - } -} - - -void SPI_ReadReg(uint8_t reg_addr, uint8_t *reg_data, uint8_t count) { - // SPI Read. Includes retries in case HFO has not started or if wait time is needed. See BQ76952 Software Development Guide for examples - uint8_t addr; - uint8_t TX_Buffer [MAX_BUFFER_SIZE] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; - unsigned int i; - unsigned int match; - unsigned int retries = 10; - - match = 0; - addr = reg_addr; - - for(i=0; i 0)) { - delayUS(500); - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); - HAL_SPI_TransmitReceive(&hspi1, TX_Buffer, rxdata, 2, 1); - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); - if (rxdata[0] == addr) { - match = 1; - reg_data[i] = rxdata[1]; - } - retries --; - } - match = 0; - addr += 1; - delayUS(500); - } -} - -void BQ769x2_SetRegister(uint16_t reg_addr, uint32_t reg_data, uint8_t datalen) -{ - uint8_t TX_Buffer[2] = {0x00, 0x00}; - uint8_t TX_RegData[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - - //TX_RegData in little endian format - TX_RegData[0] = reg_addr & 0xff; - TX_RegData[1] = (reg_addr >> 8) & 0xff; - TX_RegData[2] = reg_data & 0xff; //1st byte of data - - switch(datalen) - { - case 1: //1 byte datalength - SPI_WriteReg(0x3E, TX_RegData, 3); - delayUS(2000); - TX_Buffer[0] = Checksum(TX_RegData, 3); - TX_Buffer[1] = 0x05; //combined length of register address and data - SPI_WriteReg(0x60, TX_Buffer, 2); // Write the checksum and length - delayUS(2000); - break; - case 2: //2 byte datalength - TX_RegData[3] = (reg_data >> 8) & 0xff; - SPI_WriteReg(0x3E, TX_RegData, 4); - delayUS(2000); - TX_Buffer[0] = Checksum(TX_RegData, 4); - TX_Buffer[1] = 0x06; //combined length of register address and data - SPI_WriteReg(0x60, TX_Buffer, 2); // Write the checksum and length - delayUS(2000); - break; - case 4: //4 byte datalength, Only used for CCGain and Capacity Gain - TX_RegData[3] = (reg_data >> 8) & 0xff; - TX_RegData[4] = (reg_data >> 16) & 0xff; - TX_RegData[5] = (reg_data >> 24) & 0xff; - SPI_WriteReg(0x3E, TX_RegData, 6); - delayUS(2000); - TX_Buffer[0] = Checksum(TX_RegData, 6); - TX_Buffer[1] = 0x08; //combined length of register address and data - SPI_WriteReg(0x60, TX_Buffer, 2); // Write the checksum and length - delayUS(2000); - break; - } -} - -void CommandSubcommands(uint16_t command) //For Command only Subcommands -// See the TRM or the BQ76952 header file for a full list of Command-only subcommands -{ //For DEEPSLEEP/SHUTDOWN subcommand you will need to call this function twice consecutively - - uint8_t TX_Reg[2] = {0x00, 0x00}; - - //TX_Reg in little endian format - TX_Reg[0] = command & 0xff; - TX_Reg[1] = (command >> 8) & 0xff; - - SPI_WriteReg(0x3E,TX_Reg,2); - delayUS(2000); -} - -void Subcommands(uint16_t command, uint16_t data, uint8_t type) -// See the TRM or the BQ76952 header file for a full list of Subcommands -{ - //security keys and Manu_data writes dont work with this function (reading these commands works) - //max readback size is 32 bytes i.e. DASTATUS, CUV/COV snapshot - uint8_t TX_Reg[4] = {0x00, 0x00, 0x00, 0x00}; - uint8_t TX_Buffer[2] = {0x00, 0x00}; - - //TX_Reg in little endian format - TX_Reg[0] = command & 0xff; - TX_Reg[1] = (command >> 8) & 0xff; - - if (type == R) {//read - SPI_WriteReg(0x3E,TX_Reg,2); - delayUS(2000); - SPI_ReadReg(0x40, RX_32Byte, 32); //RX_32Byte is a global variable - } - else if (type == W) { - //FET_Control, REG12_Control - TX_Reg[2] = data & 0xff; - SPI_WriteReg(0x3E,TX_Reg,3); - delayUS(1000); - TX_Buffer[0] = Checksum(TX_Reg, 3); - TX_Buffer[1] = 0x05; //combined length of registers address and data - SPI_WriteReg(0x60, TX_Buffer, 2); - delayUS(1000); - } - else if (type == W2){ //write data with 2 bytes - //CB_Active_Cells, CB_SET_LVL - TX_Reg[2] = data & 0xff; - TX_Reg[3] = (data >> 8) & 0xff; - SPI_WriteReg(0x3E,TX_Reg,4); - delayUS(1000); - TX_Buffer[0] = Checksum(TX_Reg, 4); - TX_Buffer[1] = 0x06; //combined length of registers address and data - SPI_WriteReg(0x60, TX_Buffer, 2); - delayUS(1000); - } -} - -void DirectCommands(uint8_t command, uint16_t data, uint8_t type) -// See the TRM or the BQ76952 header file for a full list of Direct Commands -{ //type: R = read, W = write - uint8_t TX_data[2] = {0x00, 0x00}; - - //little endian format - TX_data[0] = data & 0xff; - TX_data[1] = (data >> 8) & 0xff; - - if (type == R) {//Read - SPI_ReadReg(command, RX_data, 2); //RX_data is a global variable - delayUS(2000); - } - if (type == W) {//write - //Control_status, alarm_status, alarm_enable all 2 bytes long - SPI_WriteReg(command,TX_data,2); - delayUS(2000); - } -} - -void BQ769x2_Init() { - // Configures all parameters in device RAM - - // Enter CONFIGUPDATE mode (Subcommand 0x0090) - It is required to be in CONFIG_UPDATE mode to program the device RAM settings - // See TRM for full description of CONFIG_UPDATE mode - CommandSubcommands(SET_CFGUPDATE); - - // After entering CONFIG_UPDATE mode, RAM registers can be programmed. When programming RAM, checksum and length must also be - // programmed for the change to take effect. All of the RAM registers are described in detail in the BQ769x2 TRM. - // An easier way to find the descriptions is in the BQStudio Data Memory screen. When you move the mouse over the register name, - // a full description of the register and the bits will pop up on the screen. - - // 'Power Config' - 0x9234 = 0x2D80 - // Setting the DSLP_LDO bit allows the LDOs to remain active when the device goes into Deep Sleep mode - // Set wake speed bits to 00 for best performance - BQ769x2_SetRegister(PowerConfig, 0x2D80, 2); - - // 'REG0 Config' - set REG0_EN bit to enable pre-regulator - BQ769x2_SetRegister(REG0Config, 0x01, 1); - - // 'REG12 Config' - Enable REG1 with 3.3V output (0x0D for 3.3V, 0x0F for 5V) - BQ769x2_SetRegister(REG12Config, 0x0D, 1); - - // Set DFETOFF pin to control BOTH CHG and DSG FET - 0x92FB = 0x42 (set to 0x00 to disable) - BQ769x2_SetRegister(DFETOFFPinConfig, 0x42, 1); - - // Set up ALERT Pin - 0x92FC = 0x2A - // This configures the ALERT pin to drive high (REG1 voltage) when enabled. - // The ALERT pin can be used as an interrupt to the MCU when a protection has triggered or new measurements are available - BQ769x2_SetRegister(ALERTPinConfig, 0x2A, 1); - - // Set TS1 to measure Cell Temperature - 0x92FD = 0x07 - BQ769x2_SetRegister(TS1Config, 0x07, 1); - - // Set TS3 to measure FET Temperature - 0x92FF = 0x0F - BQ769x2_SetRegister(TS3Config, 0x0F, 1); - - // Set HDQ to measure Cell Temperature - 0x9300 = 0x07 - BQ769x2_SetRegister(HDQPinConfig, 0x00, 1); // No thermistor installed on EVM HDQ pin, so set to 0x00 - - // 'VCell Mode' - Enable 16 cells - 0x9304 = 0x0000; Writing 0x0000 sets the default of 16 cells - BQ769x2_SetRegister(VCellMode, 0x0000, 2); - - // Enable protections in 'Enabled Protections A' 0x9261 = 0xBC - // Enables SCD (short-circuit), OCD1 (over-current in discharge), OCC (over-current in charge), - // COV (over-voltage), CUV (under-voltage) - BQ769x2_SetRegister(EnabledProtectionsA, 0xBC, 1); - - // Enable all protections in 'Enabled Protections B' 0x9262 = 0xF7 - // Enables OTF (over-temperature FET), OTINT (internal over-temperature), OTD (over-temperature in discharge), - // OTC (over-temperature in charge), UTINT (internal under-temperature), UTD (under-temperature in discharge), UTC (under-temperature in charge) - BQ769x2_SetRegister(EnabledProtectionsB, 0xF7, 1); - - // 'Default Alarm Mask' - 0x..82 Enables the FullScan and ADScan bits, default value = 0xF800 - BQ769x2_SetRegister(DefaultAlarmMask, 0xF882, 2); - - // Set up Cell Balancing Configuration - 0x9335 = 0x03 - Automated balancing while in Relax or Charge modes - // Also see "Cell Balancing with BQ769x2 Battery Monitors" document on ti.com - BQ769x2_SetRegister(BalancingConfiguration, 0x03, 1); - - // Set up CUV (under-voltage) Threshold - 0x9275 = 0x31 (2479 mV) - // CUV Threshold is this value multiplied by 50.6mV - BQ769x2_SetRegister(CUVThreshold, 0x31, 1); - - // Set up COV (over-voltage) Threshold - 0x9278 = 0x55 (4301 mV) - // COV Threshold is this value multiplied by 50.6mV - BQ769x2_SetRegister(COVThreshold, 0x55, 1); - - // Set up OCC (over-current in charge) Threshold - 0x9280 = 0x05 (10 mV = 10A across 1mOhm sense resistor) Units in 2mV - BQ769x2_SetRegister(OCCThreshold, 0x05, 1); - - // Set up OCD1 Threshold - 0x9282 = 0x0A (20 mV = 20A across 1mOhm sense resistor) units of 2mV - BQ769x2_SetRegister(OCD1Threshold, 0x0A, 1); - - // Set up SCD Threshold - 0x9286 = 0x05 (100 mV = 100A across 1mOhm sense resistor) 0x05=100mV - BQ769x2_SetRegister(SCDThreshold, 0x05, 1); - - // Set up SCD Delay - 0x9287 = 0x03 (30 us) Enabled with a delay of (value - 1) * 15 �s; min value of 1 - BQ769x2_SetRegister(SCDDelay, 0x03, 1); - - // Set up SCDL Latch Limit to 1 to set SCD recovery only with load removal 0x9295 = 0x01 - // If this is not set, then SCD will recover based on time (SCD Recovery Time parameter). - BQ769x2_SetRegister(SCDLLatchLimit, 0x01, 1); - - // Exit CONFIGUPDATE mode - Subcommand 0x0092 - CommandSubcommands(EXIT_CFGUPDATE); -} - -// ********************************* FET Control Commands *************************************** - -void BQ769x2_BOTHOFF () { - // Disables all FETs using the DFETOFF (BOTHOFF) pin - // The DFETOFF pin on the BQ76952EVM should be connected to the MCU board to use this function - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); // DFETOFF pin (BOTHOFF) set high -} - -void BQ769x2_RESET_BOTHOFF () { - // Resets DFETOFF (BOTHOFF) pin - // The DFETOFF pin on the BQ76952EVM should be connected to the MCU board to use this function - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); // DFETOFF pin (BOTHOFF) set low -} - -void BQ769x2_ReadFETStatus() { - // Read FET Status to see which FETs are enabled - DirectCommands(FETStatus, 0x00, R); - FET_Status = (RX_data[1]*256 + RX_data[0]); - DSG = ((0x4 & RX_data[0])>>2);// discharge FET state - CHG = (0x1 & RX_data[0]);// charge FET state - PCHG = ((0x2 & RX_data[0])>>1);// pre-charge FET state - PDSG = ((0x8 & RX_data[0])>>3);// pre-discharge FET state -} - -// ********************************* End of FET Control Commands ********************************* - -// ********************************* BQ769x2 Power Commands ***************************************** - -void BQ769x2_ShutdownPin() { - // Puts the device into SHUTDOWN mode using the RST_SHUT pin - // The RST_SHUT pin on the BQ76952EVM should be connected to the MCU board to use this function - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET); // Sets RST_SHUT pin -} - -void BQ769x2_ReleaseShutdownPin() { - // Releases the RST_SHUT pin - // The RST_SHUT pin on the BQ76952EVM should be connected to the MCU board to use this function - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET); // Resets RST_SHUT pin -} - -// ********************************* End of BQ769x2 Power Commands ***************************************** - - -// ********************************* BQ769x2 Status and Fault Commands ***************************************** - -uint16_t BQ769x2_ReadAlarmStatus() { - // Read this register to find out why the ALERT pin was asserted - DirectCommands(AlarmStatus, 0x00, R); - return (RX_data[1]*256 + RX_data[0]); -} - -void BQ769x2_ReadSafetyStatus() { //good example functions - // Read Safety Status A/B/C and find which bits are set - // This shows which primary protections have been triggered - DirectCommands(SafetyStatusA, 0x00, R); - value_SafetyStatusA = (RX_data[1]*256 + RX_data[0]); - //Example Fault Flags - UV_Fault = ((0x4 & RX_data[0])>>2); - OV_Fault = ((0x8 & RX_data[0])>>3); - SCD_Fault = ((0x8 & RX_data[1])>>3); - OCD_Fault = ((0x2 & RX_data[1])>>1); - DirectCommands(SafetyStatusB, 0x00, R); - value_SafetyStatusB = (RX_data[1]*256 + RX_data[0]); - DirectCommands(SafetyStatusC, 0x00, R); - value_SafetyStatusC = (RX_data[1]*256 + RX_data[0]); - if ((value_SafetyStatusA + value_SafetyStatusB + value_SafetyStatusC) > 1) { - ProtectionsTriggered = 1; } - else { - ProtectionsTriggered = 0; } -} - -void BQ769x2_ReadPFStatus() { - // Read Permanent Fail Status A/B/C and find which bits are set - // This shows which permanent failures have been triggered - DirectCommands(PFStatusA, 0x00, R); - value_PFStatusA = (RX_data[1]*256 + RX_data[0]); - DirectCommands(PFStatusB, 0x00, R); - value_PFStatusB = (RX_data[1]*256 + RX_data[0]); - DirectCommands(PFStatusC, 0x00, R); - value_PFStatusC = (RX_data[1]*256 + RX_data[0]); -} - -// ********************************* End of BQ769x2 Status and Fault Commands ***************************************** - - -// ********************************* BQ769x2 Measurement Commands ***************************************** - - -uint16_t BQ769x2_ReadVoltage(uint8_t command) -// This function can be used to read a specific cell voltage or stack / pack / LD voltage -{ - //RX_data is global var - DirectCommands(command, 0x00, R); - if(command >= Cell1Voltage && command <= Cell16Voltage) {//Cells 1 through 16 (0x14 to 0x32) - return (RX_data[1]*256 + RX_data[0]); //voltage is reported in mV - } - else {//stack, Pack, LDCommand - return 10 * (RX_data[1]*256 + RX_data[0]); //voltage is reported in 0.01V units - } - -} -void BQ769x2_ReadAllVoltages() -// Reads all cell voltages, Stack voltage, PACK pin voltage, and LD pin voltage -{ - int cellvoltageholder = Cell1Voltage; //Cell1Voltage is 0x14 - for (int x = 0; x < 16; x++){//Reads all cell voltages - CellVoltage[x] = BQ769x2_ReadVoltage(cellvoltageholder); - cellvoltageholder = cellvoltageholder + 2; - } - Stack_Voltage = BQ769x2_ReadVoltage(StackVoltage); - Pack_Voltage = BQ769x2_ReadVoltage(PACKPinVoltage); - LD_Voltage = BQ769x2_ReadVoltage(LDPinVoltage); -} - -uint16_t BQ769x2_ReadCurrent() -// Reads PACK current -{ - DirectCommands(CC2Current, 0x00, R); - return (RX_data[1]*256 + RX_data[0]); // current is reported in mA -} - -float BQ769x2_ReadTemperature(uint8_t command) -{ - DirectCommands(command, 0x00, R); - //RX_data is a global var - return (0.1 * (float)(RX_data[1]*256 + RX_data[0])) - 273.15; // converts from 0.1K to Celcius -} - -void BQ769x2_ReadPassQ(){ // Read Accumulated Charge and Time from DASTATUS6 - Subcommands(DASTATUS6, 0x00, R); - AccumulatedCharge_Int = ((RX_32Byte[3]<<24) + (RX_32Byte[2]<<16) + (RX_32Byte[1]<<8) + RX_32Byte[0]); //Bytes 0-3 - AccumulatedCharge_Frac = ((RX_32Byte[7]<<24) + (RX_32Byte[6]<<16) + (RX_32Byte[5]<<8) + RX_32Byte[4]); //Bytes 4-7 - AccumulatedCharge_Time = ((RX_32Byte[11]<<24) + (RX_32Byte[10]<<16) + (RX_32Byte[9]<<8) + RX_32Byte[8]); //Bytes 8-11 -} - -// ********************************* End of BQ769x2 Measurement Commands ***************************************** - - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_SPI1_Init(); - MX_USART2_UART_Init(); - MX_TIM1_Init(); - /* USER CODE BEGIN 2 */ - // Start timer - HAL_TIM_Base_Start(&htim1); - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); // SPI_CS pin set high - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET); // RST_SHUT pin set low - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); // DFETOFF pin (BOTHOFF) set low - delayUS(10000); - - CommandSubcommands(BQ769x2_RESET); // Resets the BQ769x2 registers - delayUS(60000); - BQ769x2_Init(); // Configure all of the BQ769x2 register settings - delayUS(10000); - CommandSubcommands(FET_ENABLE); // Enable the CHG and DSG FETs - delayUS(10000); - CommandSubcommands(SLEEP_DISABLE); // Sleep mode is enabled by default. For this example, Sleep is disabled to - // demonstrate full-speed measurements in Normal mode. - - delayUS(60000); delayUS(60000); delayUS(60000); delayUS(60000); //wait to start measurements after FETs close - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - - //Reads Cell, Stack, Pack, LD Voltages, Pack Current and TS1/TS3 Temperatures in a loop - //This basic example polls the Alarm Status register to see if protections have triggered or new measurements are ready - //The ALERT pin can also be used as an interrupt to the microcontroller for fastest response time instead of polling - //In this example the LED on the microcontroller board will be turned on to indicate a protection has triggered and will - //be turned off if the protection condition has cleared. - - AlarmBits = BQ769x2_ReadAlarmStatus(); - if (AlarmBits & 0x80) { // Check if FULLSCAN is complete. If set, new measurements are available - BQ769x2_ReadAllVoltages(); - Pack_Current = BQ769x2_ReadCurrent(); - Temperature[0] = BQ769x2_ReadTemperature(TS1Temperature); - Temperature[1] = BQ769x2_ReadTemperature(TS3Temperature); - DirectCommands(AlarmStatus, 0x0080, W); // Clear the FULLSCAN bit - } - - if (AlarmBits & 0xC000) { // If Safety Status bits are showing in AlarmStatus register - BQ769x2_ReadSafetyStatus(); // Read the Safety Status registers to find which protections have triggered - if (ProtectionsTriggered & 1) { - HAL_GPIO_WritePin(GPIOA, LD2_Pin, GPIO_PIN_SET); }// Turn on the LED to indicate Protection has triggered - DirectCommands(AlarmStatus, 0xF800, W); // Clear the Safety Status Alarm bits. - } - else - { - if (ProtectionsTriggered & 1) { - BQ769x2_ReadSafetyStatus(); - if (!(ProtectionsTriggered & 1)) - { - HAL_GPIO_WritePin(GPIOA, LD2_Pin, GPIO_PIN_RESET); - } - } // Turn off the LED if Safety Status has cleared which means the protection condition is no longer present - } - delayUS(20000); // repeat loop every 20 ms - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL8; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief SPI1 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI1_Init(void) -{ - - /* USER CODE BEGIN SPI1_Init 0 */ - - /* USER CODE END SPI1_Init 0 */ - - /* USER CODE BEGIN SPI1_Init 1 */ - - /* USER CODE END SPI1_Init 1 */ - hspi1.Instance = SPI1; - hspi1.Init.Mode = SPI_MODE_MASTER; - hspi1.Init.Direction = SPI_DIRECTION_2LINES; - hspi1.Init.DataSize = SPI_DATASIZE_8BIT; - hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; - hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; - hspi1.Init.NSS = SPI_NSS_SOFT; - hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64; - hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; - hspi1.Init.TIMode = SPI_TIMODE_DISABLE; - hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_ENABLE; - hspi1.Init.CRCPolynomial = 7; - if (HAL_SPI_Init(&hspi1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SPI1_Init 2 */ - - /* USER CODE END SPI1_Init 2 */ - -} - -/** - * @brief TIM1 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM1_Init(void) -{ - - /* USER CODE BEGIN TIM1_Init 0 */ - - /* USER CODE END TIM1_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM1_Init 1 */ - - /* USER CODE END TIM1_Init 1 */ - htim1.Instance = TIM1; - htim1.Init.Prescaler = 63; - htim1.Init.CounterMode = TIM_COUNTERMODE_UP; - htim1.Init.Period = 65535; - htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim1.Init.RepetitionCounter = 0; - htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim1) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM1_Init 2 */ - - /* USER CODE END TIM1_Init 2 */ - -} - -/** - * @brief USART2 Initialization Function - * @param None - * @retval None - */ -static void MX_USART2_UART_Init(void) -{ - - /* USER CODE BEGIN USART2_Init 0 */ - - /* USER CODE END USART2_Init 0 */ - - /* USER CODE BEGIN USART2_Init 1 */ - - /* USER CODE END USART2_Init 1 */ - huart2.Instance = USART2; - huart2.Init.BaudRate = 115200; - huart2.Init.WordLength = UART_WORDLENGTH_8B; - huart2.Init.StopBits = UART_STOPBITS_1; - huart2.Init.Parity = UART_PARITY_NONE; - huart2.Init.Mode = UART_MODE_TX_RX; - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART2_Init 2 */ - - /* USER CODE END USART2_Init 2 */ - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOA, LD2_Pin|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10, GPIO_PIN_RESET); - - /*Configure GPIO pin : B1_Pin */ - GPIO_InitStruct.Pin = B1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : LD2_Pin PA8 PA9 PA10 */ - GPIO_InitStruct.Pin = LD2_Pin|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pin : PB6 */ - GPIO_InitStruct.Pin = GPIO_PIN_6; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* EXTI interrupt init*/ - HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); - -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 4394f6e9..49849dea 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -54,7 +54,8 @@ int main ( void ) bms_set_protection_threshold(); read_cells_1to6(); bms_battery_status(); - _delay(10000); //wait 1 second + + From 7de7f88a873cf98b1c03effa637c27d01516c61a Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 22 Jan 2026 14:54:03 +0100 Subject: [PATCH 18/30] feat: add temperature sampling functions and SPI link test --- bms/bms/bms_config/src/ic_bms/bms_spi.h | 6 ++- bms/bms/bms_config/src/ic_bms/spi_link_test.c | 45 +++++++++++++++++++ bms/bms/bms_config/src/ic_bms/spi_link_test.h | 6 +++ bms/bms/bms_config/src/main.c | 9 ++-- 4 files changed, 59 insertions(+), 7 deletions(-) create mode 100644 bms/bms/bms_config/src/ic_bms/spi_link_test.c create mode 100644 bms/bms/bms_config/src/ic_bms/spi_link_test.h diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index c9a7cfc9..e7ec8dc9 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -47,6 +47,9 @@ #define THERMISOR_TEMP 0x6A #define INTERNAL_TEMP 0x68 +#define TS1_TEMP 0x70 +#define TS2_TEMP 0x72 +#define TS3_TEMP 0x74 //command only (R) @@ -87,7 +90,8 @@ bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length); void bms_set_protection_threshold(void); void bms_battery_status(void); void read_cells_1to6(void); - +void bms_sample_temps(void); +bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC); diff --git a/bms/bms/bms_config/src/ic_bms/spi_link_test.c b/bms/bms/bms_config/src/ic_bms/spi_link_test.c new file mode 100644 index 00000000..73b1ffbb --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/spi_link_test.c @@ -0,0 +1,45 @@ +#include "spi_link_test.h" +#include "bms_spi.h" +#include +#include +#include + +static void PRINT_BUF(const char *tag, const uint8_t *b, uint8_t n) +{ + printf("%s:", tag); + for (uint8_t i = 0; i < n; i++) + printf(" %02X", b[i]); + printf("\r\n"); +} + +void SPI_LINK_TEST_RUN_ONCE(void) +{ + const uint8_t BASE = 0x10; + uint8_t tx[4] = { 0xA5, 0x5A, 0xC3, 0x3C }; + uint8_t rx[4] = { 0 }; + + printf("\r\n=== SPI LINK TEST (SAMC21 master) ===\r\n"); + + /* This uses YOUR actual write_reg implementation */ + if (!write_reg(BASE, tx, (uint8_t)sizeof(tx))) + { + printf("write_reg FAILED\r\n"); + return; + } + + /* This uses YOUR actual read_reg implementation (pipelined read + CRC check) */ + if (!read_reg(BASE, rx, (uint8_t)sizeof(rx))) + { + printf("read_reg FAILED\r\n"); + return; + } + + PRINT_BUF("TX", tx, (uint8_t)sizeof(tx)); + PRINT_BUF("RX", rx, (uint8_t)sizeof(rx)); + + bool ok = true; + for (uint8_t i = 0; i < (uint8_t)sizeof(tx); i++) + if (tx[i] != rx[i]) ok = false; + + printf("RESULT: %s\r\n", ok ? "OK" : "FAIL"); +} diff --git a/bms/bms/bms_config/src/ic_bms/spi_link_test.h b/bms/bms/bms_config/src/ic_bms/spi_link_test.h new file mode 100644 index 00000000..14d1a069 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/spi_link_test.h @@ -0,0 +1,6 @@ +#ifndef SPI_LINK_TEST_H +#define SPI_LINK_TEST_H + +void spi_link_test_run_once(void); + +#endif diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 49849dea..8412518a 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -27,6 +27,7 @@ #include // Defines EXIT_FAILURE #include "definitions.h" // SYS function prototypes #include "ic_bms/bms_spi.h" +#include "spi_link_test.h" #include @@ -54,12 +55,8 @@ int main ( void ) bms_set_protection_threshold(); read_cells_1to6(); bms_battery_status(); - - - - - - + bms_sample_temps(); + spi_link_test_run_once(); while ( true ) { From fe104d62186b5b6fd171f24d84c3dd4ec111e4f6 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Tue, 3 Feb 2026 16:33:02 +0100 Subject: [PATCH 19/30] feat: added bothoff functionality (next: CAN) --- bms/bms/bms_config/src/ic_bms/bms_spi.h | 7 +++ bms/bms/bms_config/src/ic_bms/spi_link_test.c | 45 ------------------- bms/bms/bms_config/src/ic_bms/spi_link_test.h | 6 --- bms/bms/bms_config/src/main.c | 3 +- 4 files changed, 8 insertions(+), 53 deletions(-) delete mode 100644 bms/bms/bms_config/src/ic_bms/spi_link_test.c delete mode 100644 bms/bms/bms_config/src/ic_bms/spi_link_test.h diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index e7ec8dc9..454ec06a 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -75,6 +75,11 @@ #define FET_STATUS 0x7F +// BOTHOFF PINS + +#define GPIO_GROUP_A 0u +#define PIN_BOTHOFF 6u +#define BOTHOFF_PIN_MASK (1u << PIN_BOTHOFF) /* Minimal driver: only SPI+CS bring-up */ @@ -92,6 +97,8 @@ void bms_battery_status(void); void read_cells_1to6(void); void bms_sample_temps(void); bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC); +void bothoff_init(void); +void bothoff_high(void); diff --git a/bms/bms/bms_config/src/ic_bms/spi_link_test.c b/bms/bms/bms_config/src/ic_bms/spi_link_test.c deleted file mode 100644 index 73b1ffbb..00000000 --- a/bms/bms/bms_config/src/ic_bms/spi_link_test.c +++ /dev/null @@ -1,45 +0,0 @@ -#include "spi_link_test.h" -#include "bms_spi.h" -#include -#include -#include - -static void PRINT_BUF(const char *tag, const uint8_t *b, uint8_t n) -{ - printf("%s:", tag); - for (uint8_t i = 0; i < n; i++) - printf(" %02X", b[i]); - printf("\r\n"); -} - -void SPI_LINK_TEST_RUN_ONCE(void) -{ - const uint8_t BASE = 0x10; - uint8_t tx[4] = { 0xA5, 0x5A, 0xC3, 0x3C }; - uint8_t rx[4] = { 0 }; - - printf("\r\n=== SPI LINK TEST (SAMC21 master) ===\r\n"); - - /* This uses YOUR actual write_reg implementation */ - if (!write_reg(BASE, tx, (uint8_t)sizeof(tx))) - { - printf("write_reg FAILED\r\n"); - return; - } - - /* This uses YOUR actual read_reg implementation (pipelined read + CRC check) */ - if (!read_reg(BASE, rx, (uint8_t)sizeof(rx))) - { - printf("read_reg FAILED\r\n"); - return; - } - - PRINT_BUF("TX", tx, (uint8_t)sizeof(tx)); - PRINT_BUF("RX", rx, (uint8_t)sizeof(rx)); - - bool ok = true; - for (uint8_t i = 0; i < (uint8_t)sizeof(tx); i++) - if (tx[i] != rx[i]) ok = false; - - printf("RESULT: %s\r\n", ok ? "OK" : "FAIL"); -} diff --git a/bms/bms/bms_config/src/ic_bms/spi_link_test.h b/bms/bms/bms_config/src/ic_bms/spi_link_test.h deleted file mode 100644 index 14d1a069..00000000 --- a/bms/bms/bms_config/src/ic_bms/spi_link_test.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef SPI_LINK_TEST_H -#define SPI_LINK_TEST_H - -void spi_link_test_run_once(void); - -#endif diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 8412518a..350647b6 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -27,7 +27,6 @@ #include // Defines EXIT_FAILURE #include "definitions.h" // SYS function prototypes #include "ic_bms/bms_spi.h" -#include "spi_link_test.h" #include @@ -56,7 +55,7 @@ int main ( void ) read_cells_1to6(); bms_battery_status(); bms_sample_temps(); - spi_link_test_run_once(); + while ( true ) { From f1bc69bf7d4162b80da5626d4e8b421e3f86e14b Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 5 Feb 2026 13:44:26 +0100 Subject: [PATCH 20/30] feat: add SPI loopback test functionality and update core versions --- .../bms_config_default/components/adc0.yml | 2 +- .../bms_config_default/components/adc1.yml | 2 +- .../bms_config_default/components/can0.yml | 2 +- .../bms_config_default/components/can1.yml | 2 +- .../bms_config_default/components/cmsis.yml | 2 +- .../bms_config_default/components/core.yml | 843 +++++++++++++++++- .../mcc/bms_config_default/components/dfp.yml | 2 +- .../bms_config_default/components/evsys.yml | 2 +- .../bms_config_default/components/nvmctrl.yml | 2 +- .../bms_config_default/components/sercom0.yml | 22 +- .../bms_config_default/components/sercom1.yml | 2 +- .../bms_config_default/components/sercom4.yml | 2 +- .../bms_config_default/components/stdio.yml | 2 +- .../mcc/bms_config_default/mcc-config.mc4 | 17 +- .../bms_config/mcc/mcc-manifest-autosave.yml | 8 +- .../mcc/mcc-manifest-generated-success.yml | 8 +- .../default/harmony-manifest-success.yml | 8 +- .../src/config/default/initialization.c | 1 + .../default/peripheral/port/plib_port.c | 40 +- .../default/peripheral/port/plib_port.h | 43 + .../spi_master/plib_sercom0_spi_master.c | 2 +- .../sercom/usart/plib_sercom4_usart.c | 2 +- bms/bms/bms_config/src/ic_bms/bms_spi.c | 65 +- bms/bms/bms_config/src/ic_bms/bms_spi.h | 4 +- bms/bms/bms_config/src/ic_bms/spi_test.c | 87 ++ bms/bms/bms_config/src/ic_bms/spi_test.h | 9 + bms/bms/bms_config/src/main.c | 6 +- bms/bms/cmake/bms/default/CMakeLists.txt | 9 +- 28 files changed, 1150 insertions(+), 46 deletions(-) create mode 100644 bms/bms/bms_config/src/ic_bms/spi_test.c create mode 100644 bms/bms/bms_config/src/ic_bms/spi_test.h diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml index f745043b..eab9bff9 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/adc0.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: adc0 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml index e001386a..b460e1ea 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/adc1.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: adc1 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml index 75139367..e681f76d 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: can0 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml index 667f40c0..e38d1719 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: can1 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml b/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml index ada4695f..d28a0297 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/cmsis.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: cmsis -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index 7aaa156c..35eb4e25 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: core -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: @@ -897,6 +897,847 @@ data: type: Dynamic type: Values type: String + PORT_GROUP_1_DIR: + attributes: + id: PORT_GROUP_1_DIR + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_OUT: + attributes: + id: PORT_GROUP_1_OUT + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PINCFG8: + attributes: + id: PORT_GROUP_1_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_8_USED: + attributes: + id: PORT_GROUP_1_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX4: + attributes: + id: PORT_GROUP_1_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_8: + attributes: + id: PORT_GROUP_1_PAD_8 + children: + - children: + - attributes: + id: core + value: PB08 + type: Dynamic + type: Values + type: String + PIN_11_PERIPHERAL_FUNCTION: + attributes: + id: PIN_11_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG5: + attributes: + id: PORT_GROUP_1_PINCFG5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_5_USED: + attributes: + id: PORT_GROUP_1_PIN_5_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX2: + attributes: + id: PORT_GROUP_1_PMUX2 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_5: + attributes: + id: PORT_GROUP_1_PAD_5 + children: + - children: + - attributes: + id: core + value: PB05 + type: Dynamic + type: Values + type: String + PIN_6_PERIPHERAL_FUNCTION: + attributes: + id: PIN_6_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_DIR: + attributes: + id: PORT_GROUP_0_DIR + children: + - children: + - attributes: + id: core + value: '0x80' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_OUT: + attributes: + id: PORT_GROUP_0_OUT + children: + - children: + - attributes: + id: core + value: '0x80' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG1: + attributes: + id: PORT_GROUP_0_PINCFG1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_1_USED: + attributes: + id: PORT_GROUP_0_PIN_1_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX0: + attributes: + id: PORT_GROUP_0_PMUX0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_1: + attributes: + id: PORT_GROUP_0_PAD_1 + children: + - children: + - attributes: + id: core + value: PA01 + type: Dynamic + type: Values + type: String + PIN_2_PERIPHERAL_FUNCTION: + attributes: + id: PIN_2_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG0: + attributes: + id: PORT_GROUP_0_PINCFG0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_0_USED: + attributes: + id: PORT_GROUP_0_PIN_0_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_0: + attributes: + id: PORT_GROUP_0_PAD_0 + children: + - children: + - attributes: + id: core + value: PA00 + type: Dynamic + type: Values + type: String + PIN_1_PERIPHERAL_FUNCTION: + attributes: + id: PIN_1_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG9: + attributes: + id: PORT_GROUP_1_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_9_USED: + attributes: + id: PORT_GROUP_1_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PINCFG3: + attributes: + id: PORT_GROUP_0_PINCFG3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_3_USED: + attributes: + id: PORT_GROUP_0_PIN_3_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX1: + attributes: + id: PORT_GROUP_0_PMUX1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_3: + attributes: + id: PORT_GROUP_0_PAD_3 + children: + - children: + - attributes: + id: core + value: PA03 + type: Dynamic + type: Values + type: String + PIN_4_PERIPHERAL_FUNCTION: + attributes: + id: PIN_4_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_DIR: + attributes: + id: PIN_2_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_PULLEN: + attributes: + id: PIN_2_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_INEN: + attributes: + id: PIN_2_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG6: + attributes: + id: PORT_GROUP_1_PINCFG6 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_6_USED: + attributes: + id: PORT_GROUP_1_PIN_6_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX3: + attributes: + id: PORT_GROUP_1_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_6: + attributes: + id: PORT_GROUP_1_PAD_6 + children: + - children: + - attributes: + id: core + value: PB06 + type: Dynamic + type: Values + type: String + PIN_9_PERIPHERAL_FUNCTION: + attributes: + id: PIN_9_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG7: + attributes: + id: PORT_GROUP_1_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_7_USED: + attributes: + id: PORT_GROUP_1_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PAD_7: + attributes: + id: PORT_GROUP_1_PAD_7 + children: + - children: + - attributes: + id: core + value: PB07 + type: Dynamic + type: Values + type: String + PIN_10_PERIPHERAL_FUNCTION: + attributes: + id: PIN_10_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PAD_9: + attributes: + id: PORT_GROUP_1_PAD_9 + children: + - children: + - attributes: + id: core + value: PB09 + type: Dynamic + type: Values + type: String + PIN_12_PERIPHERAL_FUNCTION: + attributes: + id: PIN_12_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG10: + attributes: + id: PORT_GROUP_0_PINCFG10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_10_USED: + attributes: + id: PORT_GROUP_0_PIN_10_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX5: + attributes: + id: PORT_GROUP_0_PMUX5 + children: + - children: + - attributes: + id: core + value: '0x20' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_10: + attributes: + id: PORT_GROUP_0_PAD_10 + children: + - children: + - attributes: + id: core + value: PA10 + type: Dynamic + type: Values + type: String + PIN_19_PERIPHERAL_FUNCTION: + attributes: + id: PIN_19_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_MODE: + attributes: + id: PIN_16_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_FUNCTION_TYPE: + attributes: + id: PIN_16_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PMUX3: + attributes: + id: PORT_GROUP_0_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_7: + attributes: + id: PORT_GROUP_0_PAD_7 + children: + - children: + - attributes: + id: core + value: PA07 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG7: + attributes: + id: PORT_GROUP_0_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_7_USED: + attributes: + id: PORT_GROUP_0_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_16_PERIPHERAL_FUNCTION: + attributes: + id: PIN_16_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_INEN: + attributes: + id: PIN_16_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_DIR: + attributes: + id: PIN_16_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_16_FUNCTION_NAME: + attributes: + id: PIN_16_FUNCTION_NAME + children: + - children: + - attributes: + value: GPIO_PA07 + type: User + type: Values + type: String + PIN_17_MODE: + attributes: + id: PIN_17_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_17_FUNCTION_TYPE: + attributes: + id: PIN_17_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD0 + type: User + type: Values + type: String + PORT_GROUP_0_PMUX4: + attributes: + id: PORT_GROUP_0_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_8: + attributes: + id: PORT_GROUP_0_PAD_8 + children: + - children: + - attributes: + id: core + value: PA08 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG8: + attributes: + id: PORT_GROUP_0_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_8_USED: + attributes: + id: PORT_GROUP_0_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_17_PERIPHERAL_FUNCTION: + attributes: + id: PIN_17_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_18_MODE: + attributes: + id: PIN_18_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_18_FUNCTION_TYPE: + attributes: + id: PIN_18_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD1 + type: User + type: Values + type: String + PORT_GROUP_0_PAD_9: + attributes: + id: PORT_GROUP_0_PAD_9 + children: + - children: + - attributes: + id: core + value: PA09 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG9: + attributes: + id: PORT_GROUP_0_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_9_USED: + attributes: + id: PORT_GROUP_0_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_18_PERIPHERAL_FUNCTION: + attributes: + id: PIN_18_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG11: + attributes: + id: PORT_GROUP_0_PINCFG11 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_11_USED: + attributes: + id: PORT_GROUP_0_PIN_11_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_11: + attributes: + id: PORT_GROUP_0_PAD_11 + children: + - children: + - attributes: + id: core + value: PA11 + type: Dynamic + type: Values + type: String + PIN_20_PERIPHERAL_FUNCTION: + attributes: + id: PIN_20_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_20_MODE: + attributes: + id: PIN_20_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_20_FUNCTION_TYPE: + attributes: + id: PIN_20_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD3 + type: User + type: Values + type: String + PIN_16_LAT: + attributes: + id: PIN_16_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml b/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml index f1de5cb7..bf031446 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/dfp.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: dfp -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml index 749f3a60..26dbf820 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: evsys -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml b/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml index d52779ca..48ca6881 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/nvmctrl.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: nvmctrl -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml index 675a9975..190d836f 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom0.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: sercom0 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: @@ -205,7 +205,7 @@ data: type: Attributes - children: - attributes: - value: '3' + value: '1' type: User type: Values type: KeyValueSet @@ -319,4 +319,22 @@ data: type: Dynamic type: Values type: Boolean + SPI_DOPO: + attributes: + id: SPI_DOPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml index 5ebba36e..1c17c58d 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom1.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: sercom1 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml index 411058c4..e8cab14d 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: sercom4 -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml b/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml index bf922231..ed513922 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/stdio.yml @@ -1,6 +1,6 @@ configVersion: 1.0.0 componentName: stdio -coreVersion: 5.8.2 +coreVersion: 5.8.4 device: ATSAMC21J18A library: [] dependency: diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index 86afd346..8948d326 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -1,9 +1,8 @@ configVersion: 1.0.0 -coreVersion: 5.8.2 -spaHostVersion: 1.0.0 +coreVersion: 5.8.4 +spaHostVersion: 1.2.1 device: ATSAMC21J18A -deviceLibrary: - className: null +deviceLibrary: {} groupModules: [] modules: - adc0 @@ -33,7 +32,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/exceptions.c hash: 42f9da2668e04ccb3473d45b149683a00f80072c6883c7918d6ce93997cd6987 - file: ../src/config/default/initialization.c - hash: 377b659de8dd37b4b694a4a0f88359507d3c6536d908fae6f55a5644c8d7aee6 + hash: 1375f7d05ec7060f5abb29c79e4b4fae0b27af9573f79ac5a616f77ab8b165bb - file: ../src/config/default/interrupts.c hash: b334b6f53c28ee3dba860dd2edd4a121b9526d6f4f96067a92960fa67c5ace92 - file: ../src/config/default/interrupts.h @@ -77,9 +76,9 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.h hash: a2f572d8ba174971959f4a9319fc61b460c00432512d38e19e28e2dfddf6cde5 - file: ../src/config/default/peripheral/port/plib_port.c - hash: 554b36ce35723948e94f7872d1d82d2876b522dd9f4d4eaa6750c080ef01365f + hash: d8c1024f8c78bb4b3891b91710ca473e9e840d9022770fc59928c8d0b0992ca3 - file: ../src/config/default/peripheral/port/plib_port.h - hash: 3381b14f9d6d7666d2c9ace139aab59d70907bfc6adbf8fdfce9db8c117262cc + hash: 0d1bcf9588384b8fcfb935d32fa0c2bd97841ae22a886f5cbb4147d473272184 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c hash: 5ad6a7aecfa835077677e73fc771c2d82f35bdf4da9b54b499203176295ed534 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h @@ -87,7 +86,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h hash: f167b04b3c6a0f83fe41b7b6f810cbf0a48b8ca7d5a747b76463dd53d3c1a2a2 - file: ../src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c - hash: 46b45fe236f74221755882245969cd1b2c83c66cb8a02b32eee89cf66be70f06 + hash: e6d008a169dbfbe9e1fa3b3087c0328430814cb0028682c512d6e5716434966b - file: ../src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h hash: 8e1550559a741d9ace2e6fb145ac015c8457aa417c877996855b73238051babb - file: ../src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h @@ -99,7 +98,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h hash: 3653b66472c558c50f7037a1dd25d2678e9a13aa718f3c53a2195e6f3919ea48 - file: ../src/config/default/pin_configurations.csv - hash: 638806ff5f63e1f18fbb25a785725c7098e300fc472df0cfcde82fbbc7b5caaa + hash: 425b48965d8457eba4933205ce346ea114b77d3ae94093c90c33192ae671b7c0 - file: ../src/config/default/startup_xc32.c hash: e6227d89e36b74af1bc21e00e80b390502c97aaaa65796291f63b2d96cf0678e - file: ../src/config/default/stdio/xc32_monitor.c diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index 2a809904..516fa51f 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,15 +2,15 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2025-10-22T14:14:56.067+02:00[Europe/Oslo] +creation_date: 2026-02-05T11:06:19.871+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown device_name: ATSAMC21J18A compiler: N/A -mcc_version: 5.6.2 -mcc_core_version: 5.8.2 -content_manager_version: 6.0.2 +mcc_version: 5.6.4 +mcc_core_version: 5.8.4 +content_manager_version: 6.0.4 is_mcc_offline: false is_using_prerelease_versions: false mcc_content_registries: https://registry.npmjs.org/ diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml index 67bb2f81..b4225a23 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -2,15 +2,15 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2025-10-22T14:14:34.229+02:00[Europe/Oslo] +creation_date: 2026-02-05T11:06:19.821+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown device_name: ATSAMC21J18A compiler: N/A -mcc_version: 5.6.2 -mcc_core_version: 5.8.2 -content_manager_version: 6.0.2 +mcc_version: 5.6.4 +mcc_core_version: 5.8.4 +content_manager_version: 6.0.4 is_mcc_offline: false is_using_prerelease_versions: false mcc_content_registries: https://registry.npmjs.org/ diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml index 76572352..28ff6baf 100644 --- a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -4,13 +4,13 @@ project: bms_config_default -creation_date: 2025-10-22T14:14:34.243+02:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +creation_date: 2026-02-05T11:06:19.827+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime operating_system: Linux mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] -mcc_version: v5.6.2 -mcc_core_version: v5.8.2 +mcc_version: v5.6.4 +mcc_core_version: v5.8.4 mplabx_version: NA # if MPLAB X plugin only -harmony_version: v5.6.2 +harmony_version: v5.6.4 compiler: NA modules: diff --git a/bms/bms/bms_config/src/config/default/initialization.c b/bms/bms/bms_config/src/config/default/initialization.c index 52f622d3..4b5a7fb2 100644 --- a/bms/bms/bms_config/src/config/default/initialization.c +++ b/bms/bms/bms_config/src/config/default/initialization.c @@ -159,6 +159,7 @@ void SYS_Initialize ( void* data ) + PORT_Initialize(); CLOCK_Initialize(); diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c index 53c22749..c1901a25 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c @@ -53,6 +53,44 @@ // ***************************************************************************** // ***************************************************************************** // ***************************************************************************** +/* Function: + + void PORT_Initialize(void) + + Summary: + Initializes the PORT Library. + + Description: + This function initializes all ports and pins as configured in the + MHC Pin Manager. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_Initialize(void) +{ + /************************** GROUP 0 Initialization *************************/ + PORT_REGS->GROUP[0].PORT_DIR = 0x80U; + PORT_REGS->GROUP[0].PORT_OUT = 0x80U; + PORT_REGS->GROUP[0].PORT_PINCFG[7] = 0x0U; + PORT_REGS->GROUP[0].PORT_PINCFG[8] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[9] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[11] = 0x1U; + + PORT_REGS->GROUP[0].PORT_PMUX[3] = 0x0U; + PORT_REGS->GROUP[0].PORT_PMUX[4] = 0x22U; + PORT_REGS->GROUP[0].PORT_PMUX[5] = 0x20U; + + /************************** GROUP 1 Initialization *************************/ + PORT_REGS->GROUP[1].PORT_PINCFG[10] = 0x1U; + PORT_REGS->GROUP[1].PORT_PINCFG[11] = 0x1U; + + PORT_REGS->GROUP[1].PORT_PMUX[5] = 0x33U; + + + +} // ***************************************************************************** /* Function: uint32_t PORT_GroupRead(PORT_GROUP group) @@ -306,4 +344,4 @@ void PORT_PinGPIOConfig(PORT_PIN pin) /* Disable peripheral control of the pin */ ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); -} \ No newline at end of file +} diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h index e8fcb4d1..701b240a 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h @@ -65,6 +65,15 @@ // ***************************************************************************** // ***************************************************************************** +/*** Macros for GPIO_PA07 pin ***/ +#define GPIO_PA07_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 7U)) +#define GPIO_PA07_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 7U)) +#define GPIO_PA07_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 7U)) +#define GPIO_PA07_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 7U)) +#define GPIO_PA07_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 7U)) +#define GPIO_PA07_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 7U)) & 0x01U) +#define GPIO_PA07_PIN PORT_PIN_PA07 + // ***************************************************************************** /* PORT Group @@ -303,6 +312,40 @@ typedef enum // Section: Generated API based on pin configurations done in Pin Manager // ***************************************************************************** // ***************************************************************************** +// ***************************************************************************** +/* Function: + void PORT_Initialize(void) + + Summary: + Initializes the PORT Library. + + Description: + This function initializes all ports and pins as configured in the + MHC Pin Manager. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Example: + + + PORT_Initialize(); + + + + Remarks: + The function should be called once before calling any other PORTS PLIB + functions. +*/ + +void PORT_Initialize(void); + // ***************************************************************************** // ***************************************************************************** // Section: PORT APIs which operates on multiple pins of a group diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c index f3ba5875..d661bbbc 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c @@ -111,7 +111,7 @@ void SERCOM0_SPI_Initialize(void) * Data In and Pin Out,Data Order and Standby mode if configured * and Selection of the Clock Phase and Polarity and Enable the SPI Module */ - SERCOM0_REGS->SPIM.SERCOM_CTRLA = SERCOM_SPIM_CTRLA_MODE_SPI_MASTER | SERCOM_SPIM_CTRLA_DOPO_PAD0 | SERCOM_SPIM_CTRLA_DIPO_PAD3 | SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW | SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE | SERCOM_SPIM_CTRLA_DORD_MSB | SERCOM_SPIM_CTRLA_ENABLE_Msk ; + SERCOM0_REGS->SPIM.SERCOM_CTRLA = SERCOM_SPIM_CTRLA_MODE_SPI_MASTER | SERCOM_SPIM_CTRLA_DOPO_PAD3 | SERCOM_SPIM_CTRLA_DIPO_PAD1 | SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW | SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE | SERCOM_SPIM_CTRLA_DORD_MSB | SERCOM_SPIM_CTRLA_ENABLE_Msk ; /* Wait for synchronization */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c index 7cd533a7..d949d3a8 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c +++ b/bms/bms/bms_config/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c @@ -99,7 +99,7 @@ void SERCOM4_USART_Initialize( void ) * Configures IBON */ - SERCOM4_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x3UL) | SERCOM_USART_INT_CTRLA_TXPO(0x1UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; /* Configure Baud Rate */ SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM4_USART_INT_BAUD_VALUE); diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 8f4888a2..3f62c5b8 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -17,9 +17,26 @@ static inline void _delay(uint32_t cycles){ for (volatile uint32_t i=0; iGROUP[bq_cs_group].PORT_DIRSET = bq_cs_mask; @@ -46,6 +63,10 @@ bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) bq_cs_low(); bool ok = SERCOM0_SPI_WriteRead(tx, length, rx, length); + if (ok) + { + ok = bq_spi_wait_idle(); + } bq_cs_high(); return ok; @@ -101,6 +122,10 @@ bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length) // Single SPI transfer with CS held low across all frames bq_cs_low(); bool ok = SERCOM0_SPI_Write(tx_bytes, sizeof tx_bytes); + if (ok) + { + ok = bq_spi_wait_idle(); + } bq_cs_high(); return ok; @@ -135,6 +160,10 @@ bool read_reg(uint8_t regAddr, uint8_t *data, uint8_t length) bq_cs_low(); bool ok = SERCOM0_SPI_WriteRead(tx, sizeof tx, rx, sizeof rx); + if (ok) + { + ok = bq_spi_wait_idle(); + } bq_cs_high(); if (!ok) return false; @@ -372,6 +401,40 @@ void read_cells_1to6(){ } + bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC) + { + uint16_t raw; + + if (temp_dC == 0) + return false; + + if (!bq_direct_command(ts_cmd, &raw, 'R')) + return false; + + *temp_dC = (int16_t)raw - 2731; // raw is signed 0.1 K -> 0.1 C + + return true; + } +/* + void bms_sample_temps(void) +{ + int16_t t1_dC, t2_dC, t3_dC; + bms_read_ts_temp(TS1_TEMP, &t1_dC); + bms_read_ts_temp(TS2_TEMP, &t2_dC); + bms_read_ts_temp(TS3_TEMP, &t3_dC); +} +*/ +void bothoff_init(void) +{ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[PIN_BOTHOFF] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRSET = BOTHOFF_PIN_MASK; + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; +} + +void bothoff_high(void) +{ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; +} diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index 454ec06a..70df55b9 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -33,8 +33,8 @@ */ // 16 cell voltage readings avaliable -#define bq_cs_group (0U) -#define bq_cs_mask (1UL << 18) +#define bq_cs_group (0U) +#define bq_cs_mask (1UL << 7) // PA07: CS (GPIO) #define R 0 // Read; Used in directcommands and Subcommands functions #define W 1 // Write; Used in directcommands and Subcommands functions diff --git a/bms/bms/bms_config/src/ic_bms/spi_test.c b/bms/bms/bms_config/src/ic_bms/spi_test.c new file mode 100644 index 00000000..8aeed662 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/spi_test.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include +#include "definitions.h" +#include "spi_test.h" + +#define SPI_TEST_CS_GROUP (0U) +#define SPI_TEST_CS_MASK (1UL << 7) // PA07 +#define SPI_TEST_WAIT_TIMEOUT (2000000UL) + +static inline void spi_test_cs_low(void) +{ + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTCLR = SPI_TEST_CS_MASK; +} + +static inline void spi_test_cs_high(void) +{ + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTSET = SPI_TEST_CS_MASK; +} + +static bool spi_test_wait_idle(void) +{ + uint32_t timeout = SPI_TEST_WAIT_TIMEOUT; + + while (SERCOM0_SPI_IsBusy()) + { + if (timeout-- == 0U) + { + return false; + } + } + + return true; +} + +static void spi_test_print_bytes(const char *label, const uint8_t *buf, size_t len) +{ + printf("%s:", label); + for (size_t i = 0; i < len; i++) + { + printf(" %02X", buf[i]); + } + printf("\n"); +} + +bool spi_test_loopback(void) +{ + uint8_t tx[] = {0xA5U, 0x5AU, 0x3CU, 0xC3U, 0x00U, 0xFFU}; + uint8_t rx[sizeof(tx)]; + bool ok = false; + + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_DIRSET = SPI_TEST_CS_MASK; + spi_test_cs_high(); + + if (SERCOM0_SPI_IsBusy()) + { + return false; + } + + memset(rx, 0, sizeof(rx)); + + spi_test_cs_low(); + ok = SERCOM0_SPI_WriteRead(tx, sizeof(tx), rx, sizeof(rx)); + if (ok) + { + ok = spi_test_wait_idle(); + } + spi_test_cs_high(); + + if (!ok) + { + printf("SPI transfer failed\n"); + return false; + } + + spi_test_print_bytes("SPI TX", tx, sizeof(tx)); + spi_test_print_bytes("SPI RX", rx, sizeof(rx)); + + return (memcmp(tx, rx, sizeof(tx)) == 0); +} + +void spi_test_run_and_print(void) +{ + bool pass = spi_test_loopback(); + printf("SPI loopback (PA08->PA09 jumper): %s\n", pass ? "PASS" : "FAIL"); +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/ic_bms/spi_test.h b/bms/bms/bms_config/src/ic_bms/spi_test.h new file mode 100644 index 00000000..be659bc9 --- /dev/null +++ b/bms/bms/bms_config/src/ic_bms/spi_test.h @@ -0,0 +1,9 @@ +#ifndef SPI_TEST_H +#define SPI_TEST_H + +#include + +bool spi_test_loopback(void); +void spi_test_run_and_print(void); + +#endif /* SPI_TEST_H */ diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 350647b6..1b527600 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -27,6 +27,7 @@ #include // Defines EXIT_FAILURE #include "definitions.h" // SYS function prototypes #include "ic_bms/bms_spi.h" +#include "ic_bms/spi_test.h" #include @@ -50,11 +51,14 @@ int main ( void ) /* Initialize all modules */ SYS_Initialize ( NULL ); + spi_test_run_and_print(); + bq76942_init(); bms_set_protection_threshold(); read_cells_1to6(); bms_battery_status(); - bms_sample_temps(); + + //bms_sample_temps(); while ( true ) diff --git a/bms/bms/cmake/bms/default/CMakeLists.txt b/bms/bms/cmake/bms/default/CMakeLists.txt index 0d8a1629..7a4f32f3 100644 --- a/bms/bms/cmake/bms/default/CMakeLists.txt +++ b/bms/bms/cmake/bms/default/CMakeLists.txt @@ -4,10 +4,6 @@ # If you want to customize cmake behavior create a user.cmake in this # directory and add it to your version control system. -if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/user.cmake) - include(user.cmake) -endif() - # format v1.00 # { @@ -18,5 +14,10 @@ project(bms_default_project LANGUAGES C CXX ASM) include("${CMAKE_CURRENT_LIST_DIR}/.generated/main.cmake") +if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/user.cmake) + include(user.cmake) +endif() + + # } From 69644441859ff2752cedb779011eae43f18ebb01 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 5 Feb 2026 16:03:25 +0100 Subject: [PATCH 21/30] feat: enhance SPI testing functionality with improved CRC checks and self-test routine --- .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- bms/bms/bms_config/src/ic_bms/spi_test.c | 124 +++++++++++++++--- bms/bms/bms_config/src/ic_bms/spi_test.h | 5 +- bms/bms/bms_config/src/main.c | 2 +- bms/bms/out/bms/bms-settings.json | 1 + 5 files changed, 110 insertions(+), 24 deletions(-) create mode 100644 bms/bms/out/bms/bms-settings.json diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index 516fa51f..f2aaf0f2 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-05T11:06:19.871+01:00[Europe/Oslo] +creation_date: 2026-02-05T14:38:04.136+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/ic_bms/spi_test.c b/bms/bms/bms_config/src/ic_bms/spi_test.c index 8aeed662..01056849 100644 --- a/bms/bms/bms_config/src/ic_bms/spi_test.c +++ b/bms/bms/bms_config/src/ic_bms/spi_test.c @@ -1,7 +1,6 @@ #include #include #include -#include #include "definitions.h" #include "spi_test.h" @@ -9,6 +8,7 @@ #define SPI_TEST_CS_MASK (1UL << 7) // PA07 #define SPI_TEST_WAIT_TIMEOUT (2000000UL) +// Drives the same CS GPIO used by the production BMS SPI path. static inline void spi_test_cs_low(void) { PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTCLR = SPI_TEST_CS_MASK; @@ -19,6 +19,7 @@ static inline void spi_test_cs_high(void) PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTSET = SPI_TEST_CS_MASK; } +// Prevents tests from hanging forever if SPI stays busy. static bool spi_test_wait_idle(void) { uint32_t timeout = SPI_TEST_WAIT_TIMEOUT; @@ -34,6 +35,7 @@ static bool spi_test_wait_idle(void) return true; } +// UART helper so we can inspect exact bytes sent/received on the live target. static void spi_test_print_bytes(const char *label, const uint8_t *buf, size_t len) { printf("%s:", label); @@ -44,44 +46,130 @@ static void spi_test_print_bytes(const char *label, const uint8_t *buf, size_t l printf("\n"); } -bool spi_test_loopback(void) +// Same CRC-8 polynomial (0x07) used in bms_spi.c framing. +static uint8_t spi_test_crc8_calc(const uint8_t *data, uint8_t len) { - uint8_t tx[] = {0xA5U, 0x5AU, 0x3CU, 0xC3U, 0x00U, 0xFFU}; - uint8_t rx[sizeof(tx)]; - bool ok = false; + uint8_t crc = 0x00U; - PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_DIRSET = SPI_TEST_CS_MASK; - spi_test_cs_high(); + for (uint8_t i = 0; i < len; i++) + { + crc ^= data[i]; + for (uint8_t b = 0; b < 8U; b++) + { + crc = (crc & 0x80U) ? (uint8_t)((crc << 1U) ^ 0x07U) : (uint8_t)(crc << 1U); + } + } + return crc; +} + +// Tests write_reg frame construction and one real SPI write transfer. +// With loopback only, this validates transport/framing (not real BQ register writes). +static bool spi_test_write_reg_exact(uint8_t reg_addr, const uint8_t *data, uint8_t length) +{ + uint8_t tx_bytes[3U * 32U]; - if (SERCOM0_SPI_IsBusy()) + if ((length == 0U) || (length > 32U) || SERCOM0_SPI_IsBusy()) { return false; } - memset(rx, 0, sizeof(rx)); + for (uint8_t i = 0U; i < length; i++) + { + uint8_t cmd = (uint8_t)(0x80U | ((reg_addr + i) & 0x7FU)); + uint8_t pair[2] = {cmd, data[i]}; + tx_bytes[3U * i + 0U] = cmd; + tx_bytes[3U * i + 1U] = data[i]; + tx_bytes[3U * i + 2U] = spi_test_crc8_calc(pair, 2U); + } + + spi_test_print_bytes("write_reg tx", tx_bytes, (size_t)(3U * length)); spi_test_cs_low(); - ok = SERCOM0_SPI_WriteRead(tx, sizeof(tx), rx, sizeof(rx)); + bool ok = SERCOM0_SPI_Write(tx_bytes, (size_t)(3U * length)); if (ok) { ok = spi_test_wait_idle(); } spi_test_cs_high(); + return ok; +} + +// Tests read_reg frame construction, SPI full-duplex transfer, and CRC parsing. +// In loopback mode, rx mirrors tx; this still validates parser/CRC path end-to-end. +static bool spi_test_read_reg_exact(uint8_t reg_addr, uint8_t *data, uint8_t length) +{ + uint8_t tx[3U * 33U]; + uint8_t rx[3U * 33U]; + uint8_t frames; + + if ((length == 0U) || (length > 32U) || SERCOM0_SPI_IsBusy()) + { + return false; + } + + frames = (uint8_t)(length + 1U); + + { + uint8_t pair0[2] = {(uint8_t)(reg_addr & 0x7FU), 0x00U}; + tx[0] = pair0[0]; + tx[1] = pair0[1]; + tx[2] = spi_test_crc8_calc(pair0, 2U); + } + for (uint8_t i = 1U; i < frames; i++) + { + uint8_t cmd = (i < (uint8_t)(frames - 1U)) ? (uint8_t)((reg_addr + i) & 0x7FU) : 0x00U; + uint8_t pair[2] = {cmd, 0x00U}; + tx[3U * i + 0U] = pair[0]; + tx[3U * i + 1U] = pair[1]; + tx[3U * i + 2U] = spi_test_crc8_calc(pair, 2U); + } + + spi_test_print_bytes("read_reg tx", tx, (size_t)(3U * frames)); + + spi_test_cs_low(); + bool ok = SERCOM0_SPI_WriteRead(tx, (size_t)(3U * frames), rx, (size_t)(3U * frames)); + if (ok) + { + ok = spi_test_wait_idle(); + } + spi_test_cs_high(); if (!ok) { - printf("SPI transfer failed\n"); return false; } - spi_test_print_bytes("SPI TX", tx, sizeof(tx)); - spi_test_print_bytes("SPI RX", rx, sizeof(rx)); + spi_test_print_bytes("read_reg rx", rx, (size_t)(3U * frames)); - return (memcmp(tx, rx, sizeof(tx)) == 0); + for (uint8_t j = 1U; j <= length; j++) + { + uint8_t *chunk = &rx[3U * j]; + if (spi_test_crc8_calc(chunk, 2U) != chunk[2]) + { + return false; + } + data[j - 1U] = chunk[1]; + } + return true; } -void spi_test_run_and_print(void) +void spi_driver_self_test_run(void) { - bool pass = spi_test_loopback(); - printf("SPI loopback (PA08->PA09 jumper): %s\n", pass ? "PASS" : "FAIL"); -} \ No newline at end of file + uint8_t wr_data[3] = {0x12U, 0x34U, 0x56U}; + uint8_t rd_data[3] = {0U}; + bool ok_write; + bool ok_read; + + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_DIRSET = SPI_TEST_CS_MASK; + spi_test_cs_high(); + + printf("=== SPI read/write reg transport test (PA08->PA09 loopback) ===\n"); + + ok_write = spi_test_write_reg_exact(0x10U, wr_data, sizeof(wr_data)); + ok_read = spi_test_read_reg_exact(0x10U, rd_data, sizeof(rd_data)); + + printf("write_reg_exact(0x10, len=3): %s\n", ok_write ? "OK" : "FAIL"); + printf("read_reg_exact(0x10, len=3): %s\n", ok_read ? "OK" : "FAIL"); + spi_test_print_bytes("read_reg data", rd_data, sizeof(rd_data)); + printf("Note: this confirms MCU SPI framing/path only; real BQ register behavior needs the BQ IC connected.\n"); +} diff --git a/bms/bms/bms_config/src/ic_bms/spi_test.h b/bms/bms/bms_config/src/ic_bms/spi_test.h index be659bc9..4710c0e2 100644 --- a/bms/bms/bms_config/src/ic_bms/spi_test.h +++ b/bms/bms/bms_config/src/ic_bms/spi_test.h @@ -1,9 +1,6 @@ #ifndef SPI_TEST_H #define SPI_TEST_H -#include - -bool spi_test_loopback(void); -void spi_test_run_and_print(void); +void spi_driver_self_test_run(void); #endif /* SPI_TEST_H */ diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 1b527600..67198073 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -51,7 +51,7 @@ int main ( void ) /* Initialize all modules */ SYS_Initialize ( NULL ); - spi_test_run_and_print(); + spi_driver_self_test_run(); bq76942_init(); bms_set_protection_threshold(); diff --git a/bms/bms/out/bms/bms-settings.json b/bms/bms/out/bms/bms-settings.json new file mode 100644 index 00000000..04c742df --- /dev/null +++ b/bms/bms/out/bms/bms-settings.json @@ -0,0 +1 @@ +{"project":"bms","configuration":"default"} \ No newline at end of file From f3ac5e7b6974d02c85ca50e2fd9760906bcd6417 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 12 Feb 2026 10:54:46 +0100 Subject: [PATCH 22/30] feat: CAN driver tested on devboard --- bms/bms/bms_config/src/app/can_facade.c | 64 ++++++++++++++++++++++++ bms/bms/bms_config/src/app/can_facade.h | 26 ++++++++++ bms/bms/bms_config/src/ic_bms/spi_test.c | 2 +- 3 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 bms/bms/bms_config/src/app/can_facade.c create mode 100644 bms/bms/bms_config/src/app/can_facade.h diff --git a/bms/bms/bms_config/src/app/can_facade.c b/bms/bms/bms_config/src/app/can_facade.c new file mode 100644 index 00000000..35b5a5ed --- /dev/null +++ b/bms/bms/bms_config/src/app/can_facade.c @@ -0,0 +1,64 @@ +#include "definitions.h" +#include "can_facade.h" + +/* RX state */ +static volatile bool rx_ready = false; +static CAN_RX_BUFFER rx_buf; + +/* CAN message RAM */ +static bool ram_bound = false; +static uint8_t can_msg_ram[CAN0_MESSAGE_RAM_CONFIG_SIZE]; + +/* RX callback */ +void APP_CAN_RxCallback(uint8_t numberOfMessage, uintptr_t context) +{ + (void)context; + (void)numberOfMessage; + + /* Fetch one message from FIFO0 */ + if (CAN0_MessageReceiveFifo(CAN_RX_FIFO_0, 1, &rx_buf)) + { + rx_ready = true; + /* Re-arm is implicit; FIFO is re-used after ack inside plib */ + } +} + +/* Init */ +void CAN_Init(void) +{ + if (!ram_bound) + { + CAN0_MessageRAMConfigSet(can_msg_ram); + ram_bound = true; + } + + /* Accept all standard/extended frames into FIFO0 (override MCC default reject). */ + CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_RXF0 | CAN_GFC_ANFE_RXF0; + + /* Register RX callback on FIFO0 */ + CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_0, APP_CAN_RxCallback, (uintptr_t)NULL); + + /* Optional: relax global filters if needed (left as-is for now) */ +} + +/* Send a standard 11-bit ID data frame */ +bool CAN_Send(uint32_t id, const uint8_t *data, uint8_t len) +{ + if (len > 8U || data == NULL) + return false; + + CAN_TX_BUFFER tx = {0}; + tx.id = (id & 0x7FFU) << 18; /* standard ID format */ + tx.xtd = 0; + tx.rtr = 0; + tx.dlc = len & 0xFU; + tx.brs = 0; + tx.fdf = 0; + tx.efc = 0; + tx.mm = 0; + for (uint8_t i = 0; i < len; i++) + tx.data[i] = data[i]; + + /* Single-message transmit via FIFO */ + return CAN0_MessageTransmitFifo(1, &tx); +} diff --git a/bms/bms/bms_config/src/app/can_facade.h b/bms/bms/bms_config/src/app/can_facade.h new file mode 100644 index 00000000..f4977390 --- /dev/null +++ b/bms/bms/bms_config/src/app/can_facade.h @@ -0,0 +1,26 @@ +#ifndef CAN_FACADE_H +#define CAN_FACADE_H + +#include +#include +#include "definitions.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Suggested arbitration IDs (11-bit standard). Lower numeric = higher priority. */ +#define CAN_ID_SHUTDOWN_CMD 0x050U /* Highest priority: killswitch/leak */ +#define CAN_ID_LEAK_ALERT 0x060U /* Telemetry alert to BMS */ +#define CAN_ID_BMS_STATUS 0x180U /* Periodic pack/FET status */ +#define CAN_ID_CELL_V_BASE 0x200U /* Cell voltages: CAN_ID_CELL_V_BASE + cell_index (0..15) */ + +void CAN_Init(void); +bool CAN_Send(uint32_t id, const uint8_t *data, uint8_t len); +void APP_CAN_RxCallback(uint8_t numberOfMessage, uintptr_t context); + +#ifdef __cplusplus +} +#endif + +#endif /* CAN_FACADE_H */ diff --git a/bms/bms/bms_config/src/ic_bms/spi_test.c b/bms/bms/bms_config/src/ic_bms/spi_test.c index 01056849..6ef98c1f 100644 --- a/bms/bms/bms_config/src/ic_bms/spi_test.c +++ b/bms/bms/bms_config/src/ic_bms/spi_test.c @@ -172,4 +172,4 @@ void spi_driver_self_test_run(void) printf("read_reg_exact(0x10, len=3): %s\n", ok_read ? "OK" : "FAIL"); spi_test_print_bytes("read_reg data", rd_data, sizeof(rd_data)); printf("Note: this confirms MCU SPI framing/path only; real BQ register behavior needs the BQ IC connected.\n"); -} +|} From 7ab4a96ca6495dd12bfeca42c90628c1db94d488 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 12 Feb 2026 16:02:29 +0100 Subject: [PATCH 23/30] feat: update CAN initialization and add wakeup pin functionality --- .../bms_config_default/components/can0.yml | 215 ++++- .../bms_config_default/components/can1.yml | 202 ---- .../bms_config_default/components/core.yml | 784 ++++++++++++++- .../bms_config_default/components/sercom4.yml | 4 +- .../mcc/bms_config_default/mcc-config.mc4 | 29 +- .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- .../mcc/mcc-manifest-generated-success.yml | 2 +- bms/bms/bms_config/src/app/can_facade.c | 132 +-- bms/bms/bms_config/src/app/can_facade.h | 55 +- .../src/config/default/definitions.h | 9 +- .../default/harmony-manifest-success.yml | 2 +- .../src/config/default/initialization.c | 12 +- .../src/config/default/interrupts.c | 5 +- .../src/config/default/interrupts.h | 1 - .../config/default/peripheral/can/plib_can0.c | 820 +++++++--------- .../config/default/peripheral/can/plib_can0.h | 40 +- .../config/default/peripheral/can/plib_can1.c | 911 ------------------ .../config/default/peripheral/can/plib_can1.h | 123 --- .../default/peripheral/can/plib_can_common.h | 523 +++------- .../default/peripheral/clock/plib_clock.c | 9 +- .../default/peripheral/nvic/plib_nvic.c | 2 - .../default/peripheral/port/plib_port.c | 35 +- .../default/peripheral/port/plib_port.h | 45 + bms/bms/bms_config/src/ic_bms/bms_spi.c | 7 + bms/bms/bms_config/src/ic_bms/spi_test.c | 6 +- bms/bms/bms_config/src/main.c | 13 +- 26 files changed, 1644 insertions(+), 2344 deletions(-) delete mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/can1.yml delete mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c delete mode 100644 bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml index e681f76d..67ee6bc4 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/can0.yml @@ -37,7 +37,7 @@ data: id: readOnly children: - type: Value - value: 'true' + value: 'false' type: Boolean type: Attributes - children: @@ -45,6 +45,9 @@ data: id: can0 value: '2' type: Dynamic + - attributes: + value: '3' + type: User type: Values type: Integer NOMINAL_SAMPLE_POINT: @@ -56,7 +59,7 @@ data: id: readOnly children: - type: Value - value: 'true' + value: 'false' type: Boolean type: Attributes - children: @@ -64,6 +67,9 @@ data: id: can0 value: '96.875' type: Dynamic + - attributes: + value: '75.0' + type: User type: Values type: Float NBTP_TOTAL_TIME_QUANTA: @@ -73,7 +79,7 @@ data: - children: - attributes: id: can0 - value: '32' + value: '24' type: Dynamic type: Values type: Integer @@ -84,7 +90,7 @@ data: - children: - attributes: id: can0 - value: '30' + value: '17' type: Dynamic type: Values type: Integer @@ -95,7 +101,7 @@ data: - children: - attributes: id: can0 - value: '1' + value: '6' type: Dynamic type: Values type: Integer @@ -106,8 +112,11 @@ data: - children: - attributes: id: can0 - value: '1' + value: '6' type: Dynamic + - attributes: + value: '5' + type: User type: Values type: Integer CALCULATED_NOMINAL_BITRATE: @@ -128,7 +137,7 @@ data: - children: - attributes: id: can0 - value: '62.500' + value: '83.333' type: Dynamic type: Values type: String @@ -149,7 +158,7 @@ data: children: - children: - attributes: - value: 'true' + value: 'false' type: User type: Values type: Boolean @@ -160,7 +169,7 @@ data: - children: - attributes: id: can0 - value: '8' + value: '24' type: Dynamic type: Values type: Integer @@ -171,7 +180,7 @@ data: - children: - attributes: id: can0 - value: '6' + value: '17' type: Dynamic type: Values type: Integer @@ -182,7 +191,7 @@ data: - children: - attributes: id: can0 - value: '1' + value: '6' type: Dynamic type: Values type: Integer @@ -193,8 +202,11 @@ data: - children: - attributes: id: can0 - value: '1' + value: '6' type: Dynamic + - attributes: + value: '5' + type: User type: Values type: Integer CALCULATED_DATA_BITRATE: @@ -215,7 +227,7 @@ data: - children: - attributes: id: can0 - value: '62.500' + value: '20.833' type: Dynamic type: Values type: String @@ -249,7 +261,7 @@ data: id: source children: - type: Value - value: ../peripheral/can_u2003/templates/plib_can_interrupt.h.ftl + value: ../peripheral/can_u2003/templates/plib_can_legacy.h.ftl type: String type: Attributes type: File @@ -262,7 +274,7 @@ data: id: source children: - type: Value - value: ../peripheral/can_u2003/templates/plib_can_interrupt.c.ftl + value: ../peripheral/can_u2003/templates/plib_can_legacy.c.ftl type: String type: Attributes type: File @@ -285,7 +297,7 @@ data: id: readOnly children: - type: Value - value: 'true' + value: 'false' type: Boolean type: Attributes - children: @@ -293,6 +305,9 @@ data: id: can0 value: '2' type: Dynamic + - attributes: + value: '0' + type: User type: Values type: Integer DATA_SAMPLE_POINT: @@ -304,7 +319,7 @@ data: id: readOnly children: - type: Value - value: 'true' + value: 'false' type: Boolean type: Attributes - children: @@ -312,6 +327,9 @@ data: id: can0 value: '87.5' type: Dynamic + - attributes: + value: '75.0' + type: User type: Values type: Float AUTO_DATA_BIT_TIMING_CALCULATION: @@ -320,7 +338,7 @@ data: children: - children: - attributes: - value: 'true' + value: 'false' type: User type: Values type: Boolean @@ -344,4 +362,165 @@ data: type: User type: Values type: Integer + headerFile: + attributes: + id: headerFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_common_legacy.h + type: String + type: Attributes + type: File + CAN_GENERATE_LEGACY_APIS: + attributes: + id: CAN_GENERATE_LEGACY_APIS + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_WATERMARK: + attributes: + id: RXF0_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + RXF0_ELEMENTS: + attributes: + id: RXF0_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + RXF0_BYTES_CFG: + attributes: + id: RXF0_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + RXF1_USE: + attributes: + id: RXF1_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + RXBUF_USE: + attributes: + id: RXBUF_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + TX_FIFO_WATERMARK: + attributes: + id: TX_FIFO_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + TX_FIFO_ELEMENTS: + attributes: + id: TX_FIFO_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + TX_FIFO_BYTES_CFG: + attributes: + id: TX_FIFO_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + FILTERS_STD_NOMATCH: + attributes: + id: FILTERS_STD_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + FILTERS_EXT_NOMATCH: + attributes: + id: FILTERS_EXT_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + TIMESTAMP_ENABLE: + attributes: + id: TIMESTAMP_ENABLE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_OVERWRITE: + attributes: + id: RXF0_OVERWRITE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml b/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml deleted file mode 100644 index e38d1719..00000000 --- a/bms/bms/bms_config/mcc/bms_config_default/components/can1.yml +++ /dev/null @@ -1,202 +0,0 @@ -configVersion: 1.0.0 -componentName: can1 -coreVersion: 5.8.4 -device: ATSAMC21J18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: can1 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: can1 - x: '196' - y: '146' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - AUTO_DATA_BIT_TIMING_CALCULATION: - attributes: - id: AUTO_DATA_BIT_TIMING_CALCULATION - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - CALCULATED_DATA_BITRATE: - attributes: - id: CALCULATED_DATA_BITRATE - children: - - children: - - attributes: - id: can1 - value: '500' - type: Dynamic - type: Values - type: Integer - CALCULATED_DATA_ERRORRATE: - attributes: - id: CALCULATED_DATA_ERRORRATE - children: - - children: - - attributes: - id: can1 - value: '0.000' - type: Dynamic - type: Values - type: String - CAN_OPMODE: - attributes: - id: CAN_OPMODE - children: - - children: - - attributes: - value: CAN FD - type: User - type: Values - type: Combo - DATA_SAMPLE_POINT: - attributes: - id: DATA_SAMPLE_POINT - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - id: can1 - value: '96.875' - type: Dynamic - type: Values - type: Float - DATA_TIME_QUANTA_PERIOD: - attributes: - id: DATA_TIME_QUANTA_PERIOD - children: - - children: - - attributes: - id: can1 - value: '62.500' - type: Dynamic - type: Values - type: String - DBTP_DBRP: - attributes: - id: DBTP_DBRP - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - id: can1 - value: '2' - type: Dynamic - type: Values - type: Integer - DBTP_DSJW: - attributes: - id: DBTP_DSJW - children: - - children: - - attributes: - id: can1 - value: '1' - type: Dynamic - type: Values - type: Integer - DBTP_DTSEG1: - attributes: - id: DBTP_DTSEG1 - children: - - children: - - attributes: - id: can1 - value: '30' - type: Dynamic - type: Values - type: Integer - DBTP_DTSEG2: - attributes: - id: DBTP_DTSEG2 - children: - - children: - - attributes: - id: can1 - value: '1' - type: Dynamic - type: Values - type: Integer - DBTP_TOTAL_TIME_QUANTA: - attributes: - id: DBTP_TOTAL_TIME_QUANTA - children: - - children: - - attributes: - id: can1 - value: '32' - type: Dynamic - type: Values - type: Integer - INTERRUPT_MODE: - attributes: - id: INTERRUPT_MODE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - instHeaderFile: - attributes: - id: instHeaderFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_interrupt.h.ftl - type: String - type: Attributes - type: File - sourceFile: - attributes: - id: sourceFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_interrupt.c.ftl - type: String - type: Attributes - type: File - userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index 35eb4e25..4bc8de4f 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -167,7 +167,7 @@ data: - children: - attributes: id: core - value: '0x1fff' + value: '0x1dff' type: Dynamic type: Values type: String @@ -343,7 +343,7 @@ data: - children: - attributes: id: core - value: '48000000' + value: '0' type: Dynamic type: Values type: Integer @@ -354,7 +354,7 @@ data: - children: - attributes: id: core - value: '48000000' + value: '0' type: Dynamic type: Values type: Integer @@ -365,7 +365,7 @@ data: - children: - attributes: id: core - value: 'true' + value: 'false' type: Dynamic type: Values type: Boolean @@ -453,7 +453,7 @@ data: - children: - attributes: id: core - value: 'false' + value: 'true' type: Dynamic type: Values type: Boolean @@ -464,8 +464,11 @@ data: - children: - attributes: id: core - value: 'true' + value: 'false' type: Dynamic + - attributes: + value: 'false' + type: User type: Values type: Boolean NVIC_16_0_HANDLER: @@ -475,7 +478,7 @@ data: - children: - attributes: id: core - value: CAN1_InterruptHandler + value: CAN1_Handler type: Dynamic type: Values type: String @@ -486,7 +489,7 @@ data: - children: - attributes: id: core - value: 'true' + value: 'false' type: Dynamic type: Values type: Boolean @@ -732,50 +735,6 @@ data: type: Dynamic type: Values type: String - CAN1_CLOCK_ENABLE: - attributes: - id: CAN1_CLOCK_ENABLE - children: - - children: - - attributes: - id: can1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN1_INTERRUPT_ENABLE: - attributes: - id: CAN1_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: can1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN1_INTERRUPT_HANDLER: - attributes: - id: CAN1_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: can1 - value: CAN1_InterruptHandler - type: Dynamic - type: Values - type: String - CAN1_INTERRUPT_HANDLER_LOCK: - attributes: - id: CAN1_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: can1 - value: 'true' - type: Dynamic - type: Values - type: Boolean SERCOM0_CORE_CLOCK_FREQUENCY: attributes: id: SERCOM0_CORE_CLOCK_FREQUENCY @@ -1034,7 +993,7 @@ data: - children: - attributes: id: core - value: '0x80' + value: '0x100c8080' type: Dynamic type: Values type: String @@ -1738,6 +1697,725 @@ data: type: User type: Values type: String + PIN_53_MODE: + attributes: + id: PIN_53_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_FUNCTION_TYPE: + attributes: + id: PIN_53_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG28: + attributes: + id: PORT_GROUP_0_PINCFG28 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_28_USED: + attributes: + id: PORT_GROUP_0_PIN_28_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_53_INEN: + attributes: + id: PIN_53_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_DIR: + attributes: + id: PIN_53_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX14: + attributes: + id: PORT_GROUP_0_PMUX14 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_28: + attributes: + id: PORT_GROUP_0_PAD_28 + children: + - children: + - attributes: + id: core + value: PA28 + type: Dynamic + type: Values + type: String + PIN_53_PERIPHERAL_FUNCTION: + attributes: + id: PIN_53_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_53_FUNCTION_NAME: + attributes: + id: PIN_53_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_G + type: User + type: Values + type: String + PIN_53_DRVSTR: + attributes: + id: PIN_53_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PIN_38_MODE: + attributes: + id: PIN_38_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_FUNCTION_TYPE: + attributes: + id: PIN_38_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG19: + attributes: + id: PORT_GROUP_0_PINCFG19 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_19_USED: + attributes: + id: PORT_GROUP_0_PIN_19_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_38_INEN: + attributes: + id: PIN_38_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_DIR: + attributes: + id: PIN_38_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX9: + attributes: + id: PORT_GROUP_0_PMUX9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_19: + attributes: + id: PORT_GROUP_0_PAD_19 + children: + - children: + - attributes: + id: core + value: PA19 + type: Dynamic + type: Values + type: String + PIN_38_PERIPHERAL_FUNCTION: + attributes: + id: PIN_38_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_38_FUNCTION_NAME: + attributes: + id: PIN_38_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_Y + type: User + type: Values + type: String + PIN_37_MODE: + attributes: + id: PIN_37_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_FUNCTION_TYPE: + attributes: + id: PIN_37_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG18: + attributes: + id: PORT_GROUP_0_PINCFG18 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_18_USED: + attributes: + id: PORT_GROUP_0_PIN_18_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_37_INEN: + attributes: + id: PIN_37_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_DIR: + attributes: + id: PIN_37_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_18: + attributes: + id: PORT_GROUP_0_PAD_18 + children: + - children: + - attributes: + id: core + value: PA18 + type: Dynamic + type: Values + type: String + PIN_37_PERIPHERAL_FUNCTION: + attributes: + id: PIN_37_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_37_FUNCTION_NAME: + attributes: + id: PIN_37_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_R + type: User + type: Values + type: String + PIN_31_MODE: + attributes: + id: PIN_31_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_FUNCTION_TYPE: + attributes: + id: PIN_31_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG14: + attributes: + id: PORT_GROUP_0_PINCFG14 + children: + - children: + - attributes: + id: core + value: '0x2' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_14_USED: + attributes: + id: PORT_GROUP_0_PIN_14_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_31_INEN: + attributes: + id: PIN_31_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_31_DIR: + attributes: + id: PIN_31_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PMUX7: + attributes: + id: PORT_GROUP_0_PMUX7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_14: + attributes: + id: PORT_GROUP_0_PAD_14 + children: + - children: + - attributes: + id: core + value: PA14 + type: Dynamic + type: Values + type: String + PIN_31_PERIPHERAL_FUNCTION: + attributes: + id: PIN_31_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_31_FUNCTION_NAME: + attributes: + id: PIN_31_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN_RX_WAKEUP + type: User + type: Values + type: String + PIN_32_MODE: + attributes: + id: PIN_32_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_FUNCTION_TYPE: + attributes: + id: PIN_32_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG15: + attributes: + id: PORT_GROUP_0_PINCFG15 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_15_USED: + attributes: + id: PORT_GROUP_0_PIN_15_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_32_INEN: + attributes: + id: PIN_32_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_DIR: + attributes: + id: PIN_32_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_15: + attributes: + id: PORT_GROUP_0_PAD_15 + children: + - children: + - attributes: + id: core + value: PA15 + type: Dynamic + type: Values + type: String + PIN_32_PERIPHERAL_FUNCTION: + attributes: + id: PIN_32_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_32_FUNCTION_NAME: + attributes: + id: PIN_32_FUNCTION_NAME + children: + - children: + - attributes: + value: STB + type: User + type: Values + type: String + PIN_31_PULLEN: + attributes: + id: PIN_31_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_DRVSTR: + attributes: + id: PIN_31_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PORT_GROUP_0_PINCFG21: + attributes: + id: PORT_GROUP_0_PINCFG21 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_21_USED: + attributes: + id: PORT_GROUP_0_PIN_21_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX10: + attributes: + id: PORT_GROUP_0_PMUX10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_21: + attributes: + id: PORT_GROUP_0_PAD_21 + children: + - children: + - attributes: + id: core + value: PA21 + type: Dynamic + type: Values + type: String + PIN_42_PERIPHERAL_FUNCTION: + attributes: + id: PIN_42_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_MODE: + attributes: + id: PIN_45_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_FUNCTION_TYPE: + attributes: + id: PIN_45_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG24: + attributes: + id: PORT_GROUP_0_PINCFG24 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_24_USED: + attributes: + id: PORT_GROUP_0_PIN_24_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX12: + attributes: + id: PORT_GROUP_0_PMUX12 + children: + - children: + - attributes: + id: core + value: '0x66' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_24: + attributes: + id: PORT_GROUP_0_PAD_24 + children: + - children: + - attributes: + id: core + value: PA24 + type: Dynamic + type: Values + type: String + PIN_45_PERIPHERAL_FUNCTION: + attributes: + id: PIN_45_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_46_MODE: + attributes: + id: PIN_46_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_46_FUNCTION_TYPE: + attributes: + id: PIN_46_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PORT_GROUP_0_PAD_25: + attributes: + id: PORT_GROUP_0_PAD_25 + children: + - children: + - attributes: + id: core + value: PA25 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG25: + attributes: + id: PORT_GROUP_0_PINCFG25 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_25_USED: + attributes: + id: PORT_GROUP_0_PIN_25_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_46_PERIPHERAL_FUNCTION: + attributes: + id: PIN_46_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml b/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml index e8cab14d..b4b5ca49 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/sercom4.yml @@ -68,8 +68,8 @@ data: - children: - attributes: id: sercom4 - x: '60' - y: '344' + x: '67' + y: '340' type: ElementPosition type: ElementPositions type: ComponentGraph diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index 8948d326..6efee931 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -8,7 +8,6 @@ modules: - adc0 - adc1 - can0 -- can1 - cmsis - core - dfp @@ -22,7 +21,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/ATSAMC21J18A.ld hash: 3fc7dbb63ae72ecd9b52572e4dd84ed79cbd37feb6064cb6d4df6fca301d09af - file: ../src/config/default/definitions.h - hash: 5c3b223526d2cb5ed3468dda6a1fe34df911ac1c46135acf8d4f73b28eadab9b + hash: 684faba403aafc7df339db66a96ecb1ff272af6fb7cfa3eb3576efb3bebe9bca - file: ../src/config/default/device.h hash: e539bb402fa4783d95ccf06235458b2e1fe01207c83c0e046a853e0385d0b6f4 - file: ../src/config/default/device_cache.h @@ -32,11 +31,11 @@ generatedFileHashHistoryMap: - file: ../src/config/default/exceptions.c hash: 42f9da2668e04ccb3473d45b149683a00f80072c6883c7918d6ce93997cd6987 - file: ../src/config/default/initialization.c - hash: 1375f7d05ec7060f5abb29c79e4b4fae0b27af9573f79ac5a616f77ab8b165bb + hash: 5c258d45783593cea48b4f20bb97db97d66b79498b80b83f7311da19ec246d0b - file: ../src/config/default/interrupts.c - hash: b334b6f53c28ee3dba860dd2edd4a121b9526d6f4f96067a92960fa67c5ace92 + hash: 5891bfdfcd6ac15ae3104b3e1b8f9dc3f23b3f3693d906c95ba2bf63f2db3325 - file: ../src/config/default/interrupts.h - hash: 8bd51246b301b4f479b766a82de6995ae32c86486b464b0328593e157052eda8 + hash: 7a7d09f2efa3d5fb17247f2395f89f2c64fcf57376d3c9f55d2f7a73480fa813 - file: ../src/config/default/libc_syscalls.c hash: 88bb2e34c939601b5b7ad076556e3ee0fcedf388436b8cddb6d6fd3e9d07472f - file: ../src/config/default/peripheral/adc/plib_adc0.c @@ -50,17 +49,13 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/adc/plib_adc_common.h hash: c3ed4d59b7017ce8159a3dd0773d5744387f9673350f439f3665b52446376d79 - file: ../src/config/default/peripheral/can/plib_can0.c - hash: 7f0eea33ffe3942f00d645cc9590cbeb93e3aacf764aa27d47528f8200877f0f + hash: 8db69bf44d038bb3cedca7630a438d3dbdb890e7bb82413fcb9561609f605248 - file: ../src/config/default/peripheral/can/plib_can0.h - hash: 82effa7ee26a29add640e0239848f8265bf69247e1c29d24fa8b05ed853de21e -- file: ../src/config/default/peripheral/can/plib_can1.c - hash: f405307acbc691f6d286c022386f428d7d5b48ee9ba68563ab62744b2478330a -- file: ../src/config/default/peripheral/can/plib_can1.h - hash: 3237de4a4f656f996a4b3c449dbd14e23be7ee0885790c1853b2c1990d714413 + hash: aed6fc83c92561a8fe3d349062fb53a50d15e8260a926267312e37be1776ffc2 - file: ../src/config/default/peripheral/can/plib_can_common.h - hash: e0e3b54f69be9d8811bbe507f91daa443ae7bff5dc724ac51baebc160097b2d6 + hash: bbff8462d7871f1cbd6b2746cbb726e4a13cf6a5e6d85d60a67803620a1679ae - file: ../src/config/default/peripheral/clock/plib_clock.c - hash: f25fa3a02969658149292d7db24592b04413717fb07310ded817f7d1c31bd12b + hash: 55dfd48597fd5a1af3f1a7cf2d201f31f8c41b390c9c487632997e437aa0e39f - file: ../src/config/default/peripheral/clock/plib_clock.h hash: 01c269741541514e997ef61546f4dbb0e23f66e27c6a957162557f13b4638baf - file: ../src/config/default/peripheral/evsys/plib_evsys.c @@ -68,7 +63,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/evsys/plib_evsys.h hash: f7d08eb8162f271ce1db384c082586a6624e506aa7f502c64c4ab5a1aadac47d - file: ../src/config/default/peripheral/nvic/plib_nvic.c - hash: 0d3ba62c35d242212df5ddc0dae9cadcc8462b3b4c49a6ae2cbcfb2a60fe5f73 + hash: d09819a3c60270cd4c30c2eb519f7241c4dbc62edb7092e24ea4417a2242b1e3 - file: ../src/config/default/peripheral/nvic/plib_nvic.h hash: 9936ac782115af41003255283fa2f603f4ff2212d16275b7c80ea8d067a9e208 - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -76,9 +71,9 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.h hash: a2f572d8ba174971959f4a9319fc61b460c00432512d38e19e28e2dfddf6cde5 - file: ../src/config/default/peripheral/port/plib_port.c - hash: d8c1024f8c78bb4b3891b91710ca473e9e840d9022770fc59928c8d0b0992ca3 + hash: ff6d0b082a519a469666037c53308de446c9bda6a302d82e87366dbfd558c9f5 - file: ../src/config/default/peripheral/port/plib_port.h - hash: 0d1bcf9588384b8fcfb935d32fa0c2bd97841ae22a886f5cbb4147d473272184 + hash: dafff9b826888261d127ef40721d4e41cd0d67c713eb8f7e0df999847609097a - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c hash: 5ad6a7aecfa835077677e73fc771c2d82f35bdf4da9b54b499203176295ed534 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h @@ -98,7 +93,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h hash: 3653b66472c558c50f7037a1dd25d2678e9a13aa718f3c53a2195e6f3919ea48 - file: ../src/config/default/pin_configurations.csv - hash: 425b48965d8457eba4933205ce346ea114b77d3ae94093c90c33192ae671b7c0 + hash: e35ae33fa8f5d966a9cd32cfcd38a19d49456cc68881315a9aeaf3fbdbdf72b3 - file: ../src/config/default/startup_xc32.c hash: e6227d89e36b74af1bc21e00e80b390502c97aaaa65796291f63b2d96cf0678e - file: ../src/config/default/stdio/xc32_monitor.c diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index f2aaf0f2..225ee0a2 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-05T14:38:04.136+01:00[Europe/Oslo] +creation_date: 2026-02-12T15:46:42.434+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml index b4225a23..9188962e 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-05T11:06:19.821+01:00[Europe/Oslo] +creation_date: 2026-02-12T15:39:48.277+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/app/can_facade.c b/bms/bms/bms_config/src/app/can_facade.c index 35b5a5ed..10bc9af1 100644 --- a/bms/bms/bms_config/src/app/can_facade.c +++ b/bms/bms/bms_config/src/app/can_facade.c @@ -1,64 +1,76 @@ -#include "definitions.h" -#include "can_facade.h" +/* + Platform: + ATSAMC21 -/* RX state */ -static volatile bool rx_ready = false; -static CAN_RX_BUFFER rx_buf; + Company: + Vortex NTNU. -/* CAN message RAM */ -static bool ram_bound = false; -static uint8_t can_msg_ram[CAN0_MESSAGE_RAM_CONFIG_SIZE]; + Author: + Markus Sandvik -/* RX callback */ -void APP_CAN_RxCallback(uint8_t numberOfMessage, uintptr_t context) -{ - (void)context; - (void)numberOfMessage; + File Name: + can_facade.c + */ - /* Fetch one message from FIFO0 */ - if (CAN0_MessageReceiveFifo(CAN_RX_FIFO_0, 1, &rx_buf)) - { - rx_ready = true; - /* Re-arm is implicit; FIFO is re-used after ack inside plib */ - } -} - -/* Init */ -void CAN_Init(void) -{ - if (!ram_bound) - { - CAN0_MessageRAMConfigSet(can_msg_ram); - ram_bound = true; - } - - /* Accept all standard/extended frames into FIFO0 (override MCC default reject). */ - CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_RXF0 | CAN_GFC_ANFE_RXF0; - - /* Register RX callback on FIFO0 */ - CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_0, APP_CAN_RxCallback, (uintptr_t)NULL); - - /* Optional: relax global filters if needed (left as-is for now) */ -} - -/* Send a standard 11-bit ID data frame */ -bool CAN_Send(uint32_t id, const uint8_t *data, uint8_t len) -{ - if (len > 8U || data == NULL) - return false; - - CAN_TX_BUFFER tx = {0}; - tx.id = (id & 0x7FFU) << 18; /* standard ID format */ - tx.xtd = 0; - tx.rtr = 0; - tx.dlc = len & 0xFU; - tx.brs = 0; - tx.fdf = 0; - tx.efc = 0; - tx.mm = 0; - for (uint8_t i = 0; i < len; i++) - tx.data[i] = data[i]; - - /* Single-message transmit via FIFO */ - return CAN0_MessageTransmitFifo(1, &tx); -} + #include "definitions.h" + #include "can_facade.h" + + /* ===== RX variables ===== */ + volatile bool rxReady = false; + + uint32_t rx_messageID = 0; + uint8_t rx_message[64] = {0}; + uint8_t rx_messageLength = 0; + uint16_t timestamp = 0; + + static CAN_MSG_RX_FRAME_ATTRIBUTE msgFrameAttr = CAN_MSG_RX_DATA_FRAME; + + /* ===== CAN RAM ===== */ + static bool s_ram_bound = false; + static uint8_t s_can_msg_ram[CAN0_MESSAGE_RAM_CONFIG_SIZE]; + + /* ===== ISR callback ===== */ + void APP_CAN_Callback(uintptr_t context) + { + (void)context; + + rxReady = true; + + printf("Callback"); + + /* Re-arm RX */ + CAN0_MessageReceive(&rx_messageID, + &rx_messageLength, + rx_message, + ×tamp, + CAN_MSG_ATTR_RX_FIFO0, + &msgFrameAttr); + } + + /* ===== Init ===== */ + void CAN_Init(void) + { + if (!s_ram_bound) + { + CAN0_MessageRAMConfigSet(s_can_msg_ram); + s_ram_bound = true; + } + + CAN0_RxCallbackRegister(APP_CAN_Callback, (uintptr_t)NULL, CAN_MSG_ATTR_RX_FIFO0); + + CAN0_MessageReceive(&rx_messageID, + &rx_messageLength, + rx_message, + ×tamp, + CAN_MSG_ATTR_RX_FIFO0, + &msgFrameAttr); + } + + /* ===== Send ===== */ + bool CAN_Send(uint32_t id, uint8_t *data, uint8_t len) + { + const CAN_MODE mode = CAN_MODE_FD_WITHOUT_BRS; + const CAN_MSG_TX_ATTRIBUTE attr = CAN_MSG_ATTR_TX_FIFO_DATA_FRAME; + + return CAN0_MessageTransmit(id, len, data, mode, attr); + } \ No newline at end of file diff --git a/bms/bms/bms_config/src/app/can_facade.h b/bms/bms/bms_config/src/app/can_facade.h index f4977390..112829eb 100644 --- a/bms/bms/bms_config/src/app/can_facade.h +++ b/bms/bms/bms_config/src/app/can_facade.h @@ -1,26 +1,37 @@ -#ifndef CAN_FACADE_H -#define CAN_FACADE_H +/* + Platform: + ATSAMC21 -#include -#include -#include "definitions.h" + Company: + Vortex NTNU. -#ifdef __cplusplus -extern "C" { -#endif + Author: + Markus Sandvik -/* Suggested arbitration IDs (11-bit standard). Lower numeric = higher priority. */ -#define CAN_ID_SHUTDOWN_CMD 0x050U /* Highest priority: killswitch/leak */ -#define CAN_ID_LEAK_ALERT 0x060U /* Telemetry alert to BMS */ -#define CAN_ID_BMS_STATUS 0x180U /* Periodic pack/FET status */ -#define CAN_ID_CELL_V_BASE 0x200U /* Cell voltages: CAN_ID_CELL_V_BASE + cell_index (0..15) */ + File Name: + can_facade.h + */ -void CAN_Init(void); -bool CAN_Send(uint32_t id, const uint8_t *data, uint8_t len); -void APP_CAN_RxCallback(uint8_t numberOfMessage, uintptr_t context); - -#ifdef __cplusplus -} -#endif - -#endif /* CAN_FACADE_H */ + #ifndef CAN_FACADE_H + #define CAN_FACADE_H + + #pragma once + #include + #include + #include "definitions.h" + + #ifdef __cplusplus + extern "C" { + #endif + + void CAN_Init(void); + bool CAN_Send(uint32_t id, uint8_t *data, uint8_t len); + void APP_CAN_Callback(uintptr_t context); + + + #ifdef __cplusplus + } + #endif + + #endif // CAN_FACADE_H + \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/definitions.h b/bms/bms/bms_config/src/config/default/definitions.h index eeba27c2..c995fad9 100644 --- a/bms/bms/bms_config/src/config/default/definitions.h +++ b/bms/bms/bms_config/src/config/default/definitions.h @@ -51,16 +51,15 @@ #include #include "peripheral/nvmctrl/plib_nvmctrl.h" #include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" -#include "peripheral/evsys/plib_evsys.h" #include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" -#include "peripheral/can/plib_can1.h" +#include "peripheral/evsys/plib_evsys.h" +#include "peripheral/adc/plib_adc0.h" #include "peripheral/port/plib_port.h" #include "peripheral/clock/plib_clock.h" #include "peripheral/nvic/plib_nvic.h" -#include "peripheral/sercom/usart/plib_sercom4_usart.h" -#include "peripheral/can/plib_can0.h" -#include "peripheral/adc/plib_adc0.h" #include "peripheral/adc/plib_adc1.h" +#include "peripheral/can/plib_can0.h" +#include "peripheral/sercom/usart/plib_sercom4_usart.h" // DOM-IGNORE-BEGIN #ifdef __cplusplus // Provide C++ Compatibility diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml index 28ff6baf..939f19f5 100644 --- a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -4,7 +4,7 @@ project: bms_config_default -creation_date: 2026-02-05T11:06:19.827+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +creation_date: 2026-02-12T15:39:48.282+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime operating_system: Linux mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] mcc_version: v5.6.4 diff --git a/bms/bms/bms_config/src/config/default/initialization.c b/bms/bms/bms_config/src/config/default/initialization.c index 4b5a7fb2..89c74f5a 100644 --- a/bms/bms/bms_config/src/config/default/initialization.c +++ b/bms/bms/bms_config/src/config/default/initialization.c @@ -170,20 +170,18 @@ void SYS_Initialize ( void* data ) SERCOM1_I2C_Initialize(); - EVSYS_Initialize(); - SERCOM0_SPI_Initialize(); - CAN1_Initialize(); - - SERCOM4_USART_Initialize(); - - CAN0_Initialize(); + EVSYS_Initialize(); ADC0_Initialize(); ADC1_Initialize(); + CAN0_Initialize(); + + SERCOM4_USART_Initialize(); + NVIC_Initialize(); diff --git a/bms/bms/bms_config/src/config/default/interrupts.c b/bms/bms/bms_config/src/config/default/interrupts.c index 11668af1..2a2bdeb0 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.c +++ b/bms/bms/bms_config/src/config/default/interrupts.c @@ -75,7 +75,7 @@ void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(vo } /* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 8.6 deviated 30 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 31 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ /* Device vectors list dummy definition*/ extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); @@ -93,6 +93,7 @@ extern void SERCOM2_Handler ( void ) __attribute__((weak, alias("Dumm extern void SERCOM3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SERCOM4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SERCOM5_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void CAN1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TCC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TCC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TCC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); @@ -143,7 +144,7 @@ const H3DeviceVectors exception_table= .pfnSERCOM4_Handler = SERCOM4_Handler, .pfnSERCOM5_Handler = SERCOM5_Handler, .pfnCAN0_Handler = CAN0_InterruptHandler, - .pfnCAN1_Handler = CAN1_InterruptHandler, + .pfnCAN1_Handler = CAN1_Handler, .pfnTCC0_Handler = TCC0_Handler, .pfnTCC1_Handler = TCC1_Handler, .pfnTCC2_Handler = TCC2_Handler, diff --git a/bms/bms/bms_config/src/config/default/interrupts.h b/bms/bms/bms_config/src/config/default/interrupts.h index 9206fa21..46d67e40 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.h +++ b/bms/bms/bms_config/src/config/default/interrupts.h @@ -62,7 +62,6 @@ void HardFault_Handler (void); void SERCOM0_SPI_InterruptHandler (void); void SERCOM1_I2C_InterruptHandler (void); void CAN0_InterruptHandler (void); -void CAN1_InterruptHandler (void); diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c index 4431844a..8a077f3b 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.c @@ -21,7 +21,7 @@ //DOM-IGNORE-BEGIN /******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. * * Subject to your compliance with these terms, you may use Microchip software * and any derivatives exclusively with Microchip products. It is your @@ -59,20 +59,56 @@ // ***************************************************************************** // ***************************************************************************** #define CAN_STD_ID_Msk 0x7FFU - -static volatile CAN_TX_FIFO_CALLBACK_OBJ can0TxFifoCallbackObj; -static volatile CAN_TX_EVENT_FIFO_CALLBACK_OBJ can0TxEventFifoCallbackObj; -static volatile CAN_RX_FIFO_CALLBACK_OBJ can0RxFifoCallbackObj[2]; -static volatile CAN_CALLBACK_OBJ can0CallbackObj; +#define CAN_CALLBACK_TX_INDEX 3U +#define NUM_RX_FIFOS 2U +#define NUM_RX_BUFFER_ELEMENTS 8U +static volatile CAN_RX_MSG can0RxMsg[NUM_RX_FIFOS][NUM_RX_BUFFER_ELEMENTS]; +static volatile CAN_CALLBACK_OBJ can0CallbackObj[4]; static volatile CAN_OBJ can0Obj; -static inline void CAN0_ZeroInitialize(volatile void* pData, size_t dataSize) +/****************************************************************************** +Local Functions +******************************************************************************/ + +static void CANLengthToDlcGet(uint8_t length, uint8_t *dlc) { - volatile uint8_t* data = (volatile uint8_t*)pData; - for (uint32_t index = 0; index < dataSize; index++) + if (length <= 8U) + { + *dlc = length; + } + else if (length <= 12U) + { + *dlc = 0x9U; + } + else if (length <= 16U) + { + *dlc = 0xAU; + } + else if (length <= 20U) + { + *dlc = 0xBU; + } + else if (length <= 24U) { - data[index] = 0U; + *dlc = 0xCU; } + else if (length <= 32U) + { + *dlc = 0xDU; + } + else if (length <= 48U) + { + *dlc = 0xEU; + } + else + { + *dlc = 0xFU; + } +} +static uint8_t CANDlcToLengthGet(uint8_t dlc) +{ + const uint8_t msgLength[] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U}; + return msgLength[dlc]; } // ***************************************************************************** @@ -109,18 +145,21 @@ void CAN0_Initialize(void) CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; /* Set Data Bit Timing and Prescaler Register */ - CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(0UL) | CAN_DBTP_DTSEG1(5UL) | CAN_DBTP_DBRP(2UL) | CAN_DBTP_DSJW(0UL); + CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(5UL) | CAN_DBTP_DTSEG1(16UL) | CAN_DBTP_DBRP(0UL) | CAN_DBTP_DSJW(4UL); /* Set Nominal Bit timing and Prescaler Register */ - CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(0UL) | CAN_NBTP_NTSEG1(29UL) | CAN_NBTP_NBRP(2UL) | CAN_NBTP_NSJW(0UL); + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(5UL) | CAN_NBTP_NTSEG1(16UL) | CAN_NBTP_NBRP(3UL) | CAN_NBTP_NSJW(4UL); /* Receive Buffer / FIFO Element Size Configuration Register */ - CAN0_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(0UL) | CAN_RXESC_F1DS(0UL); + CAN0_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(7UL); /* Transmit Buffer/FIFO Element Size Configuration Register */ - CAN0_REGS->CAN_TXESC = CAN_TXESC_TBDS(0UL); + CAN0_REGS->CAN_TXESC = CAN_TXESC_TBDS(7UL); /* Global Filter Configuration Register */ - CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; + CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_RXF0 | CAN_GFC_ANFE_RXF0; + + /* Timestamp Counter Configuration Register */ + CAN0_REGS->CAN_TSCC = CAN_TSCC_TCP(0UL) | CAN_TSCC_TSS_INC; /* Set the operation mode */ CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; @@ -139,264 +178,229 @@ void CAN0_Initialize(void) CAN0_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; /* Enable CAN interrupts */ - CAN0_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk - | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk - | CAN_IE_TFEE_Msk - | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk - | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk - | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk - - | CAN_IE_MRAFE_Msk; - - CAN0_ZeroInitialize(&can0Obj.msgRAMConfig, sizeof(CAN_MSG_RAM_CONFIG)); + CAN0_REGS->CAN_IE = CAN_IE_BOE_Msk; + + // Initialize the CAN PLib Object + can0Obj.txBufferIndex = 0U; + can0Obj.rxBufferIndex1 = 0U; + can0Obj.rxBufferIndex2 = 0U; + (void) memset(can0RxMsg, 0x00, sizeof(can0RxMsg)); + (void) memset(&can0Obj.msgRAMConfig, 0x00, sizeof(CAN_MSG_RAM_CONFIG)); } - // ***************************************************************************** /* Function: - bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) + bool CAN0_MessageTransmit(uint32_t id, uint8_t length, uint8_t* data, CAN_MODE mode, CAN_MSG_TX_ATTRIBUTE msgAttr) Summary: - Transmit multiple messages into CAN bus from Tx FIFO. + Transmits a message into CAN bus. Precondition: CAN0_Initialize must have been called for the associated CAN instance. Parameters: - numberOfMessage - Total number of message. - txBuffer - Pointer to Tx buffer + id - 11-bit / 29-bit identifier (ID). + length - length of data buffer in number of bytes. + data - pointer to source data buffer + mode - CAN mode Classic CAN or CAN FD without BRS or CAN FD with BRS + msgAttr - Data Frame or Remote frame using Tx FIFO or Tx Buffer Returns: Request status. true - Request was successful. false - Request has failed. */ -bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) +bool CAN0_MessageTransmit(uint32_t id, uint8_t length, uint8_t* data, CAN_MODE mode, CAN_MSG_TX_ATTRIBUTE msgAttr) { - uint8_t *txFifo = NULL; - uint8_t *txBuf = (uint8_t *)txBuffer; - uint32_t bufferNumber = 0U; - uint8_t tfqpi = 0U; - uint8_t count = 0U; - bool transmitFifo_event = false; - - if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) + uint8_t dlc = 0U; + uint8_t tfqpi = 0U; + can_txbe_registers_t *fifo = NULL; + static uint8_t messageMarker = 0U; + bool op_success = false; + (void) mode; + + switch (msgAttr) { - tfqpi = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); - - for (count = 0U; count < numberOfMessage; count++) - { - txFifo = (uint8_t *)((uint8_t*)can0Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE)); - - (void) memcpy(txFifo, txBuf, CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE); - - txBuf += CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE; - bufferNumber |= (1UL << tfqpi); - tfqpi++; - if (tfqpi == 1U) + case CAN_MSG_ATTR_TX_FIFO_DATA_FRAME: + case CAN_MSG_ATTR_TX_FIFO_RTR_FRAME: + /* The FIFO is not full */ + if (0U == (CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQF_Msk)) { - tfqpi = 0U; + tfqpi = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + fifo = (can_txbe_registers_t *) ((uint8_t*)can0Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE)); + op_success = true; } - } - - __DSB(); - - /* Set Transmission request */ - CAN0_REGS->CAN_TXBAR = bufferNumber; - - transmitFifo_event = true; + break; + default: + /* Invalid Message Attribute */ + break; } - return transmitFifo_event; -} - -// ***************************************************************************** -/* Function: - uint8_t CAN0_TxFifoFreeLevelGet(void) - - Summary: - Returns Tx FIFO Free Level. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. + if (op_success) + { + /* If the id is longer than 11 bits, it is considered as extended identifier */ + if (id > CAN_STD_ID_Msk) + { + /* An extended identifier is stored into ID */ + fifo->CAN_TXBE_0 = (id & CAN_TXBE_0_ID_Msk) | CAN_TXBE_0_XTD_Msk; + } + else + { + /* A standard identifier is stored into ID[28:18] */ + fifo->CAN_TXBE_0 = id << 18U; + } + if (length > 64U) + { + length = 64U; + } - Parameters: - None. + CANLengthToDlcGet(length, &dlc); - Returns: - Tx FIFO Free Level. -*/ -uint8_t CAN0_TxFifoFreeLevelGet(void) -{ - return (uint8_t)(CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); -} + fifo->CAN_TXBE_1 = CAN_TXBE_1_DLC((uint32_t)dlc); -// ***************************************************************************** -/* Function: - bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) + if(mode == CAN_MODE_FD_WITH_BRS) + { + fifo->CAN_TXBE_1 |= CAN_TXBE_1_FDF_Msk | CAN_TXBE_1_BRS_Msk; + } + else if (mode == CAN_MODE_FD_WITHOUT_BRS) + { + fifo->CAN_TXBE_1 |= CAN_TXBE_1_FDF_Msk; + } + else + { + /* Do nothing */ + } + if ((msgAttr == CAN_MSG_ATTR_TX_BUFFER_DATA_FRAME) || (msgAttr == CAN_MSG_ATTR_TX_FIFO_DATA_FRAME)) + { + /* copy the data into the payload */ + (void) memcpy((uint8_t *)&fifo->CAN_TXBE_DATA, data, length); + } + else if ((msgAttr == CAN_MSG_ATTR_TX_BUFFER_RTR_FRAME) || (msgAttr == CAN_MSG_ATTR_TX_FIFO_RTR_FRAME)) + { + fifo->CAN_TXBE_0 |= CAN_TXBE_0_RTR_Msk; + } + else + { + /* Do nothing */ + } - Summary: - Check if Transmission request is pending for the specific Tx buffer. + messageMarker++; + fifo->CAN_TXBE_1 |= (((uint32_t)(messageMarker) << CAN_TXBE_1_MM_Pos) & CAN_TXBE_1_MM_Msk) | CAN_TXBE_1_EFC_Msk; - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. + CAN0_REGS->CAN_TXBTIE = 1UL << tfqpi; - Parameters: - None. + /* request the transmit */ + CAN0_REGS->CAN_TXBAR = 1UL << tfqpi; - Returns: - true - Transmission request is pending. - false - Transmission request is not pending. -*/ -bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) -{ - return ((CAN0_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); + CAN0_REGS->CAN_IE |= CAN_IE_TCE_Msk; + } + return op_success; } // ***************************************************************************** /* Function: - bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) + bool CAN0_MessageReceive(uint32_t *id, uint8_t *length, uint8_t *data, uint16_t *timestamp, + CAN_MSG_RX_ATTRIBUTE msgAttr, CAN_MSG_RX_FRAME_ATTRIBUTE *msgFrameAttr) Summary: - Read Tx Event FIFO for the transmitted messages. + Receives a message from CAN bus. Precondition: CAN0_Initialize must have been called for the associated CAN instance. Parameters: - numberOfTxEvent - Total number of Tx Event - txEventFifo - Pointer to Tx Event FIFO + id - Pointer to 11-bit / 29-bit identifier (ID) to be received. + length - Pointer to data length in number of bytes to be received. + data - pointer to destination data buffer + timestamp - Pointer to Rx message timestamp, timestamp value is 0 if timestamp is disabled + msgAttr - Message to be read from Rx FIFO0 or Rx FIFO1 or Rx Buffer + msgFrameAttr - Data frame or Remote frame to be received Returns: Request status. true - Request was successful. false - Request has failed. */ -bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) +bool CAN0_MessageReceive(uint32_t *id, uint8_t *length, uint8_t *data, uint16_t *timestamp, + CAN_MSG_RX_ATTRIBUTE msgAttr, CAN_MSG_RX_FRAME_ATTRIBUTE *msgFrameAttr) { - uint8_t txefgi = 0U; - uint8_t count = 0U; - uint8_t *txEvent = NULL; - uint8_t *txEvtFifo = (uint8_t *)txEventFifo; - bool txFifo_event = false; + uint8_t bufferIndex = 0U; + bool status = false; - if (txEventFifo != NULL) + switch (msgAttr) { - /* Read data from the Rx FIFO0 */ - txefgi = (uint8_t)((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); - for (count = 0U; count < numberOfTxEvent; count++) - { - txEvent = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); - - (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); - - if ((count + 1U) == numberOfTxEvent) - { - break; - } - txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); - txefgi++; - if (txefgi == 1U) - { - txefgi = 0U; - } - } - - /* Ack the Tx Event FIFO position */ - CAN0_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); - - txFifo_event = true; + case CAN_MSG_ATTR_RX_FIFO0: + bufferIndex = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + can0RxMsg[msgAttr][bufferIndex].rxId = id; + can0RxMsg[msgAttr][bufferIndex].rxBuffer = data; + can0RxMsg[msgAttr][bufferIndex].rxsize = length; + can0RxMsg[msgAttr][bufferIndex].timestamp = timestamp; + can0RxMsg[msgAttr][bufferIndex].msgFrameAttr = msgFrameAttr; + CAN0_REGS->CAN_IE |= CAN_IE_RF0NE_Msk; + status = true; + break; + default: + /* Do nothing */ + break; } - return txFifo_event; + return status; } - // ***************************************************************************** /* Function: - bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) + bool CAN0_TransmitEventFIFOElementGet(uint32_t *id, uint8_t *messageMarker, uint16_t *timestamp) Summary: - Read messages from Rx FIFO0/FIFO1. + Get the Transmit Event FIFO Element for the transmitted message. Precondition: CAN0_Initialize must have been called for the associated CAN instance. Parameters: - rxFifoNum - Rx FIFO number - numberOfMessage - Total number of message - rxBuffer - Pointer to Rx buffer + id - Pointer to 11-bit / 29-bit identifier (ID) to be received. + messageMarker - Pointer to Tx message message marker number to be received + timestamp - Pointer to Tx message timestamp to be received, timestamp value is 0 if Timestamp is disabled Returns: Request status. true - Request was successful. false - Request has failed. */ -bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) +bool CAN0_TransmitEventFIFOElementGet(uint32_t *id, uint8_t *messageMarker, uint16_t *timestamp) { - uint8_t rxgi = 0U; - uint8_t count = 0U; - uint8_t *rxFifo = NULL; - uint8_t *rxBuf = (uint8_t *)rxBuffer; + can_txefe_registers_t *txEventFIFOElement = NULL; + uint8_t txefgi = 0U; bool status = false; - if (rxBuffer != NULL) + /* Check if Tx Event FIFO Element available */ + if ((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk) != 0U) { - switch (rxFifoNum) + /* Get a pointer to Tx Event FIFO Element */ + txefgi = (uint8_t)((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); + txEventFIFOElement = (can_txefe_registers_t *) ((uint8_t *)can0Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(can_txefe_registers_t))); + + /* Check if it's a extended message type */ + if (0U != (txEventFIFOElement->CAN_TXEFE_0 & CAN_TXEFE_0_XTD_Msk)) { - case CAN_RX_FIFO_0: - /* Read data from the Rx FIFO0 */ - rxgi = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); - for (count = 0U; count < numberOfMessage; count++) - { - rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN0_RX_FIFO0_ELEMENT_SIZE)); - - (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO0_ELEMENT_SIZE); - - if ((count + 1U) == numberOfMessage) - { - break; - } - rxBuf += CAN0_RX_FIFO0_ELEMENT_SIZE; - rxgi++; - if (rxgi == 1U) - { - rxgi = 0U; - } - } - - /* Ack the fifo position */ - CAN0_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); - - status = true; - break; - case CAN_RX_FIFO_1: - /* Read data from the Rx FIFO1 */ - rxgi = (uint8_t)((CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); - for (count = 0U; count < numberOfMessage; count++) - { - rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN0_RX_FIFO1_ELEMENT_SIZE)); - - (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO1_ELEMENT_SIZE); - - if ((count + 1U) == numberOfMessage) - { - break; - } - rxBuf += CAN0_RX_FIFO1_ELEMENT_SIZE; - rxgi++; - if (rxgi == 1U) - { - rxgi = 0U; - } - } - /* Ack the fifo position */ - CAN0_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); - - status = true; - break; - default: - /* Do nothing */ - break; + *id = txEventFIFOElement->CAN_TXEFE_0 & CAN_TXEFE_0_ID_Msk; } + else + { + *id = (txEventFIFOElement->CAN_TXEFE_0 >> 18U) & CAN_STD_ID_Msk; + } + + *messageMarker = (uint8_t)((txEventFIFOElement->CAN_TXEFE_1 & CAN_TXEFE_1_MM_Msk) >> CAN_TXEFE_1_MM_Pos); + + /* Get timestamp from transmitted message */ + if (timestamp != NULL) + { + *timestamp = (uint16_t)(txEventFIFOElement->CAN_TXEFE_1 & CAN_TXEFE_1_TXTS_Msk); + } + + /* Ack the Tx Event FIFO position */ + CAN0_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); + + /* Tx Event FIFO Element read successfully, so return true */ + status = true; } return status; } @@ -460,6 +464,71 @@ void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) *rxErrorCount = (uint8_t)((CAN0_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); } +// ***************************************************************************** +/* Function: + bool CAN0_InterruptGet(CAN_INTERRUPT_MASK interruptMask) + + Summary: + Returns the Interrupt status. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + interruptMask - Interrupt source number + + Returns: + true - Requested interrupt is occurred. + false - Requested interrupt is not occurred. +*/ +bool CAN0_InterruptGet(CAN_INTERRUPT_MASK interruptMask) +{ + return ((CAN0_REGS->CAN_IR & (uint32_t)interruptMask) != 0x0U); +} + +// ***************************************************************************** +/* Function: + void CAN0_InterruptClear(CAN_INTERRUPT_MASK interruptMask) + + Summary: + Clears Interrupt status. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + interruptMask - Interrupt to be cleared + + Returns: + None +*/ +void CAN0_InterruptClear(CAN_INTERRUPT_MASK interruptMask) +{ + CAN0_REGS->CAN_IR = (uint32_t)interruptMask; +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxFIFOIsFull(void) + + Summary: + Returns true if Tx FIFO is full otherwise false. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None + + Returns: + true - Tx FIFO is full. + false - Tx FIFO is not full. +*/ +bool CAN0_TxFIFOIsFull(void) +{ + return ((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQF_Msk) == CAN_TXFQS_TFQF_Msk); +} + // ***************************************************************************** /* Function: void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) @@ -479,7 +548,6 @@ void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) Returns: None */ -/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) { uint32_t offset = 0U; @@ -500,25 +568,19 @@ void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) can0Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; offset = CAN0_RX_FIFO0_SIZE; /* Receive FIFO 0 Configuration Register */ - CAN0_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | + CAN0_REGS->CAN_RXF0C = CAN_RXF0C_F0S(8UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | CAN_RXF0C_F0SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO0Address); - can0Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN0_RX_FIFO1_SIZE; - /* Receive FIFO 1 Configuration Register */ - CAN0_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | - CAN_RXF1C_F1SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO1Address); - can0Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); offset += CAN0_TX_FIFO_BUFFER_SIZE; /* Transmit Buffer/FIFO Configuration Register */ - CAN0_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | + CAN0_REGS->CAN_TXBC = CAN_TXBC_TFQS(8UL) | CAN_TXBC_TBSA((uint32_t)can0Obj.msgRAMConfig.txBuffersAddress); can0Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); offset += CAN0_TX_EVENT_FIFO_SIZE; /* Transmit Event FIFO Configuration Register */ - CAN0_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | + CAN0_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(8UL) | CAN_TXEFC_EFSA((uint32_t)can0Obj.msgRAMConfig.txEventFIFOAddress); @@ -532,8 +594,6 @@ void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) /* Wait for configuration complete */ } } -/* MISRAC 2012 deviation block end for Rule 11.3*/ - @@ -560,135 +620,9 @@ void CAN0_SleepModeExit(void) } } -bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) -{ - bool status = false; - uint32_t numOfTimeQuanta; - uint8_t tseg1; - float temp1; - float temp2; - - if ((setup != NULL) && (bitTiming != NULL)) - { - if (setup->nominalBitTimingSet == true) - { - numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); - if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) - { - if (setup->nominalSamplePoint < 50.0f) - { - setup->nominalSamplePoint = 50.0f; - } - temp1 = (float)numOfTimeQuanta; - temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; - tseg1 = (uint8_t)temp2; - bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); - bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; - bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; - bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; - bitTiming->nominalBitTimingSet = true; - status = true; - } - else - { - bitTiming->nominalBitTimingSet = false; - } - } - if (setup->dataBitTimingSet == true) - { - numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->dataBitRate * ((uint32_t)setup->dataPrescaler + 1U)); - if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 49U)) - { - if (setup->dataSamplePoint < 50.0f) - { - setup->dataSamplePoint = 50.0f; - } - temp1 = (float)numOfTimeQuanta; - temp2 = (temp1 * setup->dataSamplePoint) / 100.0f; - tseg1 = (uint8_t)temp2; - bitTiming->dataBitTiming.dataTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); - bitTiming->dataBitTiming.dataTimeSegment1 = tseg1 - 2U; - bitTiming->dataBitTiming.dataSJW = bitTiming->dataBitTiming.dataTimeSegment2; - bitTiming->dataBitTiming.dataPrescaler = setup->dataPrescaler; - bitTiming->dataBitTimingSet = true; - status = true; - } - else - { - bitTiming->dataBitTimingSet = false; - status = false; - } - } - } - - return status; -} - -bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) -{ - bool status = false; - bool nominalBitTimingSet = false; - bool dataBitTimingSet = false; - - if ((bitTiming->nominalBitTimingSet == true) - && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) - && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) - && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) - && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) - { - nominalBitTimingSet = true; - } - - if ((bitTiming->dataBitTimingSet == true) - && ((bitTiming->dataBitTiming.dataTimeSegment1 >= 0x1U) && (bitTiming->dataBitTiming.dataTimeSegment1 <= 0x1FU)) - && (bitTiming->dataBitTiming.dataTimeSegment2 <= 0xFU) - && (bitTiming->dataBitTiming.dataPrescaler <= 0x1FU) - && (bitTiming->dataBitTiming.dataSJW <= 0xFU)) - { - dataBitTimingSet = true; - } - - if ((nominalBitTimingSet == true) || (dataBitTimingSet == true)) - { - /* Start CAN initialization */ - CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - if (dataBitTimingSet == true) - { - /* Set Data Bit Timing and Prescaler Register */ - CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(bitTiming->dataBitTiming.dataTimeSegment2) | CAN_DBTP_DTSEG1(bitTiming->dataBitTiming.dataTimeSegment1) | CAN_DBTP_DBRP(bitTiming->dataBitTiming.dataPrescaler) | CAN_DBTP_DSJW(bitTiming->dataBitTiming.dataSJW); - } - if (nominalBitTimingSet == true) - { - /* Set Nominal Bit timing and Prescaler Register */ - CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); - } - - /* Set the operation mode */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; - - - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - status = true; - } - return status; -} - - // ***************************************************************************** /* Function: - void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) + void CAN0_TxCallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) Summary: Sets the pointer to the function (and it's context) to be called when the @@ -699,7 +633,7 @@ bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) Parameters: callback - A pointer to a function with a calling signature defined - by the CAN_TX_FIFO_CALLBACK data type. + by the CAN_CALLBACK data type. contextHandle - A value (usually a pointer) passed (unused) into the function identified by the callback parameter. @@ -707,18 +641,18 @@ bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) Returns: None. */ -void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) +void CAN0_TxCallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) { if (callback != NULL) { - can0TxFifoCallbackObj.callback = callback; - can0TxFifoCallbackObj.context = contextHandle; + can0CallbackObj[CAN_CALLBACK_TX_INDEX].callback = callback; + can0CallbackObj[CAN_CALLBACK_TX_INDEX].context = contextHandle; } } // ***************************************************************************** /* Function: - void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) + void CAN0_RxCallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle, CAN_MSG_RX_ATTRIBUTE msgAttr) Summary: Sets the pointer to the function (and it's context) to be called when the @@ -729,84 +663,22 @@ void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contex Parameters: callback - A pointer to a function with a calling signature defined - by the CAN_TX_EVENT_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can0TxEventFifoCallbackObj.callback = callback; - can0TxEventFifoCallbackObj.context = contextHandle; - - } -} - - -// ***************************************************************************** -/* Function: - void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - rxFifoNum - Rx FIFO Number - - callback - A pointer to a function with a calling signature defined - by the CAN_RX_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can0RxFifoCallbackObj[rxFifoNum].callback = callback; - can0RxFifoCallbackObj[rxFifoNum].context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined by the CAN_CALLBACK data type. contextHandle - A value (usually a pointer) passed (unused) into the function identified by the callback parameter. + msgAttr - Message to be read from Rx FIFO0 or Rx FIFO1 or Rx Buffer + Returns: None. */ -void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) +void CAN0_RxCallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle, CAN_MSG_RX_ATTRIBUTE msgAttr) { if (callback != NULL) { - can0CallbackObj.callback = callback; - can0CallbackObj.context = contextHandle; + can0CallbackObj[msgAttr].callback = callback; + can0CallbackObj[msgAttr].context = contextHandle; } } @@ -837,47 +709,93 @@ void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) */ void __attribute__((used)) CAN0_InterruptHandler(void) { - uint8_t numberOfMessage = 0; - uint8_t numberOfTxEvent = 0; - + uint8_t length = 0U; + uint8_t rxgi = 0U; + uint8_t bufferIndex = 0U; + bool testCondition = false; + can_rxf0e_registers_t *rxf0eFifo = NULL; uint32_t ir = CAN0_REGS->CAN_IR; - /* Additional temporary variable used to prevent MISRA violations (Rule 13.x) */ - uintptr_t context; - - if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) + /* Check if error occurred */ + if ((ir & CAN_IR_BO_Msk) != 0U) { - CAN0_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); - if (can0CallbackObj.callback != NULL) - { - context = can0CallbackObj.context; - can0CallbackObj.callback(ir, context); - } + CAN0_REGS->CAN_IR = CAN_IR_BO_Msk; } /* New Message in Rx FIFO 0 */ if ((ir & CAN_IR_RF0N_Msk) != 0U) { CAN0_REGS->CAN_IR = CAN_IR_RF0N_Msk; + CAN0_REGS->CAN_IE &= (~CAN_IE_RF0NE_Msk); - numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); - - if (can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) + if ((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk) != 0U) { - context = can0RxFifoCallbackObj[CAN_RX_FIFO_0].context; - can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, context); + /* Read data from the Rx FIFO0 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + rxf0eFifo = (can_rxf0e_registers_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN0_RX_FIFO0_ELEMENT_SIZE)); + + /* Get received identifier */ + if ((rxf0eFifo->CAN_RXF0E_0 & CAN_RXF0E_0_XTD_Msk) != 0U) + { + *can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].rxId = rxf0eFifo->CAN_RXF0E_0 & CAN_RXF0E_0_ID_Msk; + } + else + { + *can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].rxId = (rxf0eFifo->CAN_RXF0E_0 >> 18U) & CAN_STD_ID_Msk; + } + + /* Check RTR and FDF bits for Remote/Data Frame */ + testCondition = ((rxf0eFifo->CAN_RXF0E_0 & CAN_RXF0E_0_RTR_Msk) != 0U); + testCondition = ((rxf0eFifo->CAN_RXF0E_1 & CAN_RXF0E_1_FDF_Msk) == 0U) && testCondition; + if (testCondition) + { + *can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].msgFrameAttr = CAN_MSG_RX_REMOTE_FRAME; + } + else + { + *can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].msgFrameAttr = CAN_MSG_RX_DATA_FRAME; + } + + /* Get received data length */ + length = CANDlcToLengthGet((uint8_t)((rxf0eFifo->CAN_RXF0E_1 & CAN_RXF0E_1_DLC_Msk) >> CAN_RXF0E_1_DLC_Pos)); + + /* Copy data to user buffer */ + (void) memcpy(can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].rxBuffer, (uint8_t *)&rxf0eFifo->CAN_RXF0E_DATA, length); + *can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].rxsize = length; + + /* Get timestamp from received message */ + if (can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].timestamp != NULL) + { + *can0RxMsg[CAN_MSG_ATTR_RX_FIFO0][rxgi].timestamp = (uint16_t)(rxf0eFifo->CAN_RXF0E_1 & CAN_RXF0E_1_RXTS_Msk); + } + + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); + + if (can0CallbackObj[CAN_MSG_ATTR_RX_FIFO0].callback != NULL) + { + can0CallbackObj[CAN_MSG_ATTR_RX_FIFO0].callback(can0CallbackObj[CAN_MSG_ATTR_RX_FIFO0].context); + } } } - /* New Message in Rx FIFO 1 */ - if ((ir & CAN_IR_RF1N_Msk) != 0U) - { - CAN0_REGS->CAN_IR = CAN_IR_RF1N_Msk; - numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); - - if (can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) + /* TX Completed */ + if ((ir & CAN_IR_TC_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_TC_Msk; + CAN0_REGS->CAN_IE &= (~CAN_IE_TCE_Msk); + for (bufferIndex = 0U; bufferIndex < (CAN0_TX_FIFO_BUFFER_SIZE/CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE); bufferIndex++) { - context = can0RxFifoCallbackObj[CAN_RX_FIFO_1].context; - can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, context); + uint32_t txbufferMask = (1UL << ((uint32_t)bufferIndex & 0x1FU)); + testCondition = ((CAN0_REGS->CAN_TXBTO & txbufferMask) != 0U); + testCondition = ((CAN0_REGS->CAN_TXBTIE & txbufferMask) != 0U) && testCondition; + if (testCondition) + { + CAN0_REGS->CAN_TXBTIE &= ~txbufferMask; + } + } + if (can0CallbackObj[CAN_CALLBACK_TX_INDEX].callback != NULL) + { + can0CallbackObj[CAN_CALLBACK_TX_INDEX].callback(can0CallbackObj[CAN_CALLBACK_TX_INDEX].context); } } @@ -885,27 +803,21 @@ void __attribute__((used)) CAN0_InterruptHandler(void) if ((ir & CAN_IR_TFE_Msk) != 0U) { CAN0_REGS->CAN_IR = CAN_IR_TFE_Msk; - if (can0TxFifoCallbackObj.callback != NULL) + uint8_t getIndex = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos); + uint8_t putIndex = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + uint8_t fifoIndex = getIndex; + while(true) { - context = can0TxFifoCallbackObj.context; - can0TxFifoCallbackObj.callback(context); - } - } - /* Tx Event FIFO new entry */ - if ((ir & CAN_IR_TEFN_Msk) != 0U) - { - CAN0_REGS->CAN_IR = CAN_IR_TEFN_Msk; - - numberOfTxEvent = (uint8_t)(CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); - - if (can0TxEventFifoCallbackObj.callback != NULL) - { - context = can0TxEventFifoCallbackObj.context; - can0TxEventFifoCallbackObj.callback(numberOfTxEvent, context); + if (fifoIndex >= putIndex) + { + break; + } + fifoIndex++; } } } + /******************************************************************************* End of File */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h index 63404486..67e61c1d 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can0.h @@ -21,7 +21,7 @@ *******************************************************************************/ //DOM-IGNORE-BEGIN /******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. * * Subject to your compliance with these terms, you may use Microchip software * and any derivatives exclusively with Microchip products. It is your @@ -73,43 +73,37 @@ // Section: Data Types // ***************************************************************************** // ***************************************************************************** -#define CAN0_CLOCK_FREQUENCY 48000000U - /* CAN0 Message RAM Configuration Size */ -#define CAN0_RX_FIFO0_ELEMENT_SIZE 16U -#define CAN0_RX_FIFO0_SIZE 16U -#define CAN0_RX_FIFO1_ELEMENT_SIZE 16U -#define CAN0_RX_FIFO1_SIZE 16U -#define CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE 16U -#define CAN0_TX_FIFO_BUFFER_SIZE 16U -#define CAN0_TX_EVENT_FIFO_SIZE 8U +#define CAN0_RX_FIFO0_ELEMENT_SIZE 72U +#define CAN0_RX_FIFO0_SIZE 576U +#define CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE 72U +#define CAN0_TX_FIFO_BUFFER_SIZE 576U +#define CAN0_TX_EVENT_FIFO_SIZE 64U /* CAN0_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver for allocating buffer from non-cached contiguous memory */ -#define CAN0_MESSAGE_RAM_CONFIG_SIZE 56U +#define CAN0_MESSAGE_RAM_CONFIG_SIZE 1216U // ***************************************************************************** // ***************************************************************************** // Section: Interface Routines // ***************************************************************************** // ***************************************************************************** -void CAN0_Initialize(void); -bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); -uint8_t CAN0_TxFifoFreeLevelGet(void); -bool CAN0_TxBufferIsBusy(uint8_t bufferNumber); -bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); -bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); +void CAN0_Initialize (void); +bool CAN0_MessageTransmit(uint32_t id, uint8_t length, uint8_t* data, CAN_MODE mode, CAN_MSG_TX_ATTRIBUTE msgAttr); +bool CAN0_MessageReceive(uint32_t *id, uint8_t *length, uint8_t *data, uint16_t *timestamp, + CAN_MSG_RX_ATTRIBUTE msgAttr, CAN_MSG_RX_FRAME_ATTRIBUTE *msgFrameAttr); +bool CAN0_TransmitEventFIFOElementGet(uint32_t *id, uint8_t *messageMarker, uint16_t *timestamp); CAN_ERROR CAN0_ErrorGet(void); void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); +bool CAN0_InterruptGet(CAN_INTERRUPT_MASK interruptMask); +void CAN0_InterruptClear(CAN_INTERRUPT_MASK interruptMask); +bool CAN0_TxFIFOIsFull(void); void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); void CAN0_SleepModeEnter(void); void CAN0_SleepModeExit(void); -bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); -bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming); -void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); +void CAN0_TxCallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); +void CAN0_RxCallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle, CAN_MSG_RX_ATTRIBUTE msgAttr); // DOM-IGNORE-BEGIN #ifdef __cplusplus // Provide C++ Compatibility } diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c deleted file mode 100644 index 3b043bb7..00000000 --- a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.c +++ /dev/null @@ -1,911 +0,0 @@ -/******************************************************************************* - Controller Area Network (CAN) Peripheral Library Source File - - Company: - Microchip Technology Inc. - - File Name: - plib_can1.c - - Summary: - CAN peripheral library interface. - - Description: - This file defines the interface to the CAN peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -//DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -//DOM-IGNORE-END -// ***************************************************************************** -// ***************************************************************************** -// Header Includes -// ***************************************************************************** -// ***************************************************************************** - -#include "device.h" -#include "interrupts.h" -#include "plib_can1.h" - -// ***************************************************************************** -// ***************************************************************************** -// Global Data -// ***************************************************************************** -// ***************************************************************************** -#define CAN_STD_ID_Msk 0x7FFU - -static volatile CAN_TX_FIFO_CALLBACK_OBJ can1TxFifoCallbackObj; -static volatile CAN_TX_EVENT_FIFO_CALLBACK_OBJ can1TxEventFifoCallbackObj; -static volatile CAN_RX_FIFO_CALLBACK_OBJ can1RxFifoCallbackObj[2]; -static volatile CAN_CALLBACK_OBJ can1CallbackObj; -static volatile CAN_OBJ can1Obj; - -static inline void CAN1_ZeroInitialize(volatile void* pData, size_t dataSize) -{ - volatile uint8_t* data = (volatile uint8_t*)pData; - for (uint32_t index = 0; index < dataSize; index++) - { - data[index] = 0U; - } -} - -// ***************************************************************************** -// ***************************************************************************** -// CAN1 PLib Interface Routines -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** -/* Function: - void CAN1_Initialize(void) - - Summary: - Initializes given instance of the CAN peripheral. - - Precondition: - None. - - Parameters: - None. - - Returns: - None -*/ -void CAN1_Initialize(void) -{ - /* Start CAN initialization */ - CAN1_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - /* Set Data Bit Timing and Prescaler Register */ - CAN1_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(0UL) | CAN_DBTP_DTSEG1(29UL) | CAN_DBTP_DBRP(2UL) | CAN_DBTP_DSJW(0UL); - - /* Set Nominal Bit timing and Prescaler Register */ - CAN1_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(23UL) | CAN_NBTP_NTSEG1(70UL) | CAN_NBTP_NBRP(0UL) | CAN_NBTP_NSJW(23UL); - - /* Receive Buffer / FIFO Element Size Configuration Register */ - CAN1_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(0UL) | CAN_RXESC_F1DS(0UL); - /* Transmit Buffer/FIFO Element Size Configuration Register */ - CAN1_REGS->CAN_TXESC = CAN_TXESC_TBDS(0UL); - - /* Global Filter Configuration Register */ - CAN1_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; - - /* Set the operation mode */ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; - - - CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Select interrupt line */ - CAN1_REGS->CAN_ILS = 0x0U; - - /* Enable interrupt line */ - CAN1_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; - - /* Enable CAN interrupts */ - CAN1_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk - | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk - | CAN_IE_TFEE_Msk - | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk - | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk - | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk - - | CAN_IE_MRAFE_Msk; - - CAN1_ZeroInitialize(&can1Obj.msgRAMConfig, sizeof(CAN_MSG_RAM_CONFIG)); -} - - -// ***************************************************************************** -/* Function: - bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) - - Summary: - Transmit multiple messages into CAN bus from Tx FIFO. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - numberOfMessage - Total number of message. - txBuffer - Pointer to Tx buffer - - Returns: - Request status. - true - Request was successful. - false - Request has failed. -*/ -bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) -{ - uint8_t *txFifo = NULL; - uint8_t *txBuf = (uint8_t *)txBuffer; - uint32_t bufferNumber = 0U; - uint8_t tfqpi = 0U; - uint8_t count = 0U; - bool transmitFifo_event = false; - - if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) - { - tfqpi = (uint8_t)((CAN1_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); - - for (count = 0U; count < numberOfMessage; count++) - { - txFifo = (uint8_t *)((uint8_t*)can1Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE)); - - (void) memcpy(txFifo, txBuf, CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE); - - txBuf += CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE; - bufferNumber |= (1UL << tfqpi); - tfqpi++; - if (tfqpi == 1U) - { - tfqpi = 0U; - } - } - - __DSB(); - - /* Set Transmission request */ - CAN1_REGS->CAN_TXBAR = bufferNumber; - - transmitFifo_event = true; - } - return transmitFifo_event; -} - -// ***************************************************************************** -/* Function: - uint8_t CAN1_TxFifoFreeLevelGet(void) - - Summary: - Returns Tx FIFO Free Level. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - None. - - Returns: - Tx FIFO Free Level. -*/ -uint8_t CAN1_TxFifoFreeLevelGet(void) -{ - return (uint8_t)(CAN1_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); -} - -// ***************************************************************************** -/* Function: - bool CAN1_TxBufferIsBusy(uint8_t bufferNumber) - - Summary: - Check if Transmission request is pending for the specific Tx buffer. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - None. - - Returns: - true - Transmission request is pending. - false - Transmission request is not pending. -*/ -bool CAN1_TxBufferIsBusy(uint8_t bufferNumber) -{ - return ((CAN1_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); -} - -// ***************************************************************************** -/* Function: - bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) - - Summary: - Read Tx Event FIFO for the transmitted messages. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - numberOfTxEvent - Total number of Tx Event - txEventFifo - Pointer to Tx Event FIFO - - Returns: - Request status. - true - Request was successful. - false - Request has failed. -*/ -bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) -{ - uint8_t txefgi = 0U; - uint8_t count = 0U; - uint8_t *txEvent = NULL; - uint8_t *txEvtFifo = (uint8_t *)txEventFifo; - bool txFifo_event = false; - - if (txEventFifo != NULL) - { - /* Read data from the Rx FIFO0 */ - txefgi = (uint8_t)((CAN1_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); - for (count = 0U; count < numberOfTxEvent; count++) - { - txEvent = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); - - (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); - - if ((count + 1U) == numberOfTxEvent) - { - break; - } - txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); - txefgi++; - if (txefgi == 1U) - { - txefgi = 0U; - } - } - - /* Ack the Tx Event FIFO position */ - CAN1_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); - - txFifo_event = true; - } - return txFifo_event; -} - - -// ***************************************************************************** -/* Function: - bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) - - Summary: - Read messages from Rx FIFO0/FIFO1. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - rxFifoNum - Rx FIFO number - numberOfMessage - Total number of message - rxBuffer - Pointer to Rx buffer - - Returns: - Request status. - true - Request was successful. - false - Request has failed. -*/ -bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) -{ - uint8_t rxgi = 0U; - uint8_t count = 0U; - uint8_t *rxFifo = NULL; - uint8_t *rxBuf = (uint8_t *)rxBuffer; - bool status = false; - - if (rxBuffer != NULL) - { - switch (rxFifoNum) - { - case CAN_RX_FIFO_0: - /* Read data from the Rx FIFO0 */ - rxgi = (uint8_t)((CAN1_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); - for (count = 0U; count < numberOfMessage; count++) - { - rxFifo = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN1_RX_FIFO0_ELEMENT_SIZE)); - - (void) memcpy(rxBuf, rxFifo, CAN1_RX_FIFO0_ELEMENT_SIZE); - - if ((count + 1U) == numberOfMessage) - { - break; - } - rxBuf += CAN1_RX_FIFO0_ELEMENT_SIZE; - rxgi++; - if (rxgi == 1U) - { - rxgi = 0U; - } - } - - /* Ack the fifo position */ - CAN1_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); - - status = true; - break; - case CAN_RX_FIFO_1: - /* Read data from the Rx FIFO1 */ - rxgi = (uint8_t)((CAN1_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); - for (count = 0U; count < numberOfMessage; count++) - { - rxFifo = (uint8_t *) ((uint8_t *)can1Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN1_RX_FIFO1_ELEMENT_SIZE)); - - (void) memcpy(rxBuf, rxFifo, CAN1_RX_FIFO1_ELEMENT_SIZE); - - if ((count + 1U) == numberOfMessage) - { - break; - } - rxBuf += CAN1_RX_FIFO1_ELEMENT_SIZE; - rxgi++; - if (rxgi == 1U) - { - rxgi = 0U; - } - } - /* Ack the fifo position */ - CAN1_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); - - status = true; - break; - default: - /* Do nothing */ - break; - } - } - return status; -} - -// ***************************************************************************** -/* Function: - CAN_ERROR CAN1_ErrorGet(void) - - Summary: - Returns the error during transfer. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - None. - - Returns: - Error during transfer. -*/ -CAN_ERROR CAN1_ErrorGet(void) -{ - CAN_ERROR error; - uint32_t errorStatus = CAN1_REGS->CAN_PSR; - - error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) - | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); - - if ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - } - - return error; -} - -// ***************************************************************************** -/* Function: - void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) - - Summary: - Returns the transmit and receive error count during transfer. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - txErrorCount - Transmit Error Count to be received - rxErrorCount - Receive Error Count to be received - - Returns: - None. -*/ -void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) -{ - *txErrorCount = (uint8_t)(CAN1_REGS->CAN_ECR & CAN_ECR_TEC_Msk); - *rxErrorCount = (uint8_t)((CAN1_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); -} - -// ***************************************************************************** -/* Function: - void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) - - Summary: - Set the Message RAM Configuration. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. - Application must allocate buffer from non-cached - contiguous memory and buffer size must be - CAN1_MESSAGE_RAM_CONFIG_SIZE - - Returns: - None -*/ -/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ -void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) -{ - uint32_t offset = 0U; - uint32_t msgRAMConfigBaseAddr = (uint32_t)msgRAMConfigBaseAddress; - - (void) memset(msgRAMConfigBaseAddress, 0x00, CAN1_MESSAGE_RAM_CONFIG_SIZE); - - /* Set CAN CCCR Init for Message RAM Configuration */ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - can1Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; - offset = CAN1_RX_FIFO0_SIZE; - /* Receive FIFO 0 Configuration Register */ - CAN1_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | - CAN_RXF0C_F0SA((uint32_t)can1Obj.msgRAMConfig.rxFIFO0Address); - - can1Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN1_RX_FIFO1_SIZE; - /* Receive FIFO 1 Configuration Register */ - CAN1_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | - CAN_RXF1C_F1SA((uint32_t)can1Obj.msgRAMConfig.rxFIFO1Address); - - can1Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN1_TX_FIFO_BUFFER_SIZE; - /* Transmit Buffer/FIFO Configuration Register */ - CAN1_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | - CAN_TXBC_TBSA((uint32_t)can1Obj.msgRAMConfig.txBuffersAddress); - - can1Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN1_TX_EVENT_FIFO_SIZE; - /* Transmit Event FIFO Configuration Register */ - CAN1_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | - CAN_TXEFC_EFSA((uint32_t)can1Obj.msgRAMConfig.txEventFIFOAddress); - - - /* Reference offset variable once to remove warning about the variable not being used after increment */ - (void)offset; - - /* Complete Message RAM Configuration by clearing CAN CCCR Init */ - CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for configuration complete */ - } -} -/* MISRAC 2012 deviation block end for Rule 11.3*/ - - - - -void CAN1_SleepModeEnter(void) -{ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) - { - /* Wait for clock stop request to complete */ - } -} - -void CAN1_SleepModeExit(void) -{ - CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) - { - /* Wait for no clock stop */ - } - CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } -} - -bool CAN1_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) -{ - bool status = false; - uint32_t numOfTimeQuanta; - uint8_t tseg1; - float temp1; - float temp2; - - if ((setup != NULL) && (bitTiming != NULL)) - { - if (setup->nominalBitTimingSet == true) - { - numOfTimeQuanta = CAN1_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); - if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) - { - if (setup->nominalSamplePoint < 50.0f) - { - setup->nominalSamplePoint = 50.0f; - } - temp1 = (float)numOfTimeQuanta; - temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; - tseg1 = (uint8_t)temp2; - bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); - bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; - bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; - bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; - bitTiming->nominalBitTimingSet = true; - status = true; - } - else - { - bitTiming->nominalBitTimingSet = false; - } - } - if (setup->dataBitTimingSet == true) - { - numOfTimeQuanta = CAN1_CLOCK_FREQUENCY / (setup->dataBitRate * ((uint32_t)setup->dataPrescaler + 1U)); - if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 49U)) - { - if (setup->dataSamplePoint < 50.0f) - { - setup->dataSamplePoint = 50.0f; - } - temp1 = (float)numOfTimeQuanta; - temp2 = (temp1 * setup->dataSamplePoint) / 100.0f; - tseg1 = (uint8_t)temp2; - bitTiming->dataBitTiming.dataTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); - bitTiming->dataBitTiming.dataTimeSegment1 = tseg1 - 2U; - bitTiming->dataBitTiming.dataSJW = bitTiming->dataBitTiming.dataTimeSegment2; - bitTiming->dataBitTiming.dataPrescaler = setup->dataPrescaler; - bitTiming->dataBitTimingSet = true; - status = true; - } - else - { - bitTiming->dataBitTimingSet = false; - status = false; - } - } - } - - return status; -} - -bool CAN1_BitTimingSet(CAN_BIT_TIMING *bitTiming) -{ - bool status = false; - bool nominalBitTimingSet = false; - bool dataBitTimingSet = false; - - if ((bitTiming->nominalBitTimingSet == true) - && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) - && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) - && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) - && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) - { - nominalBitTimingSet = true; - } - - if ((bitTiming->dataBitTimingSet == true) - && ((bitTiming->dataBitTiming.dataTimeSegment1 >= 0x1U) && (bitTiming->dataBitTiming.dataTimeSegment1 <= 0x1FU)) - && (bitTiming->dataBitTiming.dataTimeSegment2 <= 0xFU) - && (bitTiming->dataBitTiming.dataPrescaler <= 0x1FU) - && (bitTiming->dataBitTiming.dataSJW <= 0xFU)) - { - dataBitTimingSet = true; - } - - if ((nominalBitTimingSet == true) || (dataBitTimingSet == true)) - { - /* Start CAN initialization */ - CAN1_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - if (dataBitTimingSet == true) - { - /* Set Data Bit Timing and Prescaler Register */ - CAN1_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(bitTiming->dataBitTiming.dataTimeSegment2) | CAN_DBTP_DTSEG1(bitTiming->dataBitTiming.dataTimeSegment1) | CAN_DBTP_DBRP(bitTiming->dataBitTiming.dataPrescaler) | CAN_DBTP_DSJW(bitTiming->dataBitTiming.dataSJW); - } - if (nominalBitTimingSet == true) - { - /* Set Nominal Bit timing and Prescaler Register */ - CAN1_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); - } - - /* Set the operation mode */ - CAN1_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; - - - CAN1_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN1_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - status = true; - } - return status; -} - - -// ***************************************************************************** -/* Function: - void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined - by the CAN_TX_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can1TxFifoCallbackObj.callback = callback; - can1TxFifoCallbackObj.context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined - by the CAN_TX_EVENT_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can1TxEventFifoCallbackObj.callback = callback; - can1TxEventFifoCallbackObj.context = contextHandle; - - } -} - - -// ***************************************************************************** -/* Function: - void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - rxFifoNum - Rx FIFO Number - - callback - A pointer to a function with a calling signature defined - by the CAN_RX_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can1RxFifoCallbackObj[rxFifoNum].callback = callback; - can1RxFifoCallbackObj[rxFifoNum].context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN1_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined - by the CAN_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can1CallbackObj.callback = callback; - can1CallbackObj.context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN1_InterruptHandler(void) - - Summary: - CAN1 Peripheral Interrupt Handler. - - Description: - This function is CAN1 Peripheral Interrupt Handler and will - called on every CAN1 interrupt. - - Precondition: - None. - - Parameters: - None. - - Returns: - None. - - Remarks: - The function is called as peripheral instance's interrupt handler if the - instance interrupt is enabled. If peripheral instance's interrupt is not - enabled user need to call it from the main while loop of the application. -*/ -void __attribute__((used)) CAN1_InterruptHandler(void) -{ - uint8_t numberOfMessage = 0; - uint8_t numberOfTxEvent = 0; - - uint32_t ir = CAN1_REGS->CAN_IR; - - /* Additional temporary variable used to prevent MISRA violations (Rule 13.x) */ - uintptr_t context; - - if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) - { - CAN1_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); - if (can1CallbackObj.callback != NULL) - { - context = can1CallbackObj.context; - can1CallbackObj.callback(ir, context); - } - } - /* New Message in Rx FIFO 0 */ - if ((ir & CAN_IR_RF0N_Msk) != 0U) - { - CAN1_REGS->CAN_IR = CAN_IR_RF0N_Msk; - - numberOfMessage = (uint8_t)(CAN1_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); - - if (can1RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) - { - context = can1RxFifoCallbackObj[CAN_RX_FIFO_0].context; - can1RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, context); - } - } - /* New Message in Rx FIFO 1 */ - if ((ir & CAN_IR_RF1N_Msk) != 0U) - { - CAN1_REGS->CAN_IR = CAN_IR_RF1N_Msk; - - numberOfMessage = (uint8_t)(CAN1_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); - - if (can1RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) - { - context = can1RxFifoCallbackObj[CAN_RX_FIFO_1].context; - can1RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, context); - } - } - - /* TX FIFO is empty */ - if ((ir & CAN_IR_TFE_Msk) != 0U) - { - CAN1_REGS->CAN_IR = CAN_IR_TFE_Msk; - if (can1TxFifoCallbackObj.callback != NULL) - { - context = can1TxFifoCallbackObj.context; - can1TxFifoCallbackObj.callback(context); - } - } - /* Tx Event FIFO new entry */ - if ((ir & CAN_IR_TEFN_Msk) != 0U) - { - CAN1_REGS->CAN_IR = CAN_IR_TEFN_Msk; - - numberOfTxEvent = (uint8_t)(CAN1_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); - - if (can1TxEventFifoCallbackObj.callback != NULL) - { - context = can1TxEventFifoCallbackObj.context; - can1TxEventFifoCallbackObj.callback(numberOfTxEvent, context); - } - } -} - -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h deleted file mode 100644 index 144bacf5..00000000 --- a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can1.h +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* - CAN Peripheral Library Interface Header File - - Company: - Microchip Technology Inc. - - File Name: - plib_can1.h - - Summary: - CAN PLIB interface declarations. - - Description: - The CAN plib provides a simple interface to manage the CAN modules on - Microchip microcontrollers. This file defines the interface declarations - for the CAN plib. - - Remarks: - None. - -*******************************************************************************/ -//DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -//DOM-IGNORE-END - -#ifndef PLIB_CAN1_H -#define PLIB_CAN1_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -/* - * This section lists the other files that are included in this file. - */ -#include -#include - -#include "device.h" -#include "plib_can_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - extern "C" { -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -#define CAN1_CLOCK_FREQUENCY 48000000U - -/* CAN1 Message RAM Configuration Size */ -#define CAN1_RX_FIFO0_ELEMENT_SIZE 16U -#define CAN1_RX_FIFO0_SIZE 16U -#define CAN1_RX_FIFO1_ELEMENT_SIZE 16U -#define CAN1_RX_FIFO1_SIZE 16U -#define CAN1_TX_FIFO_BUFFER_ELEMENT_SIZE 16U -#define CAN1_TX_FIFO_BUFFER_SIZE 16U -#define CAN1_TX_EVENT_FIFO_SIZE 8U - -/* CAN1_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver - for allocating buffer from non-cached contiguous memory */ -#define CAN1_MESSAGE_RAM_CONFIG_SIZE 56U - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** -void CAN1_Initialize(void); -bool CAN1_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); -uint8_t CAN1_TxFifoFreeLevelGet(void); -bool CAN1_TxBufferIsBusy(uint8_t bufferNumber); -bool CAN1_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); -bool CAN1_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); -CAN_ERROR CAN1_ErrorGet(void); -void CAN1_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); -void CAN1_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); -void CAN1_SleepModeEnter(void); -void CAN1_SleepModeExit(void); -bool CAN1_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); -bool CAN1_BitTimingSet(CAN_BIT_TIMING *bitTiming); -void CAN1_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN1_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN1_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN1_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - } -#endif -// DOM-IGNORE-END - -#endif // PLIB_CAN1_H - -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h index b5f9f963..34ae0a17 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h +++ b/bms/bms/bms_config/src/config/default/peripheral/can/plib_can_common.h @@ -21,7 +21,7 @@ // DOM-IGNORE-BEGIN /******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. * * Subject to your compliance with these terms, you may use Microchip software * and any derivatives exclusively with Microchip products. It is your @@ -60,7 +60,7 @@ // Section: Preprocessor macros // ***************************************************************************** // ***************************************************************************** - + // ***************************************************************************** /* CAN Transfer Errors @@ -73,27 +73,27 @@ Remarks: None. */ - -#define CAN_ERROR_NONE 0x0U -#define CAN_ERROR_LEC_STUFF 0x1U -#define CAN_ERROR_LEC_FORM 0x2U -#define CAN_ERROR_LEC_ACK 0x3U -#define CAN_ERROR_LEC_BIT1 0x4U -#define CAN_ERROR_LEC_BIT0 0x5U -#define CAN_ERROR_LEC_CRC 0x6U -#define CAN_ERROR_LEC_NC 0x7U -#define CAN_ERROR_PASSIVE 0x20U -#define CAN_ERROR_WARNING_STATUS 0x40U -#define CAN_ERROR_BUS_OFF 0x80U -#define CAN_ERROR_DLEC_STUFF 0x100U -#define CAN_ERROR_DLEC_FORM 0x200U -#define CAN_ERROR_DLEC_ACK 0x300U -#define CAN_ERROR_DLEC_BIT1 0x400U -#define CAN_ERROR_DLEC_BIT0 0x500U -#define CAN_ERROR_DLEC_CRC 0x600U -#define CAN_ERROR_DLEC_NC 0x700U -#define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U -#define CAN_ERROR_INVALID 0xFFFFFFFFU + + #define CAN_ERROR_NONE 0x0U + #define CAN_ERROR_LEC_STUFF 0x1U + #define CAN_ERROR_LEC_FORM 0x2U + #define CAN_ERROR_LEC_ACK 0x3U + #define CAN_ERROR_LEC_BIT1 0x4U + #define CAN_ERROR_LEC_BIT0 0x5U + #define CAN_ERROR_LEC_CRC 0x6U + #define CAN_ERROR_LEC_NC 0x7U + #define CAN_ERROR_PASSIVE 0x20U + #define CAN_ERROR_WARNING_STATUS 0x40U + #define CAN_ERROR_BUS_OFF 0x80U + #define CAN_ERROR_DLEC_STUFF 0x100U + #define CAN_ERROR_DLEC_FORM 0x200U + #define CAN_ERROR_DLEC_ACK 0x300U + #define CAN_ERROR_DLEC_BIT1 0x400U + #define CAN_ERROR_DLEC_BIT0 0x500U + #define CAN_ERROR_DLEC_CRC 0x600U + #define CAN_ERROR_DLEC_NC 0x700U + #define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U + #define CAN_ERROR_INVALID 0xFFFFFFFFU // ***************************************************************************** // ***************************************************************************** @@ -102,22 +102,84 @@ // ***************************************************************************** // ***************************************************************************** -/* CAN Rx FIFO Number +/* CAN Mode + + Summary: + CAN Mode for Classic CAN and CAN FD. + + Description: + This data type defines CAN mode Classic CAN, CAN FD without BRS(Bit rate switching) + and CAN FD with BRS. + + Remarks: + None. +*/ +typedef enum +{ + CAN_MODE_NORMAL = 0U, + CAN_MODE_FD_WITHOUT_BRS, + CAN_MODE_FD_WITH_BRS +} CAN_MODE; + +// ***************************************************************************** +/* CAN Tx Message Attribute + + Summary: + CAN Tx Message Attribute for Tx Buffer/FIFO. + + Description: + This data type defines CAN Tx Message Attribute. Only One attribute + need to be passed as parameter value while invoking message transmit function. + + Remarks: + None. +*/ +typedef enum +{ + CAN_MSG_ATTR_TX_FIFO_DATA_FRAME = 0U, + CAN_MSG_ATTR_TX_FIFO_RTR_FRAME, + CAN_MSG_ATTR_TX_BUFFER_DATA_FRAME, + CAN_MSG_ATTR_TX_BUFFER_RTR_FRAME +} CAN_MSG_TX_ATTRIBUTE; + +// ***************************************************************************** +/* CAN Rx Message Attribute + + Summary: + CAN Rx Message Attribute for Rx Buffer/FIFO0/FIFO1. + + Description: + This data type defines CAN Rx Message Attribute. Only One attribute + need to be passed as parameter value while invoking message receive function. + + Remarks: + None. +*/ +typedef enum +{ + CAN_MSG_ATTR_RX_FIFO0 = 0U, + CAN_MSG_ATTR_RX_FIFO1, + CAN_MSG_ATTR_RX_BUFFER +} CAN_MSG_RX_ATTRIBUTE; + +// ***************************************************************************** +/* CAN Message Object Type RX Frame Attribute Summary: - CAN Rx FIFO Number. + CAN Message RX Frame Attribute for Data Frame and Remote Frame. Description: - This data type defines CAN Rx FIFO number for Rx FIFO0 and FIFO1. + This data type defines CAN Message RX Frame Attribute for Data Frame and Remote Frame. Remarks: None. */ typedef enum { - CAN_RX_FIFO_0 = 0U, - CAN_RX_FIFO_1 -} CAN_RX_FIFO_NUM; + CAN_MSG_RX_DATA_FRAME = 0U, + CAN_MSG_RX_REMOTE_FRAME +} CAN_MSG_RX_FRAME_ATTRIBUTE; + // ***************************************************************************** /* CAN Interrupt Mask @@ -177,62 +239,6 @@ typedef enum */ typedef uint32_t CAN_ERROR; -// ***************************************************************************** -/* CAN Tx FIFO Callback - - Summary: - CAN Callback Function Pointer for Tx FIFO. - - Description: - This data type defines the CAN Callback Function Pointer for Tx FIFO. - - Remarks: - None. -*/ -typedef void (*CAN_TX_FIFO_CALLBACK) (uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN TX/RX Buffers Callback - - Summary: - CAN Callback Function Pointer for TX/RX Buffers. - - Description: - This data type defines the CAN Callback Function Pointer for TX/RX Buffers. - - Remarks: - None. -*/ -typedef void (*CAN_TXRX_BUFFERS_CALLBACK) (uint8_t bufferNumber, uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN Tx Event FIFO Callback - - Summary: - CAN Callback Function Pointer for Tx Event FIFO. - - Description: - This data type defines the CAN Callback Function Pointer for Tx Event FIFO. - - Remarks: - None. -*/ -typedef void (*CAN_TX_EVENT_FIFO_CALLBACK) (uint8_t numberOfTxEvent, uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN Rx FIFO0/FIFO1 Callback - - Summary: - CAN Callback Function Pointer for Rx FIFO0/FIFO1. - - Description: - This data type defines the CAN Callback Function Pointer for Rx FIFO0/FIFO1. - - Remarks: - None. -*/ -typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t contextHandle); - // ***************************************************************************** /* CAN Callback @@ -245,7 +251,7 @@ typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t context Remarks: None. */ -typedef void (*CAN_CALLBACK) (uint32_t interruptStatus, uintptr_t contextHandle); +typedef void (*CAN_CALLBACK) (uintptr_t contextHandle); // ***************************************************************************** /* CAN Message RAM Configuration @@ -286,320 +292,36 @@ typedef struct } CAN_MSG_RAM_CONFIG; // ***************************************************************************** -/* CAN Rx Buffer and FIFO Element - - Summary: - CAN Rx Buffer and FIFO Element Structure. - - Description: - This data structure defines CAN Rx Buffer and FIFO Element. - - Remarks: - None. -*/ -typedef struct -{ - /* Identifier */ - unsigned int id:29; - /* Remote Transmission Request */ - unsigned int rtr:1; - /* Extended Identifier */ - unsigned int xtd:1; - /* Error State Indicator */ - unsigned int esi:1; - - /* Rx Timestamp */ - unsigned int rxts:16; - /* Data Length Code */ - unsigned int dlc:4; - /* Bit Rate Switching */ - unsigned int brs:1; - /* FD Format */ - unsigned int fdf:1; - /* Reserved */ - unsigned int :2; - /* Filter Index */ - unsigned int fidx:7; - /* Accepted Non-matching Frame */ - unsigned int anmf:1; - - /* Data field */ - uint8_t data[8]; - -} CAN_RX_BUFFER; - -// ***************************************************************************** -/* CAN Tx Buffer Element - - Summary: - CAN Tx Buffer Element Structure. - - Description: - This data structure defines CAN Tx Buffer Element. - - Remarks: - None. -*/ -typedef struct -{ - /* Identifier */ - unsigned int id:29; - /* Remote Transmission Request */ - unsigned int rtr:1; - /* Extended Identifier */ - unsigned int xtd:1; - /* Error State Indicator */ - unsigned int esi:1; - - /* Reserved */ - unsigned int :16; - /* Data Length Code */ - unsigned int dlc:4; - /* Bit Rate Switching */ - unsigned int brs:1; - /* FD Format */ - unsigned int fdf:1; - /* Reserved */ - unsigned int :1; - /* Event FIFO Control */ - unsigned int efc:1; - /* Message Marker */ - unsigned int mm:8; - - /* Data field */ - uint8_t data[8]; - -} CAN_TX_BUFFER; - -// ***************************************************************************** -/* CAN Tx Event FIFO Element - - Summary: - CAN Tx Event FIFO Element Structure. - - Description: - This data structure defines CAN Tx Event FIFO Element. - - Remarks: - None. -*/ -typedef struct -{ - /* Identifier */ - unsigned int id:29; - /* Remote Transmission Request */ - unsigned int rtr:1; - /* Extended Identifier */ - unsigned int xtd:1; - /* Error State Indicator */ - unsigned int esi:1; - - /* Tx Timestamp */ - unsigned int txts:16; - /* Data Length Code */ - unsigned int dlc:4; - /* Bit Rate Switch */ - unsigned int brs:1; - /* FD Format */ - unsigned int fdf:1; - /* Event Type */ - unsigned int et:2; - /* Message Marker */ - unsigned int mm:8; - -} CAN_TX_EVENT_FIFO; - -// ***************************************************************************** -/* CAN Nominal Bit Timing Parameters - - Summary: - CAN Nominal Bit Timing Parameter structure. - - Description: - This data structure defines Nominal Bit Timing Parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Nominal Time segment after sample point */ - uint8_t nominalTimeSegment2; - - /* Nominal Time segment before sample point */ - uint8_t nominalTimeSegment1; - - /* Nominal Baud Rate Prescaler */ - uint16_t nominalPrescaler; - - /* Nominal Syncronization Jump Width */ - uint8_t nominalSJW; - -} CAN_NOMINAL_BIT_TIMING; - -// ***************************************************************************** -/* CAN Data Bit Timing Parameters - - Summary: - CAN Data Bit Timing Parameter structure. - - Description: - This data structure defines Data Bit Timing Parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Data Time segment after sample point */ - uint8_t dataTimeSegment2; - - /* Data Time segment before sample point */ - uint8_t dataTimeSegment1; - - /* Data Baud Rate Prescaler */ - uint8_t dataPrescaler; - - /* Data Syncronization Jump Width */ - uint8_t dataSJW; - -} CAN_DATA_BIT_TIMING; - -// ***************************************************************************** -/* CAN Bit Timing Parameters - - Summary: - CAN Bit Timing Parameter structure. - - Description: - This data structure defines Bit Timing Parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Nominal bit timing set flag */ - bool nominalBitTimingSet; - - /* Nominal bit timing parameters */ - CAN_NOMINAL_BIT_TIMING nominalBitTiming; - - /* Data bit timing set flag */ - bool dataBitTimingSet; - - /* Data bit timing parameters */ - CAN_DATA_BIT_TIMING dataBitTiming; -} CAN_BIT_TIMING; - -// ***************************************************************************** -/* CAN Bit Timing Setup - - Summary: - CAN Bit Timing Setup structure. - - Description: - This data structure defines Bit Timing Setup parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Nominal bit timing set flag */ - bool nominalBitTimingSet; - - /* Nominal bit rate */ - uint32_t nominalBitRate; - - /* Nominal Sample Point */ - float nominalSamplePoint; - - /* Nominal Baud Rate Prescaler */ - uint16_t nominalPrescaler; - - /* Data bit timing set flag */ - bool dataBitTimingSet; - - /* Data bit rate */ - uint32_t dataBitRate; - - /* Data Sample Point */ - float dataSamplePoint; - - /* Data Baud Rate Prescaler */ - uint8_t dataPrescaler; - -} CAN_BIT_TIMING_SETUP; - -// ***************************************************************************** -/* CAN Tx FIFO Callback Object - - Summary: - CAN transfer event callback structure for Tx FIFO. - - Description: - This data structure stores transfer event callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* Transfer Event Callback */ - CAN_TX_FIFO_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_TX_FIFO_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Tx/Rx Buffers Callback Object - - Summary: - CAN transfer event callback structure for Tx/Rx Buffers. - - Description: - This data structure stores transfer event callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* Transfer Event Callback */ - CAN_TXRX_BUFFERS_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_TXRX_BUFFERS_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Tx Event FIFO Callback Object +/* CAN RX Message Summary: - CAN transfer event callback structure for Tx Event FIFO. + CAN RX Message Buffer structure. Description: - This data structure stores transfer event callback and it's context. + This data structure stores RX Message. Remarks: None. */ typedef struct { - /* Transfer Event Callback */ - CAN_TX_EVENT_FIFO_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_TX_EVENT_FIFO_CALLBACK_OBJ; + /* Rx Message ID */ + uint32_t *rxId; + /* Rx Message buffer */ + uint8_t *rxBuffer; + /* Rx Message size */ + uint8_t *rxsize; + /* Rx Message timestamp */ + uint16_t *timestamp; + /* Rx Message frame attribute */ + CAN_MSG_RX_FRAME_ATTRIBUTE *msgFrameAttr; +} CAN_RX_MSG; // ***************************************************************************** -/* CAN Rx FIFO0/FIFO1 Callback Object +/* CAN Callback Object Summary: - CAN transfer event callback structure for Rx FIFO0/FIFO1. + CAN transfer event callback structure. Description: This data structure stores transfer event callback and it's context. @@ -610,30 +332,9 @@ typedef struct typedef struct { /* Transfer Event Callback */ - CAN_RX_FIFO_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_RX_FIFO_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Callback Object - - Summary: - CAN interrupt status callback structure. - - Description: - This data structure stores interrupt status callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* CAN Interrupt Status Callback */ CAN_CALLBACK callback; - /* CAN Interrupt Status Callback Context */ + /* Transfer Event Callback Context */ uintptr_t context; } CAN_CALLBACK_OBJ; @@ -651,6 +352,12 @@ typedef struct */ typedef struct { + /* Tx Buffer Index */ + uint32_t txBufferIndex; + /* Rx Buffer Index */ + uint32_t rxBufferIndex1; + uint32_t rxBufferIndex2; + /* Message RAM Configuration */ CAN_MSG_RAM_CONFIG msgRAMConfig; diff --git a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c index d5277453..629f309b 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c +++ b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c @@ -126,13 +126,6 @@ void CLOCK_Initialize (void) { /* Wait for synchronization */ } - /* Selection of the Generator and write Lock for CAN1 */ - GCLK_REGS->GCLK_PCHCTRL[27] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; - - while ((GCLK_REGS->GCLK_PCHCTRL[27] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) - { - /* Wait for synchronization */ - } /* Selection of the Generator and write Lock for ADC0 */ GCLK_REGS->GCLK_PCHCTRL[33] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; @@ -148,7 +141,7 @@ void CLOCK_Initialize (void) /* Wait for synchronization */ } /* Configure the AHB Bridge Clocks */ - MCLK_REGS->MCLK_AHBMASK = 0x1fffU; + MCLK_REGS->MCLK_AHBMASK = 0x1dffU; diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c index c6c35377..bc6956e9 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c +++ b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c @@ -63,8 +63,6 @@ void NVIC_Initialize( void ) NVIC_EnableIRQ(SERCOM1_IRQn); NVIC_SetPriority(CAN0_IRQn, 3); NVIC_EnableIRQ(CAN0_IRQn); - NVIC_SetPriority(CAN1_IRQn, 3); - NVIC_EnableIRQ(CAN1_IRQn); diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c index c1901a25..66ffa845 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c @@ -71,26 +71,33 @@ void PORT_Initialize(void) { /************************** GROUP 0 Initialization *************************/ - PORT_REGS->GROUP[0].PORT_DIR = 0x80U; + PORT_REGS->GROUP[0].PORT_DIR = 0x100c8080U; PORT_REGS->GROUP[0].PORT_OUT = 0x80U; PORT_REGS->GROUP[0].PORT_PINCFG[7] = 0x0U; PORT_REGS->GROUP[0].PORT_PINCFG[8] = 0x1U; PORT_REGS->GROUP[0].PORT_PINCFG[9] = 0x1U; PORT_REGS->GROUP[0].PORT_PINCFG[11] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[14] = 0x2U; + PORT_REGS->GROUP[0].PORT_PINCFG[15] = 0x0U; + PORT_REGS->GROUP[0].PORT_PINCFG[18] = 0x0U; + PORT_REGS->GROUP[0].PORT_PINCFG[19] = 0x0U; + PORT_REGS->GROUP[0].PORT_PINCFG[24] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[25] = 0x1U; + PORT_REGS->GROUP[0].PORT_PINCFG[28] = 0x0U; PORT_REGS->GROUP[0].PORT_PMUX[3] = 0x0U; - PORT_REGS->GROUP[0].PORT_PMUX[4] = 0x22U; - PORT_REGS->GROUP[0].PORT_PMUX[5] = 0x20U; - - /************************** GROUP 1 Initialization *************************/ - PORT_REGS->GROUP[1].PORT_PINCFG[10] = 0x1U; - PORT_REGS->GROUP[1].PORT_PINCFG[11] = 0x1U; - - PORT_REGS->GROUP[1].PORT_PMUX[5] = 0x33U; - - - -} + PORT_REGS->GROUP[0].PORT_PMUX[4] = 0x22U; + PORT_REGS->GROUP[0].PORT_PMUX[5] = 0x20U; + PORT_REGS->GROUP[0].PORT_PMUX[7] = 0x0U; + PORT_REGS->GROUP[0].PORT_PMUX[9] = 0x0U; + PORT_REGS->GROUP[0].PORT_PMUX[12] = 0x66U; + PORT_REGS->GROUP[0].PORT_PMUX[14] = 0x0U; + + /************************** GROUP 1 Initialization *************************/ + + + +} // ***************************************************************************** /* Function: uint32_t PORT_GroupRead(PORT_GROUP group) @@ -344,4 +351,4 @@ void PORT_PinGPIOConfig(PORT_PIN pin) /* Disable peripheral control of the pin */ ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); -} +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h index 701b240a..6bd561d7 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h @@ -74,6 +74,51 @@ #define GPIO_PA07_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 7U)) & 0x01U) #define GPIO_PA07_PIN PORT_PIN_PA07 +/*** Macros for CAN_RX_WAKEUP pin ***/ +#define CAN_RX_WAKEUP_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 14U)) +#define CAN_RX_WAKEUP_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 14U)) +#define CAN_RX_WAKEUP_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 14U)) +#define CAN_RX_WAKEUP_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 14U)) +#define CAN_RX_WAKEUP_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 14U)) +#define CAN_RX_WAKEUP_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 14U)) & 0x01U) +#define CAN_RX_WAKEUP_PIN PORT_PIN_PA14 + +/*** Macros for STB pin ***/ +#define STB_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 15U)) +#define STB_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 15U)) +#define STB_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 15U)) +#define STB_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 15U)) +#define STB_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 15U)) +#define STB_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 15U)) & 0x01U) +#define STB_PIN PORT_PIN_PA15 + +/*** Macros for LED_R pin ***/ +#define LED_R_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 18U)) +#define LED_R_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 18U)) +#define LED_R_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 18U)) +#define LED_R_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 18U)) +#define LED_R_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 18U)) +#define LED_R_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 18U)) & 0x01U) +#define LED_R_PIN PORT_PIN_PA18 + +/*** Macros for LED_Y pin ***/ +#define LED_Y_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 19U)) +#define LED_Y_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 19U)) +#define LED_Y_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 19U)) +#define LED_Y_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 19U)) +#define LED_Y_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 19U)) +#define LED_Y_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 19U)) & 0x01U) +#define LED_Y_PIN PORT_PIN_PA19 + +/*** Macros for LED_G pin ***/ +#define LED_G_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 28U)) +#define LED_G_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 28U)) +#define LED_G_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 28U)) +#define LED_G_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 28U)) +#define LED_G_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 28U)) +#define LED_G_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 28U)) & 0x01U) +#define LED_G_PIN PORT_PIN_PA28 + // ***************************************************************************** /* PORT Group diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 3f62c5b8..da6204d1 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -438,3 +438,10 @@ void bothoff_high(void) { PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; } + +void can_wakeup_pin(void){ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRCLR = (1u << 16U); // Set as input + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] |= PORT_PINCFG_INEN_Msk; // Enable INPUT +} + diff --git a/bms/bms/bms_config/src/ic_bms/spi_test.c b/bms/bms/bms_config/src/ic_bms/spi_test.c index 6ef98c1f..8056caac 100644 --- a/bms/bms/bms_config/src/ic_bms/spi_test.c +++ b/bms/bms/bms_config/src/ic_bms/spi_test.c @@ -75,7 +75,7 @@ static bool spi_test_write_reg_exact(uint8_t reg_addr, const uint8_t *data, uint for (uint8_t i = 0U; i < length; i++) { - uint8_t cmd = (uint8_t)(0x80U | ((reg_addr + i) & 0x7FU)); + uint8_t cmd = (uint8_t)(0x80U | (uint8_t)((reg_addr + i) & 0x7FU)); uint8_t pair[2] = {cmd, data[i]}; tx_bytes[3U * i + 0U] = cmd; tx_bytes[3U * i + 1U] = data[i]; @@ -118,7 +118,7 @@ static bool spi_test_read_reg_exact(uint8_t reg_addr, uint8_t *data, uint8_t len for (uint8_t i = 1U; i < frames; i++) { - uint8_t cmd = (i < (uint8_t)(frames - 1U)) ? (uint8_t)((reg_addr + i) & 0x7FU) : 0x00U; + uint8_t cmd = (i < (uint8_t)(frames - 1U)) ? (uint8_t)((reg_addr + i) & 0x7FU) : (uint8_t)0x00U; uint8_t pair[2] = {cmd, 0x00U}; tx[3U * i + 0U] = pair[0]; tx[3U * i + 1U] = pair[1]; @@ -172,4 +172,4 @@ void spi_driver_self_test_run(void) printf("read_reg_exact(0x10, len=3): %s\n", ok_read ? "OK" : "FAIL"); spi_test_print_bytes("read_reg data", rd_data, sizeof(rd_data)); printf("Note: this confirms MCU SPI framing/path only; real BQ register behavior needs the BQ IC connected.\n"); -|} +} diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 67198073..72a83483 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -28,6 +28,7 @@ #include "definitions.h" // SYS function prototypes #include "ic_bms/bms_spi.h" #include "ic_bms/spi_test.h" +#include "app/can_facade.h" #include @@ -38,11 +39,11 @@ // Section: Main Entry Point // ***************************************************************************** // ***************************************************************************** - -static inline void _delay(uint32_t cycles){ - - for (volatile uint32_t i=0; i Date: Tue, 17 Feb 2026 17:13:54 +0100 Subject: [PATCH 24/30] feat: implement CAN telemetry and added RTC --- .../bms_config_default/components/core.yml | 77 +++++++ .../mcc/bms_config_default/components/rtc.yml | 51 +++++ .../mcc/bms_config_default/mcc-config.mc4 | 15 +- .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- .../mcc/mcc-manifest-generated-success.yml | 2 +- bms/bms/bms_config/src/app/can_facade.c | 9 +- bms/bms/bms_config/src/app/can_telemetry.c | 53 +++++ bms/bms/bms_config/src/app/can_telemetry.h | 8 + .../src/config/default/definitions.h | 7 +- .../default/harmony-manifest-success.yml | 2 +- .../src/config/default/initialization.c | 10 +- .../src/config/default/interrupts.c | 5 +- .../src/config/default/interrupts.h | 1 + .../default/peripheral/nvic/plib_nvic.c | 2 + .../config/default/peripheral/rtc/plib_rtc.h | 116 +++++++++++ .../default/peripheral/rtc/plib_rtc_timer.c | 196 ++++++++++++++++++ bms/bms/bms_config/src/ic_bms/bms_spi.c | 53 ++--- bms/bms/bms_config/src/ic_bms/bms_spi.h | 2 +- bms/bms/bms_config/src/main.c | 20 +- 19 files changed, 585 insertions(+), 46 deletions(-) create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml create mode 100644 bms/bms/bms_config/src/app/can_telemetry.c create mode 100644 bms/bms/bms_config/src/app/can_telemetry.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index 4bc8de4f..8623dcfd 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -2416,6 +2416,83 @@ data: type: User type: Values type: String + RTC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: RTC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_ENABLE: + attributes: + id: NVIC_2_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_ENABLE: + attributes: + id: RTC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER_LOCK: + attributes: + id: NVIC_2_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_HANDLER_LOCK: + attributes: + id: RTC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER: + attributes: + id: NVIC_2_0_HANDLER + children: + - children: + - attributes: + id: core + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_HANDLER: + attributes: + id: RTC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: rtc + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml b/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml new file mode 100644 index 00000000..263ae14a --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml @@ -0,0 +1,51 @@ +configVersion: 1.0.0 +componentName: rtc +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: rtc + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: rtc + x: '496' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + RTC_MODE0_MATCHCLR: + attributes: + id: RTC_MODE0_MATCHCLR + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RTC_MODE0_TIMER_COMPARE: + attributes: + id: RTC_MODE0_TIMER_COMPARE + children: + - children: + - attributes: + value: '257' + type: User + type: Values + type: Hex + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index 6efee931..406b6d4a 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -13,6 +13,7 @@ modules: - dfp - evsys - nvmctrl +- rtc - sercom0 - sercom1 - sercom4 @@ -21,7 +22,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/ATSAMC21J18A.ld hash: 3fc7dbb63ae72ecd9b52572e4dd84ed79cbd37feb6064cb6d4df6fca301d09af - file: ../src/config/default/definitions.h - hash: 684faba403aafc7df339db66a96ecb1ff272af6fb7cfa3eb3576efb3bebe9bca + hash: 91773b88696c5b4a6431831370c738d56c0f75ee7c3fdd6522ed2982d3dcf4a0 - file: ../src/config/default/device.h hash: e539bb402fa4783d95ccf06235458b2e1fe01207c83c0e046a853e0385d0b6f4 - file: ../src/config/default/device_cache.h @@ -31,11 +32,11 @@ generatedFileHashHistoryMap: - file: ../src/config/default/exceptions.c hash: 42f9da2668e04ccb3473d45b149683a00f80072c6883c7918d6ce93997cd6987 - file: ../src/config/default/initialization.c - hash: 5c258d45783593cea48b4f20bb97db97d66b79498b80b83f7311da19ec246d0b + hash: 8571cf5ef9bd7b59949eb0ad322d4df2a15f5f75acd03528e8eb29a6ff0426a7 - file: ../src/config/default/interrupts.c - hash: 5891bfdfcd6ac15ae3104b3e1b8f9dc3f23b3f3693d906c95ba2bf63f2db3325 + hash: 9c48d638647fdc662b2073aa563426438e910ec20067ccb65cf4a61880390dac - file: ../src/config/default/interrupts.h - hash: 7a7d09f2efa3d5fb17247f2395f89f2c64fcf57376d3c9f55d2f7a73480fa813 + hash: 7275d94d754366f503520ce86b1690658f7f10875ffac6e8d7ca2d8386b31bf9 - file: ../src/config/default/libc_syscalls.c hash: 88bb2e34c939601b5b7ad076556e3ee0fcedf388436b8cddb6d6fd3e9d07472f - file: ../src/config/default/peripheral/adc/plib_adc0.c @@ -63,7 +64,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/evsys/plib_evsys.h hash: f7d08eb8162f271ce1db384c082586a6624e506aa7f502c64c4ab5a1aadac47d - file: ../src/config/default/peripheral/nvic/plib_nvic.c - hash: d09819a3c60270cd4c30c2eb519f7241c4dbc62edb7092e24ea4417a2242b1e3 + hash: 01df70e005995a9d644632584b14656ef8c117097045e0284b7b59674f43d009 - file: ../src/config/default/peripheral/nvic/plib_nvic.h hash: 9936ac782115af41003255283fa2f603f4ff2212d16275b7c80ea8d067a9e208 - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -74,6 +75,10 @@ generatedFileHashHistoryMap: hash: ff6d0b082a519a469666037c53308de446c9bda6a302d82e87366dbfd558c9f5 - file: ../src/config/default/peripheral/port/plib_port.h hash: dafff9b826888261d127ef40721d4e41cd0d67c713eb8f7e0df999847609097a +- file: ../src/config/default/peripheral/rtc/plib_rtc.h + hash: 92e9a13ceda691e011ad7efff84d616e8466f744723f8135850fc171fd53ac3b +- file: ../src/config/default/peripheral/rtc/plib_rtc_timer.c + hash: 23efd5b08dbe8c73a689fcf4291823b6c896acebbdfb7bf2ac5386ec5d86fec0 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c hash: 5ad6a7aecfa835077677e73fc771c2d82f35bdf4da9b54b499203176295ed534 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index 225ee0a2..f320f71a 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-12T15:46:42.434+01:00[Europe/Oslo] +creation_date: 2026-02-17T17:07:23.671+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml index 9188962e..fe21d7f9 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-12T15:39:48.277+01:00[Europe/Oslo] +creation_date: 2026-02-17T17:07:23.641+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/app/can_facade.c b/bms/bms/bms_config/src/app/can_facade.c index 10bc9af1..5dd9e300 100644 --- a/bms/bms/bms_config/src/app/can_facade.c +++ b/bms/bms/bms_config/src/app/can_facade.c @@ -12,8 +12,9 @@ can_facade.c */ - #include "definitions.h" - #include "can_facade.h" +#include "definitions.h" +#include "peripheral/port/plib_port.h" +#include "can_facade.h" /* ===== RX variables ===== */ volatile bool rxReady = false; @@ -50,6 +51,10 @@ /* ===== Init ===== */ void CAN_Init(void) { + + STB_OutputEnable(); + STB_Clear(); + CAN_RX_WAKEUP_InputEnable(); if (!s_ram_bound) { CAN0_MessageRAMConfigSet(s_can_msg_ram); diff --git a/bms/bms/bms_config/src/app/can_telemetry.c b/bms/bms/bms_config/src/app/can_telemetry.c new file mode 100644 index 00000000..17bfc8fc --- /dev/null +++ b/bms/bms/bms_config/src/app/can_telemetry.c @@ -0,0 +1,53 @@ +#include "app/can_telemetry.h" +#include "app/can_facade.h" +#include "ic_bms/bms_spi.h" + +#include +#include + +#define CAN_ID_CELLS_ALL 0x180 +#define CELLS_COUNT 6 +#define CELLS_PAYLOAD_LEN 12 + +static volatile bool telemetry_due = false; + +void CAN_telemetry_init(void) +{ + telemetry_due = false; +} + +void CAN_telemetry_tickISR(void) +{ + telemetry_due = true; +} + +void CAN_voltage_send(void) +{ + uint16_t cell_mV[CELLS_COUNT] = {0}; + uint8_t payload[CELLS_PAYLOAD_LEN]; + uint8_t i; + bool ok; + + if (!telemetry_due) + return; + + telemetry_due = false; + + ok = read_cells_1to6(cell_mV); + if (!ok) + { + //handle read error + } + + for (i = 0; i < CELLS_COUNT; i++) + { + payload[2 * i] = (uint8_t)(cell_mV[i] & 0xFF); + payload[2 * i + 1] = (uint8_t)((cell_mV[i] >> 8) & 0xFF); + } + + ok = CAN_Send(CAN_ID_CELLS_ALL, payload, CELLS_PAYLOAD_LEN); + if (!ok) + { + // optional: handle send error + } +} diff --git a/bms/bms/bms_config/src/app/can_telemetry.h b/bms/bms/bms_config/src/app/can_telemetry.h new file mode 100644 index 00000000..be9c650f --- /dev/null +++ b/bms/bms/bms_config/src/app/can_telemetry.h @@ -0,0 +1,8 @@ +#ifndef CAN_TELEMETRY_H +#define CAN_TELEMETRY_H + +void CAN_telemetry_init(void); +void CAN_telemetry_tickISR(void); // call from timer/RTC callback +void CAN_voltage_send(void); // call from main loop + +#endif diff --git a/bms/bms/bms_config/src/config/default/definitions.h b/bms/bms/bms_config/src/config/default/definitions.h index c995fad9..131d0de4 100644 --- a/bms/bms/bms_config/src/config/default/definitions.h +++ b/bms/bms/bms_config/src/config/default/definitions.h @@ -53,13 +53,14 @@ #include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" #include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" #include "peripheral/evsys/plib_evsys.h" -#include "peripheral/adc/plib_adc0.h" #include "peripheral/port/plib_port.h" #include "peripheral/clock/plib_clock.h" #include "peripheral/nvic/plib_nvic.h" -#include "peripheral/adc/plib_adc1.h" -#include "peripheral/can/plib_can0.h" #include "peripheral/sercom/usart/plib_sercom4_usart.h" +#include "peripheral/can/plib_can0.h" +#include "peripheral/rtc/plib_rtc.h" +#include "peripheral/adc/plib_adc0.h" +#include "peripheral/adc/plib_adc1.h" // DOM-IGNORE-BEGIN #ifdef __cplusplus // Provide C++ Compatibility diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml index 939f19f5..5ce4b379 100644 --- a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -4,7 +4,7 @@ project: bms_config_default -creation_date: 2026-02-12T15:39:48.282+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +creation_date: 2026-02-17T17:07:23.646+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime operating_system: Linux mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] mcc_version: v5.6.4 diff --git a/bms/bms/bms_config/src/config/default/initialization.c b/bms/bms/bms_config/src/config/default/initialization.c index 89c74f5a..2ee3b0ce 100644 --- a/bms/bms/bms_config/src/config/default/initialization.c +++ b/bms/bms/bms_config/src/config/default/initialization.c @@ -174,15 +174,17 @@ void SYS_Initialize ( void* data ) EVSYS_Initialize(); + SERCOM4_USART_Initialize(); - ADC0_Initialize(); - - ADC1_Initialize(); CAN0_Initialize(); - SERCOM4_USART_Initialize(); + RTC_Initialize(); + ADC0_Initialize(); + + ADC1_Initialize(); + NVIC_Initialize(); diff --git a/bms/bms/bms_config/src/config/default/interrupts.c b/bms/bms/bms_config/src/config/default/interrupts.c index 2a2bdeb0..f9e4cffb 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.c +++ b/bms/bms/bms_config/src/config/default/interrupts.c @@ -75,14 +75,13 @@ void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(vo } /* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 8.6 deviated 31 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 30 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ /* Device vectors list dummy definition*/ extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SysTick_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SYSTEM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void WDT_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void RTC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void EIC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); @@ -130,7 +129,7 @@ const H3DeviceVectors exception_table= .pfnSysTick_Handler = SysTick_Handler, .pfnSYSTEM_Handler = SYSTEM_Handler, .pfnWDT_Handler = WDT_Handler, - .pfnRTC_Handler = RTC_Handler, + .pfnRTC_Handler = RTC_InterruptHandler, .pfnEIC_Handler = EIC_Handler, .pfnFREQM_Handler = FREQM_Handler, .pfnTSENS_Handler = TSENS_Handler, diff --git a/bms/bms/bms_config/src/config/default/interrupts.h b/bms/bms/bms_config/src/config/default/interrupts.h index 46d67e40..a75778b7 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.h +++ b/bms/bms/bms_config/src/config/default/interrupts.h @@ -59,6 +59,7 @@ void Reset_Handler (void); void NonMaskableInt_Handler (void); void HardFault_Handler (void); +void RTC_InterruptHandler (void); void SERCOM0_SPI_InterruptHandler (void); void SERCOM1_I2C_InterruptHandler (void); void CAN0_InterruptHandler (void); diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c index bc6956e9..41b995e8 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c +++ b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c @@ -57,6 +57,8 @@ void NVIC_Initialize( void ) /* Enable the interrupt sources and configure the priorities as configured * from within the "Interrupt Manager" of MHC. */ + NVIC_SetPriority(RTC_IRQn, 3); + NVIC_EnableIRQ(RTC_IRQn); NVIC_SetPriority(SERCOM0_IRQn, 3); NVIC_EnableIRQ(SERCOM0_IRQn); NVIC_SetPriority(SERCOM1_IRQn, 3); diff --git a/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc.h b/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc.h new file mode 100644 index 00000000..a68c0c25 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc.h @@ -0,0 +1,116 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc.h + + Summary: + RTC PLIB Header file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_RTC_H +#define PLIB_RTC_H + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +/* Frequency of Counter Clock for RTC */ +#define RTC_COUNTER_CLOCK_FREQUENCY (1024U / (1UL << (0x1U - 1U))) + +#define RTC_TIMER32_INT_MASK_PER0 RTC_MODE0_INTENSET_PER0_Msk +#define RTC_TIMER32_INT_MASK_PER1 RTC_MODE0_INTENSET_PER1_Msk +#define RTC_TIMER32_INT_MASK_PER2 RTC_MODE0_INTENSET_PER2_Msk +#define RTC_TIMER32_INT_MASK_PER3 RTC_MODE0_INTENSET_PER3_Msk +#define RTC_TIMER32_INT_MASK_PER4 RTC_MODE0_INTENSET_PER4_Msk +#define RTC_TIMER32_INT_MASK_PER5 RTC_MODE0_INTENSET_PER5_Msk +#define RTC_TIMER32_INT_MASK_PER6 RTC_MODE0_INTENSET_PER6_Msk +#define RTC_TIMER32_INT_MASK_PER7 RTC_MODE0_INTENSET_PER7_Msk +#define RTC_TIMER32_INT_MASK_CMP0 RTC_MODE0_INTENSET_CMP0_Msk +#define RTC_TIMER32_INT_MASK_OVF RTC_MODE0_INTENSET_OVF_Msk +#define RTC_TIMER32_INT_MASK_INVALID 0xFFFFFFFFU +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +typedef uint32_t RTC_TIMER32_INT_MASK; +typedef void (*RTC_TIMER32_CALLBACK)( RTC_TIMER32_INT_MASK intCause, uintptr_t context ); + +typedef struct +{ + /* Timer 32Bit */ + RTC_TIMER32_CALLBACK timer32BitCallback; + RTC_TIMER32_INT_MASK timer32intCause; + uintptr_t context; +} RTC_OBJECT; + +void RTC_Initialize(void); +void RTC_Timer32CountSyncEnable ( void ); +void RTC_Timer32CountSyncDisable ( void ); +void RTC_Timer32Start ( void ); +void RTC_Timer32Stop ( void ); +void RTC_Timer32CounterSet ( uint32_t count ); +uint32_t RTC_Timer32CounterGet ( void ); +uint32_t RTC_Timer32FrequencyGet ( void ); +void RTC_Timer32CompareSet ( uint32_t compareValue ); +uint32_t RTC_Timer32PeriodGet ( void ); +void RTC_Timer32InterruptEnable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32InterruptDisable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_RTC_H */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c b/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c new file mode 100644 index 00000000..afbe6115 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c @@ -0,0 +1,196 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc_timer.c + + Summary: + RTC PLIB Implementation file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance in timer mode. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_rtc.h" +#include + +static volatile RTC_OBJECT rtcObj; + + +void RTC_Initialize(void) +{ + RTC_REGS->MODE0.RTC_CTRLA = RTC_MODE0_CTRLA_SWRST_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_SWRST_Msk) == RTC_MODE0_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization after Software Reset */ + } + + + RTC_REGS->MODE0.RTC_CTRLA = (uint16_t)(RTC_MODE0_CTRLA_MODE(0UL) | RTC_MODE0_CTRLA_PRESCALER(0x1UL) | RTC_MODE0_CTRLA_COUNTSYNC_Msk |RTC_MODE0_CTRLA_MATCHCLR_Msk ); + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + RTC_REGS->MODE0.RTC_COMP = 0x101U; + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } + +} + + +void RTC_Timer32CountSyncEnable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32CountSyncDisable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_COUNTSYNC_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32Start ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_ENABLE_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for synchronization after Enabling RTC */ + } +} + + +void RTC_Timer32Stop ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_ENABLE_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization after Disabling RTC */ + } +} + +void RTC_Timer32CounterSet ( uint32_t count ) +{ + RTC_REGS->MODE0.RTC_COUNT = count; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization after writing value to Count Register */ + } +} + +void RTC_Timer32CompareSet ( uint32_t compareValue ) +{ + RTC_REGS->MODE0.RTC_COMP = compareValue; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } +} +uint32_t RTC_Timer32CounterGet ( void ) +{ + if ((RTC_REGS->MODE0.RTC_CTRLA & RTC_MODE0_CTRLA_COUNTSYNC_Msk) == 0U) + { + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + } + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization before reading value from Count Register */ + } + return(RTC_REGS->MODE0.RTC_COUNT); +} + +uint32_t RTC_Timer32PeriodGet ( void ) +{ + /* Get 32Bit Compare Value */ + /*lint -e{9048} PC lint incorrectly reports a missing 'U' Suffix */ + return (RTC_MODE0_COUNT_COUNT_Msk); +} + +uint32_t RTC_Timer32FrequencyGet ( void ) +{ + /* Return Frequency of RTC Clock */ + return RTC_COUNTER_CLOCK_FREQUENCY; +} + +void RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENSET = (uint16_t)interruptMask; +} + +void RTC_Timer32InterruptDisable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENCLR = (uint16_t)interruptMask; +} + + +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ) +{ + rtcObj.timer32BitCallback = callback; + rtcObj.context = context; +} + +void __attribute__((used)) RTC_InterruptHandler( void ) +{ + rtcObj.timer32intCause = (RTC_TIMER32_INT_MASK) RTC_REGS->MODE0.RTC_INTFLAG; + RTC_REGS->MODE0.RTC_INTFLAG = (uint16_t)RTC_MODE0_INTFLAG_Msk; + (void)RTC_REGS->MODE0.RTC_INTFLAG; + + /* Invoke registered Callback function */ + if(rtcObj.timer32BitCallback != NULL) + { + RTC_TIMER32_INT_MASK timer32intCause = rtcObj.timer32intCause; + uintptr_t context = rtcObj.context; + rtcObj.timer32BitCallback( timer32intCause, context ); + } +} diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index da6204d1..7e480796 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -213,7 +213,7 @@ bool bq_direct_command(uint8_t command, uint16_t *data, char type) bool bq_command_only(uint16_t subcmd){ - // Send 0x3E/0x3F in one SPI frame (lead’s request) + // Send 0x3E/0x3F in one SPI frame uint8_t two[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) @@ -376,33 +376,38 @@ void bms_battery_status(void){ } -void read_cells_1to6(){ - const uint8_t CellVoltageAddr[6]={CELL_1_VOLTAGE, CELL_2_VOLTAGE, CELL_3_VOLTAGE, CELL_4_VOLTAGE, CELL_5_VOLTAGE, CELL_6_VOLTAGE}; - uint16_t raw = 0; - float voltage = 0.0f; - uint8_t i = 0; - - for (i=0; i<6; i++){ - if (bq_direct_command(CellVoltageAddr[i], &raw , R)) - { - voltage = raw*0.001f; // Convert mV to V - printf("Cell %u Voltage: %.3f V\n", i+1, voltage); - } - else { - { - printf("Failed to read Cell %u Voltage\n", i+1); - } - } - - +bool read_cells_1to6(uint16_t cell_mV[6]) +{ + const uint8_t addr[6] = { + CELL_1_VOLTAGE, CELL_2_VOLTAGE, CELL_3_VOLTAGE, + CELL_4_VOLTAGE, CELL_5_VOLTAGE, CELL_6_VOLTAGE + }; + uint16_t raw = 0U; + uint8_t i; + bool ok = true; + + if (cell_mV == NULL) + return false; + + for (i = 0U; i < 6U; i++) + { + if (bq_direct_command(addr[i], &raw, R)) + { + cell_mV[i] = raw; // mV + } + else + { + cell_mV[i] = 0U; + ok = false; + } } - - } + return ok; +} + - bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC) - { +bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC){ uint16_t raw; if (temp_dC == 0) diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index 70df55b9..a4f09062 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -94,7 +94,7 @@ bool bq_read_subcommand(uint16_t subcmd, uint8_t *data, uint8_t length); bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length); void bms_set_protection_threshold(void); void bms_battery_status(void); -void read_cells_1to6(void); +bool read_cells_1to6(uint16_t cell_mV[6]); void bms_sample_temps(void); bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC); void bothoff_init(void); diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 72a83483..40181802 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -29,8 +29,10 @@ #include "ic_bms/bms_spi.h" #include "ic_bms/spi_test.h" #include "app/can_facade.h" +#include "app/can_telemetry.h" #include +#include @@ -46,18 +48,33 @@ extern uint8_t rx_messageLength; extern uint16_t timestamp; +static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) +{ + (void)intCause; + (void)context; + CAN_telemetry_tickISR(); +} + + int main ( void ) { /* Initialize all modules */ SYS_Initialize ( NULL ); + CAN_Init(); + CAN_telemetry_init(); + RTC_Timer32CallbackRegister(TelemetryRtcCb, 0); + RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK_CMP0); + RTC_Timer32Start(); + + spi_driver_self_test_run(); bq76942_init(); bms_set_protection_threshold(); - read_cells_1to6(); bms_battery_status(); + //bms_sample_temps(); @@ -66,6 +83,7 @@ int main ( void ) { /* Maintain state machines of all polled MPLAB Harmony modules. */ SYS_Tasks ( ); + CAN_voltage_send(); } From 9877336bba1d6773deb70f0b11a0d1725ecd921a Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 19 Feb 2026 12:59:14 +0100 Subject: [PATCH 25/30] feat: Added RTC and CAN functionality --- .../mcc/bms_config_default/components/rtc.yml | 2 +- .../mcc/bms_config_default/mcc-config.mc4 | 2 +- .../components/adc0.yml | 237 ++ .../components/adc1.yml | 207 ++ .../components/can0.yml | 526 ++++ .../components/cmsis.yml | 24 + .../components/core.yml | 2508 +++++++++++++++++ .../components/dfp.yml | 31 + .../components/evsys.yml | 31 + .../components/nvmctrl.yml | 31 + .../components/rtc.yml | 51 + .../components/sercom0.yml | 340 +++ .../components/sercom1.yml | 308 ++ .../components/sercom4.yml | 275 ++ .../components/stdio.yml | 64 + .../bms_config_default_default/mcc-config.mc4 | 287 ++ .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- .../mcc/mcc-manifest-generated-success.yml | 2 +- bms/bms/bms_config/src/app/can_facade.c | 3 +- bms/bms/bms_config/src/app/can_telemetry.c | 119 +- bms/bms/bms_config/src/app/can_telemetry.h | 17 + .../default/harmony-manifest-success.yml | 2 +- .../default/peripheral/rtc/plib_rtc_timer.c | 2 +- bms/bms/bms_config/src/ic_bms/bms_spi.c | 16 +- bms/bms/bms_config/src/main.c | 9 +- 25 files changed, 5069 insertions(+), 27 deletions(-) create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/adc0.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/adc1.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/can0.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/cmsis.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/core.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/dfp.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/evsys.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/nvmctrl.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/rtc.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/sercom0.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/sercom1.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/sercom4.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/components/stdio.yml create mode 100644 bms/bms/bms_config/mcc/bms_config_default_default/mcc-config.mc4 diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml b/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml index 263ae14a..a1b11609 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/rtc.yml @@ -44,7 +44,7 @@ data: children: - children: - attributes: - value: '257' + value: '101' type: User type: Values type: Hex diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index 406b6d4a..512de79c 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -78,7 +78,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/rtc/plib_rtc.h hash: 92e9a13ceda691e011ad7efff84d616e8466f744723f8135850fc171fd53ac3b - file: ../src/config/default/peripheral/rtc/plib_rtc_timer.c - hash: 23efd5b08dbe8c73a689fcf4291823b6c896acebbdfb7bf2ac5386ec5d86fec0 + hash: 4a4a7c2350c37f32423dcf769c5d1e1d1d4dca3c83fd9b846c95c5368fda37ac - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c hash: 5ad6a7aecfa835077677e73fc771c2d82f35bdf4da9b54b499203176295ed534 - file: ../src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/adc0.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/adc0.yml new file mode 100644 index 00000000..eab9bff9 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/adc0.yml @@ -0,0 +1,237 @@ +configVersion: 1.0.0 +componentName: adc0 +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc0 + x: '30' + y: '216' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc0 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc0 + value: ADC0_RESRDY_IRQn + type: Dynamic + type: Values + type: String + ADC_CTRLB_PRESCALER: + attributes: + id: ADC_CTRLB_PRESCALER + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + ADC_CTRLC_DIFFMODE: + attributes: + id: ADC_CTRLC_DIFFMODE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + ADC_CONV_TRIGGER: + attributes: + id: ADC_CONV_TRIGGER + children: + - children: + - attributes: + value: SW Trigger + type: User + type: Values + type: Combo + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/adc1.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/adc1.yml new file mode 100644 index 00000000..b460e1ea --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/adc1.yml @@ -0,0 +1,207 @@ +configVersion: 1.0.0 +componentName: adc1 +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc1 + x: '30' + y: '148' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc1 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc1 + value: ADC1_RESRDY_IRQn + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/can0.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/can0.yml new file mode 100644 index 00000000..67ee6bc4 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/can0.yml @@ -0,0 +1,526 @@ +configVersion: 1.0.0 +componentName: can0 +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: can0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: can0 + x: '196' + y: '220' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + NBTP_NBRP: + attributes: + id: NBTP_NBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + - attributes: + value: '3' + type: User + type: Values + type: Integer + NOMINAL_SAMPLE_POINT: + attributes: + id: NOMINAL_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '96.875' + type: Dynamic + - attributes: + value: '75.0' + type: User + type: Values + type: Float + NBTP_TOTAL_TIME_QUANTA: + attributes: + id: NBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG1: + attributes: + id: NBTP_NTSEG1 + children: + - children: + - attributes: + id: can0 + value: '17' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG2: + attributes: + id: NBTP_NTSEG2 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + NBTP_NSJW: + attributes: + id: NBTP_NSJW + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + - attributes: + value: '5' + type: User + type: Values + type: Integer + CALCULATED_NOMINAL_BITRATE: + attributes: + id: CALCULATED_NOMINAL_BITRATE + children: + - children: + - attributes: + id: can0 + value: '500' + type: Dynamic + type: Values + type: Integer + NOMINAL_TIME_QUANTA_PERIOD: + attributes: + id: NOMINAL_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '83.333' + type: Dynamic + type: Values + type: String + CALCULATED_NOMINAL_ERRORRATE: + attributes: + id: CALCULATED_NOMINAL_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + AUTO_NOMINAL_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_NOMINAL_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + DBTP_TOTAL_TIME_QUANTA: + attributes: + id: DBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG1: + attributes: + id: DBTP_DTSEG1 + children: + - children: + - attributes: + id: can0 + value: '17' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG2: + attributes: + id: DBTP_DTSEG2 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + DBTP_DSJW: + attributes: + id: DBTP_DSJW + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + - attributes: + value: '5' + type: User + type: Values + type: Integer + CALCULATED_DATA_BITRATE: + attributes: + id: CALCULATED_DATA_BITRATE + children: + - children: + - attributes: + id: can0 + value: '2000' + type: Dynamic + type: Values + type: Integer + DATA_TIME_QUANTA_PERIOD: + attributes: + id: DATA_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '20.833' + type: Dynamic + type: Values + type: String + CALCULATED_DATA_ERRORRATE: + attributes: + id: CALCULATED_DATA_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + CAN_OPMODE: + attributes: + id: CAN_OPMODE + children: + - children: + - attributes: + value: CAN FD + type: User + type: Values + type: Combo + instHeaderFile: + attributes: + id: instHeaderFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_legacy.h.ftl + type: String + type: Attributes + type: File + sourceFile: + attributes: + id: sourceFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_legacy.c.ftl + type: String + type: Attributes + type: File + INTERRUPT_MODE: + attributes: + id: INTERRUPT_MODE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + DBTP_DBRP: + attributes: + id: DBTP_DBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + - attributes: + value: '0' + type: User + type: Values + type: Integer + DATA_SAMPLE_POINT: + attributes: + id: DATA_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '87.5' + type: Dynamic + - attributes: + value: '75.0' + type: User + type: Values + type: Float + AUTO_DATA_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_DATA_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + DATA_BITRATE: + attributes: + id: DATA_BITRATE + children: + - children: + - attributes: + value: '2000' + type: User + type: Values + type: Integer + NOMINAL_BITRATE: + attributes: + id: NOMINAL_BITRATE + children: + - children: + - attributes: + value: '500' + type: User + type: Values + type: Integer + headerFile: + attributes: + id: headerFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_common_legacy.h + type: String + type: Attributes + type: File + CAN_GENERATE_LEGACY_APIS: + attributes: + id: CAN_GENERATE_LEGACY_APIS + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_WATERMARK: + attributes: + id: RXF0_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + RXF0_ELEMENTS: + attributes: + id: RXF0_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + RXF0_BYTES_CFG: + attributes: + id: RXF0_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + RXF1_USE: + attributes: + id: RXF1_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + RXBUF_USE: + attributes: + id: RXBUF_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + TX_FIFO_WATERMARK: + attributes: + id: TX_FIFO_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + TX_FIFO_ELEMENTS: + attributes: + id: TX_FIFO_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + TX_FIFO_BYTES_CFG: + attributes: + id: TX_FIFO_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + FILTERS_STD_NOMATCH: + attributes: + id: FILTERS_STD_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + FILTERS_EXT_NOMATCH: + attributes: + id: FILTERS_EXT_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + TIMESTAMP_ENABLE: + attributes: + id: TIMESTAMP_ENABLE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_OVERWRITE: + attributes: + id: RXF0_OVERWRITE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/cmsis.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/cmsis.yml new file mode 100644 index 00000000..d28a0297 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/cmsis.yml @@ -0,0 +1,24 @@ +configVersion: 1.0.0 +componentName: cmsis +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: cmsis + type: module + version: '' +- dependencyPackage: '' + name: CMSIS_5 + type: package + version: 5.9.1-dev +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/core.yml new file mode 100644 index 00000000..8623dcfd --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/core.yml @@ -0,0 +1,2508 @@ +configVersion: 1.0.0 +componentName: core +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: core + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: core + x: '80' + y: '4' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC0_CLOCK_ENABLE: + attributes: + id: ADC0_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC0_CLOCK_FREQUENCY: + attributes: + id: ADC0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + CAN0_CLOCK_ENABLE: + attributes: + id: CAN0_CLOCK_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_CLOCK_FREQUENCY: + attributes: + id: CAN0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_22_CHEN: + attributes: + id: GCLK_ID_22_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_22_FREQ: + attributes: + id: GCLK_ID_22_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_25_CHEN: + attributes: + id: GCLK_ID_25_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_25_FREQ: + attributes: + id: GCLK_ID_25_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_26_CHEN: + attributes: + id: GCLK_ID_26_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_26_FREQ: + attributes: + id: GCLK_ID_26_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_33_CHEN: + attributes: + id: GCLK_ID_33_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_33_FREQ: + attributes: + id: GCLK_ID_33_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + MCLK_AHB_INITIAL_VALUE: + attributes: + id: MCLK_AHB_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1dff' + type: Dynamic + type: Values + type: String + MCLK_APBC_INITIAL_VALUE: + attributes: + id: MCLK_APBC_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x60026' + type: Dynamic + type: Values + type: String + NVIC_12_0_ENABLE: + attributes: + id: NVIC_12_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_HANDLER: + attributes: + id: NVIC_12_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM3_Handler + type: Dynamic + type: Values + type: String + NVIC_12_0_HANDLER_LOCK: + attributes: + id: NVIC_12_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_ENABLE: + attributes: + id: NVIC_14_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_HANDLER: + attributes: + id: NVIC_14_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM5_Handler + type: Dynamic + type: Values + type: String + NVIC_14_0_HANDLER_LOCK: + attributes: + id: NVIC_14_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM3_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM3_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM5_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM5_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM5_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM5_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_FREQUENCY: + attributes: + id: ADC1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_FREQ: + attributes: + id: GCLK_ID_34_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_CHEN: + attributes: + id: GCLK_ID_34_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_ENABLE: + attributes: + id: ADC1_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_CLOCK_FREQUENCY: + attributes: + id: CAN1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_FREQ: + attributes: + id: GCLK_ID_27_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_CHEN: + attributes: + id: GCLK_ID_27_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM1_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_FREQ: + attributes: + id: GCLK_ID_20_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_CHEN: + attributes: + id: GCLK_ID_20_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_ENABLE: + attributes: + id: NVIC_10_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER_LOCK: + attributes: + id: NVIC_10_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER: + attributes: + id: NVIC_10_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + CAN1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_16_0_ENABLE: + attributes: + id: NVIC_16_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + NVIC_16_0_HANDLER: + attributes: + id: NVIC_16_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN1_Handler + type: Dynamic + type: Values + type: String + NVIC_16_0_HANDLER_LOCK: + attributes: + id: NVIC_16_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_ENABLE: + attributes: + id: NVIC_15_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE: + attributes: + id: CAN0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_HANDLER: + attributes: + id: NVIC_15_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + CAN0_INTERRUPT_HANDLER: + attributes: + id: CAN0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: can0 + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_15_0_HANDLER_LOCK: + attributes: + id: NVIC_15_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_HANDLER_LOCK: + attributes: + id: CAN0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM4_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_FREQ: + attributes: + id: GCLK_ID_23_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_CHEN: + attributes: + id: GCLK_ID_23_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM4_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_ENABLE: + attributes: + id: NVIC_13_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER_LOCK: + attributes: + id: NVIC_13_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM4_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER: + attributes: + id: NVIC_13_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM4_INTERRUPT_HANDLER: + attributes: + id: SERCOM4_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom4 + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM1_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM1_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER: + attributes: + id: SERCOM1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom1 + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM0_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_FREQ: + attributes: + id: GCLK_ID_19_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_CHEN: + attributes: + id: GCLK_ID_19_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM0_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_ENABLE: + attributes: + id: NVIC_9_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER_LOCK: + attributes: + id: NVIC_9_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER: + attributes: + id: NVIC_9_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_INTERRUPT_HANDLER: + attributes: + id: SERCOM0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom0 + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + PORT_GROUP_1_DIR: + attributes: + id: PORT_GROUP_1_DIR + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_OUT: + attributes: + id: PORT_GROUP_1_OUT + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PINCFG8: + attributes: + id: PORT_GROUP_1_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_8_USED: + attributes: + id: PORT_GROUP_1_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX4: + attributes: + id: PORT_GROUP_1_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_8: + attributes: + id: PORT_GROUP_1_PAD_8 + children: + - children: + - attributes: + id: core + value: PB08 + type: Dynamic + type: Values + type: String + PIN_11_PERIPHERAL_FUNCTION: + attributes: + id: PIN_11_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG5: + attributes: + id: PORT_GROUP_1_PINCFG5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_5_USED: + attributes: + id: PORT_GROUP_1_PIN_5_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX2: + attributes: + id: PORT_GROUP_1_PMUX2 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_5: + attributes: + id: PORT_GROUP_1_PAD_5 + children: + - children: + - attributes: + id: core + value: PB05 + type: Dynamic + type: Values + type: String + PIN_6_PERIPHERAL_FUNCTION: + attributes: + id: PIN_6_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_DIR: + attributes: + id: PORT_GROUP_0_DIR + children: + - children: + - attributes: + id: core + value: '0x100c8080' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_OUT: + attributes: + id: PORT_GROUP_0_OUT + children: + - children: + - attributes: + id: core + value: '0x80' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG1: + attributes: + id: PORT_GROUP_0_PINCFG1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_1_USED: + attributes: + id: PORT_GROUP_0_PIN_1_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX0: + attributes: + id: PORT_GROUP_0_PMUX0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_1: + attributes: + id: PORT_GROUP_0_PAD_1 + children: + - children: + - attributes: + id: core + value: PA01 + type: Dynamic + type: Values + type: String + PIN_2_PERIPHERAL_FUNCTION: + attributes: + id: PIN_2_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG0: + attributes: + id: PORT_GROUP_0_PINCFG0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_0_USED: + attributes: + id: PORT_GROUP_0_PIN_0_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_0: + attributes: + id: PORT_GROUP_0_PAD_0 + children: + - children: + - attributes: + id: core + value: PA00 + type: Dynamic + type: Values + type: String + PIN_1_PERIPHERAL_FUNCTION: + attributes: + id: PIN_1_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG9: + attributes: + id: PORT_GROUP_1_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_9_USED: + attributes: + id: PORT_GROUP_1_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PINCFG3: + attributes: + id: PORT_GROUP_0_PINCFG3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_3_USED: + attributes: + id: PORT_GROUP_0_PIN_3_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX1: + attributes: + id: PORT_GROUP_0_PMUX1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_3: + attributes: + id: PORT_GROUP_0_PAD_3 + children: + - children: + - attributes: + id: core + value: PA03 + type: Dynamic + type: Values + type: String + PIN_4_PERIPHERAL_FUNCTION: + attributes: + id: PIN_4_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_DIR: + attributes: + id: PIN_2_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_PULLEN: + attributes: + id: PIN_2_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_INEN: + attributes: + id: PIN_2_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG6: + attributes: + id: PORT_GROUP_1_PINCFG6 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_6_USED: + attributes: + id: PORT_GROUP_1_PIN_6_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX3: + attributes: + id: PORT_GROUP_1_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_6: + attributes: + id: PORT_GROUP_1_PAD_6 + children: + - children: + - attributes: + id: core + value: PB06 + type: Dynamic + type: Values + type: String + PIN_9_PERIPHERAL_FUNCTION: + attributes: + id: PIN_9_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG7: + attributes: + id: PORT_GROUP_1_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_7_USED: + attributes: + id: PORT_GROUP_1_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PAD_7: + attributes: + id: PORT_GROUP_1_PAD_7 + children: + - children: + - attributes: + id: core + value: PB07 + type: Dynamic + type: Values + type: String + PIN_10_PERIPHERAL_FUNCTION: + attributes: + id: PIN_10_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PAD_9: + attributes: + id: PORT_GROUP_1_PAD_9 + children: + - children: + - attributes: + id: core + value: PB09 + type: Dynamic + type: Values + type: String + PIN_12_PERIPHERAL_FUNCTION: + attributes: + id: PIN_12_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG10: + attributes: + id: PORT_GROUP_0_PINCFG10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_10_USED: + attributes: + id: PORT_GROUP_0_PIN_10_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX5: + attributes: + id: PORT_GROUP_0_PMUX5 + children: + - children: + - attributes: + id: core + value: '0x20' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_10: + attributes: + id: PORT_GROUP_0_PAD_10 + children: + - children: + - attributes: + id: core + value: PA10 + type: Dynamic + type: Values + type: String + PIN_19_PERIPHERAL_FUNCTION: + attributes: + id: PIN_19_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_MODE: + attributes: + id: PIN_16_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_FUNCTION_TYPE: + attributes: + id: PIN_16_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PMUX3: + attributes: + id: PORT_GROUP_0_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_7: + attributes: + id: PORT_GROUP_0_PAD_7 + children: + - children: + - attributes: + id: core + value: PA07 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG7: + attributes: + id: PORT_GROUP_0_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_7_USED: + attributes: + id: PORT_GROUP_0_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_16_PERIPHERAL_FUNCTION: + attributes: + id: PIN_16_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_INEN: + attributes: + id: PIN_16_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_DIR: + attributes: + id: PIN_16_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_16_FUNCTION_NAME: + attributes: + id: PIN_16_FUNCTION_NAME + children: + - children: + - attributes: + value: GPIO_PA07 + type: User + type: Values + type: String + PIN_17_MODE: + attributes: + id: PIN_17_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_17_FUNCTION_TYPE: + attributes: + id: PIN_17_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD0 + type: User + type: Values + type: String + PORT_GROUP_0_PMUX4: + attributes: + id: PORT_GROUP_0_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_8: + attributes: + id: PORT_GROUP_0_PAD_8 + children: + - children: + - attributes: + id: core + value: PA08 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG8: + attributes: + id: PORT_GROUP_0_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_8_USED: + attributes: + id: PORT_GROUP_0_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_17_PERIPHERAL_FUNCTION: + attributes: + id: PIN_17_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_18_MODE: + attributes: + id: PIN_18_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_18_FUNCTION_TYPE: + attributes: + id: PIN_18_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD1 + type: User + type: Values + type: String + PORT_GROUP_0_PAD_9: + attributes: + id: PORT_GROUP_0_PAD_9 + children: + - children: + - attributes: + id: core + value: PA09 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG9: + attributes: + id: PORT_GROUP_0_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_9_USED: + attributes: + id: PORT_GROUP_0_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_18_PERIPHERAL_FUNCTION: + attributes: + id: PIN_18_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG11: + attributes: + id: PORT_GROUP_0_PINCFG11 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_11_USED: + attributes: + id: PORT_GROUP_0_PIN_11_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_11: + attributes: + id: PORT_GROUP_0_PAD_11 + children: + - children: + - attributes: + id: core + value: PA11 + type: Dynamic + type: Values + type: String + PIN_20_PERIPHERAL_FUNCTION: + attributes: + id: PIN_20_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_20_MODE: + attributes: + id: PIN_20_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_20_FUNCTION_TYPE: + attributes: + id: PIN_20_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD3 + type: User + type: Values + type: String + PIN_16_LAT: + attributes: + id: PIN_16_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String + PIN_53_MODE: + attributes: + id: PIN_53_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_FUNCTION_TYPE: + attributes: + id: PIN_53_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG28: + attributes: + id: PORT_GROUP_0_PINCFG28 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_28_USED: + attributes: + id: PORT_GROUP_0_PIN_28_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_53_INEN: + attributes: + id: PIN_53_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_DIR: + attributes: + id: PIN_53_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX14: + attributes: + id: PORT_GROUP_0_PMUX14 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_28: + attributes: + id: PORT_GROUP_0_PAD_28 + children: + - children: + - attributes: + id: core + value: PA28 + type: Dynamic + type: Values + type: String + PIN_53_PERIPHERAL_FUNCTION: + attributes: + id: PIN_53_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_53_FUNCTION_NAME: + attributes: + id: PIN_53_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_G + type: User + type: Values + type: String + PIN_53_DRVSTR: + attributes: + id: PIN_53_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PIN_38_MODE: + attributes: + id: PIN_38_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_FUNCTION_TYPE: + attributes: + id: PIN_38_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG19: + attributes: + id: PORT_GROUP_0_PINCFG19 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_19_USED: + attributes: + id: PORT_GROUP_0_PIN_19_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_38_INEN: + attributes: + id: PIN_38_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_DIR: + attributes: + id: PIN_38_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX9: + attributes: + id: PORT_GROUP_0_PMUX9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_19: + attributes: + id: PORT_GROUP_0_PAD_19 + children: + - children: + - attributes: + id: core + value: PA19 + type: Dynamic + type: Values + type: String + PIN_38_PERIPHERAL_FUNCTION: + attributes: + id: PIN_38_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_38_FUNCTION_NAME: + attributes: + id: PIN_38_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_Y + type: User + type: Values + type: String + PIN_37_MODE: + attributes: + id: PIN_37_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_FUNCTION_TYPE: + attributes: + id: PIN_37_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG18: + attributes: + id: PORT_GROUP_0_PINCFG18 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_18_USED: + attributes: + id: PORT_GROUP_0_PIN_18_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_37_INEN: + attributes: + id: PIN_37_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_DIR: + attributes: + id: PIN_37_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_18: + attributes: + id: PORT_GROUP_0_PAD_18 + children: + - children: + - attributes: + id: core + value: PA18 + type: Dynamic + type: Values + type: String + PIN_37_PERIPHERAL_FUNCTION: + attributes: + id: PIN_37_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_37_FUNCTION_NAME: + attributes: + id: PIN_37_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_R + type: User + type: Values + type: String + PIN_31_MODE: + attributes: + id: PIN_31_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_FUNCTION_TYPE: + attributes: + id: PIN_31_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG14: + attributes: + id: PORT_GROUP_0_PINCFG14 + children: + - children: + - attributes: + id: core + value: '0x2' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_14_USED: + attributes: + id: PORT_GROUP_0_PIN_14_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_31_INEN: + attributes: + id: PIN_31_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_31_DIR: + attributes: + id: PIN_31_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PMUX7: + attributes: + id: PORT_GROUP_0_PMUX7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_14: + attributes: + id: PORT_GROUP_0_PAD_14 + children: + - children: + - attributes: + id: core + value: PA14 + type: Dynamic + type: Values + type: String + PIN_31_PERIPHERAL_FUNCTION: + attributes: + id: PIN_31_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_31_FUNCTION_NAME: + attributes: + id: PIN_31_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN_RX_WAKEUP + type: User + type: Values + type: String + PIN_32_MODE: + attributes: + id: PIN_32_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_FUNCTION_TYPE: + attributes: + id: PIN_32_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG15: + attributes: + id: PORT_GROUP_0_PINCFG15 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_15_USED: + attributes: + id: PORT_GROUP_0_PIN_15_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_32_INEN: + attributes: + id: PIN_32_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_DIR: + attributes: + id: PIN_32_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_15: + attributes: + id: PORT_GROUP_0_PAD_15 + children: + - children: + - attributes: + id: core + value: PA15 + type: Dynamic + type: Values + type: String + PIN_32_PERIPHERAL_FUNCTION: + attributes: + id: PIN_32_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_32_FUNCTION_NAME: + attributes: + id: PIN_32_FUNCTION_NAME + children: + - children: + - attributes: + value: STB + type: User + type: Values + type: String + PIN_31_PULLEN: + attributes: + id: PIN_31_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_DRVSTR: + attributes: + id: PIN_31_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PORT_GROUP_0_PINCFG21: + attributes: + id: PORT_GROUP_0_PINCFG21 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_21_USED: + attributes: + id: PORT_GROUP_0_PIN_21_USED + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX10: + attributes: + id: PORT_GROUP_0_PMUX10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_21: + attributes: + id: PORT_GROUP_0_PAD_21 + children: + - children: + - attributes: + id: core + value: PA21 + type: Dynamic + type: Values + type: String + PIN_42_PERIPHERAL_FUNCTION: + attributes: + id: PIN_42_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_MODE: + attributes: + id: PIN_45_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_FUNCTION_TYPE: + attributes: + id: PIN_45_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG24: + attributes: + id: PORT_GROUP_0_PINCFG24 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_24_USED: + attributes: + id: PORT_GROUP_0_PIN_24_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX12: + attributes: + id: PORT_GROUP_0_PMUX12 + children: + - children: + - attributes: + id: core + value: '0x66' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_24: + attributes: + id: PORT_GROUP_0_PAD_24 + children: + - children: + - attributes: + id: core + value: PA24 + type: Dynamic + type: Values + type: String + PIN_45_PERIPHERAL_FUNCTION: + attributes: + id: PIN_45_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_46_MODE: + attributes: + id: PIN_46_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_46_FUNCTION_TYPE: + attributes: + id: PIN_46_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PORT_GROUP_0_PAD_25: + attributes: + id: PORT_GROUP_0_PAD_25 + children: + - children: + - attributes: + id: core + value: PA25 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG25: + attributes: + id: PORT_GROUP_0_PINCFG25 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_25_USED: + attributes: + id: PORT_GROUP_0_PIN_25_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_46_PERIPHERAL_FUNCTION: + attributes: + id: PIN_46_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + RTC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: RTC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_ENABLE: + attributes: + id: NVIC_2_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_ENABLE: + attributes: + id: RTC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER_LOCK: + attributes: + id: NVIC_2_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_HANDLER_LOCK: + attributes: + id: RTC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER: + attributes: + id: NVIC_2_0_HANDLER + children: + - children: + - attributes: + id: core + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_HANDLER: + attributes: + id: RTC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: rtc + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + userData: + children: + - attributes: + canvasHeight: '0' + canvasWidth: '0' + type: GraphSettings + - children: + - attributes: + id: profile0 + name: Main + type: Profile + type: PowerProfiles + type: UserData diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/dfp.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/dfp.yml new file mode 100644 index 00000000..bf031446 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/dfp.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: dfp +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: dfp + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: dfp + x: '520' + y: '11' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/evsys.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/evsys.yml new file mode 100644 index 00000000..26dbf820 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/evsys.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: evsys +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: evsys + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: evsys + x: '202' + y: '10' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/nvmctrl.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/nvmctrl.yml new file mode 100644 index 00000000..48ca6881 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/nvmctrl.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: nvmctrl +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: nvmctrl + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: nvmctrl + x: '339' + y: '7' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/rtc.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/rtc.yml new file mode 100644 index 00000000..263ae14a --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/rtc.yml @@ -0,0 +1,51 @@ +configVersion: 1.0.0 +componentName: rtc +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: rtc + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: rtc + x: '496' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + RTC_MODE0_MATCHCLR: + attributes: + id: RTC_MODE0_MATCHCLR + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RTC_MODE0_TIMER_COMPARE: + attributes: + id: RTC_MODE0_TIMER_COMPARE + children: + - children: + - attributes: + value: '257' + type: User + type: Values + type: Hex + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom0.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom0.yml new file mode 100644 index 00000000..190d836f --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom0.yml @@ -0,0 +1,340 @@ +configVersion: 1.0.0 +componentName: sercom0 +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom0 + x: '538' + y: '152' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom0 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SERCOM_SPIM_COMMON_HEADER: + attributes: + id: SERCOM_SPIM_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_HEADER: + attributes: + id: SERCOM_SPIM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_SOURCE: + attributes: + id: SERCOM_SPIM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '23' + type: Dynamic + type: Values + type: Integer + SPI_CLOCK_PHASE: + attributes: + id: SPI_CLOCK_PHASE + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SPI_DIPO: + attributes: + id: SPI_DIPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom0 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom0 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom0 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + SPI_DOPO: + attributes: + id: SPI_DOPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom1.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom1.yml new file mode 100644 index 00000000..1c17c58d --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom1.yml @@ -0,0 +1,308 @@ +configVersion: 1.0.0 +componentName: sercom1 +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom1 + x: '368' + y: '153' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom1 + value: '232' + type: Dynamic + type: Values + type: Hex + I2C_CLOCK_SPEED_HZ: + attributes: + id: I2C_CLOCK_SPEED_HZ + children: + - children: + - attributes: + id: sercom1 + value: '100000' + type: Dynamic + type: Values + type: Integer + I2C_SCLSM: + attributes: + id: I2C_SCLSM + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + SERCOM_I2CM_HEADER: + attributes: + id: SERCOM_I2CM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_MASTER_HEADER: + attributes: + id: SERCOM_I2CM_MASTER_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_SOURCE: + attributes: + id: SERCOM_I2CM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '2' + type: User + type: Values + type: KeyValueSet + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom1 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom1 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom4.yml b/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom4.yml new file mode 100644 index 00000000..b4b5ca49 --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default_default/components/sercom4.yml @@ -0,0 +1,275 @@ +configVersion: 1.0.0 +componentName: sercom4 +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom4 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: SERCOM4_I2C + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_SPI + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: stdio + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: UART + type: String + type: Attributes + type: DirectCapability + type: Attachments + type: sercom4 + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom4 + x: '67' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom4 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM4_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM4_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_OPERATING_MODE: + attributes: + id: USART_OPERATING_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - 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f320f71a..21fef62d 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-17T17:07:23.671+01:00[Europe/Oslo] +creation_date: 2026-02-19T11:04:40.702+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml index fe21d7f9..decffc3c 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-17T17:07:23.641+01:00[Europe/Oslo] +creation_date: 2026-02-19T10:14:36.905+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/app/can_facade.c b/bms/bms/bms_config/src/app/can_facade.c index 5dd9e300..4279f8f0 100644 --- a/bms/bms/bms_config/src/app/can_facade.c +++ b/bms/bms/bms_config/src/app/can_facade.c @@ -37,7 +37,7 @@ rxReady = true; - printf("Callback"); + /* Re-arm RX */ CAN0_MessageReceive(&rx_messageID, @@ -54,6 +54,7 @@ STB_OutputEnable(); STB_Clear(); + ////////////////////// CAN_RX_WAKEUP_InputEnable(); if (!s_ram_bound) { diff --git a/bms/bms/bms_config/src/app/can_telemetry.c b/bms/bms/bms_config/src/app/can_telemetry.c index 17bfc8fc..96eba08e 100644 --- a/bms/bms/bms_config/src/app/can_telemetry.c +++ b/bms/bms/bms_config/src/app/can_telemetry.c @@ -2,23 +2,32 @@ #include "app/can_facade.h" #include "ic_bms/bms_spi.h" + #include #include -#define CAN_ID_CELLS_ALL 0x180 -#define CELLS_COUNT 6 -#define CELLS_PAYLOAD_LEN 12 +extern volatile bool rxReady; +extern uint32_t rx_messageID; +extern uint8_t rx_message[64]; +extern uint8_t rx_messageLength; + + + -static volatile bool telemetry_due = false; + + +static volatile bool flag_vol_tx = false; +static volatile bool flag_temp_tx = false; void CAN_telemetry_init(void) { - telemetry_due = false; + flag_vol_tx = false; } void CAN_telemetry_tickISR(void) { - telemetry_due = true; + flag_vol_tx = true; + flag_temp_tx = true; } void CAN_voltage_send(void) @@ -28,10 +37,10 @@ void CAN_voltage_send(void) uint8_t i; bool ok; - if (!telemetry_due) + if (!flag_vol_tx) return; - telemetry_due = false; + flag_vol_tx = false; ok = read_cells_1to6(cell_mV); if (!ok) @@ -45,9 +54,99 @@ void CAN_voltage_send(void) payload[2 * i + 1] = (uint8_t)((cell_mV[i] >> 8) & 0xFF); } - ok = CAN_Send(CAN_ID_CELLS_ALL, payload, CELLS_PAYLOAD_LEN); + ok = CAN_Send(CAN_VOLTAGE_ID, payload, CELLS_PAYLOAD_LEN); if (!ok) { - // optional: handle send error + //handle send error } } +void CAN_temp_send(void) +{ + int16_t t1_dC, t2_dC, t3_dC; + uint8_t payload[6]; + bool ok; + + if (!flag_temp_tx) + return; + + flag_temp_tx = false; + + bms_read_ts_temp(TS1_TEMP, &t1_dC); + bms_read_ts_temp(TS2_TEMP, &t2_dC); + bms_read_ts_temp(TS3_TEMP, &t3_dC); + + payload[0] = (uint8_t)(t1_dC & 0xFF); + payload[1] = (uint8_t)((t1_dC >> 8) & 0xFF); + payload[2] = (uint8_t)(t2_dC & 0xFF); + payload[3] = (uint8_t)((t2_dC >> 8) & 0xFF); + payload[4] = (uint8_t)(t3_dC & 0xFF); + payload[5] = (uint8_t)((t3_dC >> 8) & 0xFF); + + ok = CAN_Send(CAN_TEMP_ID, payload, sizeof(payload)); + if (!ok) + { + //handle send error + } + + +} + +void CAN_bothoff_rx(void) +{ + + if(!rxReady) + return; + rxReady = false; + + if ((rx_messageID == CAN_ID_BOTHOFF_CMD) && (rx_messageLength > 0) && rx_message[0] == BOTHOFF_CMD_BYTE) + { + + bothoff_init(); + bothoff_high(); + } + + +} + +void CAN_stb_mode(void){ + + if(!rxReady) + return; + rxReady = false; + + if(rx_messageID == CAN_STANDBYMODE_ID && rx_messageLength > 0){ + + uint8_t standby_mode = rx_message[0]; + + + switch (standby_mode) { + case 0x00: + // normal operation mode + break; + case 0x01: + // low power standby mode + break; + case 0x02: + // deep sleep mode + break; + default: + // Handle invalid standby mode value + break; + } + } +} + +void CAN_rst(void){ + if(!rxReady) + return; + rxReady = false; + + if(rx_messageID == CAN_RST_MCU && rx_messageLength > 0){ + + uint8_t rst_cmd = rx_message[0]; + + if(rst_cmd == CAN_RST_MCU){ + NVIC_SystemReset(); + } + } +} \ No newline at end of file diff --git a/bms/bms/bms_config/src/app/can_telemetry.h b/bms/bms/bms_config/src/app/can_telemetry.h index be9c650f..839fda31 100644 --- a/bms/bms/bms_config/src/app/can_telemetry.h +++ b/bms/bms/bms_config/src/app/can_telemetry.h @@ -1,8 +1,25 @@ #ifndef CAN_TELEMETRY_H #define CAN_TELEMETRY_H +#define CELLS_COUNT 6 +#define CELLS_PAYLOAD_LEN 12 +#define CAN_ID_BOTHOFF_CMD 0x200 //EXAMPLE VALUE +#define BOTHOFF_CMD_BYTE 0xA5 +#define CAN_TEMP_ID 0x100 //EXAMPLE VALUE +#define CAN_VOLTAGE_ID 0x101 //EXAMPLE VALUE + +//legg til func for current, pressure, standbymode, reset mcu + +#define CAN_PRESSURE_ID 0x102 //EXAMPLE VALUE +#define CAN_STANDBYMODE_ID 0x103 //EXAMPLE VALUE +#define CAN_RST_MCU 0x104 //EXAMPLE VALUE +#define CAN_CURRENT_ID 0x105 //EXAMPLE VALUE + + void CAN_telemetry_init(void); void CAN_telemetry_tickISR(void); // call from timer/RTC callback void CAN_voltage_send(void); // call from main loop +void CAN_bothoff_rx(void); + #endif diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml index 5ce4b379..a8349565 100644 --- a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -4,7 +4,7 @@ project: bms_config_default -creation_date: 2026-02-17T17:07:23.646+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +creation_date: 2026-02-19T10:14:36.918+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime operating_system: Linux mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] mcc_version: v5.6.4 diff --git a/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c b/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c index afbe6115..d6566db1 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c +++ b/bms/bms/bms_config/src/config/default/peripheral/rtc/plib_rtc_timer.c @@ -63,7 +63,7 @@ void RTC_Initialize(void) { /* Wait for Synchronization */ } - RTC_REGS->MODE0.RTC_COMP = 0x101U; + RTC_REGS->MODE0.RTC_COMP = 0x65U; while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) { /* Wait for Synchronization after writing Compare Value */ diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 7e480796..6f6d72dd 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -383,14 +383,14 @@ bool read_cells_1to6(uint16_t cell_mV[6]) CELL_1_VOLTAGE, CELL_2_VOLTAGE, CELL_3_VOLTAGE, CELL_4_VOLTAGE, CELL_5_VOLTAGE, CELL_6_VOLTAGE }; - uint16_t raw = 0U; + uint16_t raw = 0; uint8_t i; bool ok = true; if (cell_mV == NULL) return false; - for (i = 0U; i < 6U; i++) + for (i = 0; i < 6; i++) { if (bq_direct_command(addr[i], &raw, R)) { @@ -398,7 +398,7 @@ bool read_cells_1to6(uint16_t cell_mV[6]) } else { - cell_mV[i] = 0U; + cell_mV[i] = 0; ok = false; } } @@ -434,18 +434,18 @@ bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC){ void bothoff_init(void) { - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[PIN_BOTHOFF] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRSET = BOTHOFF_PIN_MASK; - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[PIN_BOTHOFF] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); // GPIO mode + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRSET = BOTHOFF_PIN_MASK; // Set as output + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; // Set LOW to turn bothoff ON } void bothoff_high(void) { - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Set HIGH to turn bothoff OFF } void can_wakeup_pin(void){ - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRCLR = (1u << 16U); // Set as input PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] |= PORT_PINCFG_INEN_Msk; // Enable INPUT } diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index 40181802..ffb62619 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -45,7 +45,7 @@ extern volatile bool rxReady; extern uint32_t rx_messageID; extern uint8_t rx_message[64]; extern uint8_t rx_messageLength; -extern uint16_t timestamp; + static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) @@ -69,11 +69,12 @@ int main ( void ) - spi_driver_self_test_run(); + //spi_driver_self_test_run(); bq76942_init(); bms_set_protection_threshold(); bms_battery_status(); + //bms_sample_temps(); @@ -84,6 +85,10 @@ int main ( void ) /* Maintain state machines of all polled MPLAB Harmony modules. */ SYS_Tasks ( ); CAN_voltage_send(); + CAN_bothoff_rx(); + + + } From 1dd75677497e4b36123f724dc895a28d6fc6add1 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 26 Feb 2026 15:53:05 +0100 Subject: [PATCH 26/30] feat: add power mode management and EIC interrupt handling --- .../bms_config_default/components/core.yml | 138 +++++++- .../mcc/bms_config_default/components/eic.yml | 112 ++++++ .../bms_config_default/components/evsys.yml | 145 +++++++- .../mcc/bms_config_default/mcc-config.mc4 | 23 +- .../bms_config/mcc/mcc-manifest-autosave.yml | 2 +- .../mcc/mcc-manifest-generated-success.yml | 2 +- bms/bms/bms_config/src/app/can_facade.c | 2 +- bms/bms/bms_config/src/app/can_telemetry.c | 8 +- bms/bms/bms_config/src/app/pwr_mode.c | 46 +++ bms/bms/bms_config/src/app/pwr_mode.h | 17 + .../src/config/default/definitions.h | 3 +- .../default/harmony-manifest-success.yml | 2 +- .../src/config/default/initialization.c | 6 +- .../src/config/default/interrupts.c | 5 +- .../src/config/default/interrupts.h | 1 + .../default/peripheral/clock/plib_clock.c | 7 + .../config/default/peripheral/eic/plib_eic.c | 187 ++++++++++ .../config/default/peripheral/eic/plib_eic.h | 324 ++++++++++++++++++ .../default/peripheral/nvic/plib_nvic.c | 2 + .../default/peripheral/port/plib_port.c | 2 +- .../default/peripheral/port/plib_port.h | 5 - bms/bms/bms_config/src/main.c | 75 +++- 22 files changed, 1076 insertions(+), 38 deletions(-) create mode 100644 bms/bms/bms_config/mcc/bms_config_default/components/eic.yml create mode 100644 bms/bms/bms_config/src/app/pwr_mode.c create mode 100644 bms/bms/bms_config/src/app/pwr_mode.h create mode 100644 bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.c create mode 100644 bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.h diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml index 8623dcfd..1fe4b287 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/core.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/core.yml @@ -2024,7 +2024,7 @@ data: children: - children: - attributes: - value: GPIO + value: EIC_EXTINT14 type: User type: Values type: String @@ -2035,7 +2035,7 @@ data: - children: - attributes: id: core - value: '0x2' + value: '0x3' type: Dynamic type: Values type: String @@ -2098,7 +2098,7 @@ data: children: - children: - attributes: - value: GPIO + value: A type: User type: Values type: String @@ -2493,6 +2493,138 @@ data: type: Dynamic type: Values type: String + MCLK_APBA_INITIAL_VALUE: + attributes: + id: MCLK_APBA_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0xfff' + type: Dynamic + type: Values + type: String + EIC_CLOCK_FREQUENCY: + attributes: + id: EIC_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_FREQ: + attributes: + id: GCLK_ID_2_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_CHEN: + attributes: + id: GCLK_ID_2_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_CLOCK_ENABLE: + attributes: + id: EIC_CLOCK_ENABLE + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: EIC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_ENABLE: + attributes: + id: NVIC_3_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_ENABLE: + attributes: + id: EIC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_HANDLER_LOCK: + attributes: + id: NVIC_3_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_HANDLER_LOCK: + attributes: + id: EIC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_HANDLER: + attributes: + id: NVIC_3_0_HANDLER + children: + - children: + - attributes: + id: core + value: EIC_InterruptHandler + type: Dynamic + type: Values + type: String + EIC_INTERRUPT_HANDLER: + attributes: + id: EIC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: eic + value: EIC_InterruptHandler + type: Dynamic + type: Values + type: String userData: children: - attributes: diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/eic.yml b/bms/bms/bms_config/mcc/bms_config_default/components/eic.yml new file mode 100644 index 00000000..6af6f4ca --- /dev/null +++ b/bms/bms/bms_config/mcc/bms_config_default/components/eic.yml @@ -0,0 +1,112 @@ +configVersion: 1.0.0 +componentName: eic +coreVersion: 5.8.4 +device: ATSAMC21J18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: eic + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: eic + x: '214' + y: '141' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + EIC_ASYNCH: + attributes: + id: EIC_ASYNCH + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + EIC_CHAN_14: + attributes: + id: EIC_CHAN_14 + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + EIC_CONFIG_FILTEN_14: + attributes: + id: EIC_CONFIG_FILTEN_14 + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + EIC_CONFIG_SENSE_14: + attributes: + id: EIC_CONFIG_SENSE_14 + children: + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + EIC_EXTINTEO: + attributes: + id: EIC_EXTINTEO + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + EIC_INT: + attributes: + id: EIC_INT + children: + - children: + - attributes: + id: eic + value: '16384' + type: Dynamic + type: Values + type: Hex + EIC_INT_14: + attributes: + id: EIC_INT_14 + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml index 26dbf820..e8ae56de 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml +++ b/bms/bms/bms_config/mcc/bms_config_default/components/evsys.yml @@ -27,5 +27,148 @@ data: type: ElementPosition type: ElementPositions type: ComponentGraph - symbols: {} + symbols: + EVSYS_CHANNEL_8_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_8_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_2_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_2_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_3_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_3_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_7_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_7_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_9_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_9_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_6_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_6_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_5_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_5_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_1_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_1_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_4_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_4_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_10_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_10_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_0_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_0_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_11_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_11_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + GENERATOR_EIC_EXTINT_14_ACTIVE: + attributes: + id: GENERATOR_EIC_EXTINT_14_ACTIVE + children: + - children: + - attributes: + id: eic + value: 'false' + type: Dynamic + type: Values + type: Boolean userData: {} diff --git a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 index 512de79c..01cb72e4 100644 --- a/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 +++ b/bms/bms/bms_config/mcc/bms_config_default/mcc-config.mc4 @@ -11,6 +11,7 @@ modules: - cmsis - core - dfp +- eic - evsys - nvmctrl - rtc @@ -22,7 +23,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/ATSAMC21J18A.ld hash: 3fc7dbb63ae72ecd9b52572e4dd84ed79cbd37feb6064cb6d4df6fca301d09af - file: ../src/config/default/definitions.h - hash: 91773b88696c5b4a6431831370c738d56c0f75ee7c3fdd6522ed2982d3dcf4a0 + hash: d814c3f2024226ad1bd15e4cb1560b514300d87d3792ff771248c98f96988aa3 - file: ../src/config/default/device.h hash: e539bb402fa4783d95ccf06235458b2e1fe01207c83c0e046a853e0385d0b6f4 - file: ../src/config/default/device_cache.h @@ -32,11 +33,11 @@ generatedFileHashHistoryMap: - file: ../src/config/default/exceptions.c hash: 42f9da2668e04ccb3473d45b149683a00f80072c6883c7918d6ce93997cd6987 - file: ../src/config/default/initialization.c - hash: 8571cf5ef9bd7b59949eb0ad322d4df2a15f5f75acd03528e8eb29a6ff0426a7 + hash: d6b32c3e1faa9f91aed07b971b98351c4ad5a59bc36f8a68ab5f5a9a506356bb - file: ../src/config/default/interrupts.c - hash: 9c48d638647fdc662b2073aa563426438e910ec20067ccb65cf4a61880390dac + hash: bde411b1d6149bc4939a30d741e49fc273ee8d9842358844f0268e557fdb9642 - file: ../src/config/default/interrupts.h - hash: 7275d94d754366f503520ce86b1690658f7f10875ffac6e8d7ca2d8386b31bf9 + hash: 8e6d99f3318c9e9704bc328a282a7f466dbb01332e75e1cc25d56f98d57866f6 - file: ../src/config/default/libc_syscalls.c hash: 88bb2e34c939601b5b7ad076556e3ee0fcedf388436b8cddb6d6fd3e9d07472f - file: ../src/config/default/peripheral/adc/plib_adc0.c @@ -56,15 +57,19 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/can/plib_can_common.h hash: bbff8462d7871f1cbd6b2746cbb726e4a13cf6a5e6d85d60a67803620a1679ae - file: ../src/config/default/peripheral/clock/plib_clock.c - hash: 55dfd48597fd5a1af3f1a7cf2d201f31f8c41b390c9c487632997e437aa0e39f + hash: 3dd25c946fd4a86db6dea8d4d0a5e1d6c4f5c34018e546acebaae57cce7e9321 - file: ../src/config/default/peripheral/clock/plib_clock.h hash: 01c269741541514e997ef61546f4dbb0e23f66e27c6a957162557f13b4638baf +- file: ../src/config/default/peripheral/eic/plib_eic.c + hash: ce9f3668c2b30aba9fa938255570fe0fe8828164acf4676acc5f0e90dcb9255e +- file: ../src/config/default/peripheral/eic/plib_eic.h + hash: bf5db362f4f8383a31b4615b925474213d956828cbdb08fc0478fc70755c637e - file: ../src/config/default/peripheral/evsys/plib_evsys.c hash: 7bb3bc0d60c4cf18638d76d3dfe9e5b13d2915d09e6a8a7bc4b5faae870c8f48 - file: ../src/config/default/peripheral/evsys/plib_evsys.h hash: f7d08eb8162f271ce1db384c082586a6624e506aa7f502c64c4ab5a1aadac47d - file: ../src/config/default/peripheral/nvic/plib_nvic.c - hash: 01df70e005995a9d644632584b14656ef8c117097045e0284b7b59674f43d009 + hash: 73abb242b2f26909209d8665e213af44796df94792c18a75683a903f521adb98 - file: ../src/config/default/peripheral/nvic/plib_nvic.h hash: 9936ac782115af41003255283fa2f603f4ff2212d16275b7c80ea8d067a9e208 - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -72,9 +77,9 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/nvmctrl/plib_nvmctrl.h hash: a2f572d8ba174971959f4a9319fc61b460c00432512d38e19e28e2dfddf6cde5 - file: ../src/config/default/peripheral/port/plib_port.c - hash: ff6d0b082a519a469666037c53308de446c9bda6a302d82e87366dbfd558c9f5 + hash: 2d9c6828948542679063f7579c2148888607a8c5e3607ce6cd68db789b110fe8 - file: ../src/config/default/peripheral/port/plib_port.h - hash: dafff9b826888261d127ef40721d4e41cd0d67c713eb8f7e0df999847609097a + hash: 495a0672f574968ceb901e5bed8f575ac19725b475c515d56a060ebfe6677f28 - file: ../src/config/default/peripheral/rtc/plib_rtc.h hash: 92e9a13ceda691e011ad7efff84d616e8466f744723f8135850fc171fd53ac3b - file: ../src/config/default/peripheral/rtc/plib_rtc_timer.c @@ -98,7 +103,7 @@ generatedFileHashHistoryMap: - file: ../src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h hash: 3653b66472c558c50f7037a1dd25d2678e9a13aa718f3c53a2195e6f3919ea48 - file: ../src/config/default/pin_configurations.csv - hash: e35ae33fa8f5d966a9cd32cfcd38a19d49456cc68881315a9aeaf3fbdbdf72b3 + hash: 2067cccac656d84bad7040877cae2bfd60afa7d9c61964be52d7a0d2cbb19f9c - file: ../src/config/default/startup_xc32.c hash: e6227d89e36b74af1bc21e00e80b390502c97aaaa65796291f63b2d96cf0678e - file: ../src/config/default/stdio/xc32_monitor.c diff --git a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml index 21fef62d..272c4afb 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-autosave.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-19T11:04:40.702+01:00[Europe/Oslo] +creation_date: 2026-02-26T15:31:44.155+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml index decffc3c..dc87d557 100644 --- a/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml +++ b/bms/bms/bms_config/mcc/mcc-manifest-generated-success.yml @@ -2,7 +2,7 @@ manifest_file_version: 1.0.0 project: bms_config_default -creation_date: 2026-02-19T10:14:36.905+01:00[Europe/Oslo] +creation_date: 2026-02-26T14:19:26.604+01:00[Europe/Oslo] operating_system: Linux mcc_mode: VSCodePlugin mcc_mode_version: Unknown diff --git a/bms/bms/bms_config/src/app/can_facade.c b/bms/bms/bms_config/src/app/can_facade.c index 4279f8f0..206bf865 100644 --- a/bms/bms/bms_config/src/app/can_facade.c +++ b/bms/bms/bms_config/src/app/can_facade.c @@ -55,7 +55,7 @@ STB_OutputEnable(); STB_Clear(); ////////////////////// - CAN_RX_WAKEUP_InputEnable(); + if (!s_ram_bound) { CAN0_MessageRAMConfigSet(s_can_msg_ram); diff --git a/bms/bms/bms_config/src/app/can_telemetry.c b/bms/bms/bms_config/src/app/can_telemetry.c index 96eba08e..9e62afe0 100644 --- a/bms/bms/bms_config/src/app/can_telemetry.c +++ b/bms/bms/bms_config/src/app/can_telemetry.c @@ -1,8 +1,7 @@ #include "app/can_telemetry.h" #include "app/can_facade.h" #include "ic_bms/bms_spi.h" - - +#include "samc21j18a.h" #include #include @@ -12,10 +11,6 @@ extern uint8_t rx_message[64]; extern uint8_t rx_messageLength; - - - - static volatile bool flag_vol_tx = false; static volatile bool flag_temp_tx = false; @@ -105,7 +100,6 @@ void CAN_bothoff_rx(void) bothoff_high(); } - } void CAN_stb_mode(void){ diff --git a/bms/bms/bms_config/src/app/pwr_mode.c b/bms/bms/bms_config/src/app/pwr_mode.c new file mode 100644 index 00000000..188d2dd8 --- /dev/null +++ b/bms/bms/bms_config/src/app/pwr_mode.c @@ -0,0 +1,46 @@ +#include "app/pwr_mode.h" +#include "definitions.h" +#include "sam.h" + +static pwr_mode_state_t g_pwr_state= PWR_MODE_ACTIVE; + + +void pwr_mode_init(void) +{ + pwr_set_idle0(); +} + +void pwr_set_idle0(void) +{ + PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_IDLE0; + + while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != + PM_SLEEPCFG_SLEEPMODE_IDLE0) + { + } +} + +void pwr_set_stb_lowpower(void) +{ + PM_REGS->PM_STDBYCFG = PM_STDBYCFG_VREGSMOD_LP; + PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_STANDBY; + + while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != + PM_SLEEPCFG_SLEEPMODE_STANDBY) + { + } +} + +void pwr_enter_sleep(void) +{ + __WFI(); +} + +void pwr_set_state(pwr_mode_state_t state){ + g_pwr_state = state; +} + +pwr_mode_state_t pwr_get_state(void) +{ + return g_pwr_state; +} diff --git a/bms/bms/bms_config/src/app/pwr_mode.h b/bms/bms/bms_config/src/app/pwr_mode.h new file mode 100644 index 00000000..f0abef31 --- /dev/null +++ b/bms/bms/bms_config/src/app/pwr_mode.h @@ -0,0 +1,17 @@ +#ifndef PWR_MODE_H +#define PWR_MODE_H + +typedef enum{ + PWR_MODE_ACTIVE=0, + PWR_MODE_STANDBY=1 +} pwr_mode_state_t; + +void pwr_mode_init(void); +void pwr_set_idle0(void); +void pwr_set_stb_lowpower(void); +void pwr_enter_sleep(void); + +void pwr_set_state(pwr_mode_state_t state); +pwr_mode_state_t pwr_get_state(void); + +#endif \ No newline at end of file diff --git a/bms/bms/bms_config/src/config/default/definitions.h b/bms/bms/bms_config/src/config/default/definitions.h index 131d0de4..188c6697 100644 --- a/bms/bms/bms_config/src/config/default/definitions.h +++ b/bms/bms/bms_config/src/config/default/definitions.h @@ -51,13 +51,14 @@ #include #include "peripheral/nvmctrl/plib_nvmctrl.h" #include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" -#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" #include "peripheral/evsys/plib_evsys.h" +#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" #include "peripheral/port/plib_port.h" #include "peripheral/clock/plib_clock.h" #include "peripheral/nvic/plib_nvic.h" #include "peripheral/sercom/usart/plib_sercom4_usart.h" #include "peripheral/can/plib_can0.h" +#include "peripheral/eic/plib_eic.h" #include "peripheral/rtc/plib_rtc.h" #include "peripheral/adc/plib_adc0.h" #include "peripheral/adc/plib_adc1.h" diff --git a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml index a8349565..52df3b41 100644 --- a/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml +++ b/bms/bms/bms_config/src/config/default/harmony-manifest-success.yml @@ -4,7 +4,7 @@ project: bms_config_default -creation_date: 2026-02-19T10:14:36.918+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +creation_date: 2026-02-26T14:19:26.607+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime operating_system: Linux mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] mcc_version: v5.6.4 diff --git a/bms/bms/bms_config/src/config/default/initialization.c b/bms/bms/bms_config/src/config/default/initialization.c index 2ee3b0ce..7038cb37 100644 --- a/bms/bms/bms_config/src/config/default/initialization.c +++ b/bms/bms/bms_config/src/config/default/initialization.c @@ -170,14 +170,16 @@ void SYS_Initialize ( void* data ) SERCOM1_I2C_Initialize(); - SERCOM0_SPI_Initialize(); - EVSYS_Initialize(); + SERCOM0_SPI_Initialize(); + SERCOM4_USART_Initialize(); CAN0_Initialize(); + EIC_Initialize(); + RTC_Initialize(); diff --git a/bms/bms/bms_config/src/config/default/interrupts.c b/bms/bms/bms_config/src/config/default/interrupts.c index f9e4cffb..e16a19a3 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.c +++ b/bms/bms/bms_config/src/config/default/interrupts.c @@ -75,14 +75,13 @@ void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(vo } /* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 8.6 deviated 30 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 29 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ /* Device vectors list dummy definition*/ extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SysTick_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void SYSTEM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void WDT_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void EIC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); extern void NVMCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); @@ -130,7 +129,7 @@ const H3DeviceVectors exception_table= .pfnSYSTEM_Handler = SYSTEM_Handler, .pfnWDT_Handler = WDT_Handler, .pfnRTC_Handler = RTC_InterruptHandler, - .pfnEIC_Handler = EIC_Handler, + .pfnEIC_Handler = EIC_InterruptHandler, .pfnFREQM_Handler = FREQM_Handler, .pfnTSENS_Handler = TSENS_Handler, .pfnNVMCTRL_Handler = NVMCTRL_Handler, diff --git a/bms/bms/bms_config/src/config/default/interrupts.h b/bms/bms/bms_config/src/config/default/interrupts.h index a75778b7..c486834d 100644 --- a/bms/bms/bms_config/src/config/default/interrupts.h +++ b/bms/bms/bms_config/src/config/default/interrupts.h @@ -60,6 +60,7 @@ void Reset_Handler (void); void NonMaskableInt_Handler (void); void HardFault_Handler (void); void RTC_InterruptHandler (void); +void EIC_InterruptHandler (void); void SERCOM0_SPI_InterruptHandler (void); void SERCOM1_I2C_InterruptHandler (void); void CAN0_InterruptHandler (void); diff --git a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c index 629f309b..2d02e693 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c +++ b/bms/bms/bms_config/src/config/default/peripheral/clock/plib_clock.c @@ -98,6 +98,13 @@ void CLOCK_Initialize (void) GCLK0_Initialize(); + /* Selection of the Generator and write Lock for EIC */ + GCLK_REGS->GCLK_PCHCTRL[2] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[2] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } /* Selection of the Generator and write Lock for SERCOM0_CORE */ GCLK_REGS->GCLK_PCHCTRL[19] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; diff --git a/bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.c b/bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.c new file mode 100644 index 00000000..791c93c0 --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.c @@ -0,0 +1,187 @@ +/******************************************************************************* + External Interrupt Controller (EIC) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_eic.c + + Summary + Source for EIC peripheral library interface Implementation. + + Description + This file defines the interface to the EIC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_eic.h" +#include "interrupts.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +/* EIC Channel Callback object */ +static volatile EIC_CALLBACK_OBJ eicCallbackObject[EXTINT_COUNT]; + + +void EIC_Initialize (void) +{ + /* Reset all registers in the EIC module to their initial state and + EIC will be disabled. */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_SWRST_Msk; + + while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_SWRST_Msk) == EIC_SYNCBUSY_SWRST_Msk) + { + /* Wait for sync */ + } + + /* EIC is by default clocked by GCLK */ + + /* NMI Control register */ + + /* Interrupt sense type and filter control for EXTINT channels 0 to 7*/ + EIC_REGS->EIC_CONFIG[0] = EIC_CONFIG_SENSE0_NONE | + EIC_CONFIG_SENSE1_NONE | + EIC_CONFIG_SENSE2_NONE | + EIC_CONFIG_SENSE3_NONE | + EIC_CONFIG_SENSE4_NONE | + EIC_CONFIG_SENSE5_NONE | + EIC_CONFIG_SENSE6_NONE | + EIC_CONFIG_SENSE7_NONE ; + + /* Interrupt sense type and filter control for EXTINT channels 8 to 15 */ + EIC_REGS->EIC_CONFIG[1] = EIC_CONFIG_SENSE0_NONE + | EIC_CONFIG_SENSE1_NONE + | EIC_CONFIG_SENSE2_NONE + | EIC_CONFIG_SENSE3_NONE + | EIC_CONFIG_SENSE4_NONE + | EIC_CONFIG_SENSE5_NONE + | EIC_CONFIG_SENSE6_BOTH | EIC_CONFIG_FILTEN6_Msk + | EIC_CONFIG_SENSE7_NONE ; + + + + + + + /* External Interrupt enable*/ + EIC_REGS->EIC_INTENSET = 0x4000U; + + /* Callbacks for enabled interrupts */ + eicCallbackObject[0].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[1].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[2].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[3].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[4].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[5].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[6].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[7].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[8].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[9].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[10].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[11].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[12].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[13].eicPinNo = EIC_PIN_MAX; + eicCallbackObject[14].eicPinNo = EIC_PIN_14; + eicCallbackObject[15].eicPinNo = EIC_PIN_MAX; + /* Enable the EIC */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_ENABLE_Msk; + + while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_ENABLE_Msk) == EIC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for sync */ + } +} + +void EIC_InterruptEnable (EIC_PIN pin) +{ + EIC_REGS->EIC_INTENSET = (1UL << (uint32_t)pin); +} + +void EIC_InterruptDisable (EIC_PIN pin) +{ + EIC_REGS->EIC_INTENCLR = (1UL << (uint32_t)pin); +} + +void EIC_CallbackRegister(EIC_PIN pin, EIC_CALLBACK callback, uintptr_t context) +{ + if (eicCallbackObject[pin].eicPinNo == pin) + { + eicCallbackObject[pin].callback = callback; + + eicCallbackObject[pin].context = context; + } +} + +void __attribute__((used)) EIC_InterruptHandler(void) +{ + uint8_t currentChannel; + uint32_t eicIntFlagStatus; + + /* Find any triggered channels, run associated callback handlers */ + for (currentChannel = 0U; currentChannel < EXTINT_COUNT; currentChannel++) + { + /* Verify if the EXTINT x Interrupt Pin is enabled */ + if (((uint8_t)eicCallbackObject[currentChannel].eicPinNo == currentChannel)) + { + /* Read the interrupt flag status */ + eicIntFlagStatus = EIC_REGS->EIC_INTFLAG & (1UL << currentChannel); + + if (0U != eicIntFlagStatus) + { + /* Find any associated callback entries in the callback table */ + if ((eicCallbackObject[currentChannel].callback != NULL)) + { + uintptr_t context = eicCallbackObject[currentChannel].context; + eicCallbackObject[currentChannel].callback(context); + } + + /* Clear interrupt flag */ + EIC_REGS->EIC_INTFLAG = (1UL << currentChannel); + } + } + } +} + diff --git a/bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.h b/bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.h new file mode 100644 index 00000000..492be05b --- /dev/null +++ b/bms/bms/bms_config/src/config/default/peripheral/eic/plib_eic.h @@ -0,0 +1,324 @@ +/******************************************************************************* External Interrupt Controller (EIC) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_eic.h + + Summary + EIC PLIB Header File. + + Description + This file defines the interface to the EIC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +/* Guards against multiple inclusion */ +#ifndef PLIB_EIC_H +#define PLIB_EIC_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part of it. +*/ + +/* EIC Pin Count */ +#define EXTINT_COUNT (16U) + +// ***************************************************************************** +/* EIC Pins + + Summary: + Identifies the available EIC pins. + + Description: + This enumeration identifies all the available EIC pins. Not all pins will be + implemented in a device. The pins described here are for documentation + purposes only. The MHC will generate this enumeration with the enabled EIC + pins only. The application should not use the constant value that are + assigned to enumeration constants as this may vary between devices. + + Remarks: + None. +*/ + + + /* External Interrupt Controller Pin 14 */ +#define EIC_PIN_14 (14U) + +#define EIC_PIN_MAX (16U) + +typedef uint16_t EIC_PIN; + +// ***************************************************************************** +/* EIC Interrupt Pin Callback Function Pointer Type + + Summary: + Defines the data type and function signature of the EIC peripheral callback + function. + + Description: + This data type defines the function signature for the EIC peripheral + callback function. The EIC peripheral will call back the client's function + with this signature when an interrupt condition has been sensed on the pin. + The EIC library allows the application to register a callback function for + each enabled external interrupt. + + Function: + void (*EIC_CALLBACK)(uintptr_t context ) + + Precondition: + EIC_Initialize must have been called for the given EIC + peripheral instance and EIC_CallbackRegister must have been + called to set the function to be called. + + Parameters: + context - Allows the caller to provide a context value (usually a pointer + to the callers context for multi-instance clients). + + Returns: + None. + + Example: + + + void EIC_Pin0Callback (uintptr_t context) + { + This means an interrupt condition has been sensed on EIC Pin 0. + } + + EIC_CallbackRegister(EIC_PIN_0, EIC_Pin0Callback, 0); + + + Remarks: + None. +*/ + +typedef void (*EIC_CALLBACK) (uintptr_t context); + +typedef struct +{ + /* External Interrupt Pin Callback Handler */ + EIC_CALLBACK callback; + + /* External Interrupt Pin Client context */ + uintptr_t context; + + /* External Interrupt Pin number */ + EIC_PIN eicPinNo; + +} EIC_CALLBACK_OBJ; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +// ***************************************************************************** +/* Function: + void EIC_Initialize (void); + + Summary: + Initializes given instance of EIC peripheral. + + Description: + This function initializes given instance of EIC peripheral of the device + with the values configured in MHC GUI. + + Precondition: + MHC GUI should be configured with the right values. + + Parameters: + None. + + Returns: + None. + + Example: + + EIC_Initialize(); + + + Remarks: + This function should only be called once during system initialization + before any other EIC function is called. +*/ + +void EIC_Initialize (void); + +// ***************************************************************************** +/* Function: + void EIC_InterruptEnable (EIC_PIN pin) + + Summary: + Enables interrupts on a pin. + + Description + This function enables interrupts on an external interrupt pin. + When enabled, the interrupt pin sense will be configured as per the + configuration set in MHC. + + Precondition: + EIC_Initialize() function must have been called for the + associated instance. + + Parameters: + pin - EIC Pin number + + Returns: + None + + Example: + + EIC_Initialize(); + EIC_InterruptEnable(EIC_PIN_3); + + + Remarks: + None. +*/ +void EIC_InterruptEnable (EIC_PIN pin); + +// ***************************************************************************** +/* Function: + void EIC_InterruptDisable (EIC_PIN pin) + + Summary: + Disables interrupts on a pin. + + Description + This function disables interrupts on an external interrupt pin. + + Precondition: + EIC_Initialize() function must have been called for the + associated instance. + + Parameters: + pin - EIC Pin number. + + Returns: + None + + Example: + + EIC_Initialize(); + EIC_InterruptDisable(EIC_PIN_3); + + + Remarks: + None. +*/ + +void EIC_InterruptDisable (EIC_PIN pin); + +// ***************************************************************************** +/* Function: + void EIC_CallbackRegister (EIC_PIN pin, EIC_CALLBACK callback + uintptr_t context); + + Summary: + Registers the function to be called when an interrupt condition has been + sensed on the pin. + + Description + This function registers the callback function to be called when an interrupt + condition has been sensed on the pin. A unique callback function can be + registered for each pin. + + When an interrupt condition has been sensed on the pin, the library will + call the registered callback function and will then clear the interrupt + condition when the callback function exits. + + Precondition: + EIC_Initialize() must have been called first for the associated + instance. + + Parameters: + pin - EIC Pin number + + callback - callback function pointer. Setting this to NULL will disable the + callback feature. + + context - An application defined context value that will be passed to the + callback function. + + Returns: + None. + + Example: + + Refer to the description of the EIC_CALLBACK data type for details on API + usage. + + + Remarks: + Context value can be set to NULL, if not required. +*/ + +void EIC_CallbackRegister(EIC_PIN pin, EIC_CALLBACK callback, uintptr_t context); + + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +#endif /* PLIB_EIC_H */ diff --git a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c index 41b995e8..c24342d4 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c +++ b/bms/bms/bms_config/src/config/default/peripheral/nvic/plib_nvic.c @@ -59,6 +59,8 @@ void NVIC_Initialize( void ) * from within the "Interrupt Manager" of MHC. */ NVIC_SetPriority(RTC_IRQn, 3); NVIC_EnableIRQ(RTC_IRQn); + NVIC_SetPriority(EIC_IRQn, 3); + NVIC_EnableIRQ(EIC_IRQn); NVIC_SetPriority(SERCOM0_IRQn, 3); NVIC_EnableIRQ(SERCOM0_IRQn); NVIC_SetPriority(SERCOM1_IRQn, 3); diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c index 66ffa845..ecc7d1a7 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.c @@ -77,7 +77,7 @@ void PORT_Initialize(void) PORT_REGS->GROUP[0].PORT_PINCFG[8] = 0x1U; PORT_REGS->GROUP[0].PORT_PINCFG[9] = 0x1U; PORT_REGS->GROUP[0].PORT_PINCFG[11] = 0x1U; - PORT_REGS->GROUP[0].PORT_PINCFG[14] = 0x2U; + PORT_REGS->GROUP[0].PORT_PINCFG[14] = 0x3U; PORT_REGS->GROUP[0].PORT_PINCFG[15] = 0x0U; PORT_REGS->GROUP[0].PORT_PINCFG[18] = 0x0U; PORT_REGS->GROUP[0].PORT_PINCFG[19] = 0x0U; diff --git a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h index 6bd561d7..ab43cf51 100644 --- a/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h +++ b/bms/bms/bms_config/src/config/default/peripheral/port/plib_port.h @@ -75,11 +75,6 @@ #define GPIO_PA07_PIN PORT_PIN_PA07 /*** Macros for CAN_RX_WAKEUP pin ***/ -#define CAN_RX_WAKEUP_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 14U)) -#define CAN_RX_WAKEUP_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 14U)) -#define CAN_RX_WAKEUP_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 14U)) -#define CAN_RX_WAKEUP_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 14U)) -#define CAN_RX_WAKEUP_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 14U)) #define CAN_RX_WAKEUP_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 14U)) & 0x01U) #define CAN_RX_WAKEUP_PIN PORT_PIN_PA14 diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index ffb62619..e86faaa0 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -30,12 +30,13 @@ #include "ic_bms/spi_test.h" #include "app/can_facade.h" #include "app/can_telemetry.h" +#include "app/pwr_mode.h" +#include "peripheral/port/plib_port.h" #include #include - // ***************************************************************************** // ***************************************************************************** // Section: Main Entry Point @@ -47,6 +48,17 @@ extern uint8_t rx_message[64]; extern uint8_t rx_messageLength; +static volatile bool can_wake_irq = false; +static uint32_t no_can_ticks=0; +#define STANDBY_TIMEOUT_TICKS 50 + +static void CAN_Wake_EIC_Callback(uintptr_t context) +{ + (void)context; + can_wake_irq = true; +} + + static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) { @@ -61,11 +73,15 @@ int main ( void ) { /* Initialize all modules */ SYS_Initialize ( NULL ); + pwr_mode_init(); CAN_Init(); CAN_telemetry_init(); RTC_Timer32CallbackRegister(TelemetryRtcCb, 0); RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK_CMP0); RTC_Timer32Start(); + EIC_CallbackRegister(EIC_PIN_14, CAN_Wake_EIC_Callback, 0); + EIC_InterruptEnable(EIC_PIN_14); + @@ -80,12 +96,67 @@ int main ( void ) //bms_sample_temps(); - while ( true ) + while ( true ) { /* Maintain state machines of all polled MPLAB Harmony modules. */ SYS_Tasks ( ); CAN_voltage_send(); CAN_bothoff_rx(); + pwr_enter_sleep(); + + switch (pwr_get_state()) + { + case PWR_MODE_ACTIVE: + { + CAN_voltage_send(); + CAN_bothoff_rx(); + if (rxReady || can_wake_irq) + { + no_can_ticks=0; + can_wake_irq=false; + } + else { + no_can_ticks++; + } + + if (no_can_ticks >= STANDBY_TIMEOUT_TICKS) + { + STB_Set(); + pwr_set_stb_lowpower(); + pwr_set_state(PWR_MODE_STANDBY); + + } + break; + } + case PWR_MODE_STANDBY: + { + if (can_wake_irq) + { + can_wake_irq=false; + no_can_ticks=0; + + STB_Clear(); //tranceiver normal mode + pwr_set_idle0(); + CAN_Init(); + pwr_set_state(PWR_MODE_ACTIVE); + } + break; + } + default: + { + no_can_ticks=0; + STB_Clear(); //tranceiver normal mode + pwr_set_idle0(); + pwr_set_state(PWR_MODE_ACTIVE); + break; + } + + + + + } + + From 1471cc062b82cd3ff181580e4f5343194e887e2e Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 5 Mar 2026 15:29:35 +0100 Subject: [PATCH 27/30] feat: added state machine for power management and CAN wake handling, cleaned up main --- bms/bms/bms_config/src/app/can_facade.c | 6 +- bms/bms/bms_config/src/app/can_telemetry.c | 75 ++----------- bms/bms/bms_config/src/app/can_telemetry.h | 3 +- bms/bms/bms_config/src/app/pwr_mode.c | 11 +- bms/bms/bms_config/src/app/state_machine.c | 118 +++++++++++++++++++++ bms/bms/bms_config/src/app/state_machine.h | 9 ++ bms/bms/bms_config/src/ic_bms/bms_spi.c | 28 +++-- bms/bms/bms_config/src/ic_bms/bms_spi.h | 5 +- bms/bms/bms_config/src/main.c | 99 ++--------------- 9 files changed, 180 insertions(+), 174 deletions(-) create mode 100644 bms/bms/bms_config/src/app/state_machine.c create mode 100644 bms/bms/bms_config/src/app/state_machine.h diff --git a/bms/bms/bms_config/src/app/can_facade.c b/bms/bms/bms_config/src/app/can_facade.c index 206bf865..4cf68592 100644 --- a/bms/bms/bms_config/src/app/can_facade.c +++ b/bms/bms/bms_config/src/app/can_facade.c @@ -56,10 +56,10 @@ STB_Clear(); ////////////////////// - if (!s_ram_bound) + if (!s_ram_bound) { - CAN0_MessageRAMConfigSet(s_can_msg_ram); - s_ram_bound = true; + CAN0_MessageRAMConfigSet(s_can_msg_ram); // Bind the CAN message RAM to the driver + s_ram_bound = true; } CAN0_RxCallbackRegister(APP_CAN_Callback, (uintptr_t)NULL, CAN_MSG_ATTR_RX_FIFO0); diff --git a/bms/bms/bms_config/src/app/can_telemetry.c b/bms/bms/bms_config/src/app/can_telemetry.c index 9e62afe0..dfb2ec63 100644 --- a/bms/bms/bms_config/src/app/can_telemetry.c +++ b/bms/bms/bms_config/src/app/can_telemetry.c @@ -5,24 +5,20 @@ #include #include -extern volatile bool rxReady; -extern uint32_t rx_messageID; -extern uint8_t rx_message[64]; -extern uint8_t rx_messageLength; static volatile bool flag_vol_tx = false; static volatile bool flag_temp_tx = false; -void CAN_telemetry_init(void) +void CAN_telemetry_init(void) { - flag_vol_tx = false; + flag_vol_tx = false; // Initialize voltage transmission flag } -void CAN_telemetry_tickISR(void) +void CAN_telemetry_tickISR(void) // Call this function every 100ms from a timer interrupt { flag_vol_tx = true; - flag_temp_tx = true; + flag_temp_tx = true; // Set temperature transmission flag } void CAN_voltage_send(void) @@ -66,10 +62,11 @@ void CAN_temp_send(void) flag_temp_tx = false; - bms_read_ts_temp(TS1_TEMP, &t1_dC); + bms_read_ts_temp(TS1_TEMP, &t1_dC); bms_read_ts_temp(TS2_TEMP, &t2_dC); bms_read_ts_temp(TS3_TEMP, &t3_dC); - + + //Divides temp data into 6 payloads (2 bytes per temp) and sends over CAN payload[0] = (uint8_t)(t1_dC & 0xFF); payload[1] = (uint8_t)((t1_dC >> 8) & 0xFF); payload[2] = (uint8_t)(t2_dC & 0xFF); @@ -86,61 +83,3 @@ void CAN_temp_send(void) } -void CAN_bothoff_rx(void) -{ - - if(!rxReady) - return; - rxReady = false; - - if ((rx_messageID == CAN_ID_BOTHOFF_CMD) && (rx_messageLength > 0) && rx_message[0] == BOTHOFF_CMD_BYTE) - { - - bothoff_init(); - bothoff_high(); - } - -} - -void CAN_stb_mode(void){ - - if(!rxReady) - return; - rxReady = false; - - if(rx_messageID == CAN_STANDBYMODE_ID && rx_messageLength > 0){ - - uint8_t standby_mode = rx_message[0]; - - - switch (standby_mode) { - case 0x00: - // normal operation mode - break; - case 0x01: - // low power standby mode - break; - case 0x02: - // deep sleep mode - break; - default: - // Handle invalid standby mode value - break; - } - } -} - -void CAN_rst(void){ - if(!rxReady) - return; - rxReady = false; - - if(rx_messageID == CAN_RST_MCU && rx_messageLength > 0){ - - uint8_t rst_cmd = rx_message[0]; - - if(rst_cmd == CAN_RST_MCU){ - NVIC_SystemReset(); - } - } -} \ No newline at end of file diff --git a/bms/bms/bms_config/src/app/can_telemetry.h b/bms/bms/bms_config/src/app/can_telemetry.h index 839fda31..ce6bd8a3 100644 --- a/bms/bms/bms_config/src/app/can_telemetry.h +++ b/bms/bms/bms_config/src/app/can_telemetry.h @@ -19,7 +19,8 @@ void CAN_telemetry_init(void); void CAN_telemetry_tickISR(void); // call from timer/RTC callback void CAN_voltage_send(void); // call from main loop -void CAN_bothoff_rx(void); +void CAN_temp_send(void); + #endif diff --git a/bms/bms/bms_config/src/app/pwr_mode.c b/bms/bms/bms_config/src/app/pwr_mode.c index 188d2dd8..80f50126 100644 --- a/bms/bms/bms_config/src/app/pwr_mode.c +++ b/bms/bms/bms_config/src/app/pwr_mode.c @@ -7,11 +7,13 @@ static pwr_mode_state_t g_pwr_state= PWR_MODE_ACTIVE; void pwr_mode_init(void) { + /* Start in the lightest sleep mode */ pwr_set_idle0(); } void pwr_set_idle0(void) { + PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_IDLE0; while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != @@ -22,6 +24,7 @@ void pwr_set_idle0(void) void pwr_set_stb_lowpower(void) { + /* Enter MCU standby; wake-up comes from an enabled interrupt. */ PM_REGS->PM_STDBYCFG = PM_STDBYCFG_VREGSMOD_LP; PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_STANDBY; @@ -33,14 +36,16 @@ void pwr_set_stb_lowpower(void) void pwr_enter_sleep(void) { - __WFI(); + /* Sleep until the next interrupt. */ + __WFI(); // Wait For Interrupt instruction to enter sleep mode + //not sure if correct method } void pwr_set_state(pwr_mode_state_t state){ - g_pwr_state = state; + g_pwr_state = state; // Update the global state variable } pwr_mode_state_t pwr_get_state(void) { - return g_pwr_state; + return g_pwr_state; // Return the current power mode state } diff --git a/bms/bms/bms_config/src/app/state_machine.c b/bms/bms/bms_config/src/app/state_machine.c new file mode 100644 index 00000000..456f7db7 --- /dev/null +++ b/bms/bms/bms_config/src/app/state_machine.c @@ -0,0 +1,118 @@ +#include "app/state_machine.h" + +#include +#include + +#include "definitions.h" +#include "app/can_telemetry.h" +#include "app/pwr_mode.h" +#include "peripheral/port/plib_port.h" +#include "app/can_facade.h" +#include "ic_bms/bms_spi.h" + +extern volatile bool rxReady; +extern uint32_t rx_messageID; +extern uint8_t rx_message[64]; +extern uint8_t rx_messageLength; + +static volatile bool s_can_wake_irq = false; +static volatile uint32_t s_rtc_tick = 0U; +static uint32_t s_last_can_tick = 0U; + +#define STBY_TO_TICKS 6000U + +void sm_init(void) +{ + s_rtc_tick = 0U; + s_last_can_tick = 0U; + s_can_wake_irq = false; +} + +void sm_on_can_wake(void) +{ + s_can_wake_irq = true; +} + +void sm_on_rtc_tick(void) +{ + s_rtc_tick++; +} + +void state_machine(void) +{ + switch (pwr_get_state()) + { + case PWR_MODE_ACTIVE: + { + uint32_t now; + bool can_alive = s_can_wake_irq; + + CAN_voltage_send(); + CAN_temp_send(); + now = s_rtc_tick; + + if (rxReady) + { + uint32_t id = rx_messageID; + uint8_t len = rx_messageLength; + uint8_t b0 = (len > 0U) ? rx_message[0] : 0U; + + rxReady = false; + can_alive = true; + + switch (id) + { + case CAN_ID_BOTHOFF_CMD: + if ((len > 0U) && (b0 == BOTHOFF_CMD_BYTE)) + { + bothoff_high(); + } + break; + + case CAN_RST_MCU: + NVIC_SystemReset(); + break; + + default: + break; + } + } + + if (can_alive) + { + s_last_can_tick = now; + s_can_wake_irq = false; + } + + if ((uint32_t)(now - s_last_can_tick) >= STBY_TO_TICKS) // Check if the time since the last CAN activity exceeds the threshold + { + STB_Set(); + pwr_set_stb_lowpower(); + pwr_set_state(PWR_MODE_STANDBY); + } + break; + } + + case PWR_MODE_STANDBY: + if (s_can_wake_irq) + { + s_can_wake_irq = false; + s_last_can_tick = s_rtc_tick; + + STB_Clear(); + pwr_set_idle0(); + CAN_Init(); + pwr_set_state(PWR_MODE_ACTIVE); + } + break; + + default: + s_last_can_tick = s_rtc_tick; + STB_Clear(); + pwr_set_idle0(); + pwr_set_state(PWR_MODE_ACTIVE); + break; + } + + pwr_enter_sleep(); +} diff --git a/bms/bms/bms_config/src/app/state_machine.h b/bms/bms/bms_config/src/app/state_machine.h new file mode 100644 index 00000000..7ce3cd11 --- /dev/null +++ b/bms/bms/bms_config/src/app/state_machine.h @@ -0,0 +1,9 @@ +#ifndef STATE_MACHINE_H +#define STATE_MACHINE_H + +void sm_init(void); +void state_machine(void); +void sm_on_can_wake(void); +void sm_on_rtc_tick(void); + +#endif diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.c b/bms/bms/bms_config/src/ic_bms/bms_spi.c index 6f6d72dd..05e886a8 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.c +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.c @@ -407,7 +407,8 @@ bool read_cells_1to6(uint16_t cell_mV[6]) -bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC){ +bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC) +{ uint16_t raw; if (temp_dC == 0) @@ -420,33 +421,40 @@ bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC){ return true; } -/* - void bms_sample_temps(void) + +bool bms_read_current(int16_t *current_mA) { - int16_t t1_dC, t2_dC, t3_dC; + uint16_t raw; + + if (current_mA == 0) + return false; + if (!bq_direct_command(CC2_CURRENT, &raw, 'R')) + return false; + + *current_mA = (int16_t)raw; + return true; - bms_read_ts_temp(TS1_TEMP, &t1_dC); - bms_read_ts_temp(TS2_TEMP, &t2_dC); - bms_read_ts_temp(TS3_TEMP, &t3_dC); } -*/ void bothoff_init(void) { PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[PIN_BOTHOFF] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); // GPIO mode PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRSET = BOTHOFF_PIN_MASK; // Set as output - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; // Set LOW to turn bothoff ON + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Safe default: HIGH (bothoff OFF) } void bothoff_high(void) { PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Set HIGH to turn bothoff OFF } +void bothoff_low(void) +{ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; // Set LOW to turn bothoff ON +} void can_wakeup_pin(void){ PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRCLR = (1u << 16U); // Set as input PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] |= PORT_PINCFG_INEN_Msk; // Enable INPUT } - diff --git a/bms/bms/bms_config/src/ic_bms/bms_spi.h b/bms/bms/bms_config/src/ic_bms/bms_spi.h index a4f09062..66c0f907 100644 --- a/bms/bms/bms_config/src/ic_bms/bms_spi.h +++ b/bms/bms/bms_config/src/ic_bms/bms_spi.h @@ -17,6 +17,7 @@ #define CELL_4_VOLTAGE 0x1A #define CELL_5_VOLTAGE 0x1C #define CELL_6_VOLTAGE 0x1E +#define CC2_CURRENT 0x3A /* @@ -63,7 +64,7 @@ #define CUV_THRESHOLD_MV 3000 #define CUV_DELAY_MS 300 -// Addresses +// Threshold Addresses #define COV_THRESHOLD_ADDR 0x9278 #define COV_DELAY_ADDR 0x9279 #define CUV_THRESHOLD_ADDR 0x9275 @@ -97,8 +98,10 @@ void bms_battery_status(void); bool read_cells_1to6(uint16_t cell_mV[6]); void bms_sample_temps(void); bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC); +bool bms_current_read(int16_t *current_userA); void bothoff_init(void); void bothoff_high(void); +void bothoff_low(void); diff --git a/bms/bms/bms_config/src/main.c b/bms/bms/bms_config/src/main.c index e86faaa0..c292dcfe 100644 --- a/bms/bms/bms_config/src/main.c +++ b/bms/bms/bms_config/src/main.c @@ -31,8 +31,8 @@ #include "app/can_facade.h" #include "app/can_telemetry.h" #include "app/pwr_mode.h" +#include "app/state_machine.h" #include "peripheral/port/plib_port.h" - #include #include @@ -42,28 +42,18 @@ // Section: Main Entry Point // ***************************************************************************** // ***************************************************************************** -extern volatile bool rxReady; -extern uint32_t rx_messageID; -extern uint8_t rx_message[64]; -extern uint8_t rx_messageLength; - - -static volatile bool can_wake_irq = false; -static uint32_t no_can_ticks=0; -#define STANDBY_TIMEOUT_TICKS 50 - -static void CAN_Wake_EIC_Callback(uintptr_t context) +static void CAN_Wake_EIC_Callback(uintptr_t context) // called when a CAN wake-up interrupt occurs on EIC pin 14 { (void)context; - can_wake_irq = true; + sm_on_can_wake(); } - -static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) +static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) // called every 100ms by the RTC timer interrupt { (void)intCause; (void)context; + sm_on_rtc_tick(); CAN_telemetry_tickISR(); } @@ -79,87 +69,20 @@ int main ( void ) RTC_Timer32CallbackRegister(TelemetryRtcCb, 0); RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK_CMP0); RTC_Timer32Start(); - EIC_CallbackRegister(EIC_PIN_14, CAN_Wake_EIC_Callback, 0); - EIC_InterruptEnable(EIC_PIN_14); - - + EIC_CallbackRegister(EIC_PIN_14, CAN_Wake_EIC_Callback, 0); + EIC_InterruptEnable(EIC_PIN_14); - //spi_driver_self_test_run(); - bq76942_init(); - bms_set_protection_threshold(); - bms_battery_status(); - - - - //bms_sample_temps(); - + bothoff_init(); + sm_init(); + //bms_battery_status(); while ( true ) { /* Maintain state machines of all polled MPLAB Harmony modules. */ SYS_Tasks ( ); - CAN_voltage_send(); - CAN_bothoff_rx(); - pwr_enter_sleep(); - - switch (pwr_get_state()) - { - case PWR_MODE_ACTIVE: - { - CAN_voltage_send(); - CAN_bothoff_rx(); - if (rxReady || can_wake_irq) - { - no_can_ticks=0; - can_wake_irq=false; - } - else { - no_can_ticks++; - } - - if (no_can_ticks >= STANDBY_TIMEOUT_TICKS) - { - STB_Set(); - pwr_set_stb_lowpower(); - pwr_set_state(PWR_MODE_STANDBY); - - } - break; - } - case PWR_MODE_STANDBY: - { - if (can_wake_irq) - { - can_wake_irq=false; - no_can_ticks=0; - - STB_Clear(); //tranceiver normal mode - pwr_set_idle0(); - CAN_Init(); - pwr_set_state(PWR_MODE_ACTIVE); - } - break; - } - default: - { - no_can_ticks=0; - STB_Clear(); //tranceiver normal mode - pwr_set_idle0(); - pwr_set_state(PWR_MODE_ACTIVE); - break; - } - - - - - } - - - - - + state_machine(); } From 08674fe57ed1ec053eb75067883d9a9d47b48720 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Tue, 10 Mar 2026 17:56:50 +0100 Subject: [PATCH 28/30] feat: mitigation to samc21e18a --- .../components/adc0.yml | 237 + .../components/adc1.yml | 207 + .../components/can0.yml | 526 +++ .../components/cmsis.yml | 24 + .../components/core.yml | 2640 +++++++++++ .../components/dfp.yml | 31 + .../components/eic.yml | 112 + .../components/evsys.yml | 174 + .../components/nvmctrl.yml | 31 + .../components/rtc.yml | 51 + .../components/sercom0.yml | 340 ++ .../components/sercom1.yml | 308 ++ .../components/sercom4.yml | 275 ++ .../components/stdio.yml | 64 + .../bms_config_default.bak0/mcc-config.mc4 | 292 ++ .../bms_config_default/components/can0.yml | 154 + .../bms_config_default/components/core.yml | 3918 +++++++++++++++++ .../mcc/bms_config_default/components/eic.yml | 84 + .../mcc/bms_config_default/components/rtc.yml | 51 + .../bms_config_default/components/sercom0.yml | 340 ++ .../bms_config_default/components/sercom1.yml | 383 ++ .../bms_config_default/components/sercom3.yml | 118 + .../mcc/bms_config_default/mcc-config.mc4 | 86 + .../components/adc0.yml | 237 + .../components/adc1.yml | 207 + .../components/can0.yml | 526 +++ .../components/cmsis.yml | 24 + .../components/core.yml | 2508 +++++++++++ .../components/dfp.yml | 31 + .../components/evsys.yml | 31 + .../components/nvmctrl.yml | 31 + .../components/rtc.yml | 51 + .../components/sercom0.yml | 340 ++ .../components/sercom1.yml | 308 ++ .../components/sercom4.yml | 275 ++ .../components/stdio.yml | 64 + .../bms_config_default_default/mcc-config.mc4 | 287 ++ .../mcc/mcc-manifest-autosave.yml | 21 + .../mcc/mcc-manifest-generated-success.yml | 21 + bms/bms/bms_config_e18a/mcc/mcc.vscode | 11 + bms/bms/bms_config_e18a/src/app/can_facade.c | 82 + bms/bms/bms_config_e18a/src/app/can_facade.h | 37 + .../bms_config_e18a/src/app/can_telemetry.c | 83 + .../bms_config_e18a/src/app/can_telemetry.h | 26 + bms/bms/bms_config_e18a/src/app/pwr_mode.c | 51 + bms/bms/bms_config_e18a/src/app/pwr_mode.h | 17 + .../bms_config_e18a/src/app/state_machine.c | 118 + .../bms_config_e18a/src/app/state_machine.h | 9 + .../src/config/default/ATSAMC21E18A.ld | 241 + .../src/config/default/definitions.h | 147 + .../src/config/default/device.h | 65 + .../src/config/default/device_cache.h | 94 + .../src/config/default/device_vectors.h | 118 + .../src/config/default/exceptions.c | 89 + .../default/harmony-manifest-success.yml | 21 + .../src/config/default/initialization.c | 161 + .../src/config/default/interrupts.c | 160 + .../src/config/default/interrupts.h | 70 + .../src/config/default/libc_syscalls.c | 61 + .../config/default/peripheral/adc/plib_adc0.c | 230 + .../config/default/peripheral/adc/plib_adc0.h | 127 + .../config/default/peripheral/adc/plib_adc1.c | 228 + .../config/default/peripheral/adc/plib_adc1.h | 127 + .../default/peripheral/adc/plib_adc_common.h | 156 + .../config/default/peripheral/can/plib_can0.c | 911 ++++ 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bms/bms/cmake/bms_config_e18a/default/CMakePresets.json diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc0.yml new file mode 100644 index 00000000..5c50ac54 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc0.yml @@ -0,0 +1,237 @@ +configVersion: 1.0.0 +componentName: adc0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc0 + x: '30' + y: '216' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc0 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc0 + value: ADC0_RESRDY_IRQn + type: Dynamic + type: Values + type: String + ADC_CTRLB_PRESCALER: + attributes: + id: ADC_CTRLB_PRESCALER + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + ADC_CTRLC_DIFFMODE: + attributes: + id: ADC_CTRLC_DIFFMODE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + ADC_CONV_TRIGGER: + attributes: + id: ADC_CONV_TRIGGER + children: + - children: + - attributes: + value: SW Trigger + type: User + type: Values + type: Combo + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc1.yml new file mode 100644 index 00000000..b9ebd9ab --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc1.yml @@ -0,0 +1,207 @@ +configVersion: 1.0.0 +componentName: adc1 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc1 + x: '30' + y: '148' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc1 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc1 + value: ADC1_RESRDY_IRQn + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/can0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/can0.yml new file mode 100644 index 00000000..0b56dbc6 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/can0.yml @@ -0,0 +1,526 @@ +configVersion: 1.0.0 +componentName: can0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: can0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: can0 + x: '196' + y: '220' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + NBTP_NBRP: + attributes: + id: NBTP_NBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + - attributes: + value: '3' + type: User + type: Values + type: Integer + NOMINAL_SAMPLE_POINT: + attributes: + id: NOMINAL_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '96.875' + type: Dynamic + - attributes: + value: '75.0' + type: User + type: Values + type: Float + NBTP_TOTAL_TIME_QUANTA: + attributes: + id: NBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG1: + attributes: + id: NBTP_NTSEG1 + children: + - children: + - attributes: + id: can0 + value: '17' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG2: + attributes: + id: NBTP_NTSEG2 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + NBTP_NSJW: + attributes: + id: NBTP_NSJW + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + - attributes: + value: '5' + type: User + type: Values + type: Integer + CALCULATED_NOMINAL_BITRATE: + attributes: + id: CALCULATED_NOMINAL_BITRATE + children: + - children: + - attributes: + id: can0 + value: '500' + type: Dynamic + type: Values + type: Integer + NOMINAL_TIME_QUANTA_PERIOD: + attributes: + id: NOMINAL_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '83.333' + type: Dynamic + type: Values + type: String + CALCULATED_NOMINAL_ERRORRATE: + attributes: + id: CALCULATED_NOMINAL_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + AUTO_NOMINAL_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_NOMINAL_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + DBTP_TOTAL_TIME_QUANTA: + attributes: + id: DBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG1: + attributes: + id: DBTP_DTSEG1 + children: + - children: + - attributes: + id: can0 + value: '17' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG2: + attributes: + id: DBTP_DTSEG2 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + DBTP_DSJW: + attributes: + id: DBTP_DSJW + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + - attributes: + value: '5' + type: User + type: Values + type: Integer + CALCULATED_DATA_BITRATE: + attributes: + id: CALCULATED_DATA_BITRATE + children: + - children: + - attributes: + id: can0 + value: '2000' + type: Dynamic + type: Values + type: Integer + DATA_TIME_QUANTA_PERIOD: + attributes: + id: DATA_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '20.833' + type: Dynamic + type: Values + type: String + CALCULATED_DATA_ERRORRATE: + attributes: + id: CALCULATED_DATA_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + CAN_OPMODE: + attributes: + id: CAN_OPMODE + children: + - children: + - attributes: + value: CAN FD + type: User + type: Values + type: Combo + instHeaderFile: + attributes: + id: instHeaderFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_legacy.h.ftl + type: String + type: Attributes + type: File + sourceFile: + attributes: + id: sourceFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_legacy.c.ftl + type: String + type: Attributes + type: File + INTERRUPT_MODE: + attributes: + id: INTERRUPT_MODE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + DBTP_DBRP: + attributes: + id: DBTP_DBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + - attributes: + value: '0' + type: User + type: Values + type: Integer + DATA_SAMPLE_POINT: + attributes: + id: DATA_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '87.5' + type: Dynamic + - attributes: + value: '75.0' + type: User + type: Values + type: Float + AUTO_DATA_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_DATA_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + DATA_BITRATE: + attributes: + id: DATA_BITRATE + children: + - children: + - attributes: + value: '2000' + type: User + type: Values + type: Integer + NOMINAL_BITRATE: + attributes: + id: NOMINAL_BITRATE + children: + - children: + - attributes: + value: '500' + type: User + type: Values + type: Integer + headerFile: + attributes: + id: headerFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_common_legacy.h + type: String + type: Attributes + type: File + CAN_GENERATE_LEGACY_APIS: + attributes: + id: CAN_GENERATE_LEGACY_APIS + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_WATERMARK: + attributes: + id: RXF0_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + RXF0_ELEMENTS: + attributes: + id: RXF0_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + RXF0_BYTES_CFG: + attributes: + id: RXF0_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + RXF1_USE: + attributes: + id: RXF1_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + RXBUF_USE: + attributes: + id: RXBUF_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + TX_FIFO_WATERMARK: + attributes: + id: TX_FIFO_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + TX_FIFO_ELEMENTS: + attributes: + id: TX_FIFO_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + TX_FIFO_BYTES_CFG: + attributes: + id: TX_FIFO_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + FILTERS_STD_NOMATCH: + attributes: + id: FILTERS_STD_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + FILTERS_EXT_NOMATCH: + attributes: + id: FILTERS_EXT_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + TIMESTAMP_ENABLE: + attributes: + id: TIMESTAMP_ENABLE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_OVERWRITE: + attributes: + id: RXF0_OVERWRITE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/cmsis.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/cmsis.yml new file mode 100644 index 00000000..f9f85905 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/cmsis.yml @@ -0,0 +1,24 @@ +configVersion: 1.0.0 +componentName: cmsis +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: cmsis + type: module + version: '' +- dependencyPackage: '' + name: CMSIS_5 + type: package + version: 5.9.1-dev +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/core.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/core.yml new file mode 100644 index 00000000..d6debb74 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/core.yml @@ -0,0 +1,2640 @@ +configVersion: 1.0.0 +componentName: core +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: core + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: core + x: '80' + y: '4' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC0_CLOCK_ENABLE: + attributes: + id: ADC0_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC0_CLOCK_FREQUENCY: + attributes: + id: ADC0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + CAN0_CLOCK_ENABLE: + attributes: + id: CAN0_CLOCK_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_CLOCK_FREQUENCY: + attributes: + id: CAN0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_22_CHEN: + attributes: + id: GCLK_ID_22_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_22_FREQ: + attributes: + id: GCLK_ID_22_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_25_CHEN: + attributes: + id: GCLK_ID_25_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_25_FREQ: + attributes: + id: GCLK_ID_25_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_26_CHEN: + attributes: + id: GCLK_ID_26_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_26_FREQ: + attributes: + id: GCLK_ID_26_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_33_CHEN: + attributes: + id: GCLK_ID_33_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_33_FREQ: + attributes: + id: GCLK_ID_33_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + MCLK_AHB_INITIAL_VALUE: + attributes: + id: MCLK_AHB_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1dff' + type: Dynamic + type: Values + type: String + MCLK_APBC_INITIAL_VALUE: + attributes: + id: MCLK_APBC_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x60036' + type: Dynamic + type: Values + type: String + NVIC_12_0_ENABLE: + attributes: + id: NVIC_12_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_HANDLER: + attributes: + id: NVIC_12_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM3_Handler + type: Dynamic + type: Values + type: String + NVIC_12_0_HANDLER_LOCK: + attributes: + id: NVIC_12_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_ENABLE: + attributes: + id: NVIC_14_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_HANDLER: + attributes: + id: NVIC_14_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM5_Handler + type: Dynamic + type: Values + type: String + NVIC_14_0_HANDLER_LOCK: + attributes: + id: NVIC_14_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM3_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM3_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM5_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM5_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM5_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM5_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_FREQUENCY: + attributes: + id: ADC1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_FREQ: + attributes: + id: GCLK_ID_34_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_CHEN: + attributes: + id: GCLK_ID_34_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_ENABLE: + attributes: + id: ADC1_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_CLOCK_FREQUENCY: + attributes: + id: CAN1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_FREQ: + attributes: + id: GCLK_ID_27_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_CHEN: + attributes: + id: GCLK_ID_27_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM1_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_FREQ: + attributes: + id: GCLK_ID_20_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_CHEN: + attributes: + id: GCLK_ID_20_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_ENABLE: + attributes: + id: NVIC_10_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER_LOCK: + attributes: + id: NVIC_10_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER: + attributes: + id: NVIC_10_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + CAN1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_16_0_ENABLE: + attributes: + id: NVIC_16_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + NVIC_16_0_HANDLER: + attributes: + id: NVIC_16_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN1_Handler + type: Dynamic + type: Values + type: String + NVIC_16_0_HANDLER_LOCK: + attributes: + id: NVIC_16_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_ENABLE: + attributes: + id: NVIC_15_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE: + attributes: + id: CAN0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_HANDLER: + attributes: + id: NVIC_15_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + CAN0_INTERRUPT_HANDLER: + attributes: + id: CAN0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: can0 + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_15_0_HANDLER_LOCK: + attributes: + id: NVIC_15_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_HANDLER_LOCK: + attributes: + id: CAN0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM4_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_FREQ: + attributes: + id: GCLK_ID_23_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_CHEN: + attributes: + id: GCLK_ID_23_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM4_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_ENABLE: + attributes: + id: NVIC_13_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER_LOCK: + attributes: + id: NVIC_13_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM4_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER: + attributes: + id: NVIC_13_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM4_INTERRUPT_HANDLER: + attributes: + id: SERCOM4_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom4 + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM1_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM1_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER: + attributes: + id: SERCOM1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom1 + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM0_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_FREQ: + attributes: + id: GCLK_ID_19_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_CHEN: + attributes: + id: GCLK_ID_19_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM0_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_ENABLE: + attributes: + id: NVIC_9_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER_LOCK: + attributes: + id: NVIC_9_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER: + attributes: + id: NVIC_9_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_INTERRUPT_HANDLER: + attributes: + id: SERCOM0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom0 + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + PORT_GROUP_1_DIR: + attributes: + id: PORT_GROUP_1_DIR + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_OUT: + attributes: + id: PORT_GROUP_1_OUT + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PINCFG8: + attributes: + id: PORT_GROUP_1_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_8_USED: + attributes: + id: PORT_GROUP_1_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX4: + attributes: + id: PORT_GROUP_1_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_8: + attributes: + id: PORT_GROUP_1_PAD_8 + children: + - children: + - attributes: + id: core + value: PB08 + type: Dynamic + type: Values + type: String + PIN_11_PERIPHERAL_FUNCTION: + attributes: + id: PIN_11_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG5: + attributes: + id: PORT_GROUP_1_PINCFG5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_5_USED: + attributes: + id: PORT_GROUP_1_PIN_5_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX2: + attributes: + id: PORT_GROUP_1_PMUX2 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_5: + attributes: + id: PORT_GROUP_1_PAD_5 + children: + - children: + - attributes: + id: core + value: PB05 + type: Dynamic + type: Values + type: String + PIN_6_PERIPHERAL_FUNCTION: + attributes: + id: PIN_6_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_DIR: + attributes: + id: PORT_GROUP_0_DIR + children: + - children: + - attributes: + id: core + value: '0x100c8080' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_OUT: + attributes: + id: PORT_GROUP_0_OUT + children: + - children: + - attributes: + id: core + value: '0x80' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG1: + attributes: + id: PORT_GROUP_0_PINCFG1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_1_USED: + attributes: + id: PORT_GROUP_0_PIN_1_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX0: + attributes: + id: PORT_GROUP_0_PMUX0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_1: + attributes: + id: PORT_GROUP_0_PAD_1 + children: + - children: + - attributes: + id: core + value: PA01 + type: Dynamic + type: Values + type: String + PIN_2_PERIPHERAL_FUNCTION: + attributes: + id: PIN_2_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG0: + attributes: + id: PORT_GROUP_0_PINCFG0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_0_USED: + attributes: + id: PORT_GROUP_0_PIN_0_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_0: + attributes: + id: PORT_GROUP_0_PAD_0 + children: + - children: + - attributes: + id: core + value: PA00 + type: Dynamic + type: Values + type: String + PIN_1_PERIPHERAL_FUNCTION: + attributes: + id: PIN_1_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG9: + attributes: + id: PORT_GROUP_1_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_9_USED: + attributes: + id: PORT_GROUP_1_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PINCFG3: + attributes: + id: PORT_GROUP_0_PINCFG3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_3_USED: + attributes: + id: PORT_GROUP_0_PIN_3_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX1: + attributes: + id: PORT_GROUP_0_PMUX1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_3: + attributes: + id: PORT_GROUP_0_PAD_3 + children: + - children: + - attributes: + id: core + value: PA03 + type: Dynamic + type: Values + type: String + PIN_4_PERIPHERAL_FUNCTION: + attributes: + id: PIN_4_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_DIR: + attributes: + id: PIN_2_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_PULLEN: + attributes: + id: PIN_2_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_INEN: + attributes: + id: PIN_2_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG6: + attributes: + id: PORT_GROUP_1_PINCFG6 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_6_USED: + attributes: + id: PORT_GROUP_1_PIN_6_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX3: + attributes: + id: PORT_GROUP_1_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_6: + attributes: + id: PORT_GROUP_1_PAD_6 + children: + - children: + - attributes: + id: core + value: PB06 + type: Dynamic + type: Values + type: String + PIN_9_PERIPHERAL_FUNCTION: + attributes: + id: PIN_9_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG7: + attributes: + id: PORT_GROUP_1_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_7_USED: + attributes: + id: PORT_GROUP_1_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PAD_7: + attributes: + id: PORT_GROUP_1_PAD_7 + children: + - children: + - attributes: + id: core + value: PB07 + type: Dynamic + type: Values + type: String + PIN_10_PERIPHERAL_FUNCTION: + attributes: + id: PIN_10_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PAD_9: + attributes: + id: PORT_GROUP_1_PAD_9 + children: + - children: + - attributes: + id: core + value: PB09 + type: Dynamic + type: Values + type: String + PIN_12_PERIPHERAL_FUNCTION: + attributes: + id: PIN_12_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG10: + attributes: + id: PORT_GROUP_0_PINCFG10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_10_USED: + attributes: + id: PORT_GROUP_0_PIN_10_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX5: + attributes: + id: PORT_GROUP_0_PMUX5 + children: + - children: + - attributes: + id: core + value: '0x20' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_10: + attributes: + id: PORT_GROUP_0_PAD_10 + children: + - children: + - attributes: + id: core + value: PA10 + type: Dynamic + type: Values + type: String + PIN_19_PERIPHERAL_FUNCTION: + attributes: + id: PIN_19_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_MODE: + attributes: + id: PIN_16_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_FUNCTION_TYPE: + attributes: + id: PIN_16_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PMUX3: + attributes: + id: PORT_GROUP_0_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_7: + attributes: + id: PORT_GROUP_0_PAD_7 + children: + - children: + - attributes: + id: core + value: PA07 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG7: + attributes: + id: PORT_GROUP_0_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_7_USED: + attributes: + id: PORT_GROUP_0_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_16_PERIPHERAL_FUNCTION: + attributes: + id: PIN_16_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_INEN: + attributes: + id: PIN_16_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_DIR: + attributes: + id: PIN_16_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_16_FUNCTION_NAME: + attributes: + id: PIN_16_FUNCTION_NAME + children: + - children: + - attributes: + value: GPIO_PA07 + type: User + type: Values + type: String + PIN_17_MODE: + attributes: + id: PIN_17_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_17_FUNCTION_TYPE: + attributes: + id: PIN_17_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD0 + type: User + type: Values + type: String + PORT_GROUP_0_PMUX4: + attributes: + id: PORT_GROUP_0_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_8: + attributes: + id: PORT_GROUP_0_PAD_8 + children: + - children: + - attributes: + id: core + value: PA08 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG8: + attributes: + id: PORT_GROUP_0_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_8_USED: + attributes: + id: PORT_GROUP_0_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_17_PERIPHERAL_FUNCTION: + attributes: + id: PIN_17_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_18_MODE: + attributes: + id: PIN_18_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_18_FUNCTION_TYPE: + attributes: + id: PIN_18_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD1 + type: User + type: Values + type: String + PORT_GROUP_0_PAD_9: + attributes: + id: PORT_GROUP_0_PAD_9 + children: + - children: + - attributes: + id: core + value: PA09 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG9: + attributes: + id: PORT_GROUP_0_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_9_USED: + attributes: + id: PORT_GROUP_0_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_18_PERIPHERAL_FUNCTION: + attributes: + id: PIN_18_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG11: + attributes: + id: PORT_GROUP_0_PINCFG11 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_11_USED: + attributes: + id: PORT_GROUP_0_PIN_11_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_11: + attributes: + id: PORT_GROUP_0_PAD_11 + children: + - children: + - attributes: + id: core + value: PA11 + type: Dynamic + type: Values + type: String + PIN_20_PERIPHERAL_FUNCTION: + attributes: + id: PIN_20_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_20_MODE: + attributes: + id: PIN_20_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_20_FUNCTION_TYPE: + attributes: + id: PIN_20_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD3 + type: User + type: Values + type: String + PIN_16_LAT: + attributes: + id: PIN_16_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String + PIN_53_MODE: + attributes: + id: PIN_53_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_FUNCTION_TYPE: + attributes: + id: PIN_53_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG28: + attributes: + id: PORT_GROUP_0_PINCFG28 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_28_USED: + attributes: + id: PORT_GROUP_0_PIN_28_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_53_INEN: + attributes: + id: PIN_53_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_DIR: + attributes: + id: PIN_53_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX14: + attributes: + id: PORT_GROUP_0_PMUX14 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_28: + attributes: + id: PORT_GROUP_0_PAD_28 + children: + - children: + - attributes: + id: core + value: PA28 + type: Dynamic + type: Values + type: String + PIN_53_PERIPHERAL_FUNCTION: + attributes: + id: PIN_53_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_53_FUNCTION_NAME: + attributes: + id: PIN_53_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_G + type: User + type: Values + type: String + PIN_53_DRVSTR: + attributes: + id: PIN_53_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PIN_38_MODE: + attributes: + id: PIN_38_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_FUNCTION_TYPE: + attributes: + id: PIN_38_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG19: + attributes: + id: PORT_GROUP_0_PINCFG19 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_19_USED: + attributes: + id: PORT_GROUP_0_PIN_19_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_38_INEN: + attributes: + id: PIN_38_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_DIR: + attributes: + id: PIN_38_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX9: + attributes: + id: PORT_GROUP_0_PMUX9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_19: + attributes: + id: PORT_GROUP_0_PAD_19 + children: + - children: + - attributes: + id: core + value: PA19 + type: Dynamic + type: Values + type: String + PIN_38_PERIPHERAL_FUNCTION: + attributes: + id: PIN_38_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_38_FUNCTION_NAME: + attributes: + id: PIN_38_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_Y + type: User + type: Values + type: String + PIN_37_MODE: + attributes: + id: PIN_37_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_FUNCTION_TYPE: + attributes: + id: PIN_37_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG18: + attributes: + id: PORT_GROUP_0_PINCFG18 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_18_USED: + attributes: + id: PORT_GROUP_0_PIN_18_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_37_INEN: + attributes: + id: PIN_37_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_DIR: + attributes: + id: PIN_37_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_18: + attributes: + id: PORT_GROUP_0_PAD_18 + children: + - children: + - attributes: + id: core + value: PA18 + type: Dynamic + type: Values + type: String + PIN_37_PERIPHERAL_FUNCTION: + attributes: + id: PIN_37_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_37_FUNCTION_NAME: + attributes: + id: PIN_37_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_R + type: User + type: Values + type: String + PIN_31_MODE: + attributes: + id: PIN_31_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_FUNCTION_TYPE: + attributes: + id: PIN_31_FUNCTION_TYPE + children: + - children: + - attributes: + value: EIC_EXTINT14 + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG14: + attributes: + id: PORT_GROUP_0_PINCFG14 + children: + - children: + - attributes: + id: core + value: '0x3' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_14_USED: + attributes: + id: PORT_GROUP_0_PIN_14_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_31_INEN: + attributes: + id: PIN_31_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_31_DIR: + attributes: + id: PIN_31_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PMUX7: + attributes: + id: PORT_GROUP_0_PMUX7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_14: + attributes: + id: PORT_GROUP_0_PAD_14 + children: + - children: + - attributes: + id: core + value: PA14 + type: Dynamic + type: Values + type: String + PIN_31_PERIPHERAL_FUNCTION: + attributes: + id: PIN_31_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: A + type: User + type: Values + type: String + PIN_31_FUNCTION_NAME: + attributes: + id: PIN_31_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN_RX_WAKEUP + type: User + type: Values + type: String + PIN_32_MODE: + attributes: + id: PIN_32_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_FUNCTION_TYPE: + attributes: + id: PIN_32_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG15: + attributes: + id: PORT_GROUP_0_PINCFG15 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_15_USED: + attributes: + id: PORT_GROUP_0_PIN_15_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_32_INEN: + attributes: + id: PIN_32_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_DIR: + attributes: + id: PIN_32_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_15: + attributes: + id: PORT_GROUP_0_PAD_15 + children: + - children: + - attributes: + id: core + value: PA15 + type: Dynamic + type: Values + type: String + PIN_32_PERIPHERAL_FUNCTION: + attributes: + id: PIN_32_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_32_FUNCTION_NAME: + attributes: + id: PIN_32_FUNCTION_NAME + children: + - children: + - attributes: + value: STB + type: User + type: Values + type: String + PIN_31_PULLEN: + attributes: + id: PIN_31_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_DRVSTR: + attributes: + id: PIN_31_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PORT_GROUP_0_PINCFG21: + attributes: + id: PORT_GROUP_0_PINCFG21 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_21_USED: + attributes: + id: PORT_GROUP_0_PIN_21_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX10: + attributes: + id: PORT_GROUP_0_PMUX10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_21: + attributes: + id: PORT_GROUP_0_PAD_21 + children: + - children: + - attributes: + id: core + value: PA21 + type: Dynamic + type: Values + type: String + PIN_42_PERIPHERAL_FUNCTION: + attributes: + id: PIN_42_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_MODE: + attributes: + id: PIN_45_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_FUNCTION_TYPE: + attributes: + id: PIN_45_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG24: + attributes: + id: PORT_GROUP_0_PINCFG24 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_24_USED: + attributes: + id: PORT_GROUP_0_PIN_24_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX12: + attributes: + id: PORT_GROUP_0_PMUX12 + children: + - children: + - attributes: + id: core + value: '0x66' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_24: + attributes: + id: PORT_GROUP_0_PAD_24 + children: + - children: + - attributes: + id: core + value: PA24 + type: Dynamic + type: Values + type: String + PIN_45_PERIPHERAL_FUNCTION: + attributes: + id: PIN_45_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_46_MODE: + attributes: + id: PIN_46_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_46_FUNCTION_TYPE: + attributes: + id: PIN_46_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PORT_GROUP_0_PAD_25: + attributes: + id: PORT_GROUP_0_PAD_25 + children: + - children: + - attributes: + id: core + value: PA25 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG25: + attributes: + id: PORT_GROUP_0_PINCFG25 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_25_USED: + attributes: + id: PORT_GROUP_0_PIN_25_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_46_PERIPHERAL_FUNCTION: + attributes: + id: PIN_46_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + RTC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: RTC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_ENABLE: + attributes: + id: NVIC_2_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_ENABLE: + attributes: + id: RTC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER_LOCK: + attributes: + id: NVIC_2_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_HANDLER_LOCK: + attributes: + id: RTC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER: + attributes: + id: NVIC_2_0_HANDLER + children: + - children: + - attributes: + id: core + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_HANDLER: + attributes: + id: RTC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: rtc + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + MCLK_APBA_INITIAL_VALUE: + attributes: + id: MCLK_APBA_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0xfff' + type: Dynamic + type: Values + type: String + EIC_CLOCK_FREQUENCY: + attributes: + id: EIC_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_FREQ: + attributes: + id: GCLK_ID_2_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_CHEN: + attributes: + id: GCLK_ID_2_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_CLOCK_ENABLE: + attributes: + id: EIC_CLOCK_ENABLE + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: EIC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_ENABLE: + attributes: + id: NVIC_3_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_ENABLE: + attributes: + id: EIC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_HANDLER_LOCK: + attributes: + id: NVIC_3_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_HANDLER_LOCK: + attributes: + id: EIC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_HANDLER: + attributes: + id: NVIC_3_0_HANDLER + children: + - children: + - attributes: + id: core + value: EIC_InterruptHandler + type: Dynamic + type: Values + type: String + EIC_INTERRUPT_HANDLER: + attributes: + id: EIC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: eic + value: EIC_InterruptHandler + type: Dynamic + type: Values + type: String + userData: + children: + - attributes: + canvasHeight: '0' + canvasWidth: '0' + type: GraphSettings + - children: + - attributes: + id: profile0 + name: Main + type: Profile + type: PowerProfiles + type: UserData diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/dfp.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/dfp.yml new file mode 100644 index 00000000..5feb0638 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/dfp.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: dfp +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: dfp + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: dfp + x: '520' + y: '11' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/eic.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/eic.yml new file mode 100644 index 00000000..78428423 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/eic.yml @@ -0,0 +1,112 @@ +configVersion: 1.0.0 +componentName: eic +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: eic + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: eic + x: '214' + y: '141' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + EIC_ASYNCH: + attributes: + id: EIC_ASYNCH + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + EIC_CHAN_14: + attributes: + id: EIC_CHAN_14 + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + EIC_CONFIG_FILTEN_14: + attributes: + id: EIC_CONFIG_FILTEN_14 + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + EIC_CONFIG_SENSE_14: + attributes: + id: EIC_CONFIG_SENSE_14 + children: + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + EIC_EXTINTEO: + attributes: + id: EIC_EXTINTEO + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + EIC_INT: + attributes: + id: EIC_INT + children: + - children: + - attributes: + id: eic + value: '16384' + type: Dynamic + type: Values + type: Hex + EIC_INT_14: + attributes: + id: EIC_INT_14 + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/evsys.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/evsys.yml new file mode 100644 index 00000000..0a0d68b7 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/evsys.yml @@ -0,0 +1,174 @@ +configVersion: 1.0.0 +componentName: evsys +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: evsys + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: evsys + x: '202' + y: '10' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + EVSYS_CHANNEL_8_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_8_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_2_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_2_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_3_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_3_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_7_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_7_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_9_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_9_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_6_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_6_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_5_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_5_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_1_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_1_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_4_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_4_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_10_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_10_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_0_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_0_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + EVSYS_CHANNEL_11_GENERATOR_ACTIVE: + attributes: + id: EVSYS_CHANNEL_11_GENERATOR_ACTIVE + children: + - children: + - attributes: + id: evsys + value: 'false' + type: Dynamic + type: Values + type: Boolean + GENERATOR_EIC_EXTINT_14_ACTIVE: + attributes: + id: GENERATOR_EIC_EXTINT_14_ACTIVE + children: + - children: + - attributes: + id: eic + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/nvmctrl.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/nvmctrl.yml new file mode 100644 index 00000000..1079fff4 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/nvmctrl.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: nvmctrl +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: nvmctrl + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: nvmctrl + x: '339' + y: '7' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/rtc.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/rtc.yml new file mode 100644 index 00000000..6b2747f8 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/rtc.yml @@ -0,0 +1,51 @@ +configVersion: 1.0.0 +componentName: rtc +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: rtc + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: rtc + x: '496' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + RTC_MODE0_MATCHCLR: + attributes: + id: RTC_MODE0_MATCHCLR + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RTC_MODE0_TIMER_COMPARE: + attributes: + id: RTC_MODE0_TIMER_COMPARE + children: + - children: + - attributes: + value: '101' + type: User + type: Values + type: Hex + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom0.yml new file mode 100644 index 00000000..018fb294 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom0.yml @@ -0,0 +1,340 @@ +configVersion: 1.0.0 +componentName: sercom0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom0 + x: '538' + y: '152' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom0 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SERCOM_SPIM_COMMON_HEADER: + attributes: + id: SERCOM_SPIM_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_HEADER: + attributes: + id: SERCOM_SPIM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_SOURCE: + attributes: + id: SERCOM_SPIM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '23' + type: Dynamic + type: Values + type: Integer + SPI_CLOCK_PHASE: + attributes: + id: SPI_CLOCK_PHASE + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SPI_DIPO: + attributes: + id: SPI_DIPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom0 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom0 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom0 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + SPI_DOPO: + attributes: + id: SPI_DOPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom1.yml new file mode 100644 index 00000000..342a2f30 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom1.yml @@ -0,0 +1,308 @@ +configVersion: 1.0.0 +componentName: sercom1 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom1 + x: '368' + y: '153' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom1 + value: '232' + type: Dynamic + type: Values + type: Hex + I2C_CLOCK_SPEED_HZ: + attributes: + id: I2C_CLOCK_SPEED_HZ + children: + - children: + - attributes: + id: sercom1 + value: '100000' + type: Dynamic + type: Values + type: Integer + I2C_SCLSM: + attributes: + id: I2C_SCLSM + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + SERCOM_I2CM_HEADER: + attributes: + id: SERCOM_I2CM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_MASTER_HEADER: + attributes: + id: SERCOM_I2CM_MASTER_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_SOURCE: + attributes: + id: SERCOM_I2CM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '2' + type: User + type: Values + type: KeyValueSet + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom1 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom1 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom4.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom4.yml new file mode 100644 index 00000000..a1b862a5 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom4.yml @@ -0,0 +1,275 @@ +configVersion: 1.0.0 +componentName: sercom4 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom4 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: SERCOM4_I2C + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_SPI + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: stdio + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: UART + type: String + type: Attributes + type: DirectCapability + type: Attachments + type: sercom4 + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom4 + x: '67' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom4 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_OPERATING_MODE: + attributes: + id: USART_OPERATING_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom4 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/stdio.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/stdio.yml new file mode 100644 index 00000000..5f8be0f2 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/stdio.yml @@ -0,0 +1,64 @@ +configVersion: 1.0.0 +componentName: stdio +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: stdio + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: sercom4 + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: SERCOM4_UART + type: String + type: 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com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: can0 + x: '826' + y: '234' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + CALCULATED_DATA_BITRATE: + attributes: + id: CALCULATED_DATA_BITRATE + children: + - children: + - attributes: + id: can0 + value: '979' + type: Dynamic + type: Values + type: Integer + CALCULATED_DATA_ERRORRATE: + attributes: + id: CALCULATED_DATA_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '95.918' + type: Dynamic + type: Values + type: String + CAN_OPMODE: + attributes: + id: CAN_OPMODE + children: + - children: + - attributes: + value: CAN FD + type: User + type: Values + type: Combo + DATA_TIME_QUANTA_PERIOD: + attributes: + id: DATA_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '20.833' + type: Dynamic + type: Values + type: String + DBTP_DSJW: + attributes: + id: DBTP_DSJW + children: + - children: + - attributes: + id: can0 + value: '8' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG1: + attributes: + id: DBTP_DTSEG1 + children: + - children: + - attributes: + id: can0 + value: '71' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG2: + attributes: + id: DBTP_DTSEG2 + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + DBTP_TOTAL_TIME_QUANTA: + attributes: + id: DBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '49' + type: Dynamic + type: Values + type: Integer + INTERRUPT_MODE: + attributes: + id: INTERRUPT_MODE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + instHeaderFile: + attributes: + id: instHeaderFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_interrupt.h.ftl + type: String + type: Attributes + type: File + sourceFile: + attributes: + id: sourceFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_interrupt.c.ftl + type: String + type: Attributes + type: File + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/core.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/core.yml new file mode 100644 index 00000000..23708017 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/core.yml @@ -0,0 +1,3918 @@ +configVersion: 1.0.0 +componentName: core +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: core + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: core + x: '80' + y: '4' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC0_CLOCK_ENABLE: + attributes: + id: ADC0_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC0_CLOCK_FREQUENCY: + attributes: + id: ADC0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + CAN0_CLOCK_ENABLE: + attributes: + id: CAN0_CLOCK_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_CLOCK_FREQUENCY: + attributes: + id: CAN0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_22_CHEN: + attributes: + id: GCLK_ID_22_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_22_FREQ: + attributes: + id: GCLK_ID_22_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_25_CHEN: + attributes: + id: GCLK_ID_25_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_25_FREQ: + attributes: + id: GCLK_ID_25_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_26_CHEN: + attributes: + id: GCLK_ID_26_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_26_FREQ: + attributes: + id: GCLK_ID_26_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_33_CHEN: + attributes: + id: GCLK_ID_33_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_33_FREQ: + attributes: + id: GCLK_ID_33_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + MCLK_AHB_INITIAL_VALUE: + attributes: + id: MCLK_AHB_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1dff' + type: Dynamic + type: Values + type: String + MCLK_APBC_INITIAL_VALUE: + attributes: + id: MCLK_APBC_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x16' + type: Dynamic + type: Values + type: String + NVIC_12_0_ENABLE: + attributes: + id: NVIC_12_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_HANDLER: + attributes: + id: NVIC_12_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM3_USART_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_12_0_HANDLER_LOCK: + attributes: + id: NVIC_12_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_ENABLE: + attributes: + id: NVIC_14_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_HANDLER: + attributes: + id: NVIC_14_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM5_Handler + type: Dynamic + type: Values + type: String + NVIC_14_0_HANDLER_LOCK: + attributes: + id: NVIC_14_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM3_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + SERCOM3_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM5_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM5_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM5_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM5_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_FREQUENCY: + attributes: + id: ADC1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_FREQ: + attributes: + id: GCLK_ID_34_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_CHEN: + attributes: + id: GCLK_ID_34_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_ENABLE: + attributes: + id: ADC1_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_CLOCK_FREQUENCY: + attributes: + id: CAN1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_FREQ: + attributes: + id: GCLK_ID_27_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_CHEN: + attributes: + id: GCLK_ID_27_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM1_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_FREQ: + attributes: + id: GCLK_ID_20_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_CHEN: + attributes: + id: GCLK_ID_20_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_ENABLE: + attributes: + id: NVIC_10_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER_LOCK: + attributes: + id: NVIC_10_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER: + attributes: + id: NVIC_10_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + CAN1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_16_0_ENABLE: + attributes: + id: NVIC_16_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + NVIC_16_0_HANDLER: + attributes: + id: NVIC_16_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN1_Handler + type: Dynamic + type: Values + type: String + NVIC_16_0_HANDLER_LOCK: + attributes: + id: NVIC_16_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_ENABLE: + attributes: + id: NVIC_15_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE: + attributes: + id: CAN0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_HANDLER: + attributes: + id: NVIC_15_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + CAN0_INTERRUPT_HANDLER: + attributes: + id: CAN0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: can0 + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_15_0_HANDLER_LOCK: + attributes: + id: NVIC_15_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_HANDLER_LOCK: + attributes: + id: CAN0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM4_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_FREQ: + attributes: + id: GCLK_ID_23_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_CHEN: + attributes: + id: GCLK_ID_23_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM4_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_ENABLE: + attributes: + id: NVIC_13_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER_LOCK: + attributes: + id: NVIC_13_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM4_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER: + attributes: + id: NVIC_13_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM4_INTERRUPT_HANDLER: + attributes: + id: SERCOM4_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom4 + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM1_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM1_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER: + attributes: + id: SERCOM1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom1 + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM0_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_FREQ: + attributes: + id: GCLK_ID_19_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_CHEN: + attributes: + id: GCLK_ID_19_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM0_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_ENABLE: + attributes: + id: NVIC_9_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER_LOCK: + attributes: + id: NVIC_9_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER: + attributes: + id: NVIC_9_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_INTERRUPT_HANDLER: + attributes: + id: SERCOM0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom0 + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + PORT_GROUP_1_DIR: + attributes: + id: PORT_GROUP_1_DIR + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_OUT: + attributes: + id: PORT_GROUP_1_OUT + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PINCFG8: + attributes: + id: PORT_GROUP_1_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_8_USED: + attributes: + id: PORT_GROUP_1_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX4: + attributes: + id: PORT_GROUP_1_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_8: + attributes: + id: PORT_GROUP_1_PAD_8 + children: + - children: + - attributes: + id: core + value: PB08 + type: Dynamic + type: Values + type: String + PIN_11_PERIPHERAL_FUNCTION: + attributes: + id: PIN_11_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG5: + attributes: + id: PORT_GROUP_1_PINCFG5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_5_USED: + attributes: + id: PORT_GROUP_1_PIN_5_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX2: + attributes: + id: PORT_GROUP_1_PMUX2 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_5: + attributes: + id: PORT_GROUP_1_PAD_5 + children: + - children: + - attributes: + id: core + value: PB05 + type: Dynamic + type: Values + type: String + PIN_6_PERIPHERAL_FUNCTION: + attributes: + id: PIN_6_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_DIR: + attributes: + id: PORT_GROUP_0_DIR + children: + - children: + - attributes: + id: core + value: '0x4' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_OUT: + attributes: + id: PORT_GROUP_0_OUT + children: + - children: + - attributes: + id: core + value: '0x440' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG1: + attributes: + id: PORT_GROUP_0_PINCFG1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_1_USED: + attributes: + id: PORT_GROUP_0_PIN_1_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX0: + attributes: + id: PORT_GROUP_0_PMUX0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_1: + attributes: + id: PORT_GROUP_0_PAD_1 + children: + - children: + - attributes: + id: core + value: PA01 + type: Dynamic + type: Values + type: String + PIN_2_PERIPHERAL_FUNCTION: + attributes: + id: PIN_2_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG0: + attributes: + id: PORT_GROUP_0_PINCFG0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_0_USED: + attributes: + id: PORT_GROUP_0_PIN_0_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_0: + attributes: + id: PORT_GROUP_0_PAD_0 + children: + - children: + - attributes: + id: core + value: PA00 + type: Dynamic + type: Values + type: String + PIN_1_PERIPHERAL_FUNCTION: + attributes: + id: PIN_1_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG9: + attributes: + id: PORT_GROUP_1_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_9_USED: + attributes: + id: PORT_GROUP_1_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PINCFG3: + attributes: + id: PORT_GROUP_0_PINCFG3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_3_USED: + attributes: + id: PORT_GROUP_0_PIN_3_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX1: + attributes: + id: PORT_GROUP_0_PMUX1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_3: + attributes: + id: PORT_GROUP_0_PAD_3 + children: + - children: + - attributes: + id: core + value: PA03 + type: Dynamic + type: Values + type: String + PIN_4_PERIPHERAL_FUNCTION: + attributes: + id: PIN_4_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_2_DIR: + attributes: + id: PIN_2_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_PULLEN: + attributes: + id: PIN_2_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_INEN: + attributes: + id: PIN_2_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG6: + attributes: + id: PORT_GROUP_1_PINCFG6 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_6_USED: + attributes: + id: PORT_GROUP_1_PIN_6_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX3: + attributes: + id: PORT_GROUP_1_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_6: + attributes: + id: PORT_GROUP_1_PAD_6 + children: + - children: + - attributes: + id: core + value: PB06 + type: Dynamic + type: Values + type: String + PIN_9_PERIPHERAL_FUNCTION: + attributes: + id: PIN_9_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG7: + attributes: + id: PORT_GROUP_1_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_7_USED: + attributes: + id: PORT_GROUP_1_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PAD_7: + attributes: + id: PORT_GROUP_1_PAD_7 + children: + - children: + - attributes: + id: core + value: PB07 + type: Dynamic + type: Values + type: String + PIN_10_PERIPHERAL_FUNCTION: + attributes: + id: PIN_10_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PAD_9: + attributes: + id: PORT_GROUP_1_PAD_9 + children: + - children: + - attributes: + id: core + value: PB09 + type: Dynamic + type: Values + type: String + PIN_12_PERIPHERAL_FUNCTION: + attributes: + id: PIN_12_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG10: + attributes: + id: PORT_GROUP_0_PINCFG10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_10_USED: + attributes: + id: PORT_GROUP_0_PIN_10_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX5: + attributes: + id: PORT_GROUP_0_PMUX5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_10: + attributes: + id: PORT_GROUP_0_PAD_10 + children: + - children: + - attributes: + id: core + value: PA10 + type: Dynamic + type: Values + type: String + PIN_19_PERIPHERAL_FUNCTION: + attributes: + id: PIN_19_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_MODE: + attributes: + id: PIN_16_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_FUNCTION_TYPE: + attributes: + id: PIN_16_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PMUX3: + attributes: + id: PORT_GROUP_0_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x30' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_7: + attributes: + id: PORT_GROUP_0_PAD_7 + children: + - children: + - attributes: + id: core + value: PA07 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG7: + attributes: + id: PORT_GROUP_0_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_7_USED: + attributes: + id: PORT_GROUP_0_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_16_PERIPHERAL_FUNCTION: + attributes: + id: PIN_16_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_INEN: + attributes: + id: PIN_16_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_DIR: + attributes: + id: PIN_16_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_16_FUNCTION_NAME: + attributes: + id: PIN_16_FUNCTION_NAME + children: + - children: + - attributes: + value: STB + type: User + type: Values + type: String + PIN_17_MODE: + attributes: + id: PIN_17_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_17_FUNCTION_TYPE: + attributes: + id: PIN_17_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM1_PAD0 + type: User + type: Values + type: String + PORT_GROUP_0_PMUX4: + attributes: + id: PORT_GROUP_0_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_8: + attributes: + id: PORT_GROUP_0_PAD_8 + children: + - children: + - attributes: + id: core + value: PA08 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG8: + attributes: + id: PORT_GROUP_0_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_8_USED: + attributes: + id: PORT_GROUP_0_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_17_PERIPHERAL_FUNCTION: + attributes: + id: PIN_17_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_18_MODE: + attributes: + id: PIN_18_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_18_FUNCTION_TYPE: + attributes: + id: PIN_18_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM1_PAD1 + type: User + type: Values + type: String + PORT_GROUP_0_PAD_9: + attributes: + id: PORT_GROUP_0_PAD_9 + children: + - children: + - attributes: + id: core + value: PA09 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG9: + attributes: + id: PORT_GROUP_0_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_9_USED: + attributes: + id: PORT_GROUP_0_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_18_PERIPHERAL_FUNCTION: + attributes: + id: PIN_18_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG11: + attributes: + id: PORT_GROUP_0_PINCFG11 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_11_USED: + attributes: + id: PORT_GROUP_0_PIN_11_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_11: + attributes: + id: PORT_GROUP_0_PAD_11 + children: + - children: + - attributes: + id: core + value: PA11 + type: Dynamic + type: Values + type: String + PIN_20_PERIPHERAL_FUNCTION: + attributes: + id: PIN_20_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_20_MODE: + attributes: + id: PIN_20_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_20_FUNCTION_TYPE: + attributes: + id: PIN_20_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_LAT: + attributes: + id: PIN_16_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String + PIN_53_MODE: + attributes: + id: PIN_53_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_FUNCTION_TYPE: + attributes: + id: PIN_53_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG28: + attributes: + id: PORT_GROUP_0_PINCFG28 + children: + - children: + - attributes: + id: core + value: '0x2' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_28_USED: + attributes: + id: PORT_GROUP_0_PIN_28_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_53_INEN: + attributes: + id: PIN_53_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_DIR: + attributes: + id: PIN_53_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX14: + attributes: + id: PORT_GROUP_0_PMUX14 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_28: + attributes: + id: PORT_GROUP_0_PAD_28 + children: + - children: + - attributes: + id: core + value: PA28 + type: Dynamic + type: Values + type: String + PIN_53_PERIPHERAL_FUNCTION: + attributes: + id: PIN_53_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_53_FUNCTION_NAME: + attributes: + id: PIN_53_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_G + type: User + type: Values + type: String + PIN_53_DRVSTR: + attributes: + id: PIN_53_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PIN_38_MODE: + attributes: + id: PIN_38_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_FUNCTION_TYPE: + attributes: + id: PIN_38_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG19: + attributes: + id: PORT_GROUP_0_PINCFG19 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_19_USED: + attributes: + id: PORT_GROUP_0_PIN_19_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_38_INEN: + attributes: + id: PIN_38_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_DIR: + attributes: + id: PIN_38_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX9: + attributes: + id: PORT_GROUP_0_PMUX9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_19: + attributes: + id: PORT_GROUP_0_PAD_19 + children: + - children: + - attributes: + id: core + value: PA19 + type: Dynamic + type: Values + type: String + PIN_38_PERIPHERAL_FUNCTION: + attributes: + id: PIN_38_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_38_FUNCTION_NAME: + attributes: + id: PIN_38_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_Y + type: User + type: Values + type: String + PIN_37_MODE: + attributes: + id: PIN_37_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_FUNCTION_TYPE: + attributes: + id: PIN_37_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG18: + attributes: + id: PORT_GROUP_0_PINCFG18 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_18_USED: + attributes: + id: PORT_GROUP_0_PIN_18_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_37_INEN: + attributes: + id: PIN_37_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_DIR: + attributes: + id: PIN_37_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_18: + attributes: + id: PORT_GROUP_0_PAD_18 + children: + - children: + - attributes: + id: core + value: PA18 + type: Dynamic + type: Values + type: String + PIN_37_PERIPHERAL_FUNCTION: + attributes: + id: PIN_37_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_37_FUNCTION_NAME: + attributes: + id: PIN_37_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_R + type: User + type: Values + type: String + PIN_31_MODE: + attributes: + id: PIN_31_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_FUNCTION_TYPE: + attributes: + id: PIN_31_FUNCTION_TYPE + children: + - children: + - attributes: + value: EIC_EXTINT14 + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG14: + attributes: + id: PORT_GROUP_0_PINCFG14 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_14_USED: + attributes: + id: PORT_GROUP_0_PIN_14_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_31_INEN: + attributes: + id: PIN_31_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_31_DIR: + attributes: + id: PIN_31_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PMUX7: + attributes: + id: PORT_GROUP_0_PMUX7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_14: + attributes: + id: PORT_GROUP_0_PAD_14 + children: + - children: + - attributes: + id: core + value: PA14 + type: Dynamic + type: Values + type: String + PIN_31_PERIPHERAL_FUNCTION: + attributes: + id: PIN_31_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: A + type: User + type: Values + type: String + PIN_31_FUNCTION_NAME: + attributes: + id: PIN_31_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN_RX_WAKEUP + type: User + type: Values + type: String + PIN_32_MODE: + attributes: + id: PIN_32_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_FUNCTION_TYPE: + attributes: + id: PIN_32_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG15: + attributes: + id: PORT_GROUP_0_PINCFG15 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_15_USED: + attributes: + id: PORT_GROUP_0_PIN_15_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_32_INEN: + attributes: + id: PIN_32_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_DIR: + attributes: + id: PIN_32_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_15: + attributes: + id: PORT_GROUP_0_PAD_15 + children: + - children: + - attributes: + id: core + value: PA15 + type: Dynamic + type: Values + type: String + PIN_32_PERIPHERAL_FUNCTION: + attributes: + id: PIN_32_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_32_FUNCTION_NAME: + attributes: + id: PIN_32_FUNCTION_NAME + children: + - children: + - attributes: + value: STB + type: User + type: Values + type: String + PIN_31_PULLEN: + attributes: + id: PIN_31_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_DRVSTR: + attributes: + id: PIN_31_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PORT_GROUP_0_PINCFG21: + attributes: + id: PORT_GROUP_0_PINCFG21 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_21_USED: + attributes: + id: PORT_GROUP_0_PIN_21_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX10: + attributes: + id: PORT_GROUP_0_PMUX10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_21: + attributes: + id: PORT_GROUP_0_PAD_21 + children: + - children: + - attributes: + id: core + value: PA21 + type: Dynamic + type: Values + type: String + PIN_42_PERIPHERAL_FUNCTION: + attributes: + id: PIN_42_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_MODE: + attributes: + id: PIN_45_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_FUNCTION_TYPE: + attributes: + id: PIN_45_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG24: + attributes: + id: PORT_GROUP_0_PINCFG24 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_24_USED: + attributes: + id: PORT_GROUP_0_PIN_24_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX12: + attributes: + id: PORT_GROUP_0_PMUX12 + children: + - children: + - attributes: + id: core + value: '0x66' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_24: + attributes: + id: PORT_GROUP_0_PAD_24 + children: + - children: + - attributes: + id: core + value: PA24 + type: Dynamic + type: Values + type: String + PIN_45_PERIPHERAL_FUNCTION: + attributes: + id: PIN_45_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_46_MODE: + attributes: + id: PIN_46_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_46_FUNCTION_TYPE: + attributes: + id: PIN_46_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PORT_GROUP_0_PAD_25: + attributes: + id: PORT_GROUP_0_PAD_25 + children: + - children: + - attributes: + id: core + value: PA25 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG25: + attributes: + id: PORT_GROUP_0_PINCFG25 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_25_USED: + attributes: + id: PORT_GROUP_0_PIN_25_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_46_PERIPHERAL_FUNCTION: + attributes: + id: PIN_46_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + RTC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: RTC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_ENABLE: + attributes: + id: NVIC_2_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_ENABLE: + attributes: + id: RTC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER_LOCK: + attributes: + id: NVIC_2_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_HANDLER_LOCK: + attributes: + id: RTC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER: + attributes: + id: NVIC_2_0_HANDLER + children: + - children: + - attributes: + id: core + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_HANDLER: + attributes: + id: RTC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: rtc + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + MCLK_APBA_INITIAL_VALUE: + attributes: + id: MCLK_APBA_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0xfff' + type: Dynamic + type: Values + type: String + EIC_CLOCK_FREQUENCY: + attributes: + id: EIC_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_FREQ: + attributes: + id: GCLK_ID_2_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_CHEN: + attributes: + id: GCLK_ID_2_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_CLOCK_ENABLE: + attributes: + id: EIC_CLOCK_ENABLE + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: EIC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_ENABLE: + attributes: + id: NVIC_3_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_ENABLE: + attributes: + id: EIC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: eic + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_HANDLER_LOCK: + attributes: + id: NVIC_3_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + EIC_INTERRUPT_HANDLER_LOCK: + attributes: + id: EIC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: eic + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_3_0_HANDLER: + attributes: + id: NVIC_3_0_HANDLER + children: + - children: + - attributes: + id: core + value: EIC_Handler + type: Dynamic + type: Values + type: String + EIC_INTERRUPT_HANDLER: + attributes: + id: EIC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: eic + value: EIC_Handler + type: Dynamic + type: Values + type: String + SERCOM3_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM3_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_INTERRUPT_ENABLE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM3_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_INTERRUPT_HANDLER: + attributes: + id: SERCOM3_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom3 + value: SERCOM3_USART_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM2_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM2_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_21_FREQ: + attributes: + id: GCLK_ID_21_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_21_CHEN: + attributes: + id: GCLK_ID_21_CHEN + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM2_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM2_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_11_0_ENABLE: + attributes: + id: NVIC_11_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_11_0_HANDLER_LOCK: + attributes: + id: NVIC_11_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + NVIC_11_0_HANDLER: + attributes: + id: NVIC_11_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM2_Handler + type: Dynamic + type: Values + type: String + PIN_13_PERIPHERAL_FUNCTION: + attributes: + id: PIN_13_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_4_MODE: + attributes: + id: PIN_4_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_4_FUNCTION_TYPE: + attributes: + id: PIN_4_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_4_INEN: + attributes: + id: PIN_4_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_4_DIR: + attributes: + id: PIN_4_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_4_FUNCTION_NAME: + attributes: + id: PIN_4_FUNCTION_NAME + children: + - children: + - attributes: + value: RST_SHUT + type: User + type: Values + type: String + PIN_5_MODE: + attributes: + id: PIN_5_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_5_FUNCTION_TYPE: + attributes: + id: PIN_5_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG4: + attributes: + id: PORT_GROUP_0_PINCFG4 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_4_USED: + attributes: + id: PORT_GROUP_0_PIN_4_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_5_INEN: + attributes: + id: PIN_5_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_5_DIR: + attributes: + id: PIN_5_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX2: + attributes: + id: PORT_GROUP_0_PMUX2 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_4: + attributes: + id: PORT_GROUP_0_PAD_4 + children: + - children: + - attributes: + id: core + value: PA04 + type: Dynamic + type: Values + type: String + PIN_5_PERIPHERAL_FUNCTION: + attributes: + id: PIN_5_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_5_FUNCTION_NAME: + attributes: + id: PIN_5_FUNCTION_NAME + children: + - children: + - attributes: + value: DDSG + type: User + type: Values + type: String + PIN_6_MODE: + attributes: + id: PIN_6_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_6_FUNCTION_TYPE: + attributes: + id: PIN_6_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG5: + attributes: + id: PORT_GROUP_0_PINCFG5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_5_USED: + attributes: + id: PORT_GROUP_0_PIN_5_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_6_INEN: + attributes: + id: PIN_6_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_6_DIR: + attributes: + id: PIN_6_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_5: + attributes: + id: PORT_GROUP_0_PAD_5 + children: + - children: + - attributes: + id: core + value: PA05 + type: Dynamic + type: Values + type: String + PIN_6_FUNCTION_NAME: + attributes: + id: PIN_6_FUNCTION_NAME + children: + - children: + - attributes: + value: DCHG + type: User + type: Values + type: String + PIN_7_MODE: + attributes: + id: PIN_7_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_7_FUNCTION_TYPE: + attributes: + id: PIN_7_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG6: + attributes: + id: PORT_GROUP_0_PINCFG6 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_6_USED: + attributes: + id: PORT_GROUP_0_PIN_6_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_7_INEN: + attributes: + id: PIN_7_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_7_DIR: + attributes: + id: PIN_7_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_6: + attributes: + id: PORT_GROUP_0_PAD_6 + children: + - children: + - attributes: + id: core + value: PA06 + type: Dynamic + type: Values + type: String + PIN_7_PERIPHERAL_FUNCTION: + attributes: + id: PIN_7_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_7_FUNCTION_NAME: + attributes: + id: PIN_7_FUNCTION_NAME + children: + - children: + - attributes: + value: BOTHOFF + type: User + type: Values + type: String + PIN_7_LAT: + attributes: + id: PIN_7_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String + PIN_8_MODE: + attributes: + id: PIN_8_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_8_FUNCTION_TYPE: + attributes: + id: PIN_8_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD3 + type: User + type: Values + type: String + PIN_8_PERIPHERAL_FUNCTION: + attributes: + id: PIN_8_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: D + type: User + type: Values + type: String + PIN_8_FUNCTION_NAME: + attributes: + id: PIN_8_FUNCTION_NAME + children: + - children: + - attributes: + value: SCK + type: User + type: Values + type: String + PIN_11_MODE: + attributes: + id: PIN_11_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_11_FUNCTION_TYPE: + attributes: + id: PIN_11_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD0 + type: User + type: Values + type: String + PIN_11_FUNCTION_NAME: + attributes: + id: PIN_11_FUNCTION_NAME + children: + - children: + - attributes: + value: MOSI + type: User + type: Values + type: String + PIN_12_MODE: + attributes: + id: PIN_12_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_12_FUNCTION_TYPE: + attributes: + id: PIN_12_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD1 + type: User + type: Values + type: String + PIN_12_FUNCTION_NAME: + attributes: + id: PIN_12_FUNCTION_NAME + children: + - children: + - attributes: + value: MISO + type: User + type: Values + type: String + PIN_13_MODE: + attributes: + id: PIN_13_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_13_FUNCTION_TYPE: + attributes: + id: PIN_13_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_13_INEN: + attributes: + id: PIN_13_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_13_DIR: + attributes: + id: PIN_13_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_13_FUNCTION_NAME: + attributes: + id: PIN_13_FUNCTION_NAME + children: + - children: + - attributes: + value: CS + type: User + type: Values + type: String + PIN_13_LAT: + attributes: + id: PIN_13_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String + PIN_14_MODE: + attributes: + id: PIN_14_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_14_FUNCTION_TYPE: + attributes: + id: PIN_14_FUNCTION_TYPE + children: + - children: + - attributes: + value: EIC_EXTINT11 + type: User + type: Values + type: String + PIN_14_PERIPHERAL_FUNCTION: + attributes: + id: PIN_14_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: A + type: User + type: Values + type: String + PIN_14_FUNCTION_NAME: + attributes: + id: PIN_14_FUNCTION_NAME + children: + - children: + - attributes: + value: ALERT + type: User + type: Values + type: String + PIN_15_MODE: + attributes: + id: PIN_15_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_15_FUNCTION_TYPE: + attributes: + id: PIN_15_FUNCTION_TYPE + children: + - children: + - attributes: + value: EIC_EXTINT14 + type: User + type: Values + type: String + PIN_15_PERIPHERAL_FUNCTION: + attributes: + id: PIN_15_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: A + type: User + type: Values + type: String + PIN_15_FUNCTION_NAME: + attributes: + id: PIN_15_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN_WAKE + type: User + type: Values + type: String + PORT_GROUP_0_PMUX8: + attributes: + id: PORT_GROUP_0_PMUX8 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_16: + attributes: + id: PORT_GROUP_0_PAD_16 + children: + - children: + - attributes: + id: core + value: PA16 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG16: + attributes: + id: PORT_GROUP_0_PINCFG16 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_16_USED: + attributes: + id: PORT_GROUP_0_PIN_16_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_17_FUNCTION_NAME: + attributes: + id: PIN_17_FUNCTION_NAME + children: + - children: + - attributes: + value: I2C SCL + type: User + type: Values + type: String + PORT_GROUP_0_PAD_17: + attributes: + id: PORT_GROUP_0_PAD_17 + children: + - children: + - attributes: + id: core + value: PA17 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG17: + attributes: + id: PORT_GROUP_0_PINCFG17 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_17_USED: + attributes: + id: PORT_GROUP_0_PIN_17_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_18_FUNCTION_NAME: + attributes: + id: PIN_18_FUNCTION_NAME + children: + - children: + - attributes: + value: I2C SDA + type: User + type: Values + type: String + PIN_19_MODE: + attributes: + id: PIN_19_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_19_FUNCTION_TYPE: + attributes: + id: PIN_19_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_19_INEN: + attributes: + id: PIN_19_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_19_DIR: + attributes: + id: PIN_19_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_19_FUNCTION_NAME: + attributes: + id: PIN_19_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_R + type: User + type: Values + type: String + PIN_20_INEN: + attributes: + id: PIN_20_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_20_DIR: + attributes: + id: PIN_20_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_20_FUNCTION_NAME: + attributes: + id: PIN_20_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_Y + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG22: + attributes: + id: PORT_GROUP_0_PINCFG22 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_22_USED: + attributes: + id: PORT_GROUP_0_PIN_22_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX11: + attributes: + id: PORT_GROUP_0_PMUX11 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_22: + attributes: + id: PORT_GROUP_0_PAD_22 + children: + - children: + - attributes: + id: core + value: PA22 + type: Dynamic + type: Values + type: String + PIN_21_PERIPHERAL_FUNCTION: + attributes: + id: PIN_21_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_27_MODE: + attributes: + id: PIN_27_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_27_FUNCTION_TYPE: + attributes: + id: PIN_27_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_27_INEN: + attributes: + id: PIN_27_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_27_DIR: + attributes: + id: PIN_27_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_27_PERIPHERAL_FUNCTION: + attributes: + id: PIN_27_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_27_FUNCTION_NAME: + attributes: + id: PIN_27_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_G + type: User + type: Values + type: String + PIN_23_MODE: + attributes: + id: PIN_23_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_23_FUNCTION_TYPE: + attributes: + id: PIN_23_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PIN_23_PERIPHERAL_FUNCTION: + attributes: + id: PIN_23_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_24_MODE: + attributes: + id: PIN_24_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_24_FUNCTION_TYPE: + attributes: + id: PIN_24_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PIN_24_PERIPHERAL_FUNCTION: + attributes: + id: PIN_24_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_23_FUNCTION_NAME: + attributes: + id: PIN_23_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PIN_24_FUNCTION_NAME: + attributes: + id: PIN_24_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PIN_21_MODE: + attributes: + id: PIN_21_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_21_FUNCTION_TYPE: + attributes: + id: PIN_21_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM3_PAD0 + type: User + type: Values + type: String + PIN_21_FUNCTION_NAME: + attributes: + id: PIN_21_FUNCTION_NAME + children: + - children: + - attributes: + value: DEBUG_TX + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG23: + attributes: + id: PORT_GROUP_0_PINCFG23 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_23_USED: + attributes: + id: PORT_GROUP_0_PIN_23_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_23: + attributes: + id: PORT_GROUP_0_PAD_23 + children: + - children: + - attributes: + id: core + value: PA23 + type: Dynamic + type: Values + type: String + PIN_22_PERIPHERAL_FUNCTION: + attributes: + id: PIN_22_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_22_MODE: + attributes: + id: PIN_22_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_22_FUNCTION_TYPE: + attributes: + id: PIN_22_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM3_PAD1 + type: User + type: Values + type: String + PIN_22_FUNCTION_NAME: + attributes: + id: PIN_22_FUNCTION_NAME + children: + - children: + - attributes: + value: DEBUD_RX + type: User + type: Values + type: String + PIN_3_MODE: + attributes: + id: PIN_3_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_3_FUNCTION_TYPE: + attributes: + id: PIN_3_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG2: + attributes: + id: PORT_GROUP_0_PINCFG2 + children: + - children: + - attributes: + id: core + value: '0x2' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_2_USED: + attributes: + id: PORT_GROUP_0_PIN_2_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_3_INEN: + attributes: + id: PIN_3_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_3_DIR: + attributes: + id: PIN_3_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_2: + attributes: + id: PORT_GROUP_0_PAD_2 + children: + - children: + - attributes: + id: core + value: PA02 + type: Dynamic + type: Values + type: String + PIN_3_PERIPHERAL_FUNCTION: + attributes: + id: PIN_3_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_3_FUNCTION_NAME: + attributes: + id: PIN_3_FUNCTION_NAME + children: + - children: + - attributes: + value: GPIO_PA02 + type: User + type: Values + type: String + userData: + children: + - attributes: + canvasHeight: '0' + canvasWidth: '0' + type: GraphSettings + - children: + - attributes: + id: profile0 + name: Main + type: Profile + type: PowerProfiles + type: UserData diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/eic.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/eic.yml new file mode 100644 index 00000000..69603549 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/eic.yml @@ -0,0 +1,84 @@ +configVersion: 1.0.0 +componentName: eic +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: eic + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: eic + x: '162' + y: '115' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + EIC_ASYNCH: + attributes: + id: EIC_ASYNCH + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + EIC_CHAN_11: + attributes: + id: EIC_CHAN_11 + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + EIC_CHAN_14: + attributes: + id: EIC_CHAN_14 + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + EIC_EXTINTEO: + attributes: + id: EIC_EXTINTEO + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + EIC_INT: + attributes: + id: EIC_INT + children: + - children: + - attributes: + id: eic + value: '0' + type: Dynamic + type: Values + type: Hex + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/rtc.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/rtc.yml new file mode 100644 index 00000000..9074a38d --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/rtc.yml @@ -0,0 +1,51 @@ +configVersion: 1.0.0 +componentName: rtc +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: rtc + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: rtc + x: '324' + y: '104' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + RTC_MODE0_MATCHCLR: + attributes: + id: RTC_MODE0_MATCHCLR + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RTC_MODE0_TIMER_COMPARE: + attributes: + id: RTC_MODE0_TIMER_COMPARE + children: + - children: + - attributes: + value: '101' + type: User + type: Values + type: Hex + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom0.yml new file mode 100644 index 00000000..d5abd014 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom0.yml @@ -0,0 +1,340 @@ +configVersion: 1.0.0 +componentName: sercom0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom0 + x: '501' + y: '106' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom0 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SERCOM_SPIM_COMMON_HEADER: + attributes: + id: SERCOM_SPIM_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_HEADER: + attributes: + id: SERCOM_SPIM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_SOURCE: + attributes: + id: SERCOM_SPIM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_RATE: + attributes: + id: SPI_BAUD_RATE + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '10000' + type: User + type: Values + type: Integer + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '2399' + type: Dynamic + type: Values + type: Integer + SPI_DIPO: + attributes: + id: SPI_DIPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SPI_DOPO: + attributes: + id: SPI_DOPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom0 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom0 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom0 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom1.yml new file mode 100644 index 00000000..d4fe5a1e --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom1.yml @@ -0,0 +1,383 @@ +configVersion: 1.0.0 +componentName: sercom1 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom1 + x: '662' + y: '106' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom1 + value: '232' + type: Dynamic + type: Values + type: Hex + I2CM_TRISE: + attributes: + id: I2CM_TRISE + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '100' + type: User + type: Values + type: Integer + I2C_CLOCK_SPEED: + attributes: + id: I2C_CLOCK_SPEED + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '100' + type: User + type: Values + type: Integer + I2C_CLOCK_SPEED_HZ: + attributes: + id: I2C_CLOCK_SPEED_HZ + children: + - children: + - attributes: + id: sercom1 + value: '100000' + type: Dynamic + type: Values + type: Integer + I2C_SCLSM: + attributes: + id: I2C_SCLSM + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + SERCOM_I2CM_HEADER: + attributes: + id: SERCOM_I2CM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_MASTER_HEADER: + attributes: + id: SERCOM_I2CM_MASTER_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_SOURCE: + attributes: + id: SERCOM_I2CM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '2' + type: User + type: Values + type: KeyValueSet + SERCOM_SPIM_COMMON_HEADER: + attributes: + id: SERCOM_SPIM_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_HEADER: + attributes: + id: SERCOM_SPIM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_SOURCE: + attributes: + id: SERCOM_SPIM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom1 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom1 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom3.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom3.yml new file mode 100644 index 00000000..1f725209 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom3.yml @@ -0,0 +1,118 @@ +configVersion: 1.0.0 +componentName: sercom3 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom3 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom3 + x: '821' + y: '105' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom3 + value: '232' + type: Dynamic + type: Values + type: Hex + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom3 + value: '23' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom3 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RXPO: + attributes: + id: USART_RXPO + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom3 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom3 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom3 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config_e18a/mcc/bms_config_default/mcc-config.mc4 new file mode 100644 index 00000000..57a73294 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default/mcc-config.mc4 @@ -0,0 +1,86 @@ +configVersion: 1.0.0 +coreVersion: 5.8.4 +spaHostVersion: 1.2.1 +device: ATSAMC21E18A +deviceLibrary: {} +groupModules: [] +modules: +- can0 +- core +- eic +- rtc +- sercom0 +- sercom1 +- sercom3 +generatedFileHashHistoryMap: +- file: ../src/config/default/ATSAMC21E18A.ld + hash: 5a42655e8eb334901d6145e274e46591a41fd72fb421ff7550af273f91a121e4 +- file: ../src/config/default/definitions.h + hash: dcec6b6e7d12e93ac4becb5851fd2f0882fd131de4a80c897e1c9da4b8b410a9 +- file: ../src/config/default/device_cache.h + hash: e2914501b361bbc93a56d6915b1bf4fac00277e61f31fdee87a587bc15dea5b6 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'' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc0 + x: '30' + y: '216' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc0 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc0 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc0 + value: ADC0_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc0 + value: ADC0_RESRDY_IRQn + type: Dynamic + type: Values + type: String + ADC_CTRLB_PRESCALER: + attributes: + id: ADC_CTRLB_PRESCALER + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + ADC_CTRLC_DIFFMODE: + attributes: + id: ADC_CTRLC_DIFFMODE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + ADC_CONV_TRIGGER: + attributes: + id: ADC_CONV_TRIGGER + children: + - children: + - attributes: + value: SW Trigger + type: User + type: Values + type: Combo + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc1.yml new file mode 100644 index 00000000..b9ebd9ab --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc1.yml @@ -0,0 +1,207 @@ +configVersion: 1.0.0 +componentName: adc1 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: adc1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: adc1 + x: '30' + y: '148' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC_CALLBACK_API: + attributes: + id: ADC_CALLBACK_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_CallbackRegister + type: Dynamic + type: Values + type: String + ADC_CHANNEL_SELECT_API: + attributes: + id: ADC_CHANNEL_SELECT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ChannelSelect + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_U: + attributes: + id: ADC_CH_PHASE_U + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN2 + type: Dynamic + type: Values + type: String + ADC_CH_PHASE_V: + attributes: + id: ADC_CH_PHASE_V + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN5 + type: Dynamic + type: Values + type: String + ADC_CH_POT: + attributes: + id: ADC_CH_POT + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_CH_VDC_BUS: + attributes: + id: ADC_CH_VDC_BUS + children: + - children: + - attributes: + id: adc1 + value: ADC_POSINPUT_AIN0 + type: Dynamic + type: Values + type: String + ADC_GET_RESULT_API: + attributes: + id: ADC_GET_RESULT_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionResultGet + type: Dynamic + type: Values + type: String + ADC_GND: + attributes: + id: ADC_GND + children: + - children: + - attributes: + id: adc1 + value: ADC_NEGINPUT_GND + type: Dynamic + type: Values + type: String + ADC_INT_CLEAR_API: + attributes: + id: ADC_INT_CLEAR_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsClear + type: Dynamic + type: Values + type: String + ADC_INT_DISABLE_API: + attributes: + id: ADC_INT_DISABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsDisable + type: Dynamic + type: Values + type: String + ADC_INT_ENABLE_API: + attributes: + id: ADC_INT_ENABLE_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_InterruptsEnable + type: Dynamic + type: Values + type: String + ADC_IS_RESULT_READY_API: + attributes: + id: ADC_IS_RESULT_READY_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStatusGet + type: Dynamic + type: Values + type: String + ADC_START_API: + attributes: + id: ADC_START_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Enable + type: Dynamic + type: Values + type: String + ADC_START_CONV_API: + attributes: + id: ADC_START_CONV_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_ConversionStart + type: Dynamic + type: Values + type: String + ADC_STOP_API: + attributes: + id: ADC_STOP_API + children: + - children: + - attributes: + id: adc1 + value: ADC1_Disable + type: Dynamic + type: Values + type: String + INTERRUPT_ADC_RESULT: + attributes: + id: INTERRUPT_ADC_RESULT + children: + - children: + - attributes: + id: adc1 + value: ADC1_RESRDY_IRQn + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/can0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/can0.yml new file mode 100644 index 00000000..0b56dbc6 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/can0.yml @@ -0,0 +1,526 @@ +configVersion: 1.0.0 +componentName: can0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: can0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: can0 + x: '196' + y: '220' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + NBTP_NBRP: + attributes: + id: NBTP_NBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + - attributes: + value: '3' + type: User + type: Values + type: Integer + NOMINAL_SAMPLE_POINT: + attributes: + id: NOMINAL_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '96.875' + type: Dynamic + - attributes: + value: '75.0' + type: User + type: Values + type: Float + NBTP_TOTAL_TIME_QUANTA: + attributes: + id: NBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG1: + attributes: + id: NBTP_NTSEG1 + children: + - children: + - attributes: + id: can0 + value: '17' + type: Dynamic + type: Values + type: Integer + NBTP_NTSEG2: + attributes: + id: NBTP_NTSEG2 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + NBTP_NSJW: + attributes: + id: NBTP_NSJW + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + - attributes: + value: '5' + type: User + type: Values + type: Integer + CALCULATED_NOMINAL_BITRATE: + attributes: + id: CALCULATED_NOMINAL_BITRATE + children: + - children: + - attributes: + id: can0 + value: '500' + type: Dynamic + type: Values + type: Integer + NOMINAL_TIME_QUANTA_PERIOD: + attributes: + id: NOMINAL_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '83.333' + type: Dynamic + type: Values + type: String + CALCULATED_NOMINAL_ERRORRATE: + attributes: + id: CALCULATED_NOMINAL_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + AUTO_NOMINAL_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_NOMINAL_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + DBTP_TOTAL_TIME_QUANTA: + attributes: + id: DBTP_TOTAL_TIME_QUANTA + children: + - children: + - attributes: + id: can0 + value: '24' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG1: + attributes: + id: DBTP_DTSEG1 + children: + - children: + - attributes: + id: can0 + value: '17' + type: Dynamic + type: Values + type: Integer + DBTP_DTSEG2: + attributes: + id: DBTP_DTSEG2 + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + type: Values + type: Integer + DBTP_DSJW: + attributes: + id: DBTP_DSJW + children: + - children: + - attributes: + id: can0 + value: '6' + type: Dynamic + - attributes: + value: '5' + type: User + type: Values + type: Integer + CALCULATED_DATA_BITRATE: + attributes: + id: CALCULATED_DATA_BITRATE + children: + - children: + - attributes: + id: can0 + value: '2000' + type: Dynamic + type: Values + type: Integer + DATA_TIME_QUANTA_PERIOD: + attributes: + id: DATA_TIME_QUANTA_PERIOD + children: + - children: + - attributes: + id: can0 + value: '20.833' + type: Dynamic + type: Values + type: String + CALCULATED_DATA_ERRORRATE: + attributes: + id: CALCULATED_DATA_ERRORRATE + children: + - children: + - attributes: + id: can0 + value: '0.000' + type: Dynamic + type: Values + type: String + CAN_OPMODE: + attributes: + id: CAN_OPMODE + children: + - children: + - attributes: + value: CAN FD + type: User + type: Values + type: Combo + instHeaderFile: + attributes: + id: instHeaderFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_legacy.h.ftl + type: String + type: Attributes + type: File + sourceFile: + attributes: + id: sourceFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_legacy.c.ftl + type: String + type: Attributes + type: File + INTERRUPT_MODE: + attributes: + id: INTERRUPT_MODE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + DBTP_DBRP: + attributes: + id: DBTP_DBRP + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '2' + type: Dynamic + - attributes: + value: '0' + type: User + type: Values + type: Integer + DATA_SAMPLE_POINT: + attributes: + id: DATA_SAMPLE_POINT + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + - children: + - attributes: + id: can0 + value: '87.5' + type: Dynamic + - attributes: + value: '75.0' + type: User + type: Values + type: Float + AUTO_DATA_BIT_TIMING_CALCULATION: + attributes: + id: AUTO_DATA_BIT_TIMING_CALCULATION + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + DATA_BITRATE: + attributes: + id: DATA_BITRATE + children: + - children: + - attributes: + value: '2000' + type: User + type: Values + type: Integer + NOMINAL_BITRATE: + attributes: + id: NOMINAL_BITRATE + children: + - children: + - attributes: + value: '500' + type: User + type: Values + type: Integer + headerFile: + attributes: + id: headerFile + children: + - children: + - attributes: + id: source + children: + - type: Value + value: ../peripheral/can_u2003/templates/plib_can_common_legacy.h + type: String + type: Attributes + type: File + CAN_GENERATE_LEGACY_APIS: + attributes: + id: CAN_GENERATE_LEGACY_APIS + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_WATERMARK: + attributes: + id: RXF0_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + RXF0_ELEMENTS: + attributes: + id: RXF0_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + RXF0_BYTES_CFG: + attributes: + id: RXF0_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + RXF1_USE: + attributes: + id: RXF1_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + RXBUF_USE: + attributes: + id: RXBUF_USE + children: + - children: + - attributes: + value: 'false' + type: User + type: Values + type: Boolean + TX_FIFO_WATERMARK: + attributes: + id: TX_FIFO_WATERMARK + children: + - children: + - attributes: + id: can0 + value: '0' + type: Dynamic + type: Values + type: Integer + TX_FIFO_ELEMENTS: + attributes: + id: TX_FIFO_ELEMENTS + children: + - children: + - attributes: + value: '8' + type: User + type: Values + type: Integer + TX_FIFO_BYTES_CFG: + attributes: + id: TX_FIFO_BYTES_CFG + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '7' + type: User + type: Values + type: KeyValueSet + FILTERS_STD_NOMATCH: + attributes: + id: FILTERS_STD_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + FILTERS_EXT_NOMATCH: + attributes: + id: FILTERS_EXT_NOMATCH + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + TIMESTAMP_ENABLE: + attributes: + id: TIMESTAMP_ENABLE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RXF0_OVERWRITE: + attributes: + id: RXF0_OVERWRITE + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/cmsis.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/cmsis.yml new file mode 100644 index 00000000..f9f85905 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/cmsis.yml @@ -0,0 +1,24 @@ +configVersion: 1.0.0 +componentName: cmsis +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: cmsis + type: module + version: '' +- dependencyPackage: '' + name: CMSIS_5 + type: package + version: 5.9.1-dev +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/core.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/core.yml new file mode 100644 index 00000000..9c2cfa8e --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/core.yml @@ -0,0 +1,2508 @@ +configVersion: 1.0.0 +componentName: core +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: core + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: core + x: '80' + y: '4' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + ADC0_CLOCK_ENABLE: + attributes: + id: ADC0_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC0_CLOCK_FREQUENCY: + attributes: + id: ADC0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + CAN0_CLOCK_ENABLE: + attributes: + id: CAN0_CLOCK_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_CLOCK_FREQUENCY: + attributes: + id: CAN0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_22_CHEN: + attributes: + id: GCLK_ID_22_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_22_FREQ: + attributes: + id: GCLK_ID_22_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_25_CHEN: + attributes: + id: GCLK_ID_25_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_25_FREQ: + attributes: + id: GCLK_ID_25_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_26_CHEN: + attributes: + id: GCLK_ID_26_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_26_FREQ: + attributes: + id: GCLK_ID_26_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_33_CHEN: + attributes: + id: GCLK_ID_33_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_33_FREQ: + attributes: + id: GCLK_ID_33_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + MCLK_AHB_INITIAL_VALUE: + attributes: + id: MCLK_AHB_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1dff' + type: Dynamic + type: Values + type: String + MCLK_APBC_INITIAL_VALUE: + attributes: + id: MCLK_APBC_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x60036' + type: Dynamic + type: Values + type: String + NVIC_12_0_ENABLE: + attributes: + id: NVIC_12_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_HANDLER: + attributes: + id: NVIC_12_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM3_Handler + type: Dynamic + type: Values + type: String + NVIC_12_0_HANDLER_LOCK: + attributes: + id: NVIC_12_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_ENABLE: + attributes: + id: NVIC_14_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_14_0_HANDLER: + attributes: + id: NVIC_14_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM5_Handler + type: Dynamic + type: Values + type: String + NVIC_14_0_HANDLER_LOCK: + attributes: + id: NVIC_14_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM3_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM3_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM5_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM5_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + SERCOM5_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM5_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_FREQUENCY: + attributes: + id: ADC1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_FREQ: + attributes: + id: GCLK_ID_34_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_34_CHEN: + attributes: + id: GCLK_ID_34_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + ADC1_CLOCK_ENABLE: + attributes: + id: ADC1_CLOCK_ENABLE + children: + - children: + - attributes: + id: adc1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN1_CLOCK_FREQUENCY: + attributes: + id: CAN1_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_FREQ: + attributes: + id: GCLK_ID_27_FREQ + children: + - children: + - attributes: + id: core + value: '0' + type: Dynamic + type: Values + type: Integer + GCLK_ID_27_CHEN: + attributes: + id: GCLK_ID_27_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM1_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_FREQ: + attributes: + id: GCLK_ID_20_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_CHEN: + attributes: + id: GCLK_ID_20_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_ENABLE: + attributes: + id: NVIC_10_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER_LOCK: + attributes: + id: NVIC_10_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER: + attributes: + id: NVIC_10_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + CAN1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_16_0_ENABLE: + attributes: + id: NVIC_16_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + NVIC_16_0_HANDLER: + attributes: + id: NVIC_16_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN1_Handler + type: Dynamic + type: Values + type: String + NVIC_16_0_HANDLER_LOCK: + attributes: + id: NVIC_16_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: CAN0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_ENABLE: + attributes: + id: NVIC_15_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_ENABLE: + attributes: + id: CAN0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_15_0_HANDLER: + attributes: + id: NVIC_15_0_HANDLER + children: + - children: + - attributes: + id: core + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + CAN0_INTERRUPT_HANDLER: + attributes: + id: CAN0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: can0 + value: CAN0_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_15_0_HANDLER_LOCK: + attributes: + id: NVIC_15_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_INTERRUPT_HANDLER_LOCK: + attributes: + id: CAN0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM4_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_FREQ: + attributes: + id: GCLK_ID_23_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_23_CHEN: + attributes: + id: GCLK_ID_23_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM4_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_ENABLE: + attributes: + id: NVIC_13_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_ENABLE: + attributes: + id: SERCOM4_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER_LOCK: + attributes: + id: NVIC_13_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM4_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM4_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_13_0_HANDLER: + attributes: + id: NVIC_13_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM4_INTERRUPT_HANDLER: + attributes: + id: SERCOM4_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom4 + value: SERCOM4_Handler + type: Dynamic + type: Values + type: String + SERCOM1_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM1_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER: + attributes: + id: SERCOM1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom1 + value: SERCOM1_I2C_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM0_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_FREQ: + attributes: + id: GCLK_ID_19_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_CHEN: + attributes: + id: GCLK_ID_19_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM0_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_ENABLE: + attributes: + id: NVIC_9_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER_LOCK: + attributes: + id: NVIC_9_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER: + attributes: + id: NVIC_9_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_INTERRUPT_HANDLER: + attributes: + id: SERCOM0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom0 + value: SERCOM0_SPI_InterruptHandler + type: Dynamic + type: Values + type: String + PORT_GROUP_1_DIR: + attributes: + id: PORT_GROUP_1_DIR + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_OUT: + attributes: + id: PORT_GROUP_1_OUT + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PINCFG8: + attributes: + id: PORT_GROUP_1_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_8_USED: + attributes: + id: PORT_GROUP_1_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX4: + attributes: + id: PORT_GROUP_1_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_8: + attributes: + id: PORT_GROUP_1_PAD_8 + children: + - children: + - attributes: + id: core + value: PB08 + type: Dynamic + type: Values + type: String + PIN_11_PERIPHERAL_FUNCTION: + attributes: + id: PIN_11_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG5: + attributes: + id: PORT_GROUP_1_PINCFG5 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_5_USED: + attributes: + id: PORT_GROUP_1_PIN_5_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX2: + attributes: + id: PORT_GROUP_1_PMUX2 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_5: + attributes: + id: PORT_GROUP_1_PAD_5 + children: + - children: + - attributes: + id: core + value: PB05 + type: Dynamic + type: Values + type: String + PIN_6_PERIPHERAL_FUNCTION: + attributes: + id: PIN_6_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_DIR: + attributes: + id: PORT_GROUP_0_DIR + children: + - children: + - attributes: + id: core + value: '0x100c8080' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_OUT: + attributes: + id: PORT_GROUP_0_OUT + children: + - children: + - attributes: + id: core + value: '0x80' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG1: + attributes: + id: PORT_GROUP_0_PINCFG1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_1_USED: + attributes: + id: PORT_GROUP_0_PIN_1_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX0: + attributes: + id: PORT_GROUP_0_PMUX0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_1: + attributes: + id: PORT_GROUP_0_PAD_1 + children: + - children: + - attributes: + id: core + value: PA01 + type: Dynamic + type: Values + type: String + PIN_2_PERIPHERAL_FUNCTION: + attributes: + id: PIN_2_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG0: + attributes: + id: PORT_GROUP_0_PINCFG0 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_0_USED: + attributes: + id: PORT_GROUP_0_PIN_0_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_0: + attributes: + id: PORT_GROUP_0_PAD_0 + children: + - children: + - attributes: + id: core + value: PA00 + type: Dynamic + type: Values + type: String + PIN_1_PERIPHERAL_FUNCTION: + attributes: + id: PIN_1_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG9: + attributes: + id: PORT_GROUP_1_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_9_USED: + attributes: + id: PORT_GROUP_1_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PINCFG3: + attributes: + id: PORT_GROUP_0_PINCFG3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_3_USED: + attributes: + id: PORT_GROUP_0_PIN_3_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX1: + attributes: + id: PORT_GROUP_0_PMUX1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_3: + attributes: + id: PORT_GROUP_0_PAD_3 + children: + - children: + - attributes: + id: core + value: PA03 + type: Dynamic + type: Values + type: String + PIN_4_PERIPHERAL_FUNCTION: + attributes: + id: PIN_4_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_DIR: + attributes: + id: PIN_2_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_PULLEN: + attributes: + id: PIN_2_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_2_INEN: + attributes: + id: PIN_2_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG6: + attributes: + id: PORT_GROUP_1_PINCFG6 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_6_USED: + attributes: + id: PORT_GROUP_1_PIN_6_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PMUX3: + attributes: + id: PORT_GROUP_1_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PAD_6: + attributes: + id: PORT_GROUP_1_PAD_6 + children: + - children: + - attributes: + id: core + value: PB06 + type: Dynamic + type: Values + type: String + PIN_9_PERIPHERAL_FUNCTION: + attributes: + id: PIN_9_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PINCFG7: + attributes: + id: PORT_GROUP_1_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_1_PIN_7_USED: + attributes: + id: PORT_GROUP_1_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_1_PAD_7: + attributes: + id: PORT_GROUP_1_PAD_7 + children: + - children: + - attributes: + id: core + value: PB07 + type: Dynamic + type: Values + type: String + PIN_10_PERIPHERAL_FUNCTION: + attributes: + id: PIN_10_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_1_PAD_9: + attributes: + id: PORT_GROUP_1_PAD_9 + children: + - children: + - attributes: + id: core + value: PB09 + type: Dynamic + type: Values + type: String + PIN_12_PERIPHERAL_FUNCTION: + attributes: + id: PIN_12_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG10: + attributes: + id: PORT_GROUP_0_PINCFG10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_10_USED: + attributes: + id: PORT_GROUP_0_PIN_10_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX5: + attributes: + id: PORT_GROUP_0_PMUX5 + children: + - children: + - attributes: + id: core + value: '0x20' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_10: + attributes: + id: PORT_GROUP_0_PAD_10 + children: + - children: + - attributes: + id: core + value: PA10 + type: Dynamic + type: Values + type: String + PIN_19_PERIPHERAL_FUNCTION: + attributes: + id: PIN_19_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_MODE: + attributes: + id: PIN_16_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_FUNCTION_TYPE: + attributes: + id: PIN_16_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PMUX3: + attributes: + id: PORT_GROUP_0_PMUX3 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_7: + attributes: + id: PORT_GROUP_0_PAD_7 + children: + - children: + - attributes: + id: core + value: PA07 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG7: + attributes: + id: PORT_GROUP_0_PINCFG7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_7_USED: + attributes: + id: PORT_GROUP_0_PIN_7_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_16_PERIPHERAL_FUNCTION: + attributes: + id: PIN_16_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_16_INEN: + attributes: + id: PIN_16_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_16_DIR: + attributes: + id: PIN_16_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_16_FUNCTION_NAME: + attributes: + id: PIN_16_FUNCTION_NAME + children: + - children: + - attributes: + value: GPIO_PA07 + type: User + type: Values + type: String + PIN_17_MODE: + attributes: + id: PIN_17_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_17_FUNCTION_TYPE: + attributes: + id: PIN_17_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD0 + type: User + type: Values + type: String + PORT_GROUP_0_PMUX4: + attributes: + id: PORT_GROUP_0_PMUX4 + children: + - children: + - attributes: + id: core + value: '0x22' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_8: + attributes: + id: PORT_GROUP_0_PAD_8 + children: + - children: + - attributes: + id: core + value: PA08 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG8: + attributes: + id: PORT_GROUP_0_PINCFG8 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_8_USED: + attributes: + id: PORT_GROUP_0_PIN_8_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_17_PERIPHERAL_FUNCTION: + attributes: + id: PIN_17_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_18_MODE: + attributes: + id: PIN_18_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_18_FUNCTION_TYPE: + attributes: + id: PIN_18_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD1 + type: User + type: Values + type: String + PORT_GROUP_0_PAD_9: + attributes: + id: PORT_GROUP_0_PAD_9 + children: + - children: + - attributes: + id: core + value: PA09 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG9: + attributes: + id: PORT_GROUP_0_PINCFG9 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_9_USED: + attributes: + id: PORT_GROUP_0_PIN_9_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_18_PERIPHERAL_FUNCTION: + attributes: + id: PIN_18_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG11: + attributes: + id: PORT_GROUP_0_PINCFG11 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_11_USED: + attributes: + id: PORT_GROUP_0_PIN_11_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PAD_11: + attributes: + id: PORT_GROUP_0_PAD_11 + children: + - children: + - attributes: + id: core + value: PA11 + type: Dynamic + type: Values + type: String + PIN_20_PERIPHERAL_FUNCTION: + attributes: + id: PIN_20_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: C + type: User + type: Values + type: String + PIN_20_MODE: + attributes: + id: PIN_20_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_20_FUNCTION_TYPE: + attributes: + id: PIN_20_FUNCTION_TYPE + children: + - children: + - attributes: + value: SERCOM0_PAD3 + type: User + type: Values + type: String + PIN_16_LAT: + attributes: + id: PIN_16_LAT + children: + - children: + - attributes: + value: High + type: User + type: Values + type: String + PIN_53_MODE: + attributes: + id: PIN_53_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_FUNCTION_TYPE: + attributes: + id: PIN_53_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG28: + attributes: + id: PORT_GROUP_0_PINCFG28 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_28_USED: + attributes: + id: PORT_GROUP_0_PIN_28_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_53_INEN: + attributes: + id: PIN_53_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_53_DIR: + attributes: + id: PIN_53_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX14: + attributes: + id: PORT_GROUP_0_PMUX14 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_28: + attributes: + id: PORT_GROUP_0_PAD_28 + children: + - children: + - attributes: + id: core + value: PA28 + type: Dynamic + type: Values + type: String + PIN_53_PERIPHERAL_FUNCTION: + attributes: + id: PIN_53_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_53_FUNCTION_NAME: + attributes: + id: PIN_53_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_G + type: User + type: Values + type: String + PIN_53_DRVSTR: + attributes: + id: PIN_53_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PIN_38_MODE: + attributes: + id: PIN_38_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_FUNCTION_TYPE: + attributes: + id: PIN_38_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG19: + attributes: + id: PORT_GROUP_0_PINCFG19 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_19_USED: + attributes: + id: PORT_GROUP_0_PIN_19_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_38_INEN: + attributes: + id: PIN_38_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_38_DIR: + attributes: + id: PIN_38_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PMUX9: + attributes: + id: PORT_GROUP_0_PMUX9 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_19: + attributes: + id: PORT_GROUP_0_PAD_19 + children: + - children: + - attributes: + id: core + value: PA19 + type: Dynamic + type: Values + type: String + PIN_38_PERIPHERAL_FUNCTION: + attributes: + id: PIN_38_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_38_FUNCTION_NAME: + attributes: + id: PIN_38_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_Y + type: User + type: Values + type: String + PIN_37_MODE: + attributes: + id: PIN_37_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_FUNCTION_TYPE: + attributes: + id: PIN_37_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG18: + attributes: + id: PORT_GROUP_0_PINCFG18 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_18_USED: + attributes: + id: PORT_GROUP_0_PIN_18_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_37_INEN: + attributes: + id: PIN_37_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_37_DIR: + attributes: + id: PIN_37_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_18: + attributes: + id: PORT_GROUP_0_PAD_18 + children: + - children: + - attributes: + id: core + value: PA18 + type: Dynamic + type: Values + type: String + PIN_37_PERIPHERAL_FUNCTION: + attributes: + id: PIN_37_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_37_FUNCTION_NAME: + attributes: + id: PIN_37_FUNCTION_NAME + children: + - children: + - attributes: + value: LED_R + type: User + type: Values + type: String + PIN_31_MODE: + attributes: + id: PIN_31_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_FUNCTION_TYPE: + attributes: + id: PIN_31_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG14: + attributes: + id: PORT_GROUP_0_PINCFG14 + children: + - children: + - attributes: + id: core + value: '0x2' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_14_USED: + attributes: + id: PORT_GROUP_0_PIN_14_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_31_INEN: + attributes: + id: PIN_31_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_31_DIR: + attributes: + id: PIN_31_DIR + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PORT_GROUP_0_PMUX7: + attributes: + id: PORT_GROUP_0_PMUX7 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_14: + attributes: + id: PORT_GROUP_0_PAD_14 + children: + - children: + - attributes: + id: core + value: PA14 + type: Dynamic + type: Values + type: String + PIN_31_PERIPHERAL_FUNCTION: + attributes: + id: PIN_31_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_31_FUNCTION_NAME: + attributes: + id: PIN_31_FUNCTION_NAME + children: + - children: + - attributes: + value: CAN_RX_WAKEUP + type: User + type: Values + type: String + PIN_32_MODE: + attributes: + id: PIN_32_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_FUNCTION_TYPE: + attributes: + id: PIN_32_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG15: + attributes: + id: PORT_GROUP_0_PINCFG15 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_15_USED: + attributes: + id: PORT_GROUP_0_PIN_15_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_32_INEN: + attributes: + id: PIN_32_INEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_32_DIR: + attributes: + id: PIN_32_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PORT_GROUP_0_PAD_15: + attributes: + id: PORT_GROUP_0_PAD_15 + children: + - children: + - attributes: + id: core + value: PA15 + type: Dynamic + type: Values + type: String + PIN_32_PERIPHERAL_FUNCTION: + attributes: + id: PIN_32_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_32_FUNCTION_NAME: + attributes: + id: PIN_32_FUNCTION_NAME + children: + - children: + - attributes: + value: STB + type: User + type: Values + type: String + PIN_31_PULLEN: + attributes: + id: PIN_31_PULLEN + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_31_DRVSTR: + attributes: + id: PIN_31_DRVSTR + children: + - children: + - attributes: + value: '0' + type: User + type: Values + type: KeyValueSet + PORT_GROUP_0_PINCFG21: + attributes: + id: PORT_GROUP_0_PINCFG21 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_21_USED: + attributes: + id: PORT_GROUP_0_PIN_21_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX10: + attributes: + id: PORT_GROUP_0_PMUX10 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_21: + attributes: + id: PORT_GROUP_0_PAD_21 + children: + - children: + - attributes: + id: core + value: PA21 + type: Dynamic + type: Values + type: String + PIN_42_PERIPHERAL_FUNCTION: + attributes: + id: PIN_42_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_MODE: + attributes: + id: PIN_45_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_45_FUNCTION_TYPE: + attributes: + id: PIN_45_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_TX + type: User + type: Values + type: String + PORT_GROUP_0_PINCFG24: + attributes: + id: PORT_GROUP_0_PINCFG24 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_24_USED: + attributes: + id: PORT_GROUP_0_PIN_24_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX12: + attributes: + id: PORT_GROUP_0_PMUX12 + children: + - children: + - attributes: + id: core + value: '0x66' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_24: + attributes: + id: PORT_GROUP_0_PAD_24 + children: + - children: + - attributes: + id: core + value: PA24 + type: Dynamic + type: Values + type: String + PIN_45_PERIPHERAL_FUNCTION: + attributes: + id: PIN_45_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + PIN_46_MODE: + attributes: + id: PIN_46_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_46_FUNCTION_TYPE: + attributes: + id: PIN_46_FUNCTION_TYPE + children: + - children: + - attributes: + value: CAN0_RX + type: User + type: Values + type: String + PORT_GROUP_0_PAD_25: + attributes: + id: PORT_GROUP_0_PAD_25 + children: + - children: + - attributes: + id: core + value: PA25 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG25: + attributes: + id: PORT_GROUP_0_PINCFG25 + children: + - children: + - attributes: + id: core + value: '0x1' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_25_USED: + attributes: + id: PORT_GROUP_0_PIN_25_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_46_PERIPHERAL_FUNCTION: + attributes: + id: PIN_46_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: G + type: User + type: Values + type: String + RTC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: RTC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_ENABLE: + attributes: + id: NVIC_2_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_ENABLE: + attributes: + id: RTC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER_LOCK: + attributes: + id: NVIC_2_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_HANDLER_LOCK: + attributes: + id: RTC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER: + attributes: + id: NVIC_2_0_HANDLER + children: + - children: + - attributes: + id: core + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_HANDLER: + attributes: + id: RTC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: rtc + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + userData: + children: + - attributes: + canvasHeight: '0' + canvasWidth: '0' + type: GraphSettings + - children: + - attributes: + id: profile0 + name: Main + type: Profile + type: PowerProfiles + type: UserData diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/dfp.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/dfp.yml new file mode 100644 index 00000000..5feb0638 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/dfp.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: dfp +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: dfp + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: dfp + x: '520' + y: '11' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/evsys.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/evsys.yml new file mode 100644 index 00000000..a2ae033c --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/evsys.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: evsys +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: evsys + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: evsys + x: '202' + y: '10' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/nvmctrl.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/nvmctrl.yml new file mode 100644 index 00000000..1079fff4 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/nvmctrl.yml @@ -0,0 +1,31 @@ +configVersion: 1.0.0 +componentName: nvmctrl +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: nvmctrl + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: nvmctrl + x: '339' + y: '7' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: {} + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/rtc.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/rtc.yml new file mode 100644 index 00000000..cae31175 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/rtc.yml @@ -0,0 +1,51 @@ +configVersion: 1.0.0 +componentName: rtc +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: rtc + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: rtc + x: '496' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + RTC_MODE0_MATCHCLR: + attributes: + id: RTC_MODE0_MATCHCLR + children: + - children: + - attributes: + value: 'true' + type: User + type: Values + type: Boolean + RTC_MODE0_TIMER_COMPARE: + attributes: + id: RTC_MODE0_TIMER_COMPARE + children: + - children: + - attributes: + value: '257' + type: User + type: Values + type: Hex + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom0.yml new file mode 100644 index 00000000..018fb294 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom0.yml @@ -0,0 +1,340 @@ +configVersion: 1.0.0 +componentName: sercom0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom0 + x: '538' + y: '152' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom0 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SERCOM_SPIM_COMMON_HEADER: + attributes: + id: SERCOM_SPIM_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_HEADER: + attributes: + id: SERCOM_SPIM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_SPIM_SOURCE: + attributes: + id: SERCOM_SPIM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '23' + type: Dynamic + type: Values + type: Integer + SPI_CLOCK_PHASE: + attributes: + id: SPI_CLOCK_PHASE + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + SPI_DIPO: + attributes: + id: SPI_DIPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '1' + type: User + type: Values + type: KeyValueSet + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom0 + value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom0 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom0 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom0 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + SPI_DOPO: + attributes: + id: SPI_DOPO + children: + - children: + - attributes: + id: visible + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + value: '3' + type: User + type: Values + type: KeyValueSet + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom1.yml new file mode 100644 index 00000000..342a2f30 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom1.yml @@ -0,0 +1,308 @@ +configVersion: 1.0.0 +componentName: sercom1 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom1 + x: '368' + y: '153' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom1 + value: '232' + type: Dynamic + type: Values + type: Hex + I2C_CLOCK_SPEED_HZ: + attributes: + id: I2C_CLOCK_SPEED_HZ + children: + - children: + - attributes: + id: sercom1 + value: '100000' + type: Dynamic + type: Values + type: Integer + I2C_SCLSM: + attributes: + id: I2C_SCLSM + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + SERCOM_I2CM_HEADER: + attributes: + id: SERCOM_I2CM_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_MASTER_HEADER: + attributes: + id: SERCOM_I2CM_MASTER_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_I2CM_SOURCE: + attributes: + id: SERCOM_I2CM_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + value: '2' + type: User + type: Values + type: KeyValueSet + SERCOM_USART_7816_HEADER: + attributes: + id: SERCOM_USART_7816_HEADER + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_7816_SOURCE: + attributes: + id: SERCOM_USART_7816_SOURCE + children: + - children: + - attributes: + id: source + children: + - type: Value + type: String + type: Attributes + type: File + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom1 + value: '' + type: Dynamic + type: Values + type: String + USART_7816_BAUD_VALUE: + attributes: + id: USART_7816_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '14' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_DATA_BITS: + attributes: + id: USART_DATA_BITS + children: + - children: + - attributes: + id: sercom1 + value: DRV_USART_DATA_8_BIT + type: Dynamic + type: Values + type: String + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom1 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom4.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom4.yml new file mode 100644 index 00000000..a1b862a5 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom4.yml @@ -0,0 +1,275 @@ +configVersion: 1.0.0 +componentName: sercom4 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom4 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: SERCOM4_I2C + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_SPI + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'false' + type: Boolean + type: Attributes + type: DirectCapability + - attributes: + id: SERCOM4_UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: stdio + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: UART + type: String + type: Attributes + type: DirectCapability + type: Attachments + type: sercom4 + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom4 + x: '67' + y: '340' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom4 + value: '232' + type: Dynamic + type: Values + type: Hex + RECEIVE_DATA_REGISTER: + attributes: + id: RECEIVE_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + SERCOM_MODE: + attributes: + id: SERCOM_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + SERCOM_USART_COMMON_HEADER: + attributes: + id: SERCOM_USART_COMMON_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_HEADER: + attributes: + id: SERCOM_USART_HEADER + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SERCOM_USART_SOURCE: + attributes: + id: SERCOM_USART_SOURCE + children: + - children: + - attributes: + id: enabled + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + type: File + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '23' + type: Dynamic + type: Values + type: Integer + TRANSMIT_DATA_REGISTER: + attributes: + id: TRANSMIT_DATA_REGISTER + children: + - children: + - attributes: + id: sercom4 + value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' + type: Dynamic + type: Values + type: String + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom4 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_INTERRUPT_MODE_ENABLE: + attributes: + id: USART_INTERRUPT_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom4 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_OPERATING_MODE: + attributes: + id: USART_OPERATING_MODE + children: + - children: + - attributes: + id: readOnly + children: + - type: Value + value: 'true' + type: Boolean + type: Attributes + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: KeyValueSet + USART_RING_BUFFER_MODE_ENABLE: + attributes: + id: USART_RING_BUFFER_MODE_ENABLE + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom4 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom4 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom4 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/stdio.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/stdio.yml new file mode 100644 index 00000000..5f8be0f2 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/stdio.yml @@ -0,0 +1,64 @@ +configVersion: 1.0.0 +componentName: stdio +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: stdio + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: + children: + - children: + - attributes: + id: UART + children: + - children: + - attributes: + id: targetComponentID + children: + - type: Value + value: sercom4 + type: String + - attributes: + id: targetAttachmentID + children: + - type: Value + value: SERCOM4_UART + type: String + type: Attributes + type: DirectDependency + type: Attachments + type: stdio + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: stdio + x: '307' + y: '339' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + DEBUG_PERIPHERAL: + attributes: + id: DEBUG_PERIPHERAL + children: + - children: + - attributes: + id: stdio + value: sercom4 + type: Dynamic + type: Values + type: String + userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/mcc-config.mc4 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f28119adbc81fb0e3c957c9aebe8fb423ad93634e76ead3caa2b0818d2e123ae +- file: ../src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h + hash: 8cda7ac3ff6f0eb5e83c4fe613dd195151b24da54167f5c3c007e599a03f1edc +- file: ../src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h + hash: a19e24c136145b4c72630d0ab7c83a7aef010f3ba165e34c56a05057a2d9fed5 +- file: ../src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h + hash: de1b5eb9ed566527b66dc06f4ecb6a43ab6800f7dac47e87c9cb42984dca41bb diff --git a/bms/bms/bms_config_e18a/mcc/mcc-manifest-autosave.yml b/bms/bms/bms_config_e18a/mcc/mcc-manifest-autosave.yml new file mode 100644 index 00000000..f40f6bc5 --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/mcc-manifest-autosave.yml @@ -0,0 +1,21 @@ +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. + +manifest_file_version: 1.0.0 +project: bms_config_default +creation_date: 2026-03-10T17:53:08.181+01:00[Europe/Oslo] +operating_system: Linux +mcc_mode: VSCodePlugin +mcc_mode_version: Unknown +device_name: ATSAMC21E18A +compiler: N/A +mcc_version: 5.6.4 +mcc_core_version: 5.8.4 +content_manager_version: 6.0.4 +is_mcc_offline: false +is_using_prerelease_versions: false +mcc_content_registries: https://registry.npmjs.org/ +device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, + version: Bundled} +packs: {name: SAMC21_DFP, version: 3.8.119} +modules: +- {name: csp, type: HARMONY, version: v3.23.0} diff --git a/bms/bms/bms_config_e18a/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config_e18a/mcc/mcc-manifest-generated-success.yml new file mode 100644 index 00000000..3d34223a --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/mcc-manifest-generated-success.yml @@ -0,0 +1,21 @@ +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. + +manifest_file_version: 1.0.0 +project: bms_config_default +creation_date: 2026-03-10T17:53:08.146+01:00[Europe/Oslo] +operating_system: Linux +mcc_mode: VSCodePlugin +mcc_mode_version: Unknown +device_name: ATSAMC21E18A +compiler: N/A +mcc_version: 5.6.4 +mcc_core_version: 5.8.4 +content_manager_version: 6.0.4 +is_mcc_offline: false +is_using_prerelease_versions: false +mcc_content_registries: https://registry.npmjs.org/ +device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, + version: Bundled} +packs: {name: SAMC21_DFP, version: 3.8.119} +modules: +- {name: csp, type: HARMONY, version: v3.23.0} diff --git a/bms/bms/bms_config_e18a/mcc/mcc.vscode b/bms/bms/bms_config_e18a/mcc/mcc.vscode new file mode 100644 index 00000000..23a8857e --- /dev/null +++ b/bms/bms/bms_config_e18a/mcc/mcc.vscode @@ -0,0 +1,11 @@ +# This file has been autogenerated by MCC. Please do not edit this file. + +configName: bms_config +fileVersion: 1.0.0 +device: ATSAMC21E18A +associatedIDEProjects: + MPLAB: + - name: bms_config_e18a + path: ../../.vscode + config: default + device: ATSAMC21E18A diff --git a/bms/bms/bms_config_e18a/src/app/can_facade.c b/bms/bms/bms_config_e18a/src/app/can_facade.c new file mode 100644 index 00000000..4cf68592 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/can_facade.c @@ -0,0 +1,82 @@ +/* + Platform: + ATSAMC21 + + Company: + Vortex NTNU. + + Author: + Markus Sandvik + + File Name: + can_facade.c + */ + +#include "definitions.h" +#include "peripheral/port/plib_port.h" +#include "can_facade.h" + + /* ===== RX variables ===== */ + volatile bool rxReady = false; + + uint32_t rx_messageID = 0; + uint8_t rx_message[64] = {0}; + uint8_t rx_messageLength = 0; + uint16_t timestamp = 0; + + static CAN_MSG_RX_FRAME_ATTRIBUTE msgFrameAttr = CAN_MSG_RX_DATA_FRAME; + + /* ===== CAN RAM ===== */ + static bool s_ram_bound = false; + static uint8_t s_can_msg_ram[CAN0_MESSAGE_RAM_CONFIG_SIZE]; + + /* ===== ISR callback ===== */ + void APP_CAN_Callback(uintptr_t context) + { + (void)context; + + rxReady = true; + + + + /* Re-arm RX */ + CAN0_MessageReceive(&rx_messageID, + &rx_messageLength, + rx_message, + ×tamp, + CAN_MSG_ATTR_RX_FIFO0, + &msgFrameAttr); + } + + /* ===== Init ===== */ + void CAN_Init(void) + { + + STB_OutputEnable(); + STB_Clear(); + ////////////////////// + + if (!s_ram_bound) + { + CAN0_MessageRAMConfigSet(s_can_msg_ram); // Bind the CAN message RAM to the driver + s_ram_bound = true; + } + + CAN0_RxCallbackRegister(APP_CAN_Callback, (uintptr_t)NULL, CAN_MSG_ATTR_RX_FIFO0); + + CAN0_MessageReceive(&rx_messageID, + &rx_messageLength, + rx_message, + ×tamp, + CAN_MSG_ATTR_RX_FIFO0, + &msgFrameAttr); + } + + /* ===== Send ===== */ + bool CAN_Send(uint32_t id, uint8_t *data, uint8_t len) + { + const CAN_MODE mode = CAN_MODE_FD_WITHOUT_BRS; + const CAN_MSG_TX_ATTRIBUTE attr = CAN_MSG_ATTR_TX_FIFO_DATA_FRAME; + + return CAN0_MessageTransmit(id, len, data, mode, attr); + } \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/app/can_facade.h b/bms/bms/bms_config_e18a/src/app/can_facade.h new file mode 100644 index 00000000..112829eb --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/can_facade.h @@ -0,0 +1,37 @@ +/* + Platform: + ATSAMC21 + + Company: + Vortex NTNU. + + Author: + Markus Sandvik + + File Name: + can_facade.h + */ + + #ifndef CAN_FACADE_H + #define CAN_FACADE_H + + #pragma once + #include + #include + #include "definitions.h" + + #ifdef __cplusplus + extern "C" { + #endif + + void CAN_Init(void); + bool CAN_Send(uint32_t id, uint8_t *data, uint8_t len); + void APP_CAN_Callback(uintptr_t context); + + + #ifdef __cplusplus + } + #endif + + #endif // CAN_FACADE_H + \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/app/can_telemetry.c b/bms/bms/bms_config_e18a/src/app/can_telemetry.c new file mode 100644 index 00000000..56fa21b7 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/can_telemetry.c @@ -0,0 +1,83 @@ +#include "app/can_telemetry.h" +#include "app/can_facade.h" +#include "ic_bms/bms_spi.h" +#include +#include + + + +static volatile bool flag_vol_tx = false; +static volatile bool flag_temp_tx = false; + +void CAN_telemetry_init(void) +{ + flag_vol_tx = false; // Initialize voltage transmission flag +} + +void CAN_telemetry_tickISR(void) // Call this function every 100ms from a timer interrupt +{ + flag_vol_tx = true; + flag_temp_tx = true; // Set temperature transmission flag +} + +void CAN_voltage_send(void) +{ + uint16_t cell_mV[CELLS_COUNT] = {0}; + uint8_t payload[CELLS_PAYLOAD_LEN]; + uint8_t i; + bool ok; + + if (!flag_vol_tx) + return; + + flag_vol_tx = false; + + ok = read_cells_1to6(cell_mV); + if (!ok) + { + //handle read error + } + + for (i = 0; i < CELLS_COUNT; i++) + { + payload[2 * i] = (uint8_t)(cell_mV[i] & 0xFF); + payload[2 * i + 1] = (uint8_t)((cell_mV[i] >> 8) & 0xFF); + } + + ok = CAN_Send(CAN_VOLTAGE_ID, payload, CELLS_PAYLOAD_LEN); + if (!ok) + { + //handle send error + } +} +void CAN_temp_send(void) +{ + int16_t t1_dC, t2_dC, t3_dC; + uint8_t payload[6]; + bool ok; + + if (!flag_temp_tx) + return; + + flag_temp_tx = false; + + bms_read_ts_temp(TS1_TEMP, &t1_dC); + bms_read_ts_temp(TS2_TEMP, &t2_dC); + bms_read_ts_temp(TS3_TEMP, &t3_dC); + + //Divides temp data into 6 payloads (2 bytes per temp) and sends over CAN + payload[0] = (uint8_t)(t1_dC & 0xFF); + payload[1] = (uint8_t)((t1_dC >> 8) & 0xFF); + payload[2] = (uint8_t)(t2_dC & 0xFF); + payload[3] = (uint8_t)((t2_dC >> 8) & 0xFF); + payload[4] = (uint8_t)(t3_dC & 0xFF); + payload[5] = (uint8_t)((t3_dC >> 8) & 0xFF); + + ok = CAN_Send(CAN_TEMP_ID, payload, sizeof(payload)); + if (!ok) + { + //handle send error + } + + +} diff --git a/bms/bms/bms_config_e18a/src/app/can_telemetry.h b/bms/bms/bms_config_e18a/src/app/can_telemetry.h new file mode 100644 index 00000000..ce6bd8a3 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/can_telemetry.h @@ -0,0 +1,26 @@ +#ifndef CAN_TELEMETRY_H +#define CAN_TELEMETRY_H + +#define CELLS_COUNT 6 +#define CELLS_PAYLOAD_LEN 12 +#define CAN_ID_BOTHOFF_CMD 0x200 //EXAMPLE VALUE +#define BOTHOFF_CMD_BYTE 0xA5 +#define CAN_TEMP_ID 0x100 //EXAMPLE VALUE +#define CAN_VOLTAGE_ID 0x101 //EXAMPLE VALUE + +//legg til func for current, pressure, standbymode, reset mcu + +#define CAN_PRESSURE_ID 0x102 //EXAMPLE VALUE +#define CAN_STANDBYMODE_ID 0x103 //EXAMPLE VALUE +#define CAN_RST_MCU 0x104 //EXAMPLE VALUE +#define CAN_CURRENT_ID 0x105 //EXAMPLE VALUE + + +void CAN_telemetry_init(void); +void CAN_telemetry_tickISR(void); // call from timer/RTC callback +void CAN_voltage_send(void); // call from main loop +void CAN_temp_send(void); + + + +#endif diff --git a/bms/bms/bms_config_e18a/src/app/pwr_mode.c b/bms/bms/bms_config_e18a/src/app/pwr_mode.c new file mode 100644 index 00000000..80f50126 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/pwr_mode.c @@ -0,0 +1,51 @@ +#include "app/pwr_mode.h" +#include "definitions.h" +#include "sam.h" + +static pwr_mode_state_t g_pwr_state= PWR_MODE_ACTIVE; + + +void pwr_mode_init(void) +{ + /* Start in the lightest sleep mode */ + pwr_set_idle0(); +} + +void pwr_set_idle0(void) +{ + + PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_IDLE0; + + while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != + PM_SLEEPCFG_SLEEPMODE_IDLE0) + { + } +} + +void pwr_set_stb_lowpower(void) +{ + /* Enter MCU standby; wake-up comes from an enabled interrupt. */ + PM_REGS->PM_STDBYCFG = PM_STDBYCFG_VREGSMOD_LP; + PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_STANDBY; + + while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != + PM_SLEEPCFG_SLEEPMODE_STANDBY) + { + } +} + +void pwr_enter_sleep(void) +{ + /* Sleep until the next interrupt. */ + __WFI(); // Wait For Interrupt instruction to enter sleep mode + //not sure if correct method +} + +void pwr_set_state(pwr_mode_state_t state){ + g_pwr_state = state; // Update the global state variable +} + +pwr_mode_state_t pwr_get_state(void) +{ + return g_pwr_state; // Return the current power mode state +} diff --git a/bms/bms/bms_config_e18a/src/app/pwr_mode.h b/bms/bms/bms_config_e18a/src/app/pwr_mode.h new file mode 100644 index 00000000..f0abef31 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/pwr_mode.h @@ -0,0 +1,17 @@ +#ifndef PWR_MODE_H +#define PWR_MODE_H + +typedef enum{ + PWR_MODE_ACTIVE=0, + PWR_MODE_STANDBY=1 +} pwr_mode_state_t; + +void pwr_mode_init(void); +void pwr_set_idle0(void); +void pwr_set_stb_lowpower(void); +void pwr_enter_sleep(void); + +void pwr_set_state(pwr_mode_state_t state); +pwr_mode_state_t pwr_get_state(void); + +#endif \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/app/state_machine.c b/bms/bms/bms_config_e18a/src/app/state_machine.c new file mode 100644 index 00000000..456f7db7 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/state_machine.c @@ -0,0 +1,118 @@ +#include "app/state_machine.h" + +#include +#include + +#include "definitions.h" +#include "app/can_telemetry.h" +#include "app/pwr_mode.h" +#include "peripheral/port/plib_port.h" +#include "app/can_facade.h" +#include "ic_bms/bms_spi.h" + +extern volatile bool rxReady; +extern uint32_t rx_messageID; +extern uint8_t rx_message[64]; +extern uint8_t rx_messageLength; + +static volatile bool s_can_wake_irq = false; +static volatile uint32_t s_rtc_tick = 0U; +static uint32_t s_last_can_tick = 0U; + +#define STBY_TO_TICKS 6000U + +void sm_init(void) +{ + s_rtc_tick = 0U; + s_last_can_tick = 0U; + s_can_wake_irq = false; +} + +void sm_on_can_wake(void) +{ + s_can_wake_irq = true; +} + +void sm_on_rtc_tick(void) +{ + s_rtc_tick++; +} + +void state_machine(void) +{ + switch (pwr_get_state()) + { + case PWR_MODE_ACTIVE: + { + uint32_t now; + bool can_alive = s_can_wake_irq; + + CAN_voltage_send(); + CAN_temp_send(); + now = s_rtc_tick; + + if (rxReady) + { + uint32_t id = rx_messageID; + uint8_t len = rx_messageLength; + uint8_t b0 = (len > 0U) ? rx_message[0] : 0U; + + rxReady = false; + can_alive = true; + + switch (id) + { + case CAN_ID_BOTHOFF_CMD: + if ((len > 0U) && (b0 == BOTHOFF_CMD_BYTE)) + { + bothoff_high(); + } + break; + + case CAN_RST_MCU: + NVIC_SystemReset(); + break; + + default: + break; + } + } + + if (can_alive) + { + s_last_can_tick = now; + s_can_wake_irq = false; + } + + if ((uint32_t)(now - s_last_can_tick) >= STBY_TO_TICKS) // Check if the time since the last CAN activity exceeds the threshold + { + STB_Set(); + pwr_set_stb_lowpower(); + pwr_set_state(PWR_MODE_STANDBY); + } + break; + } + + case PWR_MODE_STANDBY: + if (s_can_wake_irq) + { + s_can_wake_irq = false; + s_last_can_tick = s_rtc_tick; + + STB_Clear(); + pwr_set_idle0(); + CAN_Init(); + pwr_set_state(PWR_MODE_ACTIVE); + } + break; + + default: + s_last_can_tick = s_rtc_tick; + STB_Clear(); + pwr_set_idle0(); + pwr_set_state(PWR_MODE_ACTIVE); + break; + } + + pwr_enter_sleep(); +} diff --git a/bms/bms/bms_config_e18a/src/app/state_machine.h b/bms/bms/bms_config_e18a/src/app/state_machine.h new file mode 100644 index 00000000..7ce3cd11 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/app/state_machine.h @@ -0,0 +1,9 @@ +#ifndef STATE_MACHINE_H +#define STATE_MACHINE_H + +void sm_init(void); +void state_machine(void); +void sm_on_can_wake(void); +void sm_on_rtc_tick(void); + +#endif diff --git a/bms/bms/bms_config_e18a/src/config/default/ATSAMC21E18A.ld b/bms/bms/bms_config_e18a/src/config/default/ATSAMC21E18A.ld new file mode 100644 index 00000000..6e2de873 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/ATSAMC21E18A.ld @@ -0,0 +1,241 @@ +/*-------------------------------------------------------------------------- + * MPLAB XC32 Compiler - ATSAMC21E18A linker script + * + * Copyright (c) 2022, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* + * Define the __XC32_RESET_HANDLER_NAME macro on the command line when you + * want to use a different name for the Reset Handler function. + */ +#ifndef __XC32_RESET_HANDLER_NAME +#define __XC32_RESET_HANDLER_NAME Reset_Handler +#endif /* __XC32_RESET_HANDLER_NAME */ + +/* Set the entry point in the ELF file. Once the entry point is in the ELF + * file, you can then use the --write-sla option to xc32-bin2hex to place + * the address into the hex file using the SLA field (RECTYPE 5). This hex + * record may be useful for a bootloader that needs to determine the entry + * point to the application. + */ +ENTRY(__XC32_RESET_HANDLER_NAME) + +/************************************************************************* + * Memory-Region Macro Definitions + * The XC32 linker preprocesses linker scripts. You may define these + * macros in the MPLAB X project properties or on the command line when + * calling the linker via the xc32-gcc shell. + *************************************************************************/ + +#ifndef ROM_ORIGIN +# define ROM_ORIGIN 0x0 +#endif +#ifndef ROM_LENGTH +# define ROM_LENGTH 0x40000 +#elif (ROM_LENGTH > 0x40000) +# error ROM_LENGTH is greater than the max size of 0x40000 +#endif +#ifndef RAM_ORIGIN +# define RAM_ORIGIN 0x20000000 +#endif +#ifndef RAM_LENGTH +# define RAM_LENGTH 0x8000 +#elif (RAM_LENGTH > 0x8000) +# error RAM_LENGTH is greater than the max size of 0x8000 +#endif + + +/************************************************************************* + * Memory-Region Definitions + * The MEMORY command describes the location and size of blocks of memory + * on the target device. The command below uses the macros defined above. + *************************************************************************/ +MEMORY +{ + rom (LRX) : ORIGIN = ROM_ORIGIN, LENGTH = ROM_LENGTH + ram (WX!R) : ORIGIN = RAM_ORIGIN, LENGTH = RAM_LENGTH + config_00804000 : ORIGIN = 0x00804000, LENGTH = 0x4 + config_00804004 : ORIGIN = 0x00804004, LENGTH = 0x4 + +} +/************************************************************************* + * Output region definitions. + * CODE_REGION defines the output region for .text/.rodata. + * DATA_REGION defines the output region for .data/.bss + * VECTOR_REGION defines the output region for .vectors. + * + * CODE_REGION defaults to 'rom', if rom is present (non-zero length), + * and 'ram' otherwise. + * DATA_REGION defaults to 'ram', which must be present. + * VECTOR_REGION defaults to CODE_REGION, unless 'boot_rom' is present. + */ +#ifndef CODE_REGION +# if ROM_LENGTH > 0 +# define CODE_REGION rom +# else +# define CODE_REGION ram +# endif +#endif +#ifndef DATA_REGION +# define DATA_REGION ram +#endif +#ifndef VECTOR_REGION +# define VECTOR_REGION CODE_REGION +#endif + +__rom_end = ORIGIN(rom) + LENGTH(rom); +__ram_end = ORIGIN(ram) + LENGTH(ram); + +/************************************************************************* + * Section Definitions - Map input sections to output sections + *************************************************************************/ +SECTIONS +{ + .config_00804000 : { + KEEP(*(.config_00804000)) + } > config_00804000 + .config_00804004 : { + KEEP(*(.config_00804004)) + } > config_00804004 + + /* + * The linker moves the .vectors section into itcm when itcm is + * enabled via the -mitcm option, but only when this .vectors output + * section exists in the linker script. + */ + .vectors : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.* .vectors_default .vectors_default.*)) + KEEP(*(.isr_vector)) + KEEP(*(.reset*)) + KEEP(*(.after_vectors)) + } > VECTOR_REGION + /* + * Code Sections - Note that standard input sections such as + * *(.text), *(.text.*), *(.rodata), & *(.rodata.*) + * are not mapped here. The best-fit allocator locates them, + * so that input sections may flow around absolute sections + * as needed. + */ + .text : + { + . = ALIGN(4); + *(.glue_7t) *(.glue_7) + *(.gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > CODE_REGION + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > CODE_REGION + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + + /* + * Align here to ensure that the .bss section occupies space up to + * _end. Align after .bss to ensure correct alignment even if the + * .bss section disappears because there are no input sections. + * + * Note that input sections named .bss* are no longer mapped here. + * The best-fit allocator locates them, so that they may flow + * around absolute sections as needed. + */ + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = . ; + _szero = .; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = . ; + _ezero = .; + } > DATA_REGION + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; + +} + diff --git a/bms/bms/bms_config_e18a/src/config/default/definitions.h b/bms/bms/bms_config_e18a/src/config/default/definitions.h new file mode 100644 index 00000000..9d8b4e29 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/definitions.h @@ -0,0 +1,147 @@ +/******************************************************************************* + System Definitions + + File Name: + definitions.h + + Summary: + project system definitions. + + Description: + This file contains the system-wide prototypes and definitions for a project. + + *******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +//DOM-IGNORE-END + +#ifndef DEFINITIONS_H +#define DEFINITIONS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include +#include +#include +#include "peripheral/sercom/usart/plib_sercom3_usart.h" +#include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" +#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" +#include "peripheral/port/plib_port.h" +#include "peripheral/clock/plib_clock.h" +#include "peripheral/nvic/plib_nvic.h" +#include "peripheral/can/plib_can0.h" +#include "peripheral/eic/plib_eic.h" +#include "peripheral/rtc/plib_rtc.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +/* Device Information */ +#define DEVICE_NAME "ATSAMC21E18A" +#define DEVICE_ARCH "CORTEX-M0PLUS" +#define DEVICE_FAMILY "SAMC" +#define DEVICE_SERIES "SAMC21" + +/* CPU clock frequency */ +#define CPU_CLOCK_FREQUENCY 48000000U + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* System Initialization Function + + Function: + void SYS_Initialize( void *data ) + + Summary: + Function that initializes all modules in the system. + + Description: + This function initializes all modules in the system, including any drivers, + services, middleware, and applications. + + Precondition: + None. + + Parameters: + data - Pointer to the data structure containing any data + necessary to initialize the module. This pointer may + be null if no data is required and default initialization + is to be used. + + Returns: + None. + + Example: + + SYS_Initialize ( NULL ); + + while ( true ) + { + SYS_Tasks ( ); + } + + + Remarks: + This function will only be called once, after system reset. +*/ + +void SYS_Initialize( void *data ); + +/* Nullify SYS_Tasks() if only PLIBs are used. */ +#define SYS_Tasks() + +// ***************************************************************************** +// ***************************************************************************** +// Section: extern declarations +// ***************************************************************************** +// ***************************************************************************** + + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* DEFINITIONS_H */ +/******************************************************************************* + End of File +*/ + diff --git a/bms/bms/bms_config_e18a/src/config/default/device.h b/bms/bms/bms_config_e18a/src/config/default/device.h new file mode 100644 index 00000000..669c7985 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/device.h @@ -0,0 +1,65 @@ +/******************************************************************************* + Device Header File + + Company: + Microchip Technology Inc. + + File Name: + device.h + + Summary: + This file includes the selected device from within the project. + The device will provide access to respective device packs. + + Description: + None + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_H +#define DEVICE_H + +#pragma GCC diagnostic push +#ifndef __cplusplus +#pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#ifndef DONT_USE_PREDEFINED_CORE_HANDLERS + #define DONT_USE_PREDEFINED_CORE_HANDLERS +#endif //DONT_USE_PREDEFINED_CORE_HANDLERS +#ifndef DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#endif //DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#include "samc21e18a.h" +#pragma GCC diagnostic pop +#include "device_cache.h" +#include "toolchain_specifics.h" + +#endif //DEVICE_H diff --git a/bms/bms/bms_config_e18a/src/config/default/device_cache.h b/bms/bms/bms_config_e18a/src/config/default/device_cache.h new file mode 100644 index 00000000..802e5dc5 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/device_cache.h @@ -0,0 +1,94 @@ +/******************************************************************************* + Cortex-M L1 Cache Header + + File Name: + device_cache.h + + Summary: + Preprocessor definitions to provide L1 Cache control. + + Description: + An MPLAB PLIB or Project can include this header to perform cache cleans, + invalidates etc. For the DCache and ICache. + + Remarks: + This header should not define any prototypes or data definitions, or + include any files that do. The file only provides macro definitions for + build-time. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_CACHE_H +#define DEVICE_CACHE_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section Includes other configuration headers necessary to completely + define this configuration. +*/ + +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: L1 Cache Configuration +// ***************************************************************************** +// ***************************************************************************** + + +#define ICACHE_ENABLE() +#define ICACHE_DISABLE() +#define ICACHE_INVALIDATE() + +#define DCACHE_ENABLE() +#define DCACHE_DISABLE() +#define DCACHE_INVALIDATE() +#define DCACHE_CLEAN() +#define DCACHE_CLEAN_INVALIDATE() +#define DCACHE_CLEAN_BY_ADDR(addr,sz) +#define DCACHE_INVALIDATE_BY_ADDR(addr,sz) +#define DCACHE_CLEAN_INVALIDATE_BY_ADDR(addr,sz) + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif // #ifndef DEVICE_CACHE_H diff --git a/bms/bms/bms_config_e18a/src/config/default/device_vectors.h b/bms/bms/bms_config_e18a/src/config/default/device_vectors.h new file mode 100644 index 00000000..a584fcdf --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/device_vectors.h @@ -0,0 +1,118 @@ +/******************************************************************************* + Cortex-M device vectors file + + Company: + Microchip Technology Inc. + + File Name: + device_vectors.h + + Summary: + Harmony3 device handler structure for cortex-M devices + + Description: + This file contains Harmony3 device handler structure for cortex-M devices + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_VECTORS_H +#define DEVICE_VECTORS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +/* Function pointer type for vector handlers */ +typedef void (*pfn_handler_t)(void); + +/* Structure defining device vector types */ +typedef struct H3DeviceVectorsTag +{ + /* Stack pointer */ + uint32_t* pvStack; + + /* CORTEX-M0PLUS handlers */ + pfn_handler_t pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + pfn_handler_t pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + pfn_handler_t pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + pfn_handler_t pfnReservedC12; + pfn_handler_t pfnReservedC11; + pfn_handler_t pfnReservedC10; + pfn_handler_t pfnReservedC9; + pfn_handler_t pfnReservedC8; + pfn_handler_t pfnReservedC7; + pfn_handler_t pfnReservedC6; + pfn_handler_t pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + pfn_handler_t pfnReservedC4; + pfn_handler_t pfnReservedC3; + pfn_handler_t pfnPendSV_Handler; /* -2 Pendable request for system service */ + pfn_handler_t pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + pfn_handler_t pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt */ + pfn_handler_t pfnWDT_Handler; /* 1 Watchdog Timer */ + pfn_handler_t pfnRTC_Handler; /* 2 Real Time Counter */ + pfn_handler_t pfnEIC_Handler; /* 3 External Interrupt Controller */ + pfn_handler_t pfnFREQM_Handler; /* 4 Frequency Meter */ + pfn_handler_t pfnTSENS_Handler; /* 5 Temperature Sensor */ + pfn_handler_t pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + pfn_handler_t pfnDMAC_Handler; /* 7 Direct Memory Controller */ + pfn_handler_t pfnEVSYS_Handler; /* 8 Event Systems */ + pfn_handler_t pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + pfn_handler_t pfnReserved13; + pfn_handler_t pfnReserved14; + pfn_handler_t pfnCAN0_Handler; /* 15 Control Area Network 0 */ + pfn_handler_t pfnReserved16; + pfn_handler_t pfnTCC0_Handler; /* 17 Timer/Counter for Control Applications 0 */ + pfn_handler_t pfnTCC1_Handler; /* 18 Timer/Counter for Control Applications 1 */ + pfn_handler_t pfnTCC2_Handler; /* 19 Timer/Counter for Control Applications 2 */ + pfn_handler_t pfnTC0_Handler; /* 20 Timer/Counter 0 */ + pfn_handler_t pfnTC1_Handler; /* 21 Timer/Counter 1 */ + pfn_handler_t pfnTC2_Handler; /* 22 Timer/Counter 2 */ + pfn_handler_t pfnTC3_Handler; /* 23 Timer/Counter 3 */ + pfn_handler_t pfnTC4_Handler; /* 24 Timer/Counter 4 */ + pfn_handler_t pfnADC0_Handler; /* 25 Analog-to-Digital Converter 0 */ + pfn_handler_t pfnADC1_Handler; /* 26 Analog-to-Digital Converter 1 */ + pfn_handler_t pfnAC_Handler; /* 27 Analog Comparators */ + pfn_handler_t pfnDAC_Handler; /* 28 Digital-to-Analog Converter */ + pfn_handler_t pfnSDADC_Handler; /* 29 Sigma-Delat Analog-to-Digital Converter */ + pfn_handler_t pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +}H3DeviceVectors; + +#endif //DEVICE_VECTORS_H diff --git a/bms/bms/bms_config_e18a/src/config/default/exceptions.c b/bms/bms/bms_config_e18a/src/config/default/exceptions.c new file mode 100644 index 00000000..664dd4ad --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/exceptions.c @@ -0,0 +1,89 @@ +/******************************************************************************* + System Exceptions File + + File Name: + exceptions.c + + Summary: + This file contains a function which overrides the default _weak_ exception + handlers provided by the interrupt.c file. + + Description: + This file redefines the default _weak_ exception handler with a more debug + friendly one. If an unexpected exception occurs the code will stop in a + while(1) loop. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "definitions.h" + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Exception Handling Routine +// ***************************************************************************** +// ***************************************************************************** +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 might be violated here if the users provide a strong + implementations to these weak handler functions. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 +*/ + + +/* Brief default interrupt handlers for core IRQs.*/ +void __attribute__((noreturn, weak)) NonMaskableInt_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn, weak)) HardFault_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + + +/* MISRAC 2012 deviation block end for rule 8.6 */ + +/******************************************************************************* + End of File + */ diff --git a/bms/bms/bms_config_e18a/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config_e18a/src/config/default/harmony-manifest-success.yml new file mode 100644 index 00000000..6192c769 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/harmony-manifest-success.yml @@ -0,0 +1,21 @@ + +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. +# Project "bms_config_default" has been created by using mentioned Harmony 3 packages + + +project: bms_config_default +creation_date: 2026-03-10T17:53:08.152+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +operating_system: Linux +mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] +mcc_version: v5.6.4 +mcc_core_version: v5.8.4 +mplabx_version: NA # if MPLAB X plugin only +harmony_version: v5.6.4 +compiler: NA + +modules: + - {name: "csp", version: "v3.23.0"} + +packs: + - {name: "SAMC21_DFP", version: "3.8.119"} + diff --git a/bms/bms/bms_config_e18a/src/config/default/initialization.c b/bms/bms/bms_config_e18a/src/config/default/initialization.c new file mode 100644 index 00000000..25bf9740 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/initialization.c @@ -0,0 +1,161 @@ +/******************************************************************************* + System Initialization File + + File Name: + initialization.c + + Summary: + This file contains source code necessary to initialize the system. + + Description: + This file contains source code necessary to initialize the system. It + implements the "SYS_Initialize" function, defines the configuration bits, + and allocates any necessary global system resources, + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "definitions.h" +#include "device.h" + + +// **************************************************************************** +// **************************************************************************** +// Section: Configuration Bits +// **************************************************************************** +// **************************************************************************** +#pragma config NVMCTRL_BOOTPROT = SIZE_0BYTES +#pragma config NVMCTRL_EEPROM_SIZE = SIZE_0BYTES +#pragma config BODVDDUSERLEVEL = 0x8U // Enter Hexadecimal value +#pragma config BODVDD_DIS = DISABLED +#pragma config BODVDD_ACTION = NONE + +#pragma config BODVDD_HYST = DISABLED +#pragma config NVMCTRL_REGION_LOCKS = 0xffffU // Enter Hexadecimal value + +#pragma config WDT_ENABLE = DISABLED +#pragma config WDT_ALWAYSON = DISABLED +#pragma config WDT_PER = CYC8 + +#pragma config WDT_WINDOW = CYC8 +#pragma config WDT_EWOFFSET = CYC8 +#pragma config WDT_WEN = DISABLED + + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Driver Initialization Data +// ***************************************************************************** +// ***************************************************************************** +/* Following MISRA-C rules are deviated in the below code block */ +/* MISRA C-2012 Rule 7.2 - Deviation record ID - H3_MISRAC_2012_R_7_2_DR_1 */ +/* MISRA C-2012 Rule 11.1 - Deviation record ID - H3_MISRAC_2012_R_11_1_DR_1 */ +/* MISRA C-2012 Rule 11.3 - Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1 */ +/* MISRA C-2012 Rule 11.8 - Deviation record ID - H3_MISRAC_2012_R_11_8_DR_1 */ + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Data +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Library/Stack Initialization Data +// ***************************************************************************** +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Initialization +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local initialization functions +// ***************************************************************************** +// ***************************************************************************** + +/* MISRAC 2012 deviation block end */ + +/******************************************************************************* + Function: + void SYS_Initialize ( void *data ) + + Summary: + Initializes the board, services, drivers, application and other modules. + + Remarks: + */ + +void SYS_Initialize ( void* data ) +{ + + /* MISRAC 2012 deviation block start */ + /* MISRA C-2012 Rule 2.2 deviated in this file. Deviation record ID - H3_MISRAC_2012_R_2_2_DR_1 */ + + + + CLOCK_Initialize(); + + + + + SERCOM3_USART_Initialize(); + + SERCOM1_I2C_Initialize(); + + SERCOM0_SPI_Initialize(); + + CAN0_Initialize(); + + EIC_Initialize(); + + RTC_Initialize(); + + + NVIC_Initialize(); + + + /* MISRAC 2012 deviation block end */ +} + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/interrupts.c b/bms/bms/bms_config_e18a/src/config/default/interrupts.c new file mode 100644 index 00000000..b5c24153 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/interrupts.c @@ -0,0 +1,160 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.c + + Summary: + Interrupt vectors mapping + + Description: + This file maps all the interrupt vectors to their corresponding + implementations. If a particular module interrupt is used, then its ISR + definition can be found in corresponding PLIB source file. If a module + interrupt is not used, then its ISR implementation is mapped to dummy + handler. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "device_vectors.h" +#include "interrupts.h" +#include "definitions.h" + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Interrupt Vector Functions +// ***************************************************************************** +// ***************************************************************************** + +/* MISRA C-2012 Rule 8.6 deviated below. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +extern uint32_t _stack; +extern const H3DeviceVectors exception_table; + +extern void Dummy_Handler(void); + +/* Brief default interrupt handler for unused IRQs.*/ +void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(void) +{ + while (true) + { + } +} + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 deviated 26 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* Device vectors list dummy definition*/ +extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SysTick_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SYSTEM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void WDT_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void EIC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void NVMCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void DMAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void EVSYS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SERCOM2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void ADC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void ADC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void AC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void DAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SDADC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void PTC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); + + +/* MISRAC 2012 deviation block end */ + +/* Multiple handlers for vector */ + + + +__attribute__ ((section(".vectors"), used)) +const H3DeviceVectors exception_table= +{ + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = &_stack, + + .pfnReset_Handler = Reset_Handler, + .pfnNonMaskableInt_Handler = NonMaskableInt_Handler, + .pfnHardFault_Handler = HardFault_Handler, + .pfnSVCall_Handler = SVCall_Handler, + .pfnPendSV_Handler = PendSV_Handler, + .pfnSysTick_Handler = SysTick_Handler, + .pfnSYSTEM_Handler = SYSTEM_Handler, + .pfnWDT_Handler = WDT_Handler, + .pfnRTC_Handler = RTC_InterruptHandler, + .pfnEIC_Handler = EIC_Handler, + .pfnFREQM_Handler = FREQM_Handler, + .pfnTSENS_Handler = TSENS_Handler, + .pfnNVMCTRL_Handler = NVMCTRL_Handler, + .pfnDMAC_Handler = DMAC_Handler, + .pfnEVSYS_Handler = EVSYS_Handler, + .pfnSERCOM0_Handler = SERCOM0_SPI_InterruptHandler, + .pfnSERCOM1_Handler = SERCOM1_I2C_InterruptHandler, + .pfnSERCOM2_Handler = SERCOM2_Handler, + .pfnSERCOM3_Handler = SERCOM3_USART_InterruptHandler, + .pfnCAN0_Handler = CAN0_InterruptHandler, + .pfnTCC0_Handler = TCC0_Handler, + .pfnTCC1_Handler = TCC1_Handler, + .pfnTCC2_Handler = TCC2_Handler, + .pfnTC0_Handler = TC0_Handler, + .pfnTC1_Handler = TC1_Handler, + .pfnTC2_Handler = TC2_Handler, + .pfnTC3_Handler = TC3_Handler, + .pfnTC4_Handler = TC4_Handler, + .pfnADC0_Handler = ADC0_Handler, + .pfnADC1_Handler = ADC1_Handler, + .pfnAC_Handler = AC_Handler, + .pfnDAC_Handler = DAC_Handler, + .pfnSDADC_Handler = SDADC_Handler, + .pfnPTC_Handler = PTC_Handler, + + +}; + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/interrupts.h b/bms/bms/bms_config_e18a/src/config/default/interrupts.h new file mode 100644 index 00000000..11816788 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/interrupts.h @@ -0,0 +1,70 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.h + + Summary: + Interrupt vectors mapping + + Description: + This file contains declarations of device vectors used by Harmony 3 + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Handler Routines +// ***************************************************************************** +// ***************************************************************************** +void Reset_Handler (void); +void NonMaskableInt_Handler (void); +void HardFault_Handler (void); +void RTC_InterruptHandler (void); +void SERCOM0_SPI_InterruptHandler (void); +void SERCOM1_I2C_InterruptHandler (void); +void SERCOM3_USART_InterruptHandler (void); +void CAN0_InterruptHandler (void); + + + +#endif // INTERRUPTS_H diff --git a/bms/bms/bms_config_e18a/src/config/default/libc_syscalls.c b/bms/bms/bms_config_e18a/src/config/default/libc_syscalls.c new file mode 100644 index 00000000..ae819a61 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/libc_syscalls.c @@ -0,0 +1,61 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include +#include "device.h" /* for ARM CMSIS __BKPT() */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated twice. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* Harmony specific + * We implement only the syscalls we want over the stubs provided by libpic32c + */ +extern void _exit(int status); + +void _exit(int status) +{ + /* Software breakpoint */ +#ifdef __DEBUG + __BKPT(0); +#endif + + /* halt CPU */ + while (true) + { + } +} + +#ifdef __cplusplus +} +#endif + +/* MISRAC 2012 deviation block end */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.c new file mode 100644 index 00000000..5b38d23d --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.c @@ -0,0 +1,230 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc0.c + + Summary + ADC0 PLIB Implementation File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "interrupts.h" +#include "plib_adc0.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +#define ADC0_LINEARITY_POS (0U) +#define ADC0_LINEARITY_Msk (0x7UL << ADC0_LINEARITY_POS) + +#define ADC0_BIASCAL_POS (3U) +#define ADC0_BIASCAL_Msk (0x7UL << ADC0_BIASCAL_POS) + + +// ***************************************************************************** +// ***************************************************************************** +// Section: ADC0 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize ADC module */ +void ADC0_Initialize( void ) +{ + /* Reset ADC */ + ADC0_REGS->ADC_CTRLA = (uint8_t)ADC_CTRLA_SWRST_Msk; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization */ + } + /* Write linearity calibration in BIASREFBUF and bias calibration in BIASCOMP */ + uint32_t calib_low_word = (uint32_t)(*(uint64_t*)OTP5_ADDR); + ADC0_REGS->ADC_CALIB = (uint16_t)((ADC_CALIB_BIASREFBUF((calib_low_word & ADC0_LINEARITY_Msk) >> ADC0_LINEARITY_POS)) | + (ADC_CALIB_BIASCOMP((calib_low_word & ADC0_BIASCAL_Msk) >> ADC0_BIASCAL_POS))); + + /* Prescaler */ + ADC0_REGS->ADC_CTRLB = (uint8_t)ADC_CTRLB_PRESCALER_DIV4; + /* Sampling length */ + ADC0_REGS->ADC_SAMPCTRL = (uint8_t)ADC_SAMPCTRL_SAMPLEN(3UL); + + /* Reference */ + ADC0_REGS->ADC_REFCTRL = (uint8_t)ADC_REFCTRL_REFSEL_INTVCC2 | ADC_REFCTRL_REFCOMP_Msk; + + /* Input pin */ + ADC0_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0; + + /* Resolution & Operation Mode */ + ADC0_REGS->ADC_CTRLC = (uint16_t)(ADC_CTRLC_RESSEL_12BIT | ADC_CTRLC_WINMODE(0UL) ); + + + /* Clear all interrupt flags */ + ADC0_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; + + while(0U != ADC0_REGS->ADC_SYNCBUSY) + { + /* Wait for Synchronization */ + } +} + +/* Enable ADC module */ +void ADC0_Enable( void ) +{ + ADC0_REGS->ADC_CTRLA |= (uint8_t)ADC_CTRLA_ENABLE_Msk; + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Disable ADC module */ +void ADC0_Disable( void ) +{ + ADC0_REGS->ADC_CTRLA &= (uint8_t)(~ADC_CTRLA_ENABLE_Msk); + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Configure channel input */ +void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) +{ + /* Configure pin scan mode and positive and negative input pins */ + ADC0_REGS->ADC_INPUTCTRL = (uint16_t) positiveInput | (uint16_t) negativeInput; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Start the ADC conversion by SW */ +void ADC0_ConversionStart( void ) +{ + /* Start conversion */ + ADC0_REGS->ADC_SWTRIG |= (uint8_t)ADC_SWTRIG_START_Msk; + + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Check whether auto sequence conversion is done */ +bool ADC0_ConversionSequenceIsFinished(void) +{ + bool seq_status = false; + if ((ADC0_REGS->ADC_SEQSTATUS & ADC_SEQSTATUS_SEQBUSY_Msk) != ADC_SEQSTATUS_SEQBUSY_Msk) + { + seq_status = true; + } + return seq_status; +} + +/* Configure window comparison threshold values */ +void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC0_REGS->ADC_WINLT = low_threshold; + ADC0_REGS->ADC_WINUT = high_threshold; + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) + { + /* Wait for Synchronization */ + } + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) + { + /* Wait for Synchronization */ + } +} + +void ADC0_WindowModeSet(ADC_WINMODE mode) +{ + ADC0_REGS->ADC_CTRLC = (ADC0_REGS->ADC_CTRLC & (uint16_t)(~ADC_CTRLC_WINMODE_Msk)) | (uint16_t)((uint32_t)mode << ADC_CTRLC_WINMODE_Pos); + while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_CTRLC_Msk) == ADC_SYNCBUSY_CTRLC_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Read the conversion result */ +uint16_t ADC0_ConversionResultGet( void ) +{ + return (uint16_t)ADC0_REGS->ADC_RESULT; +} + +void ADC0_InterruptsClear(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTFLAG = (uint8_t)interruptMask; +} + +void ADC0_InterruptsEnable(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTENSET = (uint8_t)interruptMask; +} + +void ADC0_InterruptsDisable(ADC_STATUS interruptMask) +{ + ADC0_REGS->ADC_INTENCLR = (uint8_t)interruptMask; +} + +/* Check whether result is ready */ +bool ADC0_ConversionStatusGet( void ) +{ + bool status; + status = (((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); + if (status == true) + { + ADC0_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_RESRDY_Msk; + } + return status; +} + + diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.h new file mode 100644 index 00000000..49ca4421 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.h @@ -0,0 +1,127 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC0) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc0.h + + Summary + ADC0 PLIB Header File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC0_H // Guards against multiple inclusion +#define PLIB_ADC0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_adc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +void ADC0_Initialize( void ); + +void ADC0_Enable( void ); + +void ADC0_Disable( void ); + +void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); + +void ADC0_ConversionStart( void ); + +uint16_t ADC0_ConversionResultGet( void ); + +void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); + +void ADC0_WindowModeSet(ADC_WINMODE mode); + +bool ADC0_ConversionSequenceIsFinished(void); + +void ADC0_InterruptsClear(ADC_STATUS interruptMask); + +void ADC0_InterruptsEnable(ADC_STATUS interruptMask); + +void ADC0_InterruptsDisable(ADC_STATUS interruptMask); + + +bool ADC0_ConversionStatusGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC0_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.c new file mode 100644 index 00000000..868eff15 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.c @@ -0,0 +1,228 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC1) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc1.c + + Summary + ADC1 PLIB Implementation File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "interrupts.h" +#include "plib_adc1.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + +#define ADC1_LINEARITY_POS (6U) +#define ADC1_LINEARITY_Msk (0x7UL << ADC1_LINEARITY_POS) + +#define ADC1_BIASCAL_POS (9U) +#define ADC1_BIASCAL_Msk (0x7UL << ADC1_BIASCAL_POS) + + +// ***************************************************************************** +// ***************************************************************************** +// Section: ADC1 Implementation +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Initialize ADC module */ +void ADC1_Initialize( void ) +{ + /* Reset ADC */ + ADC1_REGS->ADC_CTRLA = (uint8_t)ADC_CTRLA_SWRST_Msk; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization */ + } + /* Write linearity calibration in BIASREFBUF and bias calibration in BIASCOMP */ + uint32_t calib_low_word = (uint32_t)(*(uint64_t*)OTP5_ADDR); + ADC1_REGS->ADC_CALIB = (uint16_t)((ADC_CALIB_BIASREFBUF((calib_low_word & ADC1_LINEARITY_Msk) >> ADC1_LINEARITY_POS)) | + (ADC_CALIB_BIASCOMP((calib_low_word & ADC1_BIASCAL_Msk) >> ADC1_BIASCAL_POS))); + + /* Prescaler */ + ADC1_REGS->ADC_CTRLB = (uint8_t)ADC_CTRLB_PRESCALER_DIV8; + /* Sampling length */ + ADC1_REGS->ADC_SAMPCTRL = (uint8_t)ADC_SAMPCTRL_SAMPLEN(3UL); + + /* Reference */ + ADC1_REGS->ADC_REFCTRL = (uint8_t)ADC_REFCTRL_REFSEL_INTVCC2 | ADC_REFCTRL_REFCOMP_Msk; + + /* Input pin */ + ADC1_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0; + + /* Resolution & Operation Mode */ + ADC1_REGS->ADC_CTRLC = (uint16_t)(ADC_CTRLC_RESSEL_12BIT | ADC_CTRLC_WINMODE(0UL) | ADC_CTRLC_FREERUN_Msk); + + + /* Clear all interrupt flags */ + ADC1_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; + + while(0U != ADC1_REGS->ADC_SYNCBUSY) + { + /* Wait for Synchronization */ + } +} + +/* Enable ADC module */ +void ADC1_Enable( void ) +{ + ADC1_REGS->ADC_CTRLA |= (uint8_t)ADC_CTRLA_ENABLE_Msk; + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Disable ADC module */ +void ADC1_Disable( void ) +{ + ADC1_REGS->ADC_CTRLA &= (uint8_t)(~ADC_CTRLA_ENABLE_Msk); + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Configure channel input */ +void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) +{ + /* Configure pin scan mode and positive and negative input pins */ + ADC1_REGS->ADC_INPUTCTRL = (uint16_t) positiveInput | (uint16_t) negativeInput; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Start the ADC conversion by SW */ +void ADC1_ConversionStart( void ) +{ + /* Start conversion */ + ADC1_REGS->ADC_SWTRIG |= (uint8_t)ADC_SWTRIG_START_Msk; + + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Check whether auto sequence conversion is done */ +bool ADC1_ConversionSequenceIsFinished(void) +{ + bool seq_status = false; + if ((ADC1_REGS->ADC_SEQSTATUS & ADC_SEQSTATUS_SEQBUSY_Msk) != ADC_SEQSTATUS_SEQBUSY_Msk) + { + seq_status = true; + } + return seq_status; +} + +/* Configure window comparison threshold values */ +void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC1_REGS->ADC_WINLT = low_threshold; + ADC1_REGS->ADC_WINUT = high_threshold; + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) + { + /* Wait for Synchronization */ + } + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) + { + /* Wait for Synchronization */ + } +} + +void ADC1_WindowModeSet(ADC_WINMODE mode) +{ + ADC1_REGS->ADC_CTRLC = (ADC1_REGS->ADC_CTRLC & (uint16_t)(~ADC_CTRLC_WINMODE_Msk)) | (uint16_t)((uint32_t)mode << ADC_CTRLC_WINMODE_Pos); + while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_CTRLC_Msk) == ADC_SYNCBUSY_CTRLC_Msk) + { + /* Wait for Synchronization */ + } +} + +/* Read the conversion result */ +uint16_t ADC1_ConversionResultGet( void ) +{ + return (uint16_t)ADC1_REGS->ADC_RESULT; +} + +void ADC1_InterruptsClear(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTFLAG = (uint8_t)interruptMask; +} + +void ADC1_InterruptsEnable(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTENSET = (uint8_t)interruptMask; +} + +void ADC1_InterruptsDisable(ADC_STATUS interruptMask) +{ + ADC1_REGS->ADC_INTENCLR = (uint8_t)interruptMask; +} + +/* Check whether result is ready */ +bool ADC1_ConversionStatusGet( void ) +{ + bool status; + status = (((ADC1_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); + if (status == true) + { + ADC1_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_RESRDY_Msk; + } + return status; +} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.h new file mode 100644 index 00000000..a0fa8afd --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.h @@ -0,0 +1,127 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC1) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_adc1.h + + Summary + ADC1 PLIB Header File. + + Description + This file defines the interface to the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC1_H // Guards against multiple inclusion +#define PLIB_ADC1_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include "plib_adc_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +void ADC1_Initialize( void ); + +void ADC1_Enable( void ); + +void ADC1_Disable( void ); + +void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); + +void ADC1_ConversionStart( void ); + +uint16_t ADC1_ConversionResultGet( void ); + +void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); + +void ADC1_WindowModeSet(ADC_WINMODE mode); + +bool ADC1_ConversionSequenceIsFinished(void); + +void ADC1_InterruptsClear(ADC_STATUS interruptMask); + +void ADC1_InterruptsEnable(ADC_STATUS interruptMask); + +void ADC1_InterruptsDisable(ADC_STATUS interruptMask); + + +bool ADC1_ConversionStatusGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC1_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc_common.h new file mode 100644 index 00000000..c1dfe852 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc_common.h @@ -0,0 +1,156 @@ +/******************************************************************************* + Analog-to-Digital Converter(ADC) Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_adc_common.h + + Summary + ADC Peripheral Library Interface Header File. + + Description + This file defines the common types for the ADC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_ADC_COMMON_H // Guards against multiple inclusion +#define PLIB_ADC_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +#define ADC_STATUS_NONE 0U +#define ADC_STATUS_RESRDY ADC_INTFLAG_RESRDY_Msk +#define ADC_STATUS_WINMON ADC_INTFLAG_WINMON_Msk +#define ADC_STATUS_OVERRUN ADC_INTFLAG_OVERRUN_Msk +#define ADC_STATUS_MASK (ADC_STATUS_RESRDY | ADC_STATUS_OVERRUN | ADC_STATUS_WINMON) +#define ADC_STATUS_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part it. +*/ + +typedef enum +{ + ADC_POSINPUT_AIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, + ADC_POSINPUT_AIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, + ADC_POSINPUT_AIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, + ADC_POSINPUT_AIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, + ADC_POSINPUT_AIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, + ADC_POSINPUT_AIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, + ADC_POSINPUT_AIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, + ADC_POSINPUT_AIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, + ADC_POSINPUT_AIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, + ADC_POSINPUT_AIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, + ADC_POSINPUT_AIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, + ADC_POSINPUT_AIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, + ADC_POSINPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, + ADC_POSINPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, + ADC_POSINPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, + ADC_POSINPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, +}ADC_POSINPUT; + +// ***************************************************************************** + +typedef enum +{ + ADC_NEGINPUT_AIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, + ADC_NEGINPUT_AIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, + ADC_NEGINPUT_AIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, + ADC_NEGINPUT_AIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, + ADC_NEGINPUT_AIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, + ADC_NEGINPUT_AIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, + ADC_NEGINPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, +}ADC_NEGINPUT; + +typedef uint32_t ADC_STATUS; +typedef enum +{ + ADC_WINMODE_DISABLED = ADC_CTRLC_WINMODE_DISABLE_Val, + ADC_WINMODE_GREATER_THAN_WINLT = ADC_CTRLC_WINMODE_MODE1_Val, + ADC_WINMODE_LESS_THAN_WINUT = ADC_CTRLC_WINMODE_MODE2_Val, + ADC_WINMODE_BETWEEN_WINLT_AND_WINUT = ADC_CTRLC_WINMODE_MODE3_Val, + ADC_WINMODE_OUTSIDE_WINLT_AND_WINUT = ADC_CTRLC_WINMODE_MODE4_Val +}ADC_WINMODE; + + +// ***************************************************************************** + + +typedef void (*ADC_CALLBACK)(ADC_STATUS status, uintptr_t context); + + +typedef struct +{ + ADC_CALLBACK callback; + + uintptr_t context; + +} ADC_CALLBACK_OBJ; + + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_ADC_COMMON_H*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.c new file mode 100644 index 00000000..19b5de3a --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.c @@ -0,0 +1,911 @@ +/******************************************************************************* + Controller Area Network (CAN) Peripheral Library Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_can0.c + + Summary: + CAN peripheral library interface. + + Description: + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Header Includes +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include "interrupts.h" +#include "plib_can0.h" + +// ***************************************************************************** +// ***************************************************************************** +// Global Data +// ***************************************************************************** +// ***************************************************************************** +#define CAN_STD_ID_Msk 0x7FFU + +static volatile CAN_TX_FIFO_CALLBACK_OBJ can0TxFifoCallbackObj; +static volatile CAN_TX_EVENT_FIFO_CALLBACK_OBJ can0TxEventFifoCallbackObj; +static volatile CAN_RX_FIFO_CALLBACK_OBJ can0RxFifoCallbackObj[2]; +static volatile CAN_CALLBACK_OBJ can0CallbackObj; +static volatile CAN_OBJ can0Obj; + +static inline void CAN0_ZeroInitialize(volatile void* pData, size_t dataSize) +{ + volatile uint8_t* data = (volatile uint8_t*)pData; + for (uint32_t index = 0; index < dataSize; index++) + { + data[index] = 0U; + } +} + +// ***************************************************************************** +// ***************************************************************************** +// CAN0 PLib Interface Routines +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void CAN0_Initialize(void) + + Summary: + Initializes given instance of the CAN peripheral. + + Precondition: + None. + + Parameters: + None. + + Returns: + None +*/ +void CAN0_Initialize(void) +{ + /* Start CAN initialization */ + CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + /* Set Data Bit Timing and Prescaler Register */ + CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(15UL) | CAN_DBTP_DTSEG1(31UL) | CAN_DBTP_DBRP(0UL) | CAN_DBTP_DSJW(7UL); + + /* Set Nominal Bit timing and Prescaler Register */ + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(23UL) | CAN_NBTP_NTSEG1(70UL) | CAN_NBTP_NBRP(0UL) | CAN_NBTP_NSJW(23UL); + + /* Receive Buffer / FIFO Element Size Configuration Register */ + CAN0_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(0UL) | CAN_RXESC_F1DS(0UL); + /* Transmit Buffer/FIFO Element Size Configuration Register */ + CAN0_REGS->CAN_TXESC = CAN_TXESC_TBDS(0UL); + + /* Global Filter Configuration Register */ + CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; + + /* Set the operation mode */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; + + + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Select interrupt line */ + CAN0_REGS->CAN_ILS = 0x0U; + + /* Enable interrupt line */ + CAN0_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; + + /* Enable CAN interrupts */ + CAN0_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk + | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk + | CAN_IE_TFEE_Msk + | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk + | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk + | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk + + | CAN_IE_MRAFE_Msk; + + CAN0_ZeroInitialize(&can0Obj.msgRAMConfig, sizeof(CAN_MSG_RAM_CONFIG)); +} + + +// ***************************************************************************** +/* Function: + bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) + + Summary: + Transmit multiple messages into CAN bus from Tx FIFO. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfMessage - Total number of message. + txBuffer - Pointer to Tx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) +{ + uint8_t *txFifo = NULL; + uint8_t *txBuf = (uint8_t *)txBuffer; + uint32_t bufferNumber = 0U; + uint8_t tfqpi = 0U; + uint8_t count = 0U; + bool transmitFifo_event = false; + + if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) + { + tfqpi = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + + for (count = 0U; count < numberOfMessage; count++) + { + txFifo = (uint8_t *)((uint8_t*)can0Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE)); + + (void) memcpy(txFifo, txBuf, CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE); + + txBuf += CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE; + bufferNumber |= (1UL << tfqpi); + tfqpi++; + if (tfqpi == 1U) + { + tfqpi = 0U; + } + } + + __DSB(); + + /* Set Transmission request */ + CAN0_REGS->CAN_TXBAR = bufferNumber; + + transmitFifo_event = true; + } + return transmitFifo_event; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN0_TxFifoFreeLevelGet(void) + + Summary: + Returns Tx FIFO Free Level. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Tx FIFO Free Level. +*/ +uint8_t CAN0_TxFifoFreeLevelGet(void) +{ + return (uint8_t)(CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) + + Summary: + Check if Transmission request is pending for the specific Tx buffer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + true - Transmission request is pending. + false - Transmission request is not pending. +*/ +bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) +{ + return ((CAN0_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) + + Summary: + Read Tx Event FIFO for the transmitted messages. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfTxEvent - Total number of Tx Event + txEventFifo - Pointer to Tx Event FIFO + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) +{ + uint8_t txefgi = 0U; + uint8_t count = 0U; + uint8_t *txEvent = NULL; + uint8_t *txEvtFifo = (uint8_t *)txEventFifo; + bool txFifo_event = false; + + if (txEventFifo != NULL) + { + /* Read data from the Rx FIFO0 */ + txefgi = (uint8_t)((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); + for (count = 0U; count < numberOfTxEvent; count++) + { + txEvent = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); + + (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); + + if ((count + 1U) == numberOfTxEvent) + { + break; + } + txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); + txefgi++; + if (txefgi == 1U) + { + txefgi = 0U; + } + } + + /* Ack the Tx Event FIFO position */ + CAN0_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); + + txFifo_event = true; + } + return txFifo_event; +} + + +// ***************************************************************************** +/* Function: + bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) + + Summary: + Read messages from Rx FIFO0/FIFO1. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO number + numberOfMessage - Total number of message + rxBuffer - Pointer to Rx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) +{ + uint8_t rxgi = 0U; + uint8_t count = 0U; + uint8_t *rxFifo = NULL; + uint8_t *rxBuf = (uint8_t *)rxBuffer; + bool status = false; + + if (rxBuffer != NULL) + { + switch (rxFifoNum) + { + case CAN_RX_FIFO_0: + /* Read data from the Rx FIFO0 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN0_RX_FIFO0_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO0_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN0_RX_FIFO0_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); + + status = true; + break; + case CAN_RX_FIFO_1: + /* Read data from the Rx FIFO1 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN0_RX_FIFO1_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO1_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN0_RX_FIFO1_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); + + status = true; + break; + default: + /* Do nothing */ + break; + } + } + return status; +} + +// ***************************************************************************** +/* Function: + CAN_ERROR CAN0_ErrorGet(void) + + Summary: + Returns the error during transfer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Error during transfer. +*/ +CAN_ERROR CAN0_ErrorGet(void) +{ + CAN_ERROR error; + uint32_t errorStatus = CAN0_REGS->CAN_PSR; + + error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) + | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); + + if ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + } + + return error; +} + +// ***************************************************************************** +/* Function: + void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) + + Summary: + Returns the transmit and receive error count during transfer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + txErrorCount - Transmit Error Count to be received + rxErrorCount - Receive Error Count to be received + + Returns: + None. +*/ +void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) +{ + *txErrorCount = (uint8_t)(CAN0_REGS->CAN_ECR & CAN_ECR_TEC_Msk); + *rxErrorCount = (uint8_t)((CAN0_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); +} + +// ***************************************************************************** +/* Function: + void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) + + Summary: + Set the Message RAM Configuration. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. + Application must allocate buffer from non-cached + contiguous memory and buffer size must be + CAN0_MESSAGE_RAM_CONFIG_SIZE + + Returns: + None +*/ +/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ +void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) +{ + uint32_t offset = 0U; + uint32_t msgRAMConfigBaseAddr = (uint32_t)msgRAMConfigBaseAddress; + + (void) memset(msgRAMConfigBaseAddress, 0x00, CAN0_MESSAGE_RAM_CONFIG_SIZE); + + /* Set CAN CCCR Init for Message RAM Configuration */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + can0Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; + offset = CAN0_RX_FIFO0_SIZE; + /* Receive FIFO 0 Configuration Register */ + CAN0_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | + CAN_RXF0C_F0SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO0Address); + + can0Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_RX_FIFO1_SIZE; + /* Receive FIFO 1 Configuration Register */ + CAN0_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | + CAN_RXF1C_F1SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO1Address); + + can0Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_TX_FIFO_BUFFER_SIZE; + /* Transmit Buffer/FIFO Configuration Register */ + CAN0_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | + CAN_TXBC_TBSA((uint32_t)can0Obj.msgRAMConfig.txBuffersAddress); + + can0Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_TX_EVENT_FIFO_SIZE; + /* Transmit Event FIFO Configuration Register */ + CAN0_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | + CAN_TXEFC_EFSA((uint32_t)can0Obj.msgRAMConfig.txEventFIFOAddress); + + + /* Reference offset variable once to remove warning about the variable not being used after increment */ + (void)offset; + + /* Complete Message RAM Configuration by clearing CAN CCCR Init */ + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for configuration complete */ + } +} +/* MISRAC 2012 deviation block end for Rule 11.3*/ + + + + +void CAN0_SleepModeEnter(void) +{ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) + { + /* Wait for clock stop request to complete */ + } +} + +void CAN0_SleepModeExit(void) +{ + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) + { + /* Wait for no clock stop */ + } + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } +} + +bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + uint32_t numOfTimeQuanta; + uint8_t tseg1; + float temp1; + float temp2; + + if ((setup != NULL) && (bitTiming != NULL)) + { + if (setup->nominalBitTimingSet == true) + { + numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) + { + if (setup->nominalSamplePoint < 50.0f) + { + setup->nominalSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; + bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; + bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; + bitTiming->nominalBitTimingSet = true; + status = true; + } + else + { + bitTiming->nominalBitTimingSet = false; + } + } + if (setup->dataBitTimingSet == true) + { + numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->dataBitRate * ((uint32_t)setup->dataPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 49U)) + { + if (setup->dataSamplePoint < 50.0f) + { + setup->dataSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->dataSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->dataBitTiming.dataTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->dataBitTiming.dataTimeSegment1 = tseg1 - 2U; + bitTiming->dataBitTiming.dataSJW = bitTiming->dataBitTiming.dataTimeSegment2; + bitTiming->dataBitTiming.dataPrescaler = setup->dataPrescaler; + bitTiming->dataBitTimingSet = true; + status = true; + } + else + { + bitTiming->dataBitTimingSet = false; + status = false; + } + } + } + + return status; +} + +bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + bool nominalBitTimingSet = false; + bool dataBitTimingSet = false; + + if ((bitTiming->nominalBitTimingSet == true) + && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) + && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) + && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) + && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) + { + nominalBitTimingSet = true; + } + + if ((bitTiming->dataBitTimingSet == true) + && ((bitTiming->dataBitTiming.dataTimeSegment1 >= 0x1U) && (bitTiming->dataBitTiming.dataTimeSegment1 <= 0x1FU)) + && (bitTiming->dataBitTiming.dataTimeSegment2 <= 0xFU) + && (bitTiming->dataBitTiming.dataPrescaler <= 0x1FU) + && (bitTiming->dataBitTiming.dataSJW <= 0xFU)) + { + dataBitTimingSet = true; + } + + if ((nominalBitTimingSet == true) || (dataBitTimingSet == true)) + { + /* Start CAN initialization */ + CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + if (dataBitTimingSet == true) + { + /* Set Data Bit Timing and Prescaler Register */ + CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(bitTiming->dataBitTiming.dataTimeSegment2) | CAN_DBTP_DTSEG1(bitTiming->dataBitTiming.dataTimeSegment1) | CAN_DBTP_DBRP(bitTiming->dataBitTiming.dataPrescaler) | CAN_DBTP_DSJW(bitTiming->dataBitTiming.dataSJW); + } + if (nominalBitTimingSet == true) + { + /* Set Nominal Bit timing and Prescaler Register */ + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); + } + + /* Set the operation mode */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; + + + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + status = true; + } + return status; +} + + +// ***************************************************************************** +/* Function: + void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0TxFifoCallbackObj.callback = callback; + can0TxFifoCallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_TX_EVENT_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0TxEventFifoCallbackObj.callback = callback; + can0TxEventFifoCallbackObj.context = contextHandle; + + } +} + + +// ***************************************************************************** +/* Function: + void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO Number + + callback - A pointer to a function with a calling signature defined + by the CAN_RX_FIFO_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0RxFifoCallbackObj[rxFifoNum].callback = callback; + can0RxFifoCallbackObj[rxFifoNum].context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) + + Summary: + Sets the pointer to the function (and it's context) to be called when the + given CAN's transfer events occur. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + callback - A pointer to a function with a calling signature defined + by the CAN_CALLBACK data type. + + contextHandle - A value (usually a pointer) passed (unused) into the function + identified by the callback parameter. + + Returns: + None. +*/ +void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) +{ + if (callback != NULL) + { + can0CallbackObj.callback = callback; + can0CallbackObj.context = contextHandle; + } +} + +// ***************************************************************************** +/* Function: + void CAN0_InterruptHandler(void) + + Summary: + CAN0 Peripheral Interrupt Handler. + + Description: + This function is CAN0 Peripheral Interrupt Handler and will + called on every CAN0 interrupt. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Remarks: + The function is called as peripheral instance's interrupt handler if the + instance interrupt is enabled. If peripheral instance's interrupt is not + enabled user need to call it from the main while loop of the application. +*/ +void __attribute__((used)) CAN0_InterruptHandler(void) +{ + uint8_t numberOfMessage = 0; + uint8_t numberOfTxEvent = 0; + + uint32_t ir = CAN0_REGS->CAN_IR; + + /* Additional temporary variable used to prevent MISRA violations (Rule 13.x) */ + uintptr_t context; + + if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) + { + CAN0_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); + if (can0CallbackObj.callback != NULL) + { + context = can0CallbackObj.context; + can0CallbackObj.callback(ir, context); + } + } + /* New Message in Rx FIFO 0 */ + if ((ir & CAN_IR_RF0N_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_RF0N_Msk; + + numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); + + if (can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) + { + context = can0RxFifoCallbackObj[CAN_RX_FIFO_0].context; + can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, context); + } + } + /* New Message in Rx FIFO 1 */ + if ((ir & CAN_IR_RF1N_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_RF1N_Msk; + + numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); + + if (can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) + { + context = can0RxFifoCallbackObj[CAN_RX_FIFO_1].context; + can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, context); + } + } + + /* TX FIFO is empty */ + if ((ir & CAN_IR_TFE_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_TFE_Msk; + if (can0TxFifoCallbackObj.callback != NULL) + { + context = can0TxFifoCallbackObj.context; + can0TxFifoCallbackObj.callback(context); + } + } + /* Tx Event FIFO new entry */ + if ((ir & CAN_IR_TEFN_Msk) != 0U) + { + CAN0_REGS->CAN_IR = CAN_IR_TEFN_Msk; + + numberOfTxEvent = (uint8_t)(CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); + + if (can0TxEventFifoCallbackObj.callback != NULL) + { + context = can0TxEventFifoCallbackObj.context; + can0TxEventFifoCallbackObj.callback(numberOfTxEvent, context); + } + } +} + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.h new file mode 100644 index 00000000..63404486 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.h @@ -0,0 +1,123 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_can0.h + + Summary: + CAN PLIB interface declarations. + + Description: + The CAN plib provides a simple interface to manage the CAN modules on + Microchip microcontrollers. This file defines the interface declarations + for the CAN plib. + + Remarks: + None. + +*******************************************************************************/ +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END + +#ifndef PLIB_CAN0_H +#define PLIB_CAN0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +/* + * This section lists the other files that are included in this file. + */ +#include +#include + +#include "device.h" +#include "plib_can_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +#define CAN0_CLOCK_FREQUENCY 48000000U + +/* CAN0 Message RAM Configuration Size */ +#define CAN0_RX_FIFO0_ELEMENT_SIZE 16U +#define CAN0_RX_FIFO0_SIZE 16U +#define CAN0_RX_FIFO1_ELEMENT_SIZE 16U +#define CAN0_RX_FIFO1_SIZE 16U +#define CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE 16U +#define CAN0_TX_FIFO_BUFFER_SIZE 16U +#define CAN0_TX_EVENT_FIFO_SIZE 8U + +/* CAN0_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver + for allocating buffer from non-cached contiguous memory */ +#define CAN0_MESSAGE_RAM_CONFIG_SIZE 56U + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +void CAN0_Initialize(void); +bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); +uint8_t CAN0_TxFifoFreeLevelGet(void); +bool CAN0_TxBufferIsBusy(uint8_t bufferNumber); +bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); +bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); +CAN_ERROR CAN0_ErrorGet(void); +void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); +void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); +void CAN0_SleepModeEnter(void); +void CAN0_SleepModeExit(void); +bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); +bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming); +void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); +void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif +// DOM-IGNORE-END + +#endif // PLIB_CAN0_H + +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can_common.h new file mode 100644 index 00000000..b5f9f963 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can_common.h @@ -0,0 +1,668 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_can_common.h + + Summary + CAN peripheral library interface. + + Description + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_CAN_COMMON_H +#define PLIB_CAN_COMMON_H + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + + // ***************************************************************************** +/* CAN Transfer Errors + + Summary: + CAN Transfer Error macros. + + Description: + Helper macros to identify CAN errors. + + Remarks: + None. +*/ + +#define CAN_ERROR_NONE 0x0U +#define CAN_ERROR_LEC_STUFF 0x1U +#define CAN_ERROR_LEC_FORM 0x2U +#define CAN_ERROR_LEC_ACK 0x3U +#define CAN_ERROR_LEC_BIT1 0x4U +#define CAN_ERROR_LEC_BIT0 0x5U +#define CAN_ERROR_LEC_CRC 0x6U +#define CAN_ERROR_LEC_NC 0x7U +#define CAN_ERROR_PASSIVE 0x20U +#define CAN_ERROR_WARNING_STATUS 0x40U +#define CAN_ERROR_BUS_OFF 0x80U +#define CAN_ERROR_DLEC_STUFF 0x100U +#define CAN_ERROR_DLEC_FORM 0x200U +#define CAN_ERROR_DLEC_ACK 0x300U +#define CAN_ERROR_DLEC_BIT1 0x400U +#define CAN_ERROR_DLEC_BIT0 0x500U +#define CAN_ERROR_DLEC_CRC 0x600U +#define CAN_ERROR_DLEC_NC 0x700U +#define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U +#define CAN_ERROR_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* CAN Rx FIFO Number + + Summary: + CAN Rx FIFO Number. + + Description: + This data type defines CAN Rx FIFO number for Rx FIFO0 and FIFO1. + + Remarks: + None. +*/ +typedef enum +{ + CAN_RX_FIFO_0 = 0U, + CAN_RX_FIFO_1 +} CAN_RX_FIFO_NUM; + +// ***************************************************************************** +/* CAN Interrupt Mask + + Summary: + CAN Interrupt Mask. + + Description: + This data type defines the CAN Interrupt sources number. + + Remarks: + None. +*/ +typedef enum +{ + CAN_INTERRUPT_RF0N_MASK = (1UL << 0U), + CAN_INTERRUPT_RF0W_MASK = (1UL << 1U), + CAN_INTERRUPT_RF0F_MASK = (1UL << 2U), + CAN_INTERRUPT_RF0L_MASK = (1UL << 3U), + CAN_INTERRUPT_RF1N_MASK = (1UL << 4U), + CAN_INTERRUPT_RF1W_MASK = (1UL << 5U), + CAN_INTERRUPT_RF1F_MASK = (1UL << 6U), + CAN_INTERRUPT_RF1L_MASK = (1UL << 7U), + CAN_INTERRUPT_HPM_MASK = (1UL << 8U), + CAN_INTERRUPT_TC_MASK = (1UL << 9U), + CAN_INTERRUPT_TCF_MASK = (1UL << 10U), + CAN_INTERRUPT_TFE_MASK = (1UL << 11U), + CAN_INTERRUPT_TEFN_MASK = (1UL << 12U), + CAN_INTERRUPT_TEFW_MASK = (1UL << 13U), + CAN_INTERRUPT_TEFF_MASK = (1UL << 14U), + CAN_INTERRUPT_TEFL_MASK = (1UL << 15U), + CAN_INTERRUPT_TSW_MASK = (1UL << 16U), + CAN_INTERRUPT_MRAF_MASK = (1UL << 17U), + CAN_INTERRUPT_TOO_MASK = (1UL << 18U), + CAN_INTERRUPT_DRX_MASK = (1UL << 19U), + CAN_INTERRUPT_ELO_MASK = (1UL << 22U), + CAN_INTERRUPT_EP_MASK = (1UL << 23U), + CAN_INTERRUPT_EW_MASK = (1UL << 24U), + CAN_INTERRUPT_BO_MASK = (1UL << 25U), + CAN_INTERRUPT_WDI_MASK = (1UL << 26U), + CAN_INTERRUPT_PEA_MASK = (1UL << 27U), + CAN_INTERRUPT_PED_MASK = (1UL << 28U), + CAN_INTERRUPT_ARA_MASK = (1UL << 29U) +}CAN_INTERRUPT_MASK; + +// ***************************************************************************** +/* CAN Transfer Error + + Summary: + CAN Transfer Error data type. + + Description: + This data type defines the CAN Transfer Error. + + Remarks: + None. +*/ +typedef uint32_t CAN_ERROR; + +// ***************************************************************************** +/* CAN Tx FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_FIFO_CALLBACK) (uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN TX/RX Buffers Callback + + Summary: + CAN Callback Function Pointer for TX/RX Buffers. + + Description: + This data type defines the CAN Callback Function Pointer for TX/RX Buffers. + + Remarks: + None. +*/ +typedef void (*CAN_TXRX_BUFFERS_CALLBACK) (uint8_t bufferNumber, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx Event FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx Event FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_EVENT_FIFO_CALLBACK) (uint8_t numberOfTxEvent, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback + + Summary: + CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Description: + This data type defines the CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Remarks: + None. +*/ +typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Callback + + Summary: + CAN Callback Function Pointer. + + Description: + This data type defines the CAN Callback Function Pointer. + + Remarks: + None. +*/ +typedef void (*CAN_CALLBACK) (uint32_t interruptStatus, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Message RAM Configuration + + Summary: + CAN Message RAM Configuration structure. + + Description: + This data structure defines the CAN Message RAM Base address for Rx FIFO0, + Rx FIFO1, Rx Buffers, Tx Buffers/FIFO, Tx Event FIFO, Standard Message ID Filter and + Extended Message ID Filter configuration. + + Remarks: + None. +*/ +typedef struct +{ + /* Rx FIFO0 base address */ + can_rxf0e_registers_t *rxFIFO0Address; + + /* Rx FIFO1 base address */ + can_rxf1e_registers_t *rxFIFO1Address; + + /* Rx Buffer base address */ + can_rxbe_registers_t *rxBuffersAddress; + + /* Tx Buffers/FIFO base address */ + can_txbe_registers_t *txBuffersAddress; + + /* Tx Event FIFO base address */ + can_txefe_registers_t *txEventFIFOAddress; + + /* Standard Message ID Filter base address */ + can_sidfe_registers_t *stdMsgIDFilterAddress; + + /* Extended Message ID Filter base address */ + can_xidfe_registers_t *extMsgIDFilterAddress; +} CAN_MSG_RAM_CONFIG; + +// ***************************************************************************** +/* CAN Rx Buffer and FIFO Element + + Summary: + CAN Rx Buffer and FIFO Element Structure. + + Description: + This data structure defines CAN Rx Buffer and FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Rx Timestamp */ + unsigned int rxts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :2; + /* Filter Index */ + unsigned int fidx:7; + /* Accepted Non-matching Frame */ + unsigned int anmf:1; + + /* Data field */ + uint8_t data[8]; + +} CAN_RX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Buffer Element + + Summary: + CAN Tx Buffer Element Structure. + + Description: + This data structure defines CAN Tx Buffer Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Reserved */ + unsigned int :16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :1; + /* Event FIFO Control */ + unsigned int efc:1; + /* Message Marker */ + unsigned int mm:8; + + /* Data field */ + uint8_t data[8]; + +} CAN_TX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Event FIFO Element + + Summary: + CAN Tx Event FIFO Element Structure. + + Description: + This data structure defines CAN Tx Event FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Tx Timestamp */ + unsigned int txts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switch */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Event Type */ + unsigned int et:2; + /* Message Marker */ + unsigned int mm:8; + +} CAN_TX_EVENT_FIFO; + +// ***************************************************************************** +/* CAN Nominal Bit Timing Parameters + + Summary: + CAN Nominal Bit Timing Parameter structure. + + Description: + This data structure defines Nominal Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal Time segment after sample point */ + uint8_t nominalTimeSegment2; + + /* Nominal Time segment before sample point */ + uint8_t nominalTimeSegment1; + + /* Nominal Baud Rate Prescaler */ + uint16_t nominalPrescaler; + + /* Nominal Syncronization Jump Width */ + uint8_t nominalSJW; + +} CAN_NOMINAL_BIT_TIMING; + +// ***************************************************************************** +/* CAN Data Bit Timing Parameters + + Summary: + CAN Data Bit Timing Parameter structure. + + Description: + This data structure defines Data Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Data Time segment after sample point */ + uint8_t dataTimeSegment2; + + /* Data Time segment before sample point */ + uint8_t dataTimeSegment1; + + /* Data Baud Rate Prescaler */ + uint8_t dataPrescaler; + + /* Data Syncronization Jump Width */ + uint8_t dataSJW; + +} CAN_DATA_BIT_TIMING; + +// ***************************************************************************** +/* CAN Bit Timing Parameters + + Summary: + CAN Bit Timing Parameter structure. + + Description: + This data structure defines Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal bit timing set flag */ + bool nominalBitTimingSet; + + /* Nominal bit timing parameters */ + CAN_NOMINAL_BIT_TIMING nominalBitTiming; + + /* Data bit timing set flag */ + bool dataBitTimingSet; + + /* Data bit timing parameters */ + CAN_DATA_BIT_TIMING dataBitTiming; +} CAN_BIT_TIMING; + +// ***************************************************************************** +/* CAN Bit Timing Setup + + Summary: + CAN Bit Timing Setup structure. + + Description: + This data structure defines Bit Timing Setup parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal bit timing set flag */ + bool nominalBitTimingSet; + + /* Nominal bit rate */ + uint32_t nominalBitRate; + + /* Nominal Sample Point */ + float nominalSamplePoint; + + /* Nominal Baud Rate Prescaler */ + uint16_t nominalPrescaler; + + /* Data bit timing set flag */ + bool dataBitTimingSet; + + /* Data bit rate */ + uint32_t dataBitRate; + + /* Data Sample Point */ + float dataSamplePoint; + + /* Data Baud Rate Prescaler */ + uint8_t dataPrescaler; + +} CAN_BIT_TIMING_SETUP; + +// ***************************************************************************** +/* CAN Tx FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx/Rx Buffers Callback Object + + Summary: + CAN transfer event callback structure for Tx/Rx Buffers. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TXRX_BUFFERS_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TXRX_BUFFERS_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx Event FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_EVENT_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_EVENT_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback Object + + Summary: + CAN transfer event callback structure for Rx FIFO0/FIFO1. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_RX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_RX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Callback Object + + Summary: + CAN interrupt status callback structure. + + Description: + This data structure stores interrupt status callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* CAN Interrupt Status Callback */ + CAN_CALLBACK callback; + + /* CAN Interrupt Status Callback Context */ + uintptr_t context; +} CAN_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN PLib Instance Object + + Summary: + CAN PLib Object structure. + + Description: + This data structure defines the CAN PLib Instance Object. + + Remarks: + None. +*/ +typedef struct +{ + /* Message RAM Configuration */ + CAN_MSG_RAM_CONFIG msgRAMConfig; + +} CAN_OBJ; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif //PLIB_CAN_COMMON_H +/******************************************************************************* + End of File +*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.c new file mode 100644 index 00000000..2403a77b --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.c @@ -0,0 +1,148 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.c + + Summary: + CLOCK PLIB Implementation File. + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_clock.h" +#include "device.h" +#include "interrupts.h" + + + + +static void OSCCTRL_Initialize(void) +{ + uint32_t calibValue = (uint32_t)(((*(uint64_t*)0x00806020UL) >> 19 ) & 0x3fffffUL); + OSCCTRL_REGS->OSCCTRL_CAL48M = calibValue; + + + /* Selection of the Division Value */ + OSCCTRL_REGS->OSCCTRL_OSC48MDIV = (uint8_t)OSCCTRL_OSC48MDIV_DIV(0UL); + + while((OSCCTRL_REGS->OSCCTRL_OSC48MSYNCBUSY & OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) == OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) + { + /* Waiting for the synchronization */ + } + + while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_OSC48MRDY_Msk) != OSCCTRL_STATUS_OSC48MRDY_Msk) + { + /* Waiting for the OSC48M Ready state */ + } + OSCCTRL_REGS->OSCCTRL_OSC48MCTRL |= OSCCTRL_OSC48MCTRL_ONDEMAND_Msk; + +} + +static void OSC32KCTRL_Initialize(void) +{ + OSC32KCTRL_REGS->OSC32KCTRL_OSC32K = 0x0UL; + + OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0UL); +} + + + +static void GCLK0_Initialize(void) +{ + + GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1UL) | GCLK_GENCTRL_SRC(6UL) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL0_Msk) == GCLK_SYNCBUSY_GENCTRL0_Msk) + { + /* wait for the Generator 0 synchronization */ + } +} + +void CLOCK_Initialize (void) +{ + /* Function to Initialize the Oscillators */ + OSCCTRL_Initialize(); + + /* Function to Initialize the 32KHz Oscillators */ + OSC32KCTRL_Initialize(); + + GCLK0_Initialize(); + + + /* Selection of the Generator and write Lock for EIC */ + GCLK_REGS->GCLK_PCHCTRL[2] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[2] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM0_CORE */ + GCLK_REGS->GCLK_PCHCTRL[19] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[19] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM1_CORE */ + GCLK_REGS->GCLK_PCHCTRL[20] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[20] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM3_CORE */ + GCLK_REGS->GCLK_PCHCTRL[22] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[22] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for CAN0 */ + GCLK_REGS->GCLK_PCHCTRL[26] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[26] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Configure the AHB Bridge Clocks */ + MCLK_REGS->MCLK_AHBMASK = 0x1dffU; + + + + /* Configure the APBC Bridge Clocks */ + MCLK_REGS->MCLK_APBCMASK = 0x16U; + + +} + + + diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.h new file mode 100644 index 00000000..71d6690a --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.h @@ -0,0 +1,143 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.h + + Summary: + CLOCK PLIB Header File. + + Description: + The Clock PLIB initializes all the oscillators based on the + requirements. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_CLOCK_H +#define PLIB_CLOCK_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void CLOCK_Initialize (void); + + Summary: + Initializes all the modules related to the system clock. + + Description: + This function initializes the clock as defined by the MHC and Clock Manager + selections. The function will configure the NVM Flash Wait states based on + the configured CPU operational frequency. It will then configure the + oscillators. + + For each of the clock sources (External Oscillator, Digital Phase Locked + Loop, Internal 48MHz Oscillator, External 32KHz oscillator and the Internal + 32KHz oscillator) enabled in MHC, the function will configure the clock + settings and will then wait till the clock is ready. In case of DPLL, the + function will wait till a lock is obtained. + + The function will then configure the Generic clock generators based on MHC + configurations. If a Generic Clock is enabled in MHC, this will be enabled + in the CLOCK_Initialize() function. The function will apply the CPU clock + divider and will wait for the Main Clock module to get ready. If the Main + Clock to the Peripheral APB and AHB interfaces was enabled in MHC, these + will be enabled in the CLOCK_Initialize() function. If the Peripheral Clock + Channels were enabled in MHC, these will be enabled in the + CLOCK_Initialize() function. + + The peripheral AHB and APB main clock and peripheral channel clocks will be + enabled when the peripheral specific initialize functions are called. This + will override the setting in MHC. The Generic Clock Generator source for + desired peripheral channel must be configured in MHC. + + Precondition: + MHC GUI should be configured with the right values. Incorrect configuration + of the Clock will result in incorrect peripheral behavior or a non + functional device. + + Parameters: + None. + + Returns: + None. + + Example: + + CLOCK_Initialize(); + + + Remarks: + This function should be called before calling other Clock library functions. +*/ + +void CLOCK_Initialize (void); + + + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_CLOCK_H */ + diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.c new file mode 100644 index 00000000..e87bf923 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.c @@ -0,0 +1,114 @@ +/******************************************************************************* + External Interrupt Controller (EIC) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_eic.c + + Summary + Source for EIC peripheral library interface Implementation. + + Description + This file defines the interface to the EIC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_eic.h" +#include "interrupts.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + + + +void EIC_Initialize (void) +{ + /* Reset all registers in the EIC module to their initial state and + EIC will be disabled. */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_SWRST_Msk; + + while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_SWRST_Msk) == EIC_SYNCBUSY_SWRST_Msk) + { + /* Wait for sync */ + } + + /* EIC is by default clocked by GCLK */ + + /* NMI Control register */ + + /* Interrupt sense type and filter control for EXTINT channels 0 to 7*/ + EIC_REGS->EIC_CONFIG[0] = EIC_CONFIG_SENSE0_NONE | + EIC_CONFIG_SENSE1_NONE | + EIC_CONFIG_SENSE2_NONE | + EIC_CONFIG_SENSE3_NONE | + EIC_CONFIG_SENSE4_NONE | + EIC_CONFIG_SENSE5_NONE | + EIC_CONFIG_SENSE6_NONE | + EIC_CONFIG_SENSE7_NONE ; + + /* Interrupt sense type and filter control for EXTINT channels 8 to 15 */ + EIC_REGS->EIC_CONFIG[1] = EIC_CONFIG_SENSE0_NONE + | EIC_CONFIG_SENSE1_NONE + | EIC_CONFIG_SENSE2_NONE + | EIC_CONFIG_SENSE3_NONE + | EIC_CONFIG_SENSE4_NONE + | EIC_CONFIG_SENSE5_NONE + | EIC_CONFIG_SENSE6_NONE + | EIC_CONFIG_SENSE7_NONE ; + + + + + + + /* Enable the EIC */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_ENABLE_Msk; + + while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_ENABLE_Msk) == EIC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for sync */ + } +} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.h new file mode 100644 index 00000000..3e50f6bf --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.h @@ -0,0 +1,189 @@ +/******************************************************************************* External Interrupt Controller (EIC) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_eic.h + + Summary + EIC PLIB Header File. + + Description + This file defines the interface to the EIC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +/* Guards against multiple inclusion */ +#ifndef PLIB_EIC_H +#define PLIB_EIC_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part of it. +*/ + +/* EIC Pin Count */ +#define EXTINT_COUNT (16U) + +// ***************************************************************************** +/* EIC Pins + + Summary: + Identifies the available EIC pins. + + Description: + This enumeration identifies all the available EIC pins. Not all pins will be + implemented in a device. The pins described here are for documentation + purposes only. The MHC will generate this enumeration with the enabled EIC + pins only. The application should not use the constant value that are + assigned to enumeration constants as this may vary between devices. + + Remarks: + None. +*/ + + + /* External Interrupt Controller Pin 11 */ +#define EIC_PIN_11 (11U) + + /* External Interrupt Controller Pin 14 */ +#define EIC_PIN_14 (14U) + +#define EIC_PIN_MAX (16U) + +typedef uint16_t EIC_PIN; + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +// ***************************************************************************** +/* Function: + void EIC_Initialize (void); + + Summary: + Initializes given instance of EIC peripheral. + + Description: + This function initializes given instance of EIC peripheral of the device + with the values configured in MHC GUI. + + Precondition: + MHC GUI should be configured with the right values. + + Parameters: + None. + + Returns: + None. + + Example: + + EIC_Initialize(); + + + Remarks: + This function should only be called once during system initialization + before any other EIC function is called. +*/ + +void EIC_Initialize (void); + +// ***************************************************************************** +/* Function: + void EIC_InterruptEnable (EIC_PIN pin) + + Summary: + Enables interrupts on a pin. + + Description + This function enables interrupts on an external interrupt pin. + When enabled, the interrupt pin sense will be configured as per the + configuration set in MHC. + + Precondition: + EIC_Initialize() function must have been called for the + associated instance. + + Parameters: + pin - EIC Pin number + + Returns: + None + + Example: + + EIC_Initialize(); + EIC_InterruptEnable(EIC_PIN_3); + + + Remarks: + None. +*/ + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +#endif /* PLIB_EIC_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.c new file mode 100644 index 00000000..0876df57 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.c @@ -0,0 +1,52 @@ +/******************************************************************************* + EVSYS Peripheral Library + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.c + + Summary: + EVSYS Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_evsys.h" +#include "interrupts.h" + + +void EVSYS_Initialize( void ) +{ /*Event Channel User Configuration*/ + + +} + + + diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.h new file mode 100644 index 00000000..9ea8b02b --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.h @@ -0,0 +1,68 @@ +/******************************************************************************* + Interface definition of EVSYS PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.h + + Summary: + Interface definition of the Event System Plib (EVSYS). + + Description: + This file defines the interface for the EVSYS Plib. + It allows user to setup event generators and users. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef EVSYS_H // Guards against multiple inclusion +#define EVSYS_H + +#include "device.h" +#include +#include + +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface +// ***************************************************************************** +// ***************************************************************************** + + + +/***************************** EVSYS API *******************************/ +void EVSYS_Initialize( void ); + +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif + +#endif diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.c new file mode 100644 index 00000000..d0a400c4 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.c @@ -0,0 +1,127 @@ +/******************************************************************************* + NVIC PLIB Implementation + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.c + + Summary: + NVIC PLIB Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "device.h" +#include "plib_nvic.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVIC Implementation +// ***************************************************************************** +// ***************************************************************************** + +void NVIC_Initialize( void ) +{ + + /* Enable NVIC Controller */ + __DMB(); + __enable_irq(); + + /* Enable the interrupt sources and configure the priorities as configured + * from within the "Interrupt Manager" of MHC. */ + NVIC_SetPriority(RTC_IRQn, 3); + NVIC_EnableIRQ(RTC_IRQn); + NVIC_SetPriority(SERCOM0_IRQn, 3); + NVIC_EnableIRQ(SERCOM0_IRQn); + NVIC_SetPriority(SERCOM1_IRQn, 3); + NVIC_EnableIRQ(SERCOM1_IRQn); + NVIC_SetPriority(SERCOM3_IRQn, 3); + NVIC_EnableIRQ(SERCOM3_IRQn); + NVIC_SetPriority(CAN0_IRQn, 3); + NVIC_EnableIRQ(CAN0_IRQn); + + + + +} + +void NVIC_INT_Enable( void ) +{ + __DMB(); + __enable_irq(); +} + +bool NVIC_INT_Disable( void ) +{ + bool processorStatus = (__get_PRIMASK() == 0U); + + __disable_irq(); + __DMB(); + + return processorStatus; +} + +void NVIC_INT_Restore( bool state ) +{ + if( state == true ) + { + __DMB(); + __enable_irq(); + } + else + { + __disable_irq(); + __DMB(); + } +} + +bool NVIC_INT_SourceDisable( IRQn_Type source ) +{ + bool processorStatus; + bool intSrcStatus; + + processorStatus = NVIC_INT_Disable(); + intSrcStatus = (NVIC_GetEnableIRQ(source) != 0U); + NVIC_DisableIRQ( source ); + NVIC_INT_Restore( processorStatus ); + + /* return the source status */ + return intSrcStatus; +} + +void NVIC_INT_SourceRestore( IRQn_Type source, bool status ) +{ + if( status ) { + NVIC_EnableIRQ( source ); + } + + return; +} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.h new file mode 100644 index 00000000..6d36bd14 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.h @@ -0,0 +1,72 @@ +/******************************************************************************* + NVIC PLIB Header + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.h + + Summary: + NVIC PLIB Header File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_NVIC_H +#define PLIB_NVIC_H + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + + +/***************************** NVIC Inline *******************************/ + +void NVIC_Initialize( void ); +void NVIC_INT_Enable( void ); +bool NVIC_INT_Disable( void ); +void NVIC_INT_Restore( bool state ); +bool NVIC_INT_SourceDisable( IRQn_Type source ); +void NVIC_INT_SourceRestore( IRQn_Type source, bool status ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END +#endif // PLIB_NVIC_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c new file mode 100644 index 00000000..36679253 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -0,0 +1,260 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.c + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include "interrupts.h" +#include "plib_nvmctrl.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVMCTRL Implementation +// ***************************************************************************** +// ***************************************************************************** + + +void NVMCTRL_Initialize(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY | NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS | NVMCTRL_CTRLB_RWS(2UL) | NVMCTRL_CTRLB_MANW_Msk; +} + +void NVMCTRL_CacheInvalidate(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_INVALL | NVMCTRL_CTRLA_CMDEX_KEY); +} +bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t *paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* Writing 32-bit words in the given address */ + for ( i = 0U; i < (NVMCTRL_RWWEEPROM_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEWP | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_RWWEEPROM_RowErase( uint32_t address ) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEER | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t *paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + return true; +} + +bool NVMCTRL_PageBufferCommit( const uint32_t address) +{ + uint16_t command = NVMCTRL_CTRLA_CMD_WP_Val; + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + if (address >= NVMCTRL_RWWEEPROM_START_ADDRESS) + { + command = NVMCTRL_CTRLA_CMD_RWWEEWP; + } + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(command | NVMCTRL_CTRLA_CMDEX_KEY); + + + return true; +} + +bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_WP_Val | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_RowErase( uint32_t address ) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_ER_Val | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + bool pagewrite_val = false; + + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= ((NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE) - NVMCTRL_USERROW_PAGESIZE))) + { + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_USERROW_PAGESIZE/4U); i++) + { + *paddress = data[i]; + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_WAP_Val | NVMCTRL_CTRLA_CMDEX_KEY; + + + pagewrite_val = true; + } + + return pagewrite_val; +} + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ) +{ + bool rowerase = false; + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= (NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE))) + { + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_EAR_Val | NVMCTRL_CTRLA_CMDEX_KEY; + + + rowerase = true; + } + + return rowerase; +} + +NVMCTRL_ERROR NVMCTRL_ErrorGet( void ) +{ + uint16_t nvm_error; + + /* Get the error bits set */ + nvm_error = (NVMCTRL_REGS->NVMCTRL_STATUS & (NVMCTRL_STATUS_NVME_Msk | NVMCTRL_STATUS_LOCKE_Msk | NVMCTRL_STATUS_PROGE_Msk)); + + /* Clear the error bits in both STATUS and INTFLAG register */ + NVMCTRL_REGS->NVMCTRL_STATUS |= nvm_error; + + NVMCTRL_REGS->NVMCTRL_INTFLAG = NVMCTRL_INTFLAG_ERROR_Msk; + + return ((NVMCTRL_ERROR) nvm_error); +} + +bool NVMCTRL_IsBusy(void) +{ + return ((NVMCTRL_REGS->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_READY_Msk)!= NVMCTRL_INTFLAG_READY_Msk); +} + +void NVMCTRL_RegionLock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_LR_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} + +void NVMCTRL_RegionUnlock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_UR_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} + +void NVMCTRL_SecurityBitSet(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_SSB_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h new file mode 100644 index 00000000..365c2866 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h @@ -0,0 +1,137 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.h + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_NVMCTRL_H +#define PLIB_NVMCTRL_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + +#define NVMCTRL_FLASH_START_ADDRESS (0x00000000U) +#define NVMCTRL_FLASH_PAGESIZE (64U) +#define NVMCTRL_FLASH_ROWSIZE (256U) + +#define NVMCTRL_EMULATED_EEPROM_START_ADDRESS (0x40000U) +#define NVMCTRL_EMULATED_EEPROM_PAGESIZE (64U) +#define NVMCTRL_EMULATED_EEPROM_SIZE (0U) + +#define NVMCTRL_RWWEEPROM_START_ADDRESS (0x00400000U) +#define NVMCTRL_RWWEEPROM_SIZE (0x2000U) +#define NVMCTRL_RWWEEPROM_PAGESIZE (64U) +#define NVMCTRL_RWWEEPROM_ROWSIZE (256U) + +#define NVMCTRL_USERROW_START_ADDRESS (0x00804000U) +#define NVMCTRL_USERROW_SIZE (0x100U) +#define NVMCTRL_USERROW_PAGESIZE (64U) + +#define NVMCTRL_ERROR_NONE 0x0U +#define NVMCTRL_ERROR_PROG 0x4U +#define NVMCTRL_ERROR_LOCK 0x8U +#define NVMCTRL_ERROR_NVM 0x10U + +typedef uint16_t NVMCTRL_ERROR; + + +void NVMCTRL_Initialize(void); + +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ); + + +bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address); + +bool NVMCTRL_PageBufferCommit( const uint32_t address); + + +bool NVMCTRL_RowErase( uint32_t address ); + +bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_RWWEEPROM_RowErase ( uint32_t address ); + +NVMCTRL_ERROR NVMCTRL_ErrorGet( void ); + +bool NVMCTRL_IsBusy( void ); + +void NVMCTRL_RegionLock (uint32_t address); + +void NVMCTRL_RegionUnlock (uint32_t address); + +void NVMCTRL_SecurityBitSet(void); + + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ); + +void NVMCTRL_CacheInvalidate ( void ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END +#endif // PLIB_NVMCTRL_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.c new file mode 100644 index 00000000..53c22749 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.c @@ -0,0 +1,309 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.c + + Summary: + Interface definition of PORT PLIB + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_port.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_IN); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value) +{ + /* Write the desired value */ + ((port_group_registers_t*)group)->PORT_OUT = (((port_group_registers_t*)group)->PORT_OUT & (~mask)) | (mask & value); +} + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_OUT); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTCLR = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTTGL = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRCLR = mask; + + for(uint32_t i = 0U; i < 32U; i++) + { + if((mask & ((uint32_t)1U << i)) != 0U) + { + ((port_group_registers_t*)group)->PORT_PINCFG[i] |= PORT_PINCFG_INEN_Msk; + } + } +} + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) +{ + uint32_t periph_func = (uint32_t) function; + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + uint32_t pinmux_val = (uint32_t)((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)]; + + /* For odd pins */ + if (0U != (pin_num & 0x01U)) + { + pinmux_val = (pinmux_val & ~0xF0U) | (periph_func << 4); + } + else + { + pinmux_val = (pinmux_val & ~0x0FU) | periph_func; + } + ((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)] = (uint8_t)pinmux_val; + + /* Enable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] |= (uint8_t)PORT_PINCFG_PMUXEN_Msk; +} + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinGPIOConfig(PORT_PIN pin) +{ + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + + /* Disable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); +} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.h new file mode 100644 index 00000000..b52fe9c4 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.h @@ -0,0 +1,918 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.h + + Summary: + PORT PLIB Header File + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_PORT_H +#define PLIB_PORT_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data types and constants +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* PORT Group + + Summary: + Identifies the port groups available on the device. + + Description: + These macros identifies all the ports groups that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the preprocessor macros as these may vary between devices. + + Port groups shown here are the ones available on the selected device. Not + all ports groups are implemented. Refer to the device specific datasheet + for more details. The MHC will generate these macros with the port + groups that are available on the device. +*/ + +/* Group 0 */ +#define PORT_GROUP_0 (PORT_BASE_ADDRESS + (0U * 0x80U)) + + +/* Helper macros to get port information from the pin */ +#define GET_PORT_GROUP(pin) ((PORT_GROUP)(PORT_BASE_ADDRESS + (0x80U * (((uint32_t)pin) >> 5U)))) +#define GET_PIN_MASK(pin) (((uint32_t)(0x1U)) << (((uint32_t)pin) & 0x1FU)) + +/* Named type for port group */ +typedef uint32_t PORT_GROUP; + + +typedef enum +{ +PERIPHERAL_FUNCTION_A = 0x0, +PERIPHERAL_FUNCTION_B = 0x1, +PERIPHERAL_FUNCTION_C = 0x2, +PERIPHERAL_FUNCTION_D = 0x3, +PERIPHERAL_FUNCTION_E = 0x4, +PERIPHERAL_FUNCTION_F = 0x5, +PERIPHERAL_FUNCTION_G = 0x6, +PERIPHERAL_FUNCTION_H = 0x7, +PERIPHERAL_FUNCTION_I = 0x8, + +}PERIPHERAL_FUNCTION; + +// ***************************************************************************** +/* PORT Pins + + Summary: + Identifies the available Ports pins. + + Description: + This enumeration identifies all the ports pins that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the enumeration constants as these may vary between devices. + + Port pins shown here are the ones available on the selected device. Not + all ports pins within a port group are implemented. Refer to the device + specific datasheet for more details. +*/ + +typedef enum +{ + /* PA00 pin */ + PORT_PIN_PA00 = 0U, + + /* PA01 pin */ + PORT_PIN_PA01 = 1U, + + /* PA02 pin */ + PORT_PIN_PA02 = 2U, + + /* PA03 pin */ + PORT_PIN_PA03 = 3U, + + /* PA04 pin */ + PORT_PIN_PA04 = 4U, + + /* PA05 pin */ + PORT_PIN_PA05 = 5U, + + /* PA06 pin */ + PORT_PIN_PA06 = 6U, + + /* PA07 pin */ + PORT_PIN_PA07 = 7U, + + /* PA08 pin */ + PORT_PIN_PA08 = 8U, + + /* PA09 pin */ + PORT_PIN_PA09 = 9U, + + /* PA10 pin */ + PORT_PIN_PA10 = 10U, + + /* PA11 pin */ + PORT_PIN_PA11 = 11U, + + /* PA14 pin */ + PORT_PIN_PA14 = 14U, + + /* PA15 pin */ + PORT_PIN_PA15 = 15U, + + /* PA16 pin */ + PORT_PIN_PA16 = 16U, + + /* PA17 pin */ + PORT_PIN_PA17 = 17U, + + /* PA18 pin */ + PORT_PIN_PA18 = 18U, + + /* PA19 pin */ + PORT_PIN_PA19 = 19U, + + /* PA22 pin */ + PORT_PIN_PA22 = 22U, + + /* PA23 pin */ + PORT_PIN_PA23 = 23U, + + /* PA24 pin */ + PORT_PIN_PA24 = 24U, + + /* PA25 pin */ + PORT_PIN_PA25 = 25U, + + /* PA27 pin */ + PORT_PIN_PA27 = 27U, + + /* PA28 pin */ + PORT_PIN_PA28 = 28U, + + /* PA30 pin */ + PORT_PIN_PA30 = 30U, + + /* PA31 pin */ + PORT_PIN_PA31 = 31U, + + /* This element should not be used in any of the PORT APIs. + * It will be used by other modules or application to denote that none of + * the PORT Pin is used */ + PORT_PIN_NONE = 65535U, + +} PORT_PIN; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Generated API based on pin configurations done in Pin Manager +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on multiple pins of a group +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the hardware state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_Read(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the output state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_GroupLatchRead(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + mask - A 32 bit value in which positions of 0s and 1s decide + which IO pins of the selected port group will be written. + 1's - Will write to corresponding IO pins. + 0's - Will remain unchanged. + + value - Value which has to be written/driven on the I/O + lines of the selected port for which mask bits are '1'. + Values for the corresponding mask bit '0' will be ignored. + Refer to the function description for effect on pins + which are not configured for output. + + Returns: + None. + + Example: + + + PORT_GroupWrite(PORT_GROUP_C, 0x0F, 0xF563D453); + + + + Remarks: + None. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 1. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupSet(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 1 on this pin will cause the pull + up to be enabled. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 0. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupClear(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will be toggled. If the + value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupToggle(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. Driving a logic 1 on this pin will cause the pull up to + be enabled. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + input. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupInputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + output. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupOutputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + None +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function); + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + None +*/ +void PORT_PinGPIOConfig(PORT_PIN pin); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on one pin at a time +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void PORT_PinWrite(PORT_PIN pin, bool value) + + Summary: + Writes the specified value to the selected pin. + + Description: + This function writes/drives the "value" on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called once. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + value - value to be written on the selected pin. + true = set pin to high (1). + false = clear pin to low (0). + + Returns: + None. + + Example: + + + bool value = true; + PORT_PinWrite(PORT_PIN_PB3, value); + + + + Remarks: + Calling this function with an input pin with the pull-up/pull-down feature + enabled will affect the pull-up/pull-down configuration. If the value is + false, the pull-down will be enabled. If the value is true, the pull-up will + be enabled. +*/ + +static inline void PORT_PinWrite(PORT_PIN pin, bool value) +{ + PORT_GroupWrite(GET_PORT_GROUP(pin), + GET_PIN_MASK(pin), + (value ? GET_PIN_MASK(pin) : 0U)); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinRead(PORT_PIN pin) + + Summary: + Read the selected pin value. + + Description: + This function reads the present state at the selected input pin. The + function can also be called to read the value of an output pin if input + sampling on the output pin is enabled in MHC. If input synchronization on + the pin is disabled in MHC, the function will cause a 2 PORT Clock cycles + delay. Enabling the synchronization eliminates the delay but will increase + power consumption. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + pin - the port pin whose state needs to be read. + + Returns: + true - the state at the pin is a logic high. + false - the state at the pin is a logic low. + + Example: + + + bool value; + value = PORT_PinRead(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline bool PORT_PinRead(PORT_PIN pin) +{ + return ((PORT_GroupRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinLatchRead(PORT_PIN pin) + + Summary: + Read the value driven on the selected pin. + + Description: + This function reads the data driven on the selected I/O line/pin. The + function does not sample the state of the hardware pin. It only returns the + value that is written to output register. Refer to the PORT_PinRead() + function if the state of the output pin needs to be read. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + true - the present value in the output latch is a logic high. + false - the present value in the output latch is a logic low. + + Example: + + + bool value; + value = PORT_PinLatchRead(PORT_PIN_PB3); + + + + Remarks: + To read actual pin value, PIN_Read API should be used. +*/ + +static inline bool PORT_PinLatchRead(PORT_PIN pin) +{ + return ((PORT_GroupLatchRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinToggle(PORT_PIN pin) + + Summary: + Toggles the selected pin. + + Description: + This function toggles/inverts the present value on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinToggle(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinToggle(PORT_PIN pin) +{ + PORT_GroupToggle(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinSet(PORT_PIN pin) + + Summary: + Sets the selected pin. + + Description: + This function drives a logic 1 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinSet(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinSet(PORT_PIN pin) +{ + PORT_GroupSet(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinClear(PORT_PIN pin) + + Summary: + Clears the selected pin. + + Description: + This function drives a logic 0 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinClear(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinClear(PORT_PIN pin) +{ + PORT_GroupClear(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinInputEnable(PORT_PIN pin) + + Summary: + Configures the selected IO pin as input. + + Description: + This function configures the selected IO pin as input. This function + override the MHC input output pin settings. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinInputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinInputEnable(PORT_PIN pin) +{ + PORT_GroupInputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinOutputEnable(PORT_PIN pin) + + Summary: + Enables selected IO pin as output. + + Description: + This function enables selected IO pin as output. Calling this function will + override the MHC input output pin configuration. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinOutputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinOutputEnable(PORT_PIN pin) +{ + PORT_GroupOutputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +} + +#endif +// DOM-IGNORE-END +#endif // PLIB_PORT_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc.h new file mode 100644 index 00000000..a68c0c25 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc.h @@ -0,0 +1,116 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc.h + + Summary: + RTC PLIB Header file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_RTC_H +#define PLIB_RTC_H + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +/* Frequency of Counter Clock for RTC */ +#define RTC_COUNTER_CLOCK_FREQUENCY (1024U / (1UL << (0x1U - 1U))) + +#define RTC_TIMER32_INT_MASK_PER0 RTC_MODE0_INTENSET_PER0_Msk +#define RTC_TIMER32_INT_MASK_PER1 RTC_MODE0_INTENSET_PER1_Msk +#define RTC_TIMER32_INT_MASK_PER2 RTC_MODE0_INTENSET_PER2_Msk +#define RTC_TIMER32_INT_MASK_PER3 RTC_MODE0_INTENSET_PER3_Msk +#define RTC_TIMER32_INT_MASK_PER4 RTC_MODE0_INTENSET_PER4_Msk +#define RTC_TIMER32_INT_MASK_PER5 RTC_MODE0_INTENSET_PER5_Msk +#define RTC_TIMER32_INT_MASK_PER6 RTC_MODE0_INTENSET_PER6_Msk +#define RTC_TIMER32_INT_MASK_PER7 RTC_MODE0_INTENSET_PER7_Msk +#define RTC_TIMER32_INT_MASK_CMP0 RTC_MODE0_INTENSET_CMP0_Msk +#define RTC_TIMER32_INT_MASK_OVF RTC_MODE0_INTENSET_OVF_Msk +#define RTC_TIMER32_INT_MASK_INVALID 0xFFFFFFFFU +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +typedef uint32_t RTC_TIMER32_INT_MASK; +typedef void (*RTC_TIMER32_CALLBACK)( RTC_TIMER32_INT_MASK intCause, uintptr_t context ); + +typedef struct +{ + /* Timer 32Bit */ + RTC_TIMER32_CALLBACK timer32BitCallback; + RTC_TIMER32_INT_MASK timer32intCause; + uintptr_t context; +} RTC_OBJECT; + +void RTC_Initialize(void); +void RTC_Timer32CountSyncEnable ( void ); +void RTC_Timer32CountSyncDisable ( void ); +void RTC_Timer32Start ( void ); +void RTC_Timer32Stop ( void ); +void RTC_Timer32CounterSet ( uint32_t count ); +uint32_t RTC_Timer32CounterGet ( void ); +uint32_t RTC_Timer32FrequencyGet ( void ); +void RTC_Timer32CompareSet ( uint32_t compareValue ); +uint32_t RTC_Timer32PeriodGet ( void ); +void RTC_Timer32InterruptEnable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32InterruptDisable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_RTC_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc_timer.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc_timer.c new file mode 100644 index 00000000..d6566db1 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc_timer.c @@ -0,0 +1,196 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc_timer.c + + Summary: + RTC PLIB Implementation file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance in timer mode. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_rtc.h" +#include + +static volatile RTC_OBJECT rtcObj; + + +void RTC_Initialize(void) +{ + RTC_REGS->MODE0.RTC_CTRLA = RTC_MODE0_CTRLA_SWRST_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_SWRST_Msk) == RTC_MODE0_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization after Software Reset */ + } + + + RTC_REGS->MODE0.RTC_CTRLA = (uint16_t)(RTC_MODE0_CTRLA_MODE(0UL) | RTC_MODE0_CTRLA_PRESCALER(0x1UL) | RTC_MODE0_CTRLA_COUNTSYNC_Msk |RTC_MODE0_CTRLA_MATCHCLR_Msk ); + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + RTC_REGS->MODE0.RTC_COMP = 0x65U; + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } + +} + + +void RTC_Timer32CountSyncEnable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32CountSyncDisable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_COUNTSYNC_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32Start ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_ENABLE_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for synchronization after Enabling RTC */ + } +} + + +void RTC_Timer32Stop ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_ENABLE_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization after Disabling RTC */ + } +} + +void RTC_Timer32CounterSet ( uint32_t count ) +{ + RTC_REGS->MODE0.RTC_COUNT = count; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization after writing value to Count Register */ + } +} + +void RTC_Timer32CompareSet ( uint32_t compareValue ) +{ + RTC_REGS->MODE0.RTC_COMP = compareValue; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } +} +uint32_t RTC_Timer32CounterGet ( void ) +{ + if ((RTC_REGS->MODE0.RTC_CTRLA & RTC_MODE0_CTRLA_COUNTSYNC_Msk) == 0U) + { + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + } + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization before reading value from Count Register */ + } + return(RTC_REGS->MODE0.RTC_COUNT); +} + +uint32_t RTC_Timer32PeriodGet ( void ) +{ + /* Get 32Bit Compare Value */ + /*lint -e{9048} PC lint incorrectly reports a missing 'U' Suffix */ + return (RTC_MODE0_COUNT_COUNT_Msk); +} + +uint32_t RTC_Timer32FrequencyGet ( void ) +{ + /* Return Frequency of RTC Clock */ + return RTC_COUNTER_CLOCK_FREQUENCY; +} + +void RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENSET = (uint16_t)interruptMask; +} + +void RTC_Timer32InterruptDisable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENCLR = (uint16_t)interruptMask; +} + + +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ) +{ + rtcObj.timer32BitCallback = callback; + rtcObj.context = context; +} + +void __attribute__((used)) RTC_InterruptHandler( void ) +{ + rtcObj.timer32intCause = (RTC_TIMER32_INT_MASK) RTC_REGS->MODE0.RTC_INTFLAG; + RTC_REGS->MODE0.RTC_INTFLAG = (uint16_t)RTC_MODE0_INTFLAG_Msk; + (void)RTC_REGS->MODE0.RTC_INTFLAG; + + /* Invoke registered Callback function */ + if(rtcObj.timer32BitCallback != NULL) + { + RTC_TIMER32_INT_MASK timer32intCause = rtcObj.timer32intCause; + uintptr_t context = rtcObj.context; + rtcObj.timer32BitCallback( timer32intCause, context ); + } +} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c new file mode 100644 index 00000000..6774f2e5 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c @@ -0,0 +1,680 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_sercom1_i2c.c + + Summary: + SERCOM I2C PLIB Implementation file + + Description: + This file defines the interface to the SERCOM I2C peripheral library. + This library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "interrupts.h" +#include "plib_sercom1_i2c_master.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + + +#define SERCOM1_I2CM_SPEED_HZ 100000 + +/* SERCOM1 I2C baud value */ +#define SERCOM1_I2CM_BAUD_VALUE (0xE8U) + + +static volatile SERCOM_I2C_OBJ sercom1I2CObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM1 I2C Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM1_I2C_Initialize(void) +{ + /* Reset the module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable smart mode */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Baud rate - Master Baud Rate*/ + SERCOM1_REGS->I2CM.SERCOM_BAUD = SERCOM1_I2CM_BAUD_VALUE; + + /* Set Operation Mode (Master), SDA Hold time, run in stand by and i2c master enable */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | SERCOM_I2CM_CTRLA_SDAHOLD_75NS | SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE | SERCOM_I2CM_CTRLA_SCLSM(0UL) | SERCOM_I2CM_CTRLA_ENABLE_Msk ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initial Bus State: IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize the SERCOM1 PLib Object */ + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Enable all Interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; +} + +static bool SERCOM1_I2C_CalculateBaudValue(uint32_t srcClkFreq, uint32_t i2cClkSpeed, uint32_t* baudVal) +{ + uint32_t baudValue = 0U; + float fSrcClkFreq = (float)srcClkFreq; + float fI2cClkSpeed = (float)i2cClkSpeed; + float fBaudValue = 0.0f; + + /* Reference clock frequency must be atleast two times the baud rate */ + if (srcClkFreq < (2U * i2cClkSpeed)) + { + return false; + } + + if (i2cClkSpeed <= 1000000U) + { + /* Standard, FM and FM+ baud calculation */ + fBaudValue = (fSrcClkFreq / fI2cClkSpeed) - ((fSrcClkFreq * (100.0f / 1000000000.0f)) + 10.0f); + baudValue = (uint32_t)fBaudValue; + } + else + { + return false; + } + if (i2cClkSpeed <= 400000U) + { + /* For I2C clock speed upto 400 kHz, the value of BAUD<7:0> determines both SCL_L and SCL_H with SCL_L = SCL_H */ + if (baudValue > (0xFFU * 2U)) + { + /* Set baud rate to the minimum possible value */ + baudValue = 0xFFU; + } + else if (baudValue <= 1U) + { + /* Baud value cannot be 0. Set baud rate to maximum possible value */ + baudValue = 1U; + } + else + { + baudValue /= 2U; + } + } + else + { + /* To maintain the ratio of SCL_L:SCL_H to 2:1, the max value of BAUD_LOW<15:8>:BAUD<7:0> can be 0xFF:0x7F. Hence BAUD_LOW + BAUD can not exceed 255+127 = 382 */ + if (baudValue >= 382U) + { + /* Set baud rate to the minimum possible value while maintaining SCL_L:SCL_H to 2:1 */ + baudValue = (0xFFUL << 8U) | (0x7FU); + } + else if (baudValue <= 3U) + { + /* Baud value cannot be 0. Set baud rate to maximum possible value while maintaining SCL_L:SCL_H to 2:1 */ + baudValue = (2UL << 8U) | 1U; + } + else + { + /* For Fm+ mode, I2C SCL_L:SCL_H to 2:1 */ + baudValue = ((((baudValue * 2U)/3U) << 8U) | (baudValue/3U)); + } + } + *baudVal = baudValue; + return true; +} + +bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ) +{ + uint32_t baudValue; + uint32_t i2cClkSpeed; + uint32_t i2cSpeedMode = 0; + + if (setup == NULL) + { + return false; + } + + i2cClkSpeed = setup->clkSpeed; + + if( srcClkFreq == 0U) + { + srcClkFreq = 48000000UL; + } + + if (SERCOM1_I2C_CalculateBaudValue(srcClkFreq, i2cClkSpeed, &baudValue) == false) + { + return false; + } + + if (i2cClkSpeed > 400000U) + { + i2cSpeedMode = 1U; + } + + /* Disable the I2C before changing the I2C clock speed */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Baud rate - Master Baud Rate*/ + SERCOM1_REGS->I2CM.SERCOM_BAUD = baudValue; + + SERCOM1_REGS->I2CM.SERCOM_CTRLA = ((SERCOM1_REGS->I2CM.SERCOM_CTRLA & ~SERCOM_I2CM_CTRLA_SPEED_Msk) | (SERCOM_I2CM_CTRLA_SPEED(i2cSpeedMode))); + + /* Re-enable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + return true; +} + +void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle) +{ + sercom1I2CObj.callback = callback; + + sercom1I2CObj.context = contextHandle; +} + + +static void SERCOM1_I2C_SendAddress(uint16_t address, bool dir) +{ + /* If operation is I2C read */ + if(dir) + { + /*

*/ + + /* Next state will be to read data */ + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; + } + else + { + /*

*/ + + /* Next state will be to write data */ + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_WRITE; + } + + + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)address << 1U) | (dir ? 1UL :0UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + +} + +static void SERCOM1_I2C_InitiateTransfer(uint16_t address, bool dir) +{ + sercom1I2CObj.writeCount = 0U; + sercom1I2CObj.readCount = 0U; + + /* Clear all flags */ + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Smart mode enabled with SCLSM = 0, - ACK is set to send while receiving the data */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB &= ~SERCOM_I2CM_CTRLB_ACKACT_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + SERCOM1_I2C_SendAddress(address, dir); +} + +static bool SERCOM1_I2C_XferSetup( + uint16_t address, + uint8_t* wrData, + uint32_t wrLength, + uint8_t* rdData, + uint32_t rdLength, + bool dir, + bool isHighSpeed +) +{ + /* Check for ongoing transfer */ + if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) + { + return false; + } + + sercom1I2CObj.address = address; + sercom1I2CObj.readBuffer = rdData; + sercom1I2CObj.readSize = rdLength; + sercom1I2CObj.writeBuffer = wrData; + sercom1I2CObj.writeSize = wrLength; + sercom1I2CObj.transferDir = dir; + sercom1I2CObj.isHighSpeed = isHighSpeed; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + + SERCOM1_I2C_InitiateTransfer(address, dir); + + return true; +} + +bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength) +{ + return SERCOM1_I2C_XferSetup(address, NULL, 0, rdData, rdLength, true, false); +} + +bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength) +{ + return SERCOM1_I2C_XferSetup(address, wrData, wrLength, NULL, 0, false, false); +} + +bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength) +{ + return SERCOM1_I2C_XferSetup(address, wrData, wrLength, rdData, rdLength, false, false); +} + + +bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound) +{ + uint8_t* pDevList = (uint8_t*)pDevicesList; + uint8_t nDevFound = 0; + + /* Check for ongoing transfer */ + if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) + { + return false; + } + + if ((pDevicesList == NULL) || (nDevicesFound == NULL)) + { + return false; + } + + *nDevicesFound = 0; + + /* Clear all flags */ + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Disable all interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENCLR = (uint8_t)SERCOM_I2CM_INTENCLR_Msk; + + for (uint16_t dev_addr = start_addr; dev_addr <= end_addr; dev_addr++) + { + while(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) + { + /* Wait for the bus to become IDLE */ + } + + /* Put the 7-bit device address on the bus with WR bit */ + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)dev_addr << 1U); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + while ((SERCOM1_REGS->I2CM.SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_MB_Msk) == 0U) + { + /* Wait for the address transfer to complete */ + } + + if ((SERCOM1_REGS->I2CM.SERCOM_STATUS & (SERCOM_I2CM_STATUS_ARBLOST_Msk | SERCOM_I2CM_STATUS_BUSERR_Msk | SERCOM_I2CM_STATUS_RXNACK_Msk)) == 0U) + { + /* No error and device responded with an ACK. Add the device to the list of found devices. */ + pDevList[nDevFound] = (uint8_t)dev_addr; + + nDevFound += 1U; + } + + /* Issue stop condition */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } + + *nDevicesFound = nDevFound; + + /* Re-enable all interrupts */ + SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; + + return true; +} + +bool SERCOM1_I2C_IsBusy(void) +{ + bool isBusy = true; + if((sercom1I2CObj.state == SERCOM_I2C_STATE_IDLE)) + { + if(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) + { + isBusy = false; + } + } + return isBusy; +} + +SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void) +{ + return sercom1I2CObj.error; +} + +void SERCOM1_I2C_TransferAbort( void ) +{ + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + // Reset the plib to IDLE state + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Disable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Re-enable the I2C module */ + SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ + SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void __attribute__((used)) SERCOM1_I2C_InterruptHandler(void) +{ + if(SERCOM1_REGS->I2CM.SERCOM_INTENSET != 0U) + { + uintptr_t context = sercom1I2CObj.context; + + /* Checks if the arbitration lost in multi-master scenario */ + if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_ARBLOST_Msk) == SERCOM_I2CM_STATUS_ARBLOST_Msk) + { + /* Set Error status */ + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; + + } + /* Check for Bus Error during transmission */ + else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSERR_Msk) == SERCOM_I2CM_STATUS_BUSERR_Msk) + { + /* Set Error status */ + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; + } + /* Checks slave acknowledge for address or data */ + else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_RXNACK_Msk) == SERCOM_I2CM_STATUS_RXNACK_Msk) + { + sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NAK; + } + else + { + switch(sercom1I2CObj.state) + { + case SERCOM_I2C_REINITIATE_TRANSFER: + + if (sercom1I2CObj.writeSize != 0U) + { + /* Initiate Write transfer */ + SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, false); + } + else + { + /* Initiate Read transfer */ + SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, true); + } + + break; + + + case SERCOM_I2C_STATE_IDLE: + + break; + + + + case SERCOM_I2C_STATE_TRANSFER_WRITE: + { + size_t writeCount = sercom1I2CObj.writeCount; + + if (writeCount == (sercom1I2CObj.writeSize)) + { + if(sercom1I2CObj.readSize != 0U) + { + + /* Write 7bit address with direction (ADDR.ADDR[0]) equal to 1*/ + SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)(sercom1I2CObj.address) << 1U) | (uint32_t)I2C_TRANSFER_READ; + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; + + } + else + { + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; + } + } + /* Write next byte */ + else + { + SERCOM1_REGS->I2CM.SERCOM_DATA = sercom1I2CObj.writeBuffer[writeCount]; + writeCount++; + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + sercom1I2CObj.writeCount = writeCount; + } + } + + break; + + case SERCOM_I2C_STATE_TRANSFER_READ: + { + size_t readCount = sercom1I2CObj.readCount; + + + if(readCount == (sercom1I2CObj.readSize - 1U)) + { + /* Set NACK and send stop condition to the slave from master */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_ACKACT_Msk | SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; + } + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Read the received data */ + sercom1I2CObj.readBuffer[readCount] = (uint8_t) SERCOM1_REGS->I2CM.SERCOM_DATA; + readCount++; + + sercom1I2CObj.readCount = readCount; + } + + break; + + default: + + /* Do nothing */ + break; + } + } + + /* Error Status */ + if(sercom1I2CObj.state == SERCOM_I2C_STATE_ERROR) + { + /* Reset the PLib objects and Interrupts */ + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + + /* Generate STOP condition */ + SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); + + /* Wait for synchronization */ + while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + if (sercom1I2CObj.callback != NULL) + { + sercom1I2CObj.callback(context); + } + } + /* Transfer Complete */ + else if(sercom1I2CObj.state == SERCOM_I2C_STATE_TRANSFER_DONE) + { + /* Reset the PLib objects and interrupts */ + sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; + sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; + + SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; + + /* Wait for the NAK and STOP bit to be transmitted out and I2C state machine to rest in IDLE state */ + while((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U)) + { + /* Do nothing */ + } + + if(sercom1I2CObj.callback != NULL) + { + sercom1I2CObj.callback(context); + } + + } + else + { + /* Do nothing */ + } + } + + return; +} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h new file mode 100644 index 00000000..d20fd0e2 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h @@ -0,0 +1,104 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Instance Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_sercom1_i2c.h + + Summary: + SERCOM I2C PLIB Header file + + Description: + This file defines the interface to the SERCOM I2C peripheral library. This + library provides access to and control of the associated peripheral + instance. +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM1_I2C_H +#define PLIB_SERCOM1_I2C_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_sercom_i2c_master_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +/* + * The following functions make up the methods (set of possible operations) of + * this interface. + */ + +void SERCOM1_I2C_Initialize(void); + +bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength); + +bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength); + +bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength); + +bool SERCOM1_I2C_IsBusy(void); + +SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void); + +void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle); + +bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ); + + +void SERCOM1_I2C_TransferAbort( void ); + +bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_SERCOM1_I2C_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h new file mode 100644 index 00000000..904a768b --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h @@ -0,0 +1,260 @@ +/******************************************************************************* + Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library + Instance Header File + + Company + Microchip Technology Inc. + + File Name + plib_sercom_i2c_master.h + + Summary + SERCOM I2C peripheral library interface. + + Description + This file defines the interface to the SERCOM I2C peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_I2C_MASTER_H +#define PLIB_SERCOM_I2C_MASTER_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SERCOM I2C Transfer type + + Summary: + List of transfer direction. + + Description: + This enum defines the I2C transfer direction. + + Remarks: + None. +*/ + +enum +{ + I2C_TRANSFER_WRITE = 0, + I2C_TRANSFER_READ = 1, +}; + +// ***************************************************************************** +/* SERCOM I2C Error. + + Summary: + Defines the possible errors that the SERCOM I2C peripheral can generate. + + Description: + This enum defines the possible error the SERCOM I2C peripheral can generate. + An error of this type is returned by the SERCOMx_I2C_ErrorGet() function. + + Remarks: + None. +*/ + +typedef enum +{ + /* No error has occurred. */ + SERCOM_I2C_ERROR_NONE, + + /* A bus transaction was NAK'ed */ + SERCOM_I2C_ERROR_NAK, + + /* A bus error has occurred. */ + SERCOM_I2C_ERROR_BUS, + +} SERCOM_I2C_ERROR; + +// ***************************************************************************** +/* SERCOM I2C State. + + Summary: + SERCOM I2C PLib Task State. + + Description: + This data type defines the SERCOM I2C PLib Task State. + + Remarks: + None. +*/ + +typedef enum +{ + /* SERCOM PLib Task Error State */ + SERCOM_I2C_STATE_ERROR = -1, + + /* SERCOM PLib Task Idle State */ + SERCOM_I2C_STATE_IDLE, + + /* SERCOM PLib Task Address Send State */ + SERCOM_I2C_STATE_ADDR_SEND, + + SERCOM_I2C_REINITIATE_TRANSFER, + /* SERCOM PLib Task Read Transfer State */ + SERCOM_I2C_STATE_TRANSFER_READ, + + /* SERCOM PLib Task Write Transfer State */ + SERCOM_I2C_STATE_TRANSFER_WRITE, + + /* SERCOM PLib Task High Speed Slave Address Send State */ + SERCOM_I2C_STATE_TRANSFER_ADDR_HS, + + /* SERCOM PLib Task Transfer Done State */ + SERCOM_I2C_STATE_TRANSFER_DONE, + +} SERCOM_I2C_STATE; + +// ***************************************************************************** +/* SERCOM I2C Callback + + Summary: + SERCOM I2C Callback Function Pointer. + + Description: + This data type defines the SERCOM I2C Callback Function Pointer. + + Remarks: + None. +*/ + +typedef void (*SERCOM_I2C_CALLBACK) +( + /*Transfer context*/ + uintptr_t contextHandle + +); + +// ***************************************************************************** +/* SERCOM I2C PLib Instance Object + + Summary: + SERCOM I2C PLib Object structure. + + Description: + This data structure defines the SERCOM I2C PLib Instance Object. + + Remarks: + None. +*/ + +typedef struct +{ + bool isHighSpeed; + + bool txMasterCode; + + bool transferDir; + + uint16_t address; + + uint8_t masterCode; + + uint8_t* writeBuffer; + + uint8_t* readBuffer; + + size_t writeSize; + + size_t readSize; + + size_t writeCount; + + size_t readCount; + + /* State */ + SERCOM_I2C_STATE state; + + /* Transfer status */ + SERCOM_I2C_ERROR error; + + /* Transfer Event Callback */ + SERCOM_I2C_CALLBACK callback; + + /* Transfer context */ + uintptr_t context; + +} SERCOM_I2C_OBJ; + +// ***************************************************************************** +/* Transaction Request Block + + Summary: + Transaction Request Block Structure. + + Description: + This data structure defines the Transaction Request Block. + + Remarks: + None. +*/ + +typedef struct +{ + /* SERCOM I2C Clock Speed */ + uint32_t clkSpeed; + +} SERCOM_I2C_TRANSFER_SETUP; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif /* PLIB_SERCOM_I2C_MASTER_H */ \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c new file mode 100644 index 00000000..3ade6cfa --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c @@ -0,0 +1,622 @@ +/******************************************************************************* + SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE(SERCOM0_SPI) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_spi_master.c + + Summary + SERCOM0_SPI Master PLIB Implementation File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_sercom0_spi_master.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: MACROS Definitions +// ***************************************************************************** +// ***************************************************************************** + + +/* SERCOM0 clk freq value for the baud calculation */ +#define SERCOM0_Frequency (48000000UL) + +/* SERCOM0 SPI baud value for 10000 Hz baud rate */ +#define SERCOM0_SPIM_BAUD_VALUE (2399UL) + +/*Global object to save SPI Exchange related data */ +static volatile SPI_OBJECT sercom0SPIObj; + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM0_SPI Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_Initialize(void); + + Summary: + Initializes instance SERCOM0 of the SERCOM module operating in SPI mode. + + Description: + This function initializes instance SERCOM0 of SERCOM module operating in SPI mode. + This function should be called before any other library function. The SERCOM + module will be configured as per the MHC settings. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_Initialize(void) +{ + /* Instantiate the SERCOM0 SPI object */ + sercom0SPIObj.callback = NULL ; + sercom0SPIObj.transferIsBusy = false ; + sercom0SPIObj.txSize = 0U; + sercom0SPIObj.rxSize = 0U; + + /* Selection of the Character Size and Receiver Enable */ + SERCOM0_REGS->SPIM.SERCOM_CTRLB = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT | SERCOM_SPIM_CTRLB_RXEN_Msk ; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Selection of the Baud Value */ + SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)SERCOM_SPIM_BAUD_BAUD(SERCOM0_SPIM_BAUD_VALUE); + + /* Configure Data Out Pin Out , Master Mode, + * Data In and Pin Out,Data Order and Standby mode if configured + * and Selection of the Clock Phase and Polarity and Enable the SPI Module + */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA = SERCOM_SPIM_CTRLA_MODE_SPI_MASTER | SERCOM_SPIM_CTRLA_DOPO_PAD3 | SERCOM_SPIM_CTRLA_DIPO_PAD1 | SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW | SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE | SERCOM_SPIM_CTRLA_DORD_MSB | SERCOM_SPIM_CTRLA_ENABLE_Msk ; + + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, + uint32_t spiSourceClock); + + Summary: + Configure SERCOM SPI operational parameters at run time. + + Description: + This function allows the application to change the SERCOM SPI operational + parameter at run time. The application can thus override the MHC defined + configuration for these parameters. The parameter are specified via the + SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter + should be initialized to the desired value. + + The application may feel need to call this function in situation where + multiple SPI slaves, each with different operation parameters, are connected + to one SPI master. This function can thus be used to setup the SPI Master to + meet the communication needs of the slave. + + Calling this function will affect any ongoing communication. The application + must thus ensure that there is no on-going communication on the SPI before + calling this function. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock) +{ + uint32_t baudValue = 0U; + + bool statusValue = false; + + if(spiSourceClock == 0U) + { + /* Fetch Master Clock Frequency directly */ + spiSourceClock = SERCOM0_Frequency; + } + + /* Disable the SPI Module */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_ENABLE_Msk); + + /* Disabling SPI module, also clears the TXC (Transmit Complete) bit to 0. TXC = 0 means transfer is not complete (busy). + As a result, calling SERCOM0_SPI_IsBusy() after a call to SERCOM0_SPI_TransferSetup() always returns busy. + Since, application must call the SERCOM0_SPI_TransferSetup() API only after ensuring that no transfer is in progress, + it is safe to clear the rxSize and txSize to 0, so as to let the SERCOM0_SPI_IsBusy() return false (not busy). + */ + sercom0SPIObj.rxSize = 0; + sercom0SPIObj.txSize = 0; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + if(setup != NULL) + { + if (setup->clockFrequency <= spiSourceClock/2U) + { + baudValue = (spiSourceClock/(2U*(setup->clockFrequency))) - 1U; + + /* Set the lowest possible baud */ + if (baudValue >= 255U) + { + baudValue = 255U; + } + + /* Selection of the Clock Polarity and Clock Phase */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_CPOL_Msk | SERCOM_SPIM_CTRLA_CPHA_Msk); + SERCOM0_REGS->SPIM.SERCOM_CTRLA |= (uint32_t)setup->clockPolarity | (uint32_t)setup->clockPhase; + + /* Selection of the Baud Value */ + SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)baudValue; + + /* Selection of the Character Size */ + SERCOM0_REGS->SPIM.SERCOM_CTRLB &= ~SERCOM_SPIM_CTRLB_CHSIZE_Msk; + SERCOM0_REGS->SPIM.SERCOM_CTRLB |= (uint32_t)setup->dataBits; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + statusValue = true; + } + } + + /* Enabling the SPI Module */ + SERCOM0_REGS->SPIM.SERCOM_CTRLA |= SERCOM_SPIM_CTRLA_ENABLE_Msk; + + /* Wait for synchronization */ + while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + return statusValue; +} + + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, + uintptr_t context); + + Summary: + Allows application to register callback with PLIB. + + Description: + This function allows application to register an event handling function + for the PLIB to call back when requested data exchange operation has + completed or any error has occurred. + The callback should be registered before the client performs exchange + operation. + At any point if application wants to stop the callback, it can use this + function with "callBack" value as NULL. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context ) +{ + sercom0SPIObj.callback = callBack; + + sercom0SPIObj.context = context; +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsBusy(void); + + Summary: + Returns transfer status of SERCOM SERCOM0SPI. + + Description: + This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The + application can use the function to check if SERCOM SERCOM0SPI module is busy + before calling any of the data transfer functions. The library does not + allow a data transfer operation if another transfer operation is already in + progress. + + This function can be used as an alternative to the callback function when + the library is operating interrupt mode. The allow the application to + implement a synchronous interface to the library. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_IsBusy(void) +{ + bool isBusy = false; + size_t txSize = sercom0SPIObj.txSize; + bool transferIsBusy = sercom0SPIObj.transferIsBusy; + + if ((sercom0SPIObj.rxSize == 0U) && (txSize == 0U)) + { + /* This means no transfer has been requested yet; hence SPI is not busy. */ + isBusy = false; + } + else + { + /* if transmit is not complete or if the state flag is not set, SPI is busy */ + isBusy = (((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U) || transferIsBusy); + } + return isBusy; +} + +bool SERCOM0_SPI_IsTransmitterBusy(void) +{ + return ((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U)? true : false; +} + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize + void* pReceiveData, size_t rxSize); + + Summary: + Write and Read data on SERCOM SERCOM0 SPI peripheral. + + Description: + This function transmits "txSize" number of bytes and receives "rxSize" + number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is + transmitted and received data is saved in the location pointed by + pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" + data units towards completion. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit and receive buffer are ownerd by the library until the data + transfer is complete and should not be modified by the application till the + transfer is complete. Only one transfer is allowed at any time. The + Application can use a callback function or a polling function to check for + completion of the transfer. If a callback is required, this should be + registered prior to calling the SERCOM0_SPI_WriteRead() function. The + application can use the SERCOM0_SPI_IsBusy() to poll for completion. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize) +{ + bool isRequestAccepted = false; + uint32_t dummyData = 0U; + size_t txSz; + + if (sercom0SPIObj.transferIsBusy == false) + { + /* Verify the request */ + if(((txSize > 0U) && (pTransmitData != NULL)) || ((rxSize > 0U) && (pReceiveData != NULL))) + { + if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_9) + { + /* For 9-bit transmission, the txSize and rxSize must be an even number. */ + if(((txSize > 0U) && ((txSize & 0x01U) != 0U)) || ((rxSize > 0U) && ((rxSize & 0x01U) != 0U))) + { + return isRequestAccepted; + } + } + + isRequestAccepted = true; + sercom0SPIObj.txBuffer = pTransmitData; + sercom0SPIObj.rxBuffer = pReceiveData; + sercom0SPIObj.rxCount = 0U; + sercom0SPIObj.txCount = 0U; + sercom0SPIObj.dummySize = 0U; + + if(pTransmitData != NULL) + { + sercom0SPIObj.txSize = txSize; + } + else + { + sercom0SPIObj.txSize = 0U; + } + + if(pReceiveData != NULL) + { + sercom0SPIObj.rxSize = rxSize; + } + else + { + sercom0SPIObj.rxSize = 0U; + } + + sercom0SPIObj.transferIsBusy = true; + + /* Flush out any unread data in SPI read buffer */ + while((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) + { + dummyData = SERCOM0_REGS->SPIM.SERCOM_DATA; + (void)dummyData; + } + + SERCOM0_REGS->SPIM.SERCOM_STATUS |= SERCOM_SPIM_STATUS_BUFOVF_Msk; + + SERCOM0_REGS->SPIM.SERCOM_INTFLAG |= (uint8_t)SERCOM_SPIM_INTFLAG_ERROR_Msk; + + txSz = sercom0SPIObj.txSize; + + if(sercom0SPIObj.rxSize > txSz) + { + sercom0SPIObj.dummySize = sercom0SPIObj.rxSize - txSz; + } + + /* Start the first write here itself, rest will happen in ISR context */ + if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_8) + { + if(sercom0SPIObj.txCount < txSz) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint8_t*)sercom0SPIObj.txBuffer); + + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + else + { + sercom0SPIObj.txSize >>= 1U; + sercom0SPIObj.dummySize >>= 1U; + sercom0SPIObj.rxSize >>= 1U; + + txSz = sercom0SPIObj.txSize; + + if(sercom0SPIObj.txCount < txSz) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint16_t*)sercom0SPIObj.txBuffer) & SERCOM_SPIM_DATA_Msk; + + sercom0SPIObj.txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU & SERCOM_SPIM_DATA_Msk; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + + if(rxSize > 0U) + { + /* Enable ReceiveComplete */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_RXC_Msk; + } + else + { + /* Enable the DataRegisterEmpty */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; + } + } + } + + return isRequestAccepted; +} + +bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize) +{ + return SERCOM0_SPI_WriteRead(pTransmitData, txSize, NULL, 0U); +} + +bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize) +{ + return SERCOM0_SPI_WriteRead(NULL, 0U, pReceiveData, rxSize); +} + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_InterruptHandler(void); + + Summary: + Handler that handles the SPI interrupts + + Description: + This Function is called from the handler to handle the exchange based on the + Interrupts. + + Remarks: + Refer plib_sercom0_spi.h file for more information. +*/ + +void __attribute__((used)) SERCOM0_SPI_InterruptHandler(void) +{ + uint32_t dataBits = 0U; + uint32_t receivedData = 0U; + static bool isLastByteTransferInProgress = false; + uintptr_t context = sercom0SPIObj.context; + + if(SERCOM0_REGS->SPIM.SERCOM_INTENSET != 0U) + { + dataBits = SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk; + + size_t rxCount = sercom0SPIObj.rxCount; + size_t txCount = sercom0SPIObj.txCount; + size_t txSize = sercom0SPIObj.txSize; + + if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) + { + receivedData = SERCOM0_REGS->SPIM.SERCOM_DATA; + + if(rxCount < sercom0SPIObj.rxSize) + { + if(dataBits == (uint32_t)SPI_DATA_BITS_8) + { + ((uint8_t*)sercom0SPIObj.rxBuffer)[rxCount] = (uint8_t)receivedData; + rxCount++; + } + else + { + ((uint16_t*)sercom0SPIObj.rxBuffer)[rxCount] = (uint16_t)receivedData; + rxCount++; + } + } + } + + /* If there are more words to be transmitted, then transmit them here and keep track of the count */ + if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_DRE_Msk) == SERCOM_SPIM_INTFLAG_DRE_Msk) + { + /* Disable the DRE interrupt. This will be enabled back if more than + * one byte is pending to be transmitted */ + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_DRE_Msk; + + if(dataBits == (uint32_t)SPI_DATA_BITS_8) + { + if(txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint8_t*)sercom0SPIObj.txBuffer)[txCount]; + txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + else + { + if(txCount < sercom0SPIObj.txSize) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint16_t*)sercom0SPIObj.txBuffer)[txCount]; + txCount++; + } + else if(sercom0SPIObj.dummySize > 0U) + { + SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU; + + sercom0SPIObj.dummySize--; + } + else + { + /* Do nothing */ + } + } + + if((sercom0SPIObj.dummySize == 0U) && (txCount == txSize)) + { + /* At higher baud rates, the data in the shift register can be + * shifted out and TXC flag can get set resulting in a + * callback been given to the application with the SPI interrupt + * pending with the application. This will then result in the + * interrupt handler being called again with nothing to transmit. + * To avoid this, a software flag is set, but + * the TXC interrupt is not enabled until the very end. + */ + + isLastByteTransferInProgress = true; + } + else if(rxCount == sercom0SPIObj.rxSize) + { + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; + + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_RXC_Msk; + } + else + { + /* Do nothing */ + } + } + + sercom0SPIObj.rxCount = rxCount; + sercom0SPIObj.txCount = txCount; + + if(((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == SERCOM_SPIM_INTFLAG_TXC_Msk) && (isLastByteTransferInProgress == true)) + { + if(rxCount == sercom0SPIObj.rxSize) + { + sercom0SPIObj.transferIsBusy = false; + + /* Disable the Data Register empty and Receive Complete Interrupt flags */ + SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)(SERCOM_SPIM_INTENCLR_DRE_Msk | SERCOM_SPIM_INTENCLR_RXC_Msk | SERCOM_SPIM_INTENSET_TXC_Msk); + + isLastByteTransferInProgress = false; + + if(sercom0SPIObj.callback != NULL) + { + sercom0SPIObj.callback(context); + } + } + } + + if(isLastByteTransferInProgress == true) + { + /* For the last byte transfer, the DRE interrupt is already disabled. + * Enable TXC interrupt to ensure no data is present in the shift + * register before application callback is called. + */ + SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_TXC_Msk; + } + } +} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h new file mode 100644 index 00000000..ac5d988c --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h @@ -0,0 +1,624 @@ +/******************************************************************************* + SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE (SERCOM0_SPI ) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_spi_master.h + + Summary + SERCOM0_SPI Master PLIB Header File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM0_SPI_MASTER_H // Guards against multiple inclusion +#define PLIB_SERCOM0_SPI_MASTER_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_sercom_spi_master_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_Initialize (void); + + Summary: + Initializes instance SERCOM0 operating in SPI mode. + + Description: + This function initializes instance SERCOM0 operating in SPI mode. + This function should be called before any other library function. The SERCOM + module will be configured as per the MHC settings. + + Precondition: + MCC GUI should be configured with the right values. The Generic Clock + configuration and the SERCOM Peripheral Clock channel should have been + configured in the clock manager GUI.The function will itself enable the + required peripheral clock channel and main clock. + + Parameters: + None. + + Returns: + None. + + Example: + + SERCOM0_SPI_Initialize(); + + + Remarks: + This function must be called once before any other SPI function is called. +*/ + +void SERCOM0_SPI_Initialize (void); + + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, + uint32_t spiSourceClock); + + Summary: + Configure SERCOM SPI operational parameters at run time. + + Description: + This function allows the application to change the SERCOM SPI operational + parameter at run time. The application can thus override the MHC defined + configuration for these parameters. The parameter are specified via the + SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter + should be initialized to the desired value. + + The application may feel need to call this function in situation where + multiple SPI slaves, each with different operation paramertes, are connected + to one SPI master. This function can thus be used to setup the SPI Master to + meet the communication needs of the slave. + + Calling this function will affect any ongoing communication. The application + must thus ensure that there is no on-going communication on the SPI before + calling this function. + + Precondition: + SERCOM SERCOM0 SPI must first be initialized using SERCOM0_SPI_Initialize(). + + Parameters : + setup - pointer to the data structure of type SPI_TRANSFER_SETUP containing + the operation parameters. Each operation parameter must be specified even if + the parameter does not need to change. + + spiSourceClock - Current value of GCLK frequency feeding the SERCOM0 core. + + Returns: + true - setup was successful. + + false - if spiSourceClock and spi clock frequencies are such that resultant + baud value is out of the possible range. + + Example: Assuming 20 MHz as peripheral Master clock frequency + + SPI_TRANSFER_SETUP setup; + setup.clockFrequency = 1000000; + setup.clockPhase = SPI_CLOCK_PHASE_TRAILING_EDGE; + setup.clockPolarity = SPI_CLOCK_POLARITY_IDLE_LOW; + setup.dataBits = SPI_DATA_BITS_8; + + if (SERCOM0_SPI_TransferSetup (&setup, 20000000) == false) + { + this means setup could not be done, debug the reason. + } + + + + Remarks: + The application would need to call this function only if the operational + parameter need to be different than the ones configured in MHC. +*/ + +bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock); + + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize + void* pReceiveData, size_t rxSize); + + Summary: + Write and Read data on SERCOM SERCOM0 SPI peripheral. + + Description: + This function transmits "txSize" number of bytes and receives "rxSize" + number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is + transmitted and received data is saved in the location pointed by + pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" + data units towards completion. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit and receive buffer are ownerd by the library until the data + transfer is complete and should not be modified by the application till the + transfer is complete. Only one transfer is allowed at any time. The + Application can use a callback function or a polling function to check for + completion of the transfer. If a callback is required, this should be + registered prior to calling the SERCOM0_SPI_WriteRead() function. The + application can use the SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. If the + peripheral instance has been configured for Interrupt mode and transfer + completion status needs to be communicated back to application via callback, + a callback should have been registered using SERCOM0_SPI_CallbackRegister() + function. + + Parameters: + pTransmitData - Pointer to the data which has to be transmitted. In a case + where only data reception is required, this pointer can be set to NULL. If + the module is configured for 9 bit data length, the data should be right + aligned in a 16 bit memory location. The size of this buffer should be + txSize. + + txSize - Number of bytes to be transmitted. For 9 but data length, a count + of 1 counts 2 bytes. This value can be different from rxSize. + + pReceiveData - Pointer to the location where the received data has to be + stored. It is user's responsibility to ensure that this location has + sufficient memory to store rxSize amount of data. In a case where only data + transmission is required, this pointer can be set to NULL. If the module is + configured for 9 bit data length, received data will be right aligned and + will be stored in a 16 bit memory location. + + rxSize - Number of bytes to be received. This value can be different from + txSize. For 9 bit data length, a size count of 1 indicates 2 bytes required + to store 9 bits of data. + + Returns: + true - If configured for Non-interrupt mode, the function has recevied and + transmitted the requested number of bytes. If configured for Interrupt mode, + the request was accepted successfully and will be processed in the + interrupt. + + false - If both pTransmitData and pReceiveData are NULL, or if both txSize + and rxSize are 0 or if txSize is non-zero but the pTransmitData is set to + NULL or rxSize is non-zero but pReceiveData is NULL. In Interrupt mode, the + function returns false if there is an on-going data transfer at the time of + calling the function. + + Example: + + + The following code snippet shows an example using the + SERCOM0_SPI_WriteRead() function in interrupt mode operation using the + callback function. + + uint8_t txBuffer[4]; + uint8_t rxBuffer[10]; + size_t txSize = 4; + size_t rxSize = 10; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + The following code snippet shows non-interrupt or blocking mode + operation. + + uint8_t txBuffer[4]; + uint8_t rxBuffer[10]; + size_t txSize = 4; + size_t rxSize = 10; + + SERCOM0_SPI_Initialize(); + + This function call will block. + SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize); + + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); + + Summary: + Writes data to SERCOM SERCOM0 SPI peripheral. + + Description: + This function writes "txSize" number of bytes on SERCOM SERCOM0 SPI module. Data + pointed by pTransmitData is transmitted. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + transferring all the data. This indicates that the operation has been + completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + transmit buffer is ownerd by the library until the data transfer is + complete and should not be modified by the application till the transfer is + complete. Only one transfer is allowed at any time. The application can use + a callback function or a polling function to check for completion of the + transfer. If a callback is required, this should be registered prior to + calling the SERCOM0_SPI_WriteRead() function. The application can use the + SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the + peripheral instance has been configured in Interrupt mode and + transfer completion status needs to be communicated back to application via + callback. + + Parameters: + pTransmitData - Pointer to the buffer containing the data which has to be + transmitted. For 9 bit mode, data should be right aligned in the 16 bit + memory location. In "Interrupt Mode", this buffer should not be modified + after calling the function and before the callback function has been called + or the SERCOM0_SPI_IsBusy() function returns false. + + txSize - Number of bytes to be transmitted. For 9 bit mode, 2 bytes make up + a count of 1. + + Returns: + true - If configured for Non-interrupt mode, the function has transmitted + the requested number of bytes. If configured for Interrupt mode, the request + was accepted successfully and will be processed in the interrupt. + + false - If pTransmitData is NULL. In Interrupt mode, the function will + additionally return false if there is an on-going data transfer at the time + of calling the function. + + Example: + + uint8_t txBuffer[4]; + size_t txSize = 4; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_Write(&txBuffer, txSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + + + Remarks: + None. + +*/ + +bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); + + Summary: + Reads data on the SERCOM SERCOM0 SPI peripheral. + + Description: + This function reads "rxSize" number of bytes on SERCOM SERCOM0 SPI module. The + received data is stored in the buffer pointed by pReceiveData. + + When "Interrupt Mode" option is unchecked in MHC, this function will be + blocking in nature. In this mode, the function will not return until all + the requested data is transferred. The function returns true after + receiving "rxSize" number of bytes. This indicates that the operation has + been completed. + + When "Interrupt Mode" option is selected in MHC, the function will be + non-blocking in nature. The function returns immediately. The data transfer + process continues in the peripheral interrupt. The application specified + receive buffer is ownerd by the library until the data transfer is + complete and should not be modified by the application till the transfer is + complete. Only one transfer is allowed at any time. The application can use + a callback function or a polling function to check for completion of the + transfer. If a callback is required, this should be registered prior to + calling the SERCOM0_SPI_WriteRead() function. The application can use the + SERCOM0_SPI_IsBusy() to poll for completion. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the + peripheral instance has been configured in Interrupt mode and + transfer completion status needs to be communicated back to application via + callback. + + Parameters: + pReceiveData - Pointer to the buffer where the received data will be stored. + For 9 bit mode, data should be right aligned in the 16 bit memory location. + In "Interrupt Mode", this buffer should not be modified after calling the + function and before the callback function has been called or the + SERCOM0_SPI_IsBusy() function returns false. + + rxSize - Number of bytes to be received. For 9 bit mode, 2 bytes make up a + count of 1. + + Returns: + true - If configured for Non-interrupt mode, the function has received the + requested number of bytes. If configured for Interrupt mode, the request was + accepted successfully and will be processed in the interrupt. + + false - If pReceiveData is NULL. In Interrupt mode, the function will + additionally return false if there is an on-going data transfer at the time + of calling the function. + + Example: + + uint8_t rxBuffer[10]; + size_t rxSize = 10; + + void APP_SPITransferHandler(uintptr_t context) + { + Transfer was completed without error, do something else now. + } + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); + if(SERCOM0_SPI_Read(&rxBuffer, rxSize)) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); + +// ***************************************************************************** +/* Function: + void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, + uintptr_t context); + + Summary: + Allows application to register callback with PLIB. + + Description: + This function allows application to register an event handling function + for the PLIB to call back when requested data exchange operation has + completed or any error has occurred. + The callback should be registered before the client performs exchange + operation. + At any point if application wants to stop the callback, it can use this + function with "callBack" value as NULL. + + Precondition: + The SERCOM0_SPI_Initialize function must have been called. + + Parameters: + callBack - Pointer to the event handler function implemented by the + user . + + context - The value of parameter will be passed back to the application + unchanged, when the callBack function is called. It can + be used to identify any application specific data object that + identifies the instance of the client module (for example, + it may be a pointer to the client module's state structure). + + Returns: + None. + + Example: + + uint8_t txBuffer[10]; + uint8_t rxBuffer[10]; + size_t txSize = 10; + size_t rxSize = 10; + + SERCOM0_SPI_Initialize(); + + SERCOM0_SPI_CallbackRegister(&APP_SPICallBack, (uintptr_t)NULL); + + if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize )) + { + request got accepted + } + else + { + request didn't get accepted, try again later with correct arguments + } + + void APP_SPICallBack(uintptr_t contextHandle) + { + Exchange was completed without error, do something else. + } + + + Remarks: + If the client does not want to be notified when the queued operation + has completed, it does not need to register a callback. +*/ + +void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsBusy (void); + + Summary: + Returns transfer status of SERCOM SERCOM0SPI. + + Description: + This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The + application can use the function to check if SERCOM SERCOM0SPI module is busy + before calling any of the data transfer functions. The library does not + allow a data transfer operation if another transfer operation is already in + progress. This function returns true when the SPI PLIB software state machine is idle and + all the bytes are transmitted out on the bus (shift register is empty). + + This function can be used as an alternative to the callback function when + the library is operating interrupt mode. The allow the application to + implement a synchronous interface to the library. + + Precondition: + The SERCOM0_SPI_Initialize() should have been called once. The module should + have been configured for interrupt mode operation in MHC. + + Parameters: + None. + + Returns: + true - Transfer is still in progress + false - Transfer is completed or no transfer is currently in progress. + + Example: + + The following code example demonstrates the use of the + SERCOM0_SPI_IsBusy() function. This example shows a blocking while + loop. The function can also be called periodically. + + uint8_t dataBuffer[20]; + + SERCOM0_SPI_Initialize(); + SERCOM0_SPI_Write(dataBuffer, 20); + + while (SERCOM0_SPI_IsBusy() == true) + { + Wait here till the transfer is done. + } + + + Remarks: + None. +*/ + +bool SERCOM0_SPI_IsBusy (void); + +// ***************************************************************************** +/* Function: + bool SERCOM0_SPI_IsTransmitterBusy (void); + + Summary: + Returns hardware transfer status of the SPI transmit shift register + + Description: + This function returns the hardware status of the transmit shift register. + The status is returned true after all the bytes have been shifted out on the + SPI bus. This function should be used when using DMA with SPI PLIB to make + sure that all the bytes have been transmitted out on the bus. For SPI + transfers without DMA, the SERCOM0_SPI_IsBusy() API must be used. + + Precondition: + The SERCOM0_SPI_Initialize() should have been called once. + + Parameters: + None. + + Returns: + true - Data is being shifted out on the SPI bus + false - All the data bytes have been shifted out on the SPI bus + + Example: + + + + + Remarks: + None. +*/ +bool SERCOM0_SPI_IsTransmitterBusy(void); + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_SERCOM0_SPI_MASTER_H */ \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h new file mode 100644 index 00000000..fcdc9dc8 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h @@ -0,0 +1,296 @@ +/******************************************************************************* + SERCOM_SPI(SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom_spi_master_common.h + + Summary + SERCOM_SPI PLIB Master Local Header File. + + Description + This file defines the interface to the SERCOM SPI peripheral library. + This library provides access to and control of the associated + peripheral instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_SPI_MASTER_COMMON_H // Guards against multiple inclusion +#define PLIB_SERCOM_SPI_MASTER_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI Clock Phase + + Summary: + Identifies SPI Clock Phase Options + + Description: + This enumeration identifies possible SPI Clock Phase Options. + + Remarks: + None. +*/ + +typedef enum +{ + SPI_CLOCK_PHASE_LEADING_EDGE = SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE, + SPI_CLOCK_PHASE_TRAILING_EDGE = SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE, + + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_CLOCK_PHASE_INVALID = 0xFFFFFFFFU + +} SPI_CLOCK_PHASE; + +// ***************************************************************************** +/* SPI Clock Polarity + + Summary: + Identifies SPI Clock Polarity Options + + Description: + This enumeration identifies possible SPI Clock Polarity Options. + + Remarks: + None. +*/ + +typedef enum +{ + SPI_CLOCK_POLARITY_IDLE_LOW = SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW, + SPI_CLOCK_POLARITY_IDLE_HIGH = SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH, + + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_CLOCK_POLARITY_INVALID = 0xFFFFFFFFU + +} SPI_CLOCK_POLARITY; + +// ***************************************************************************** +/* SPI Data Bits + + Summary: + Identifies SPI bits per transfer + + Description: + This enumeration identifies number of bits per SPI transfer. + + Remarks: + For 9 bit mode, data should be right aligned in the 16 bit + memory location. +*/ + +typedef enum +{ + SPI_DATA_BITS_8 = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT, + SPI_DATA_BITS_9 = SERCOM_SPIM_CTRLB_CHSIZE_9_BIT, + + + /* Force the compiler to reserve 32-bit space for each enum value */ + SPI_DATA_BITS_INVALID = 0xFFFFFFFFU + +} SPI_DATA_BITS; + +// ***************************************************************************** +/* SPI Transfer Setup Parameters + + Summary: + Identifies the setup parameters which can be changed dynamically. + + Description + This structure identifies the possible setup parameters for SPI + which can be changed dynamically if needed. + + Remarks: + None. +*/ + +typedef struct +{ + /* Baud Rate or clock frequency */ + uint32_t clockFrequency; + + /* Clock Phase */ + SPI_CLOCK_PHASE clockPhase; + + /* Clock Polarity */ + SPI_CLOCK_POLARITY clockPolarity; + + /* Number of bits per transfer */ + SPI_DATA_BITS dataBits; + +} SPI_TRANSFER_SETUP; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI CallBack Function Pointer + + Summary: + Pointer to a SPI Call back function. + + Description: + This data type defines the required function signature for the + SPI event handling callback function. Application must register + a pointer to an event handling function whose function signature (parameter + and return value types) match the types specified by this function pointer + in order to receive event calls back from the PLIB. + + The parameters and return values are described here and a partial example + implementation is provided. + + Parameters: + context - Value identifying the context of the application that + registered the event handling function + + Returns: + None. + + Example: + + + SPI1_CallbackRegister(&APP_SPICallBack, NULL); + void APP_SPICallBack(uintptr_t contextHandle) + { + if( SPI_ERROR_NONE == SPI1_ErrorGet()) + { + Exchange was completed without error, do something else now. + } + } + + + Remarks: + The context parameter contains the a handle to the client context, + provided at the time the event handling function was registered using the + SPIx_CallbackRegister function. This context handle value is + passed back to the client as the "context" parameter. It can be any value + (such as a pointer to the client's data) necessary to identify the client + context or instance of the client that made the data exchange + request. + + The event handler function executes in the PLIB's interrupt context. It is + recommended of the application to not perform process intensive or blocking + operations with in this function. +*/ + +typedef void (*SERCOM_SPI_CALLBACK)(uintptr_t context); + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local: **** Local SPI Object**** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* SPI Object + + Summary: + Defines the data type for the data structures used for peripheral + operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + /* Pointer to the transmitter buffer */ + void * txBuffer; + + /* Pointer to the received buffer */ + void * rxBuffer; + + size_t txSize; + + size_t rxSize; + + size_t dummySize; + + /* Size of the receive processed exchange size */ + size_t rxCount; + + /* Size of the transmit processed exchange size */ + size_t txCount; + + /* Exchange busy status of the SPI */ + bool transferIsBusy; + + /* SPI Event handler */ + SERCOM_SPI_CALLBACK callback; + + /* Context */ + uintptr_t context; + + uint32_t status; + +} SPI_OBJECT; + +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif + +#endif //PLIB_SERCOM_SPI_MASTER_COMMON_H \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c new file mode 100644 index 00000000..ca5c9b13 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c @@ -0,0 +1,615 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom3_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom3_usart.h" +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM3 USART baud value for 115200 Hz baud rate */ +#define SERCOM3_USART_INT_BAUD_VALUE (63019UL) + +static volatile SERCOM_USART_OBJECT sercom3USARTObj; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM3 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM3_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM3_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM3_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM3_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM3_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM3_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM3_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM3_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM3_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize instance object */ + sercom3USARTObj.rxBuffer = NULL; + sercom3USARTObj.rxSize = 0; + sercom3USARTObj.rxProcessedSize = 0; + sercom3USARTObj.rxBusyStatus = false; + sercom3USARTObj.rxCallback = NULL; + sercom3USARTObj.txBuffer = NULL; + sercom3USARTObj.txSize = 0; + sercom3USARTObj.txProcessedSize = 0; + sercom3USARTObj.txBusyStatus = false; + sercom3USARTObj.txCallback = NULL; + sercom3USARTObj.errorStatus = USART_ERROR_NONE; +} + + + + + +uint32_t SERCOM3_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM3_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + bool transferProgress = sercom3USARTObj.txBusyStatus; + transferProgress = sercom3USARTObj.rxBusyStatus || transferProgress; + if(transferProgress) + { + /* Transaction is in progress, so return without updating settings */ + return setupStatus; + } + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM3_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM3_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA = (SERCOM3_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM3_REGS->USART_INT.SERCOM_CTRLB = (SERCOM3_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA = (SERCOM3_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM3_REGS->USART_INT.SERCOM_CTRLB = (SERCOM3_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM3_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = sercom3USARTObj.errorStatus; + + sercom3USARTObj.errorStatus = USART_ERROR_NONE; + + return errorStatus; +} + +void SERCOM3_USART_Enable( void ) +{ + if((SERCOM3_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM3_USART_Disable( void ) +{ + if((SERCOM3_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM3_USART_TransmitterEnable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM3_USART_TransmitterDisable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM3_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint32_t processedSize = 0U; + + if(buffer != NULL) + { + if(sercom3USARTObj.txBusyStatus == false) + { + sercom3USARTObj.txBuffer = buffer; + sercom3USARTObj.txSize = size; + sercom3USARTObj.txBusyStatus = true; + + size_t txSize = sercom3USARTObj.txSize; + + /* Initiate the transfer by sending first byte */ + while (((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) && + (processedSize < txSize)) + { + if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)(buffer))[processedSize]; + } + else + { + /* 9-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)(buffer))[processedSize]; + } + processedSize += 1U; + } + sercom3USARTObj.txProcessedSize = processedSize; + SERCOM3_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk; + + writeStatus = true; + } + } + + return writeStatus; +} + + +bool SERCOM3_USART_WriteIsBusy( void ) +{ + return sercom3USARTObj.txBusyStatus; +} + +size_t SERCOM3_USART_WriteCountGet( void ) +{ + return sercom3USARTObj.txProcessedSize; +} + +void SERCOM3_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom3USARTObj.txCallback = callback; + + sercom3USARTObj.txContext = context; +} + + +bool SERCOM3_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM3_USART_ReceiverEnable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM3_USART_ReceiverDisable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM3_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + + if(buffer != NULL) + { + if(sercom3USARTObj.rxBusyStatus == false) + { + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM3_USART_ErrorClear(); + + sercom3USARTObj.rxBuffer = buffer; + sercom3USARTObj.rxSize = size; + sercom3USARTObj.rxProcessedSize = 0U; + sercom3USARTObj.rxBusyStatus = true; + sercom3USARTObj.errorStatus = USART_ERROR_NONE; + + readStatus = true; + + /* Enable receive and error interrupt */ + SERCOM3_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)(SERCOM_USART_INT_INTENSET_ERROR_Msk | SERCOM_USART_INT_INTENSET_RXC_Msk); + } + } + + return readStatus; +} + +bool SERCOM3_USART_ReadIsBusy( void ) +{ + return sercom3USARTObj.rxBusyStatus; +} + +size_t SERCOM3_USART_ReadCountGet( void ) +{ + return sercom3USARTObj.rxProcessedSize; +} + +bool SERCOM3_USART_ReadAbort(void) +{ + if (sercom3USARTObj.rxBusyStatus == true) + { + /* Disable receive and error interrupt */ + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + sercom3USARTObj.rxBusyStatus = false; + + /* If required application should read the num bytes processed prior to calling the read abort API */ + sercom3USARTObj.rxSize = 0U; + sercom3USARTObj.rxProcessedSize = 0U; + } + + return true; +} + +void SERCOM3_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom3USARTObj.rxCallback = callback; + + sercom3USARTObj.rxContext = context; +} + + +static void __attribute__((used)) SERCOM3_USART_ISR_ERR_Handler( void ) +{ + USART_ERROR errorStatus; + + errorStatus = (USART_ERROR) (SERCOM3_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + /* Save the error to be reported later */ + sercom3USARTObj.errorStatus = errorStatus; + + /* Clear the error flags and flush out the error bytes */ + SERCOM3_USART_ErrorClear(); + + /* Disable error and receive interrupt to abort on-going transfer */ + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + /* Clear the RX busy flag */ + sercom3USARTObj.rxBusyStatus = false; + + if(sercom3USARTObj.rxCallback != NULL) + { + uintptr_t rxContext = sercom3USARTObj.rxContext; + + sercom3USARTObj.rxCallback(rxContext); + } + } +} + +static void __attribute__((used)) SERCOM3_USART_ISR_RX_Handler( void ) +{ + uint16_t temp; + + + if(sercom3USARTObj.rxBusyStatus == true) + { + size_t rxSize = sercom3USARTObj.rxSize; + + if(sercom3USARTObj.rxProcessedSize < rxSize) + { + uintptr_t rxContext = sercom3USARTObj.rxContext; + + temp = (uint16_t)SERCOM3_REGS->USART_INT.SERCOM_DATA; + size_t rxProcessedSize = sercom3USARTObj.rxProcessedSize; + + if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + ((uint8_t*)sercom3USARTObj.rxBuffer)[rxProcessedSize] = (uint8_t) (temp); + } + else + { + /* 9-bit mode */ + ((uint16_t*)sercom3USARTObj.rxBuffer)[rxProcessedSize] = temp; + } + + /* Increment processed size */ + rxProcessedSize++; + sercom3USARTObj.rxProcessedSize = rxProcessedSize; + + if(rxProcessedSize == sercom3USARTObj.rxSize) + { + sercom3USARTObj.rxBusyStatus = false; + sercom3USARTObj.rxSize = 0U; + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_RXC_Msk | SERCOM_USART_INT_INTENCLR_ERROR_Msk); + + if(sercom3USARTObj.rxCallback != NULL) + { + sercom3USARTObj.rxCallback(rxContext); + } + } + + } + } +} + +static void __attribute__((used)) SERCOM3_USART_ISR_TX_Handler( void ) +{ + bool dataRegisterEmpty; + bool dataAvailable; + if(sercom3USARTObj.txBusyStatus == true) + { + size_t txProcessedSize = sercom3USARTObj.txProcessedSize; + + dataAvailable = (txProcessedSize < sercom3USARTObj.txSize); + dataRegisterEmpty = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + + while(dataRegisterEmpty && dataAvailable) + { + if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)sercom3USARTObj.txBuffer)[txProcessedSize]; + } + else + { + /* 9-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)sercom3USARTObj.txBuffer)[txProcessedSize]; + } + /* Increment processed size */ + txProcessedSize++; + + dataAvailable = (txProcessedSize < sercom3USARTObj.txSize); + dataRegisterEmpty = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + } + + sercom3USARTObj.txProcessedSize = txProcessedSize; + + if(txProcessedSize >= sercom3USARTObj.txSize) + { + sercom3USARTObj.txBusyStatus = false; + sercom3USARTObj.txSize = 0U; + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)SERCOM_USART_INT_INTENCLR_DRE_Msk; + + if(sercom3USARTObj.txCallback != NULL) + { + uintptr_t txContext = sercom3USARTObj.txContext; + sercom3USARTObj.txCallback(txContext); + } + } + } +} + +void __attribute__((used)) SERCOM3_USART_InterruptHandler( void ) +{ + bool testCondition; + if(SERCOM3_REGS->USART_INT.SERCOM_INTENSET != 0U) + { + /* Checks for error flag */ + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_ERROR_Msk) == SERCOM_USART_INT_INTFLAG_ERROR_Msk); + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_ERROR_Msk) == SERCOM_USART_INT_INTENSET_ERROR_Msk) && testCondition; + if(testCondition) + { + SERCOM3_USART_ISR_ERR_Handler(); + } + + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_DRE_Msk) == SERCOM_USART_INT_INTENSET_DRE_Msk) && testCondition; + /* Checks for data register empty flag */ + if(testCondition) + { + SERCOM3_USART_ISR_TX_Handler(); + } + + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk); + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_RXC_Msk) == SERCOM_USART_INT_INTENSET_RXC_Msk) && testCondition; + /* Checks for receive complete empty flag */ + if(testCondition) + { + SERCOM3_USART_ISR_RX_Handler(); + } + } +} + + + + diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h new file mode 100644 index 00000000..22cbca64 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h @@ -0,0 +1,121 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom3_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM3_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM3_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM3_USART_Initialize( void ); + +bool SERCOM3_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM3_USART_Enable( void ); + +void SERCOM3_USART_Disable( void ); + +void SERCOM3_USART_TransmitterEnable( void ); + +void SERCOM3_USART_TransmitterDisable( void ); + +bool SERCOM3_USART_Write( void *buffer, const size_t size ); + +bool SERCOM3_USART_TransmitComplete( void ); + + +bool SERCOM3_USART_WriteIsBusy( void ); + +size_t SERCOM3_USART_WriteCountGet( void ); + +void SERCOM3_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + + +void SERCOM3_USART_ReceiverEnable( void ); + +void SERCOM3_USART_ReceiverDisable( void ); + +bool SERCOM3_USART_Read( void *buffer, const size_t size ); + +bool SERCOM3_USART_ReadIsBusy( void ); + +size_t SERCOM3_USART_ReadCountGet( void ); + +bool SERCOM3_USART_ReadAbort(void); + +void SERCOM3_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + +USART_ERROR SERCOM3_USART_ErrorGet( void ); + +uint32_t SERCOM3_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM3_USART_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c new file mode 100644 index 00000000..89ba9800 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c @@ -0,0 +1,462 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom4_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom4_usart.h" + +/* + * ATSAMC21E18A exposes SERCOM3 register base for the PA22/PA23 UART route. + * Keep SERCOM4 USART API names stable for existing application code. + */ +#ifndef SERCOM4_REGS +#define SERCOM4_REGS SERCOM3_REGS +#endif +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM4 USART baud value for 115200 Hz baud rate */ +#define SERCOM4_USART_INT_BAUD_VALUE (63019UL) + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM4 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM4_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM4_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM4_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM4_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x3UL) | SERCOM_USART_INT_CTRLA_TXPO(0x1UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM4_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + + + + + +uint32_t SERCOM4_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM4_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM4_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = (SERCOM4_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM4_REGS->USART_INT.SERCOM_CTRLB = (SERCOM4_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA = (SERCOM4_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM4_REGS->USART_INT.SERCOM_CTRLB = (SERCOM4_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM4_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + SERCOM4_USART_ErrorClear(); + } + + return errorStatus; +} + +void SERCOM4_USART_Enable( void ) +{ + if((SERCOM4_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM4_USART_Disable( void ) +{ + if((SERCOM4_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM4_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM4_USART_TransmitterEnable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM4_USART_TransmitterDisable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM4_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint8_t *pu8Data = (uint8_t*)buffer; + uint16_t *pu16Data = (uint16_t*)buffer; + uint32_t u32Index = 0U; + + if(buffer != NULL) + { + /* Blocks while buffer is being transferred */ + while(u32Index < size) + { + /* Check if USART is ready for new data */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk) == 0U) + { + /* Do nothing */ + } + + /* Write data to USART module */ + if (((SERCOM4_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM4_REGS->USART_INT.SERCOM_DATA = pu8Data[u32Index]; + } + else + { + /* 9-bit mode */ + SERCOM4_REGS->USART_INT.SERCOM_DATA = pu16Data[u32Index]; + } + + /* Increment index */ + u32Index++; + } + writeStatus = true; + } + + return writeStatus; +} + + +bool SERCOM4_USART_TransmitterIsReady( void ) +{ + bool transmitterStatus = false; + + if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) + { + transmitterStatus = true; + } + + return transmitterStatus; +} + +void SERCOM4_USART_WriteByte( int data ) +{ + /* Check if USART is ready for new data */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == 0U) + { + /* Do nothing */ + } + + SERCOM4_REGS->USART_INT.SERCOM_DATA = (uint16_t)data; +} + +bool SERCOM4_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM4_USART_ReceiverEnable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM4_USART_ReceiverDisable( void ) +{ + SERCOM4_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM4_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + uint8_t* pu8Data = (uint8_t*)buffer; + uint16_t *pu16Data = (uint16_t*)buffer; + uint32_t u32Index = 0U; + USART_ERROR errorStatus = USART_ERROR_NONE; + + if(buffer != NULL) + { + + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM4_USART_ErrorClear(); + + while(u32Index < size) + { + /* Check if USART has new data */ + while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == 0U) + { + /* Do nothing */ + } + + errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + break; + } + + if (((SERCOM4_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + pu8Data[u32Index] = (uint8_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; + } + else + { + /* 9-bit mode */ + pu16Data[u32Index] = (uint16_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; + } + + /* Increment index */ + u32Index++; + } + + if(size == u32Index) + { + readStatus = true; + } + } + + return readStatus; +} + +bool SERCOM4_USART_ReceiverIsReady( void ) +{ + bool receiverStatus = false; + + if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + receiverStatus = true; + } + + return receiverStatus; +} + +int SERCOM4_USART_ReadByte( void ) +{ + return (int)SERCOM4_REGS->USART_INT.SERCOM_DATA; +} + + + + + diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h new file mode 100644 index 00000000..bc21fb11 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h @@ -0,0 +1,115 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom4_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM4_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM4_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM4_USART_Initialize( void ); + +bool SERCOM4_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM4_USART_Enable( void ); + +void SERCOM4_USART_Disable( void ); + +void SERCOM4_USART_TransmitterEnable( void ); + +void SERCOM4_USART_TransmitterDisable( void ); + +bool SERCOM4_USART_Write( void *buffer, const size_t size ); + +bool SERCOM4_USART_TransmitComplete( void ); + + +bool SERCOM4_USART_TransmitterIsReady( void ); + +void SERCOM4_USART_WriteByte( int data ); + + +void SERCOM4_USART_ReceiverEnable( void ); + +void SERCOM4_USART_ReceiverDisable( void ); + +bool SERCOM4_USART_Read( void *buffer, const size_t size ); + +bool SERCOM4_USART_ReceiverIsReady( void ); + +int SERCOM4_USART_ReadByte( void ); + +USART_ERROR SERCOM4_USART_ErrorGet( void ); + +uint32_t SERCOM4_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM4_USART_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h new file mode 100644 index 00000000..ab6321c6 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h @@ -0,0 +1,405 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchronous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom_usart_common.h + + Summary + Data Type definition of the USART Peripheral Interface Plib. + + Description + This file defines the Data Types for the USART Plib. + + Remarks: + None. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_USART_COMMON_H // Guards against multiple inclusion +#define PLIB_SERCOM_USART_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* USART Error convenience macros */ +// ***************************************************************************** +// ***************************************************************************** + /* Error status when no error has occurred */ +#define USART_ERROR_NONE 0U + + /* Error status when parity error has occurred */ +#define USART_ERROR_PARITY SERCOM_USART_INT_STATUS_PERR_Msk + + /* Error status when framing error has occurred */ +#define USART_ERROR_FRAMING SERCOM_USART_INT_STATUS_FERR_Msk + + /* Error status when overrun error has occurred */ +#define USART_ERROR_OVERRUN SERCOM_USART_INT_STATUS_BUFOVF_Msk + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* USART Errors + + Summary: + Defines the data type for the USART peripheral errors. + + Description: + This may be used to check the type of error occurred with the USART + peripheral during error status. + + Remarks: + None. +*/ + +typedef uint16_t USART_ERROR; + +// ***************************************************************************** +/* USART DATA + + Summary: + Defines the data type for the USART peripheral data. + + Description: + This may be used to check the type of data with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_DATA_5_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT, + USART_DATA_6_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT, + USART_DATA_7_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT, + USART_DATA_8_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT, + USART_DATA_9_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT, + + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_DATA_INVALID = 0xFFFFFFFFU + +} USART_DATA; + +// ***************************************************************************** +/* USART PARITY + + Summary: + Defines the data type for the USART peripheral parity. + + Description: + This may be used to check the type of parity with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_PARITY_EVEN = SERCOM_USART_INT_CTRLB_PMODE_EVEN, + + USART_PARITY_ODD = SERCOM_USART_INT_CTRLB_PMODE_ODD, + + /* This enum is defined to set frame format only + * This value won't be written to register + */ + USART_PARITY_NONE = 0x2, + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_PARITY_INVALID = 0xFFFFFFFFU + +} USART_PARITY; + +// ***************************************************************************** +/* USART STOP + + Summary: + Defines the data type for the USART peripheral stop bits. + + Description: + This may be used to check the type of stop bits with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_STOP_0_BIT = SERCOM_USART_INT_CTRLB_SBMODE_1_BIT, + USART_STOP_1_BIT = SERCOM_USART_INT_CTRLB_SBMODE_2_BIT, + + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_STOP_INVALID = 0xFFFFFFFFU + +} USART_STOP; + +// ***************************************************************************** +/* USART LIN Command + + Summary: + Defines the data type for the USART peripheral LIN Command. + + Description: + This may be used to set the USART LIN Master mode command. + + Remarks: + None. +*/ + +typedef enum +{ + USART_LIN_MASTER_CMD_NONE = SERCOM_USART_INT_CTRLB_LINCMD_NONE, + + USART_LIN_MASTER_CMD_SOFTWARE_CONTROLLED = SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD, + + USART_LIN_MASTER_CMD_AUTO_TRANSMIT = SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD + +} USART_LIN_MASTER_CMD; + +// ***************************************************************************** +/* USART Serial Configuration + + Summary: + Defines the data type for the USART serial configurations. + + Description: + This may be used to set the serial configurations for USART. + + Remarks: + None. +*/ + +typedef struct +{ + uint32_t baudRate; + + USART_PARITY parity; + + USART_DATA dataWidth; + + USART_STOP stopBits; + +} USART_SERIAL_SETUP; + +// ***************************************************************************** +/* Callback Function Pointer + + Summary: + Defines the data type and function signature for the USART peripheral + callback function. + + Description: + This data type defines the function signature for the USART peripheral + callback function. The USART peripheral will call back the client's + function with this signature when the USART buffer event has occurred. + + Remarks: + None. +*/ + +typedef void (*SERCOM_USART_CALLBACK)( uintptr_t context ); + +// ***************************************************************************** +/* SERCOM USART Object + + Summary: + Defines the data type for the data structures used for + peripheral operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + void * txBuffer; + + size_t txSize; + + size_t txProcessedSize; + + SERCOM_USART_CALLBACK txCallback; + + uintptr_t txContext; + + bool txBusyStatus; + + void * rxBuffer; + + size_t rxSize; + + size_t rxProcessedSize; + + SERCOM_USART_CALLBACK rxCallback; + + uintptr_t rxContext; + + bool rxBusyStatus; + + USART_ERROR errorStatus; + +} SERCOM_USART_OBJECT; + + +typedef enum +{ + /* Threshold number of bytes are available in the receive ring buffer */ + SERCOM_USART_EVENT_READ_THRESHOLD_REACHED = 0, + + /* Receive ring buffer is full. Application must read the data out to avoid missing data on the next RX interrupt. */ + SERCOM_USART_EVENT_READ_BUFFER_FULL, + + /* USART error. Application must call the SERCOMx_USART_ErrorGet API to get the type of error and clear the error. */ + SERCOM_USART_EVENT_READ_ERROR, + + /* Threshold number of free space is available in the transmit ring buffer */ + SERCOM_USART_EVENT_WRITE_THRESHOLD_REACHED, + + /* Recevie break signal is detected */ + SERCOM_USART_EVENT_BREAK_SIGNAL_DETECTED, +}SERCOM_USART_EVENT; + +// ***************************************************************************** +/* Callback Function Pointer + + Summary: + Defines the data type and function signature for the USART peripheral + callback function. + + Description: + This data type defines the function signature for the USART peripheral + callback function. The USART peripheral will call back the client's + function with this signature when the USART buffer event has occurred. + + Remarks: + None. +*/ + +typedef void (*SERCOM_USART_RING_BUFFER_CALLBACK)(SERCOM_USART_EVENT event, uintptr_t context ); + +// ***************************************************************************** +/* SERCOM USART Ring Buffer Object + + Summary: + Defines the data type for the data structures used for + peripheral operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + SERCOM_USART_RING_BUFFER_CALLBACK wrCallback; + + uintptr_t wrContext; + + uint32_t wrInIndex; + + uint32_t wrOutIndex; + + uint32_t wrBufferSize; + + bool isWrNotificationEnabled; + + uint32_t wrThreshold; + + bool isWrNotifyPersistently; + + SERCOM_USART_RING_BUFFER_CALLBACK rdCallback; + + uintptr_t rdContext; + + uint32_t rdInIndex; + + uint32_t rdOutIndex; + + uint32_t rdBufferSize; + + bool isRdNotificationEnabled; + + uint32_t rdThreshold; + + bool isRdNotifyPersistently; + + USART_ERROR errorStatus; + +} SERCOM_USART_RING_BUFFER_OBJECT; + +// ***************************************************************************** +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM_USART_COMMON_H diff --git a/bms/bms/bms_config_e18a/src/config/default/startup_xc32.c b/bms/bms/bms_config_e18a/src/config/default/startup_xc32.c new file mode 100644 index 00000000..d9430dd5 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/startup_xc32.c @@ -0,0 +1,145 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include "device.h" +#include "interrupts.h" + +/* + * The MPLAB X Simulator does not yet support simulation of programming the + * GPNVM bits yet. We can remove this once it supports the FRDY bit. + */ + /* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.1 deviated 1 time. Deviation record ID - H3_MISRAC_2012_R_21_1_DR_1 */ +#ifdef __MPLAB_DEBUGGER_SIMULATOR +#define __XC32_SKIP_STARTUP_GPNVM_WAIT +#endif +/* MISRAC 2012 deviation block end */ + +/* + * This startup code relies on features that are specific to the MPLAB XC32 + * toolchain. Do not use it with other toolchains. + */ +#ifndef __XC32 +#warning This startup code is intended for use with the MPLAB XC32 Compiler only. +#endif + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated 5 times. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 6 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ + +/* array initialization function */ +extern void __attribute__((long_call)) __libc_init_array(void); + +/* Optional application-provided functions */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_bootstrap(void); + +/* Reserved for use by the MPLAB XC32 Compiler */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_bootstrap(void); + +/* Linker defined variables */ +extern uint32_t __svectors; +#if defined (__REINIT_STACK_POINTER) +extern uint32_t _stack; +#endif + +/* MISRAC 2012 deviation block end */ + + +extern int main(void); + + + +/* Brief default application function used as a weak reference */ +extern void Dummy_App_Func(void); +void __attribute__((optimize("-O1"),long_call))Dummy_App_Func(void) +{ + /* Do nothing */ + return; +} + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void __attribute__((optimize("-O1"), section(".text.Reset_Handler"), long_call, noreturn)) Reset_Handler(void) +{ +#ifdef SCB_VTOR_TBLOFF_Msk + uint32_t *pSrc; +#endif + +#if defined (__REINIT_STACK_POINTER) + /* Initialize SP from linker-defined _stack symbol. */ + __set_MSP((uint32_t)&_stack); + +#ifdef SCB_VTOR_TBLOFF_Msk + /* Buy stack for locals */ + __asm__ volatile ("sub sp, sp, #8" : : : "sp"); +#endif + __asm__ volatile ("add r7, sp, #0" : : : "r7"); +#endif + + /* Call the optional application-provided _on_reset() function. */ + _on_reset(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_reset(); + + /* Initialize data after TCM is enabled. + * Data initialization from the XC32 .dinit template */ + __pic32c_data_initialization(); + + +# ifdef SCB_VTOR_TBLOFF_Msk + /* Set the vector-table base address in FLASH */ + pSrc = (uint32_t *) & __svectors; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); +# endif /* SCB_VTOR_TBLOFF_Msk */ + + /* Initialize the C library */ + __libc_init_array(); + + /* Call the optional application-provided _on_bootstrap() function. */ + _on_bootstrap(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_bootstrap(); + + /* Branch to application's main function */ + (void)main(); + +#if (defined(__DEBUG) || defined(__DEBUG_D)) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + + while (true) + { + /* Infinite loop */ + } +} diff --git a/bms/bms/bms_config_e18a/src/config/default/stdio/xc32_monitor.c b/bms/bms/bms_config_e18a/src/config/default/stdio/xc32_monitor.c new file mode 100644 index 00000000..8d9df630 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/stdio/xc32_monitor.c @@ -0,0 +1,54 @@ +/******************************************************************************* + Debug Console Source file + + Company: + Microchip Technology Inc. + + File Name: + xc32_monitor.c + + Summary: + debug console Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +#include + +extern int read(int handle, void *buffer, unsigned int len); +extern int write(int handle, void * buffer, size_t count); + + +int read(int handle, void *buffer, unsigned int len) +{ + return -1; +} + +int write(int handle, void * buffer, size_t count) +{ + return -1; +} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/toolchain_specifics.h b/bms/bms/bms_config_e18a/src/config/default/toolchain_specifics.h new file mode 100644 index 00000000..96407a4e --- /dev/null +++ b/bms/bms/bms_config_e18a/src/config/default/toolchain_specifics.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef TOOLCHAIN_SPECIFICS_H +#define TOOLCHAIN_SPECIFICS_H + +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +#pragma GCC diagnostic push +#ifndef __cplusplus + #pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#include "cmsis_compiler.h" +#pragma GCC diagnostic pop + +#include + +#define NO_INIT __attribute__((section(".no_init"))) +#define SECTION(a) __attribute__((__section__(a))) + +#define CACHE_LINE_SIZE (4u) +#define CACHE_ALIGN + +#define CACHE_ALIGNED_SIZE_GET(size) ((size) + ((((size) % (CACHE_LINE_SIZE))!= 0U)? ((CACHE_LINE_SIZE) - ((size) % (CACHE_LINE_SIZE))) : (0U))) + +#ifndef FORMAT_ATTRIBUTE + #define FORMAT_ATTRIBUTE(archetype, string_index, first_to_check) __attribute__ ((format (archetype, string_index, first_to_check))) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // end of header + diff --git a/bms/bms/bms_config_e18a/src/ic_bms/BQ769x2Header.h b/bms/bms/bms_config_e18a/src/ic_bms/BQ769x2Header.h new file mode 100644 index 00000000..fe82dbf3 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/ic_bms/BQ769x2Header.h @@ -0,0 +1,409 @@ +//BQ769x2 General Program Header File + +//Data Memory registers Name in TRM +#define Cell1Gain 0x9180 //Calibration:Voltage:Cell 1 Gain +#define Cell2Gain 0x9182 //Calibration:Voltage:Cell 2 Gain +#define Cell3Gain 0x9184 //Calibration:Voltage:Cell 3 Gain +#define Cell4Gain 0x9186 //Calibration:Voltage:Cell 4 Gain +#define Cell5Gain 0x9188 //Calibration:Voltage:Cell 5 Gain +#define Cell6Gain 0x918A //Calibration:Voltage:Cell 6 Gain +#define Cell7Gain 0x918C //Calibration:Voltage:Cell 7 Gain +#define Cell8Gain 0x918E //Calibration:Voltage:Cell 8 Gain +#define Cell9Gain 0x9190 //Calibration:Voltage:Cell 9 Gain +#define Cell10Gain 0x9192 //Calibration:Voltage:Cell 10 Gain +#define Cell11Gain 0x9194 //Calibration:Voltage:Cell 11 Gain +#define Cell12Gain 0x9196 //Calibration:Voltage:Cell 12 Gain +#define Cell13Gain 0x9198 //Calibration:Voltage:Cell 13 Gain +#define Cell14Gain 0x919A //Calibration:Voltage:Cell 14 Gain +#define Cell15Gain 0x919C //Calibration:Voltage:Cell 15 Gain +#define Cell16Gain 0x919E //Calibration:Voltage:Cell 16 Gain +#define PackGain 0x91A0 //Calibration:Voltage:Pack Gain +#define TOSGain 0x91A2 //Calibration:Voltage:TOS Gain +#define LDGain 0x91A4 //Calibration:Voltage:LD Gain +#define ADCGain 0x91A6 //Calibration:Voltage:ADC Gain +#define CCGain 0x91A8 //Calibration:Current:CC Gain +#define CapacityGain 0x91AC //Calibration:Current:Capacity Gain +#define VcellOffset 0x91B0 //Calibration:Vcell Offset:Vcell Offset +#define VdivOffset 0x91B2 //Calibration:V Divider Offset:Vdiv Offset +#define CoulombCounterOffsetSamples 0x91C6 //Calibration:Current Offset:Coulomb Counter Offset Samples +#define BoardOffset 0x91C8 //Calibration:Current Offset:Board Offset +#define InternalTempOffset 0x91CA //Calibration:Temperature:Internal Temp Offset +#define CFETOFFTempOffset 0x91CB //Calibration:Temperature:CFETOFF Temp Offset +#define DFETOFFTempOffset 0x91CC //Calibration:Temperature:DFETOFF Temp Offset +#define ALERTTempOffset 0x91CD //Calibration:Temperature:ALERT Temp Offset +#define TS1TempOffset 0x91CE //Calibration:Temperature:TS1 Temp Offset +#define TS2TempOffset 0x91CF //Calibration:Temperature:TS2 Temp Offset +#define TS3TempOffset 0x91D0 //Calibration:Temperature:TS3 Temp Offset +#define HDQTempOffset 0x91D1 //Calibration:Temperature:HDQ Temp Offset +#define DCHGTempOffset 0x91D2 //Calibration:Temperature:DCHG Temp Offset +#define DDSGTempOffset 0x91D3 //Calibration:Temperature:DDSG Temp Offset +#define IntGain 0x91E2 //Calibration:Internal Temp Model:Int Gain +#define Intbaseoffset 0x91E4 //Calibration:Internal Temp Model:Int base offset +#define IntMaximumAD 0x91E6 //Calibration:Internal Temp Model:Int Maximum AD +#define IntMaximumTemp 0x91E8 //Calibration:Internal Temp Model:Int Maximum Temp +#define T18kCoeffa1 0x91EA //Calibration:18K Temperature Model:Coeff a1 +#define T18kCoeffa2 0x91EC //Calibration:18K Temperature Model:Coeff a2 +#define T18kCoeffa3 0x91EE //Calibration:18K Temperature Model:Coeff a3 +#define T18kCoeffa4 0x91F0 //Calibration:18K Temperature Model:Coeff a4 +#define T18kCoeffa5 0x91F2 //Calibration:18K Temperature Model:Coeff a5 +#define T18kCoeffb1 0x91F4 //Calibration:18K Temperature Model:Coeff b1 +#define T18kCoeffb2 0x91F6 //Calibration:18K Temperature Model:Coeff b2 +#define T18kCoeffb3 0x91F8 //Calibration:18K Temperature Model:Coeff b3 +#define T18kCoeffb4 0x91FA //Calibration:18K Temperature Model:Coeff b4 +#define T18kAdc0 0x91FE //Calibration:18K Temperature Model:Adc0 +#define T180kCoeffa1 0x9200 //Calibration:180K Temperature Model:Coeff a1 +#define T180kCoeffa2 0x9202 //Calibration:180K Temperature Model:Coeff a2 +#define T180kCoeffa3 0x9204 //Calibration:180K Temperature Model:Coeff a3 +#define T180kCoeffa4 0x9206 //Calibration:180K Temperature Model:Coeff a4 +#define T180kCoeffa5 0x9208 //Calibration:180K Temperature Model:Coeff a5 +#define T180kCoeffb1 0x920A //Calibration:180K Temperature Model:Coeff b1 +#define T180kCoeffb2 0x920C //Calibration:180K Temperature Model:Coeff b2 +#define T180kCoeffb3 0x920E //Calibration:180K Temperature Model:Coeff b3 +#define T180kCoeffb4 0x9210 //Calibration:180K Temperature Model:Coeff b4 +#define T180kAdc0 0x9214 //Calibration:180K Temperature Model:Adc0 +#define CustomCoeffa1 0x9216 //Calibration:Custom Temperature Model:Coeff a1 +#define CustomCoeffa2 0x9218 //Calibration:Custom Temperature Model:Coeff a2 +#define CustomCoeffa3 0x921A //Calibration:Custom Temperature Model:Coeff a3 +#define CustomCoeffa4 0x921C //Calibration:Custom Temperature Model:Coeff a4 +#define CustomCoeffa5 0x921E //Calibration:Custom Temperature Model:Coeff a5 +#define CustomCoeffb1 0x9220 //Calibration:Custom Temperature Model:Coeff b1 +#define CustomCoeffb2 0x9222 //Calibration:Custom Temperature Model:Coeff b2 +#define CustomCoeffb3 0x9224 //Calibration:Custom Temperature Model:Coeff b3 +#define CustomCoeffb4 0x9226 //Calibration:Custom Temperature Model:Coeff b4 +#define CustomRc0 0x9228 //Calibration:Custom Temperature Model:Rc0 +#define CustomAdc0 0x922A //Calibration:Custom Temperature Model:Adc0 +#define CoulombCounterDeadband 0x922D //Calibration:Current Deadband:Coulomb Counter Deadband +#define CUVThresholdOverride 0x91D4 //Calibration:CUV:CUV Threshold Override +#define COVThresholdOverride 0x91D6 //Calibration:COV:COV Threshold Override +#define MinBlowFuseVoltage 0x9231 //Settings:Fuse:Min Blow Fuse Voltage +#define FuseBlowTimeout 0x9233 //Settings:Fuse:Fuse Blow Timeout +#define PowerConfig 0x9234 //Settings:Configuration:Power Config +#define REG12Config 0x9236 //Settings:Configuration:REG12 Config +#define REG0Config 0x9237 //Settings:Configuration:REG0 Config +#define HWDRegulatorOptions 0x9238 //Settings:Configuration:HWD Regulator Options +#define CommType 0x9239 //Settings:Configuration:Comm Type +#define I2CAddress 0x923A //Settings:Configuration:I2C Address +#define SPIConfiguration 0x923C //Settings:Configuration:SPI Configuration +#define CommIdleTime 0x923D //Settings:Configuration:Comm Idle Time +#define CFETOFFPinConfig 0x92FA //Settings:Configuration:CFETOFF Pin Config +#define DFETOFFPinConfig 0x92FB //Settings:Configuration:DFETOFF Pin Config +#define ALERTPinConfig 0x92FC //Settings:Configuration:ALERT Pin Config +#define TS1Config 0x92FD //Settings:Configuration:TS1 Config +#define TS2Config 0x92FE //Settings:Configuration:TS2 Config +#define TS3Config 0x92FF //Settings:Configuration:TS3 Config +#define HDQPinConfig 0x9300 //Settings:Configuration:HDQ Pin Config +#define DCHGPinConfig 0x9301 //Settings:Configuration:DCHG Pin Config +#define DDSGPinConfig 0x9302 //Settings:Configuration:DDSG Pin Config +#define DAConfiguration 0x9303 //Settings:Configuration:DA Configuration +#define VCellMode 0x9304 //Settings:Configuration:Vcell Mode +#define CC3Samples 0x9307 //Settings:Configuration:CC3 Samples +#define ProtectionConfiguration 0x925F //Settings:Protection:Protection Configuration +#define EnabledProtectionsA 0x9261 //Settings:Protection:Enabled Protections A +#define EnabledProtectionsB 0x9262 //Settings:Protection:Enabled Protections B +#define EnabledProtectionsC 0x9263 //Settings:Protection:Enabled Protections C +#define CHGFETProtectionsA 0x9265 //Settings:Protection:CHG FET Protections A +#define CHGFETProtectionsB 0x9266 //Settings:Protection:CHG FET Protections B +#define CHGFETProtectionsC 0x9267 //Settings:Protection:CHG FET Protections C +#define DSGFETProtectionsA 0x9269 //Settings:Protection:DSG FET Protections A +#define DSGFETProtectionsB 0x926A //Settings:Protection:DSG FET Protections B +#define DSGFETProtectionsC 0x926B //Settings:Protection:DSG FET Protections C +#define BodyDiodeThreshold 0x9273 //Settings:Protection:Body Diode Threshold +#define DefaultAlarmMask 0x926D //Settings:Alarm:Default Alarm Mask +#define SFAlertMaskA 0x926F //Settings:Alarm:SF Alert Mask A +#define SFAlertMaskB 0x9270 //Settings:Alarm:SF Alert Mask B +#define SFAlertMaskC 0x9271 //Settings:Alarm:SF Alert Mask C +#define PFAlertMaskA 0x92C4 //Settings:Alarm:PF Alert Mask A +#define PFAlertMaskB 0x92C5 //Settings:Alarm:PF Alert Mask B +#define PFAlertMaskC 0x92C6 //Settings:Alarm:PF Alert Mask C +#define PFAlertMaskD 0x92C7 //Settings:Alarm:PF Alert Mask D +#define EnabledPFA 0x92C0 //Settings:Permanent Failure:Enabled PF A +#define EnabledPFB 0x92C1 //Settings:Permanent Failure:Enabled PF B +#define EnabledPFC 0x92C2 //Settings:Permanent Failure:Enabled PF C +#define EnabledPFD 0x92C3 //Settings:Permanent Failure:Enabled PF D +#define FETOptions 0x9308 //Settings:FET:FET Options +#define ChgPumpControl 0x9309 //Settings:FET:Chg Pump Control +#define PrechargeStartVoltage 0x930A //Settings:FET:Precharge Start Voltage +#define PrechargeStopVoltage 0x930C //Settings:FET:Precharge Stop Voltage +#define PredischargeTimeout 0x930E //Settings:FET:Predischarge Timeout +#define PredischargeStopDelta 0x930F //Settings:FET:Predischarge Stop Delta +#define DsgCurrentThreshold 0x9310 //Settings:Current Thresholds:Dsg Current Threshold +#define ChgCurrentThreshold 0x9312 //Settings:Current Thresholds:Chg Current Threshold +#define CheckTime 0x9314 //Settings:Cell Open-Wire:Check Time +#define Cell1Interconnect 0x9315 //Settings:Interconnect Resistances:Cell 1 Interconnect +#define Cell2Interconnect 0x9317 //Settings:Interconnect Resistances:Cell 2 Interconnect +#define Cell3Interconnect 0x9319 //Settings:Interconnect Resistances:Cell 3 Interconnect +#define Cell4Interconnect 0x931B //Settings:Interconnect Resistances:Cell 4 Interconnect +#define Cell5Interconnect 0x931D //Settings:Interconnect Resistances:Cell 5 Interconnect +#define Cell6Interconnect 0x931F //Settings:Interconnect Resistances:Cell 6 Interconnect +#define Cell7Interconnect 0x9321 //Settings:Interconnect Resistances:Cell 7 Interconnect +#define Cell8Interconnect 0x9323 //Settings:Interconnect Resistances:Cell 8 Interconnect +#define Cell9Interconnect 0x9325 //Settings:Interconnect Resistances:Cell 9 Interconnect +#define Cell10Interconnect 0x9327 //Settings:Interconnect Resistances:Cell 10 Interconnect +#define Cell11Interconnect 0x9329 //Settings:Interconnect Resistances:Cell 11 Interconnect +#define Cell12Interconnect 0x932B //Settings:Interconnect Resistances:Cell 12 Interconnect +#define Cell13Interconnect 0x932D //Settings:Interconnect Resistances:Cell 13 Interconnect +#define Cell14Interconnect 0x932F //Settings:Interconnect Resistances:Cell 14 Interconnect +#define Cell15Interconnect 0x9331 //Settings:Interconnect Resistances:Cell 15 Interconnect +#define Cell16Interconnect 0x9333 //Settings:Interconnect Resistances:Cell 16 Interconnect +#define MfgStatusInit 0x9343 //Settings:Manufacturing:Mfg Status Init +#define BalancingConfiguration 0x9335 //Settings:Cell Balancing Config:Balancing Configuration +#define MinCellTemp 0x9336 //Settings:Cell Balancing Config:Min Cell Temp +#define MaxCellTemp 0x9337 //Settings:Cell Balancing Config:Max Cell Temp +#define MaxInternalTemp 0x9338 //Settings:Cell Balancing Config:Max Internal Temp +#define CellBalanceInterval 0x9339 //Settings:Cell Balancing Config:Cell Balance Interval +#define CellBalanceMaxCells 0x933A //Settings:Cell Balancing Config:Cell Balance Max Cells +#define CellBalanceMinCellVCharge 0x933B //Settings:Cell Balancing Config:Cell Balance Min Cell V (Charge) +#define CellBalanceMinDeltaCharge 0x933D //Settings:Cell Balancing Config:Cell Balance Min Delta (Charge) +#define CellBalanceStopDeltaCharge 0x933E //Settings:Cell Balancing Config:Cell Balance Stop Delta (Charge) +#define CellBalanceMinCellVRelax 0x933F //Settings:Cell Balancing Config:Cell Balance Min Cell V (Relax) +#define CellBalanceMinDeltaRelax 0x9341 //Settings:Cell Balancing Config:Cell Balance Min Delta (Relax) +#define CellBalanceStopDeltaRelax 0x9342 //Settings:Cell Balancing Config:Cell Balance Stop Delta (Relax) +#define ShutdownCellVoltage 0x923F //Power:Shutdown:Shutdown Cell Voltage +#define ShutdownStackVoltage 0x9241 //Power:Shutdown:Shutdown Stack Voltage +#define LowVShutdownDelay 0x9243 //Power:Shutdown:Low V Shutdown Delay +#define ShutdownTemperature 0x9244 //Power:Shutdown:Shutdown Temperature +#define ShutdownTemperatureDelay 0x9245 //Power:Shutdown:Shutdown Temperature Delay +#define FETOffDelay 0x9252 //Power:Shutdown:FET Off Delay +#define ShutdownCommandDelay 0x9253 //Power:Shutdown:Shutdown Command Delay +#define AutoShutdownTime 0x9254 //Power:Shutdown:Auto Shutdown Time +#define RAMFailShutdownTime 0x9255 //Power:Shutdown:RAM Fail Shutdown Time +#define SleepCurrent 0x9248 //Power:Sleep:Sleep Current +#define VoltageTime 0x924A //Power:Sleep:Voltage Time +#define WakeComparatorCurrent 0x924B //Power:Sleep:Wake Comparator Current +#define SleepHysteresisTime 0x924D //Power:Sleep:Sleep Hysteresis Time +#define SleepChargerVoltageThreshold 0x924E //Power:Sleep:Sleep Charger Voltage Threshold +#define SleepChargerPACKTOSDelta 0x9250 //Power:Sleep:Sleep Charger PACK-TOS Delta +#define ConfigRAMSignature 0x91E0 //System Data:Integrity:Config RAM Signature +#define CUVThreshold 0x9275 //Protections:CUV:Threshold +#define CUVDelay 0x9276 //Protections:CUV:Delay +#define CUVRecoveryHysteresis 0x927B //Protections:CUV:Recovery Hysteresis +#define COVThreshold 0x9278 //Protections:COV:Threshold +#define COVDelay 0x9279 //Protections:COV:Delay +#define COVRecoveryHysteresis 0x927C //Protections:COV:Recovery Hysteresis +#define COVLLatchLimit 0x927D //Protections:COVL:Latch Limit +#define COVLCounterDecDelay 0x927E //Protections:COVL:Counter Dec Delay +#define COVLRecoveryTime 0x927F //Protections:COVL:Recovery Time +#define OCCThreshold 0x9280 //Protections:OCC:Threshold +#define OCCDelay 0x9281 //Protections:OCC:Delay +#define OCCRecoveryThreshold 0x9288 //Protections:OCC:Recovery Threshold +#define OCCPACKTOSDelta 0x92B0 //Protections:OCC:PACK-TOS Delta +#define OCD1Threshold 0x9282 //Protections:OCD1:Threshold +#define OCD1Delay 0x9283 //Protections:OCD1:Delay +#define OCD2Threshold 0x9284 //Protections:OCD2:Threshold +#define OCD2Delay 0x9285 //Protections:OCD2:Delay +#define SCDThreshold 0x9286 //Protections:SCD:Threshold +#define SCDDelay 0x9287 //Protections:SCD:Delay +#define SCDRecoveryTime 0x9294 //Protections:SCD:Recovery Time +#define OCD3Threshold 0x928A //Protections:OCD3:Threshold +#define OCD3Delay 0x928C //Protections:OCD3:Delay +#define OCDRecoveryThreshold 0x928D //Protections:OCD:Recovery Threshold +#define OCDLLatchLimit 0x928F //Protections:OCDL:Latch Limit +#define OCDLCounterDecDelay 0x9290 //Protections:OCDL:Counter Dec Delay +#define OCDLRecoveryTime 0x9291 //Protections:OCDL:Recovery Time +#define OCDLRecoveryThreshold 0x9292 //Protections:OCDL:Recovery Threshold +#define SCDLLatchLimit 0x9295 //Protections:SCDL:Latch Limit +#define SCDLCounterDecDelay 0x9296 //Protections:SCDL:Counter Dec Delay +#define SCDLRecoveryTime 0x9297 //Protections:SCDL:Recovery Time +#define SCDLRecoveryThreshold 0x9298 //Protections:SCDL:Recovery Threshold +#define OTCThreshold 0x929A //Protections:OTC:Threshold +#define OTCDelay 0x920B //Protections:OTC:Delay +#define OTCRecovery 0x929C //Protections:OTC:Recovery +#define OTDThreshold 0x929D //Protections:OTD:Threshold +#define OTDDelay 0x929E //Protections:OTD:Delay +#define OTDRecovery 0x929F //Protections:OTD:Recovery +#define OTFThreshold 0x92A0 //Protections:OTF:Threshold +#define OTFDelay 0x92A1 //Protections:OTF:Delay +#define OTFRecovery 0x92A2 //Protections:OTF:Recovery +#define OTINTThreshold 0x92A3 //Protections:OTINT:Threshold +#define OTINTDelay 0x92A4 //Protections:OTINT:Delay +#define OTINTRecovery 0x92A5 //Protections:OTINT:Recovery +#define UTCThreshold 0x92A6 //Protections:UTC:Threshold +#define UTCDelay 0x92A7 //Protections:UTC:Delay +#define UTCRecovery 0x92A8 //Protections:UTC:Recovery +#define UTDThreshold 0x92A9 //Protections:UTD:Threshold +#define UTDDelay 0x92AA //Protections:UTD:Delay +#define UTDRecovery 0x92AB //Protections:UTD:Recovery +#define UTINTThreshold 0x92AC //Protections:UTINT:Threshold +#define UTINTDelay 0x92AD //Protections:UTINT:Delay +#define UTINTRecovery 0x92AE //Protections:UTINT:Recovery +#define ProtectionsRecoveryTime 0x92AF //Protections:Recovery:Time +#define HWDDelay 0x92B2 //Protections:HWD:Delay +#define LoadDetectActiveTime 0x92B4 //Protections:Load Detect:Active Time +#define LoadDetectRetryDelay 0x92B5 //Protections:Load Detect:Retry Delay +#define LoadDetectTimeout 0x92B6 //Protections:Load Detect:Timeout +#define PTOChargeThreshold 0x92BA //Protections:PTO:Charge Threshold +#define PTODelay 0x92BC //Protections:PTO:Delay +#define PTOReset 0x92BE //Protections:PTO:Reset +#define CUDEPThreshold 0x92C8 //Permanent Fail:CUDEP:Threshold +#define CUDEPDelay 0x92CA //Permanent Fail:CUDEP:Delay +#define SUVThreshold 0x92CB //Permanent Fail:SUV:Threshold +#define SUVDelay 0x92CD //Permanent Fail:SUV:Delay +#define SOVThreshold 0x92CE //Permanent Fail:SOV:Threshold +#define SOVDelay 0x92D0 //Permanent Fail:SOV:Delay +#define TOSSThreshold 0x92D1 //Permanent Fail:TOS:Threshold +#define TOSSDelay 0x92D3 //Permanent Fail:TOS:Delay +#define SOCCThreshold 0x92D4 //Permanent Fail:SOCC:Threshold +#define SOCCDelay 0x92D6 //Permanent Fail:SOCC:Delay +#define SOCDThreshold 0x92D7 //Permanent Fail:SOCD:Threshold +#define SOCDDelay 0x92D9 //Permanent Fail:SOCD:Delay +#define SOTThreshold 0x92DA //Permanent Fail:SOT:Threshold +#define SOTDelay 0x92DB //Permanent Fail:SOT:Delay +#define SOTFThreshold 0x92DC //Permanent Fail:SOTF:Threshold +#define SOTFDelay 0x92DD //Permanent Fail:SOTF:Delay +#define VIMRCheckVoltage 0x92DE //Permanent Fail:VIMR:Check Voltage +#define VIMRMaxRelaxCurrent 0x92E0 //Permanent Fail:VIMR:Max Relax Current +#define VIMRThreshold 0x92E2 //Permanent Fail:VIMR:Threshold +#define VIMRDelay 0x92E4 //Permanent Fail:VIMR:Delay +#define VIMRRelaxMinDuration 0x92E5 //Permanent Fail:VIMR:Relax Min Duration +#define VIMACheckVoltage 0x92E7 //Permanent Fail:VIMA:Check Voltage +#define VIMAMinActiveCurrent 0x92E9 //Permanent Fail:VIMA:Min Active Current +#define VIMAThreshold 0x92EB //Permanent Fail:VIMA:Threshold +#define VIMADelay 0x92ED //Permanent Fail:VIMA:Delay +#define CFETFOFFThreshold 0x92EE //Permanent Fail:CFETF:OFF Threshold +#define CFETFOFFDelay 0x92F0 //Permanent Fail:CFETF:OFF Delay +#define DFETFOFFThreshold 0x92F1 //Permanent Fail:DFETF:OFF Threshold +#define DFETFOFFDelay 0x92F3 //Permanent Fail:DFETF:OFF Delay +#define VSSFFailThreshold 0x92F4 //Permanent Fail:VSSF:Fail Threshold +#define VSSFDelay 0x92F6 //Permanent Fail:VSSF:Delay +#define PF2LVLDelay 0x92F7 //Permanent Fail:2LVL:Delay +#define LFOFDelay 0x92F8 //Permanent Fail:LFOF:Delay +#define HWMXDelay 0x92F9 //Permanent Fail:HWMX:Delay +#define SecuritySettings 0x9256 //Security:Settings:Security Settings +#define UnsealKeyStep1 0x9257 //Security:Keys:Unseal Key Step 1 +#define UnsealKeyStep2 0x9259 //Security:Keys:Unseal Key Step 2 +#define FullAccessKeyStep1 0x925B //Security:Keys:Full Access Key Step 1 +#define FullAccessKeyStep2 0x925D //Security:Keys:Full Access Key Step 2 + +//Direct Commands +#define ControlStatus 0x00 +#define SafetyAlertA 0x02 +#define SafetyStatusA 0x03 +#define SafetyAlertB 0x04 +#define SafetyStatusB 0x05 +#define SafetyAlertC 0x06 +#define SafetyStatusC 0x07 +#define PFAlertA 0x0A +#define PFStatusA 0x0B +#define PFAlertB 0x0C +#define PFStatusB 0x0D +#define PFAlertC 0x0E +#define PFStatusC 0x0F +#define PFAlertD 0x10 +#define PFStatusD 0x11 +#define BatteryStatus 0x12 +#define Cell1Voltage 0x14 +#define Cell2Voltage 0x16 +#define Cell3Voltage 0x18 +#define Cell4Voltage 0x1A +#define Cell5Voltage 0x1C +#define Cell6Voltage 0x1E +#define Cell7Voltage 0x20 +#define Cell8Voltage 0x22 +#define Cell9Voltage 0x24 +#define Cell10Voltage 0x26 +#define Cell11Voltage 0x28 +#define Cell12Voltage 0x2A +#define Cell13Voltage 0x2C +#define Cell14Voltage 0x2E +#define Cell15Voltage 0x30 +#define Cell16Voltage 0x32 +#define StackVoltage 0x34 +#define PACKPinVoltage 0x36 +#define LDPinVoltage 0x38 +#define CC2Current 0x3A +#define AlarmStatus 0x62 +#define AlarmRawStatus 0x64 +#define AlarmEnable 0x66 +#define IntTemperature 0x68 +#define CFETOFFTemperature 0x6A +#define DFETOFFTemperature 0x6C +#define ALERTTemperature 0x6E +#define TS1Temperature 0x70 +#define TS2Temperature 0x72 +#define TS3Temperature 0x74 +#define HDQTemperature 0x76 +#define DCHGTemperature 0x78 +#define DDSGTemperature 0x7A +#define FETStatus 0x7F + +//Subcommands +#define DEVICE_NUMBER 0x0001 +#define FW_VERSION 0x0002 +#define HW_VERSION 0x0003 +#define IROM_SIG 0x0004 +#define STATIC_CFG_SIG 0x0005 +#define PREV_MACWRITE 0x0007 +#define DROM_SIG 0x0009 +#define SECURITY_KEYS 0x0035 +#define SAVED_PF_STATUS 0x0053 +#define MANUFACTURINGSTATUS 0x0057 +#define MANU_DATA 0x0070 +#define DASTATUS1 0x0071 +#define DASTATUS2 0x0072 +#define DASTATUS3 0x0073 +#define DASTATUS4 0x0074 +#define DASTATUS5 0x0075 +#define DASTATUS6 0x0076 +#define DASTATUS7 0x0077 +#define CUV_SNAPSHOT 0x0080 +#define COV_SNAPSHOT 0X0081 +#define CB_ACTIVE_CELLS 0x0083 +#define CB_SET_LVL 0x0084 +#define CBSTATUS1 0x0085 +#define CBSTATUS2 0x0086 +#define CBSTATUS3 0x0087 +#define FET_CONTROL 0x0097 +#define REG12_CONTROL 0x0098 +#define OTP_WR_CHECK 0x00A0 +#define OTP_WRITE 0x00A1 +#define READ_CAL1 0xF081 +#define CAL_CUV 0xF090 +#define CAL_COV 0xF091 + +// Command Only Subcommands +#define EXIT_DEEPSLEEP 0x000E +#define DEEPSLEEP 0x000F +#define SHUTDOWN 0x0010 +#define BQ769x2_RESET 0x0012 //"RESET" in documentation +#define PDSGTEST 0x001C +#define FUSE_TOGGLE 0x001D +#define PCHGTEST 0x001E +#define CHGTEST 0x001F +#define DSGTEST 0x0020 +#define FET_ENABLE 0x0022 +#define PF_ENABLE 0x0024 +#define PF_RESET 0x0029 +#define SEAL 0x0030 +#define RESET_PASSQ 0x0082 +#define PTO_RECOVER 0x008A +#define SET_CFGUPDATE 0x0090 +#define EXIT_CFGUPDATE 0x0092 +#define DSG_PDSG_OFF 0x0093 +#define CHG_PCHG_OFF 0x0094 +#define ALL_FETS_OFF 0x0095 +#define ALL_FETS_ON 0x0096 +#define SLEEP_ENABLE 0x0099 +#define SLEEP_DISABLE 0x009A +#define OCDL_RECOVER 0x009B +#define SCDL_RECOVER 0x009C +#define LOAD_DETECT_RESTART 0x009D +#define LOAD_DETECT_ON 0x009E +#define LOAD_DETECT_OFF 0x009F +#define CFETOFF_LO 0x2800 +#define DFETOFF_LO 0x2801 +#define ALERT_LO 0x2802 +#define HDQ_LO 0x2806 +#define DCHG_LO 0x2807 +#define DDSG_LO 0x2808 +#define CFETOFF_HI 0x2810 +#define DFETOFF_HI 0x2811 +#define ALERT_HI 0x2812 +#define HDQ_HI 0x2816 +#define DCHG_HI 0x2817 +#define DDSG_HI 0x2818 +#define PF_FORCE_A 0x2857 +#define PF_FORCE_B 0x29A3 +#define SWAP_COMM_MODE 0x29BC +#define SWAP_TO_I2C 0x29E7 +#define SWAP_TO_SPI 0x7C35 +#define SWAP_TO_HDQ 0x7C40 diff --git a/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.c b/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.c new file mode 100644 index 00000000..05e886a8 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.c @@ -0,0 +1,460 @@ +#include +#include +#include +#include +#include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" +#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" +#include "definitions.h" +#include "bms_spi.h" + + + + +static inline void bq_cs_low(void) { PORT_REGS->GROUP[bq_cs_group].PORT_OUTCLR = bq_cs_mask; } +static inline void bq_cs_high(void) { PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; } + +static inline void _delay(uint32_t cycles){ + + for (volatile uint32_t i=0; iGROUP[bq_cs_group].PORT_DIRSET = bq_cs_mask; + PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; // Set HIGH (inactive) + + // --- IC configuration sequence --- + bq_command_only(ENTER_CONFIG_UPDATE); + bms_set_protection_threshold(); + bq_command_only(EXIT_CONFIG_UPDATE); + + // Status check + uint8_t status = 0; + if (bq_direct_read(0x12, &status, 1)) + printf("BQ76942 communication OK\n"); + else + printf("BQ76942 communication failed\n"); +} + + +bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) +{ + if (SERCOM0_SPI_IsBusy()) + return false; + + bq_cs_low(); + bool ok = SERCOM0_SPI_WriteRead(tx, length, rx, length); + if (ok) + { + ok = bq_spi_wait_idle(); + } + bq_cs_high(); + + return ok; +} + +static uint8_t bq_crc8_calc(const uint8_t *data, uint8_t len) +{ + uint8_t crc = 0x00; // init + + for (uint8_t i = 0; i < len; i++) { + + crc ^= data[i]; // XOR in next byte + for (uint8_t b = 0; b < 8; b++) { + if (crc & 0x80) // test MSB + crc = (uint8_t)((crc << 1) ^ 0x07); + else + crc <<= 1; + } + } + return crc; +} + + +bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length) +{ + + + if (SERCOM0_SPI_IsBusy()) + return false; + if (length == 0) + return true; + + // Pack back-to-back 24-bit frames: [cmd, data_byte, crc] * length + uint8_t tx_bytes[3 * length]; + + for (uint8_t i=0;i> 8) & 0xFF; // MSB + ok = bq_direct_write(command, buf, 2); + } + else if (type == 'R') // Read + { + ok = bq_direct_read(command, buf, 2); + if (ok) + *data = (uint16_t)(buf[0] | (buf[1] << 8)); // Little endian + } + + + return ok; +} + + +bool bq_command_only(uint16_t subcmd){ + + + // Send 0x3E/0x3F in one SPI frame + uint8_t two[2] = { + (uint8_t)(subcmd & 0xFF), + (uint8_t)((subcmd >> 8) & 0xFF) + }; + if (!write_reg(0x3E, two, 2)) + return false; + + return true; +} + +/* + example of BQ_commandOnly usage: + + Reset the BQ76942 + BQ_CommandOnly(RESET); +*/ + + +bool bq_read_sub_command(uint16_t subcmd, uint8_t *data, uint8_t length) +{ + if (length > 32) + length = 32; + + // Write subcommand (0x3E LSB, 0x3F MSB) in one frame + uint8_t sub[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) }; + if (!write_reg(0x3E, sub, 2)) + return false; + + // Poll for echo of 0x3E/0x3F (in as few frames as possible) + uint8_t echo[2] = {0xFF, 0xFF}; + uint32_t tries = 0; + do { + if (!read_reg(0x3E, echo, 2)) + return false; + if (++tries > BQ_SUBCMD_MAX_POLLS) + return false; + } while ((echo[0] == 0xFF && echo[1] == 0xFF) || echo[0] != sub[0] || echo[1] != sub[1]); + + // Read full buffer 0x40..0x61 (34 bytes) in one frame + uint8_t buf[34]; + if (!read_reg(0x40, buf, sizeof(buf))) + return false; + + uint8_t len_total = buf[0x61 - 0x40]; + if (len_total < 4) // must include 0x3E,0x3F,0x60,0x61 => 4 minimum + return false; + + uint8_t buf_len = (uint8_t)(len_total - 4); + if (buf_len > 32) + buf_len = 32; + + // Copy out payload (0x40.. as the buffer start) + uint8_t to_copy = (length < buf_len) ? length : buf_len; + memcpy(data, buf, to_copy); + + // Verify checksum + uint8_t sum = (uint8_t)(sub[0] + sub[1]); + for (uint8_t i = 0; i < buf_len; i++) + sum = (uint8_t)(sum + buf[i]); + + uint8_t ck_calc = (uint8_t)(0xFF - (sum & 0xFF)); + uint8_t ck_read = buf[0x60 - 0x40]; + + return (ck_read == ck_calc); +} + +bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length) +{ + if (length > 32) + return false; + + // Subcommand in one frame + uint8_t sub[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) }; + if (!write_reg(0x3E, sub, 2)) + return false; + + // Write payload 0x40.. in one frame + if (length > 0 && !write_reg(0x40, data, length)) + return false; + + // Write checksum+length (0x60, 0x61) in one frame + uint8_t sum = (uint8_t)(sub[0] + sub[1]); + for (uint8_t i = 0; i < length; i++) + sum = (uint8_t)(sum + data[i]); + + //verify checksum + uint8_t tail[2]; + tail[0] = (uint8_t)(0xFF - (sum & 0xFF)); + tail[1] = (uint8_t)(4 + length); + if (!write_reg(0x60, tail, 2)) + return false; + + return true; +} + + + +void bms_set_protection_threshold(void) +{ + + bq_command_only(ENTER_CONFIG_UPDATE); + + + uint8_t cov_val = (uint8_t)(COV_THRESHOLD_MV / 50.6f + 0.5f); + if (cov_val < 20) cov_val = 20; + if (cov_val > 110) cov_val = 110; + bq_write_subcommand(COV_THRESHOLD_ADDR, &cov_val, 1); + + uint16_t cov_delay_ticks = (uint16_t)(COV_DELAY_MS / 3.3f + 0.5f); + uint8_t cov_delay_bytes[2] = { + (uint8_t)(cov_delay_ticks & 0xFF), + (uint8_t)((cov_delay_ticks >> 8) & 0xFF) + }; + bq_write_subcommand(COV_DELAY_ADDR, cov_delay_bytes, 2); + + + uint8_t cuv_val = (uint8_t)(CUV_THRESHOLD_MV / 50.6f + 0.5f); + if (cuv_val < 20) cuv_val = 20; + if (cuv_val > 110) cuv_val = 110; + bq_write_subcommand(CUV_THRESHOLD_ADDR, &cuv_val, 1); + + uint16_t cuv_delay_ticks = (uint16_t)(CUV_DELAY_MS / 3.3f + 0.5f); + uint8_t cuv_delay_bytes[2] = { + (uint8_t)(cuv_delay_ticks & 0xFF), + (uint8_t)((cuv_delay_ticks >> 8) & 0xFF) + }; + bq_write_subcommand(CUV_DELAY_ADDR, cuv_delay_bytes, 2); + + + bq_command_only(EXIT_CONFIG_UPDATE); +} + + +void bms_battery_status(void){ + + uint8_t fetReg=0; + + if(!bq_direct_read(FET_STATUS, &fetReg, 1)){ + printf("Failed to read FET status\n"); + return; + } + + bool chg_on = (fetReg & (1 << 0)); // CHG_FET bit + bool pchg_on = (fetReg & (1 << 1)); // PCHG_FET bit + bool dsg_on = (fetReg & (1 << 2)); // DSG_FET bit + + + if (pchg_on) + printf("Battery in precharge mode\n"); //maybe not printf + else if (chg_on && !dsg_on) + printf("Battery is charging\n"); + else if (dsg_on && !chg_on) + printf("Battery is discharging\n"); + else if (!chg_on && !dsg_on) + printf("Battery is idle\n"); + else + printf("Both CHG_FET and DSG_FET ACTIVE (transition)\n"); + + + +} + + +bool read_cells_1to6(uint16_t cell_mV[6]) +{ + const uint8_t addr[6] = { + CELL_1_VOLTAGE, CELL_2_VOLTAGE, CELL_3_VOLTAGE, + CELL_4_VOLTAGE, CELL_5_VOLTAGE, CELL_6_VOLTAGE + }; + uint16_t raw = 0; + uint8_t i; + bool ok = true; + + if (cell_mV == NULL) + return false; + + for (i = 0; i < 6; i++) + { + if (bq_direct_command(addr[i], &raw, R)) + { + cell_mV[i] = raw; // mV + } + else + { + cell_mV[i] = 0; + ok = false; + } + } + return ok; +} + + + +bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC) +{ + uint16_t raw; + + if (temp_dC == 0) + return false; + + if (!bq_direct_command(ts_cmd, &raw, 'R')) + return false; + + *temp_dC = (int16_t)raw - 2731; // raw is signed 0.1 K -> 0.1 C + + return true; + } + +bool bms_read_current(int16_t *current_mA) +{ + uint16_t raw; + + if (current_mA == 0) + return false; + if (!bq_direct_command(CC2_CURRENT, &raw, 'R')) + return false; + + *current_mA = (int16_t)raw; + return true; + + +} + +void bothoff_init(void) +{ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[PIN_BOTHOFF] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); // GPIO mode + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRSET = BOTHOFF_PIN_MASK; // Set as output + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Safe default: HIGH (bothoff OFF) +} + +void bothoff_high(void) +{ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Set HIGH to turn bothoff OFF +} +void bothoff_low(void) +{ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; // Set LOW to turn bothoff ON +} + +void can_wakeup_pin(void){ + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRCLR = (1u << 16U); // Set as input + PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] |= PORT_PINCFG_INEN_Msk; // Enable INPUT +} diff --git a/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.h b/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.h new file mode 100644 index 00000000..66c0f907 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.h @@ -0,0 +1,112 @@ +#ifndef BMS_SPI_H +#define BMS_SPI_H + +#include +#include + + + +//direct commands + +#define BATTERY_STATUS 0x12 +#define STACK_VOLTAGE 0x34 + +#define CELL_1_VOLTAGE 0x14 +#define CELL_2_VOLTAGE 0x16 +#define CELL_3_VOLTAGE 0x18 +#define CELL_4_VOLTAGE 0x1A +#define CELL_5_VOLTAGE 0x1C +#define CELL_6_VOLTAGE 0x1E +#define CC2_CURRENT 0x3A + + +/* +#define Cell7Voltage 0x20 +#define Cell8Voltage 0x22 +#define Cell9Voltage 0x24 +#define Cell10Voltage 0x26 +#define Cell11Voltage 0x28 +#define Cell12Voltage 0x2A +#define Cell13Voltage 0x2C +#define Cell14Voltage 0x2E +#define Cell15Voltage 0x30 +#define Cell16Voltage 0x32 + +*/ // 16 cell voltage readings avaliable + +#define bq_cs_group (0U) +#define bq_cs_mask (1UL << 7) // PA07: CS (GPIO) + +#define R 0 // Read; Used in directcommands and Subcommands functions +#define W 1 // Write; Used in directcommands and Subcommands functions +#define BQ_SUBCMD_MAX_POLLS 2000u + + +#define SWAP_COMM_MODE 0x29BC +#define SWAP_TO_SPI 0x7C35 +#define SWAP_TO_I2C 0x29E7 //maybe needed + +#define THERMISOR_TEMP 0x6A +#define INTERNAL_TEMP 0x68 +#define TS1_TEMP 0x70 +#define TS2_TEMP 0x72 +#define TS3_TEMP 0x74 + +//command only (R) + +#define RESET 0x0012 +#define SHUTDOWN 0x0010 + +// Thresholds and Delays values (TBC) + +#define COV_THRESHOLD_MV 4250 +#define COV_DELAY_MS 200 +#define CUV_THRESHOLD_MV 3000 +#define CUV_DELAY_MS 300 + +// Threshold Addresses +#define COV_THRESHOLD_ADDR 0x9278 +#define COV_DELAY_ADDR 0x9279 +#define CUV_THRESHOLD_ADDR 0x9275 +#define CUV_DELAY_ADDR 0x9276 + +//Config Mode +#define ENTER_CONFIG_UPDATE 0x0090 +#define EXIT_CONFIG_UPDATE 0x0092 + +#define FET_STATUS 0x7F + +// BOTHOFF PINS + +#define GPIO_GROUP_A 0u +#define PIN_BOTHOFF 6u +#define BOTHOFF_PIN_MASK (1u << PIN_BOTHOFF) + +/* Minimal driver: only SPI+CS bring-up */ + +void bq76942_init(void); +bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length); +bool read_reg(uint8_t regAddr, uint8_t *data, uint8_t length); +bool bq_direct_command(uint8_t command, uint16_t *data, char type); +bool bq_command_only(uint16_t subcmd); +bool bq_direct_read(uint8_t command, uint8_t *data, uint8_t count); +bool bq_direct_write(uint8_t command, const uint8_t *data, uint8_t count); +bool bq_read_subcommand(uint16_t subcmd, uint8_t *data, uint8_t length); +bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length); +void bms_set_protection_threshold(void); +void bms_battery_status(void); +bool read_cells_1to6(uint16_t cell_mV[6]); +void bms_sample_temps(void); +bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC); +bool bms_current_read(int16_t *current_userA); +void bothoff_init(void); +void bothoff_high(void); +void bothoff_low(void); + + + + + + + +#endif /* bq76942_H */ diff --git a/bms/bms/bms_config_e18a/src/ic_bms/spi_test.c b/bms/bms/bms_config_e18a/src/ic_bms/spi_test.c new file mode 100644 index 00000000..8056caac --- /dev/null +++ b/bms/bms/bms_config_e18a/src/ic_bms/spi_test.c @@ -0,0 +1,175 @@ +#include +#include +#include +#include "definitions.h" +#include "spi_test.h" + +#define SPI_TEST_CS_GROUP (0U) +#define SPI_TEST_CS_MASK (1UL << 7) // PA07 +#define SPI_TEST_WAIT_TIMEOUT (2000000UL) + +// Drives the same CS GPIO used by the production BMS SPI path. +static inline void spi_test_cs_low(void) +{ + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTCLR = SPI_TEST_CS_MASK; +} + +static inline void spi_test_cs_high(void) +{ + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTSET = SPI_TEST_CS_MASK; +} + +// Prevents tests from hanging forever if SPI stays busy. +static bool spi_test_wait_idle(void) +{ + uint32_t timeout = SPI_TEST_WAIT_TIMEOUT; + + while (SERCOM0_SPI_IsBusy()) + { + if (timeout-- == 0U) + { + return false; + } + } + + return true; +} + +// UART helper so we can inspect exact bytes sent/received on the live target. +static void spi_test_print_bytes(const char *label, const uint8_t *buf, size_t len) +{ + printf("%s:", label); + for (size_t i = 0; i < len; i++) + { + printf(" %02X", buf[i]); + } + printf("\n"); +} + +// Same CRC-8 polynomial (0x07) used in bms_spi.c framing. +static uint8_t spi_test_crc8_calc(const uint8_t *data, uint8_t len) +{ + uint8_t crc = 0x00U; + + for (uint8_t i = 0; i < len; i++) + { + crc ^= data[i]; + for (uint8_t b = 0; b < 8U; b++) + { + crc = (crc & 0x80U) ? (uint8_t)((crc << 1U) ^ 0x07U) : (uint8_t)(crc << 1U); + } + } + return crc; +} + +// Tests write_reg frame construction and one real SPI write transfer. +// With loopback only, this validates transport/framing (not real BQ register writes). +static bool spi_test_write_reg_exact(uint8_t reg_addr, const uint8_t *data, uint8_t length) +{ + uint8_t tx_bytes[3U * 32U]; + + if ((length == 0U) || (length > 32U) || SERCOM0_SPI_IsBusy()) + { + return false; + } + + for (uint8_t i = 0U; i < length; i++) + { + uint8_t cmd = (uint8_t)(0x80U | (uint8_t)((reg_addr + i) & 0x7FU)); + uint8_t pair[2] = {cmd, data[i]}; + tx_bytes[3U * i + 0U] = cmd; + tx_bytes[3U * i + 1U] = data[i]; + tx_bytes[3U * i + 2U] = spi_test_crc8_calc(pair, 2U); + } + + spi_test_print_bytes("write_reg tx", tx_bytes, (size_t)(3U * length)); + + spi_test_cs_low(); + bool ok = SERCOM0_SPI_Write(tx_bytes, (size_t)(3U * length)); + if (ok) + { + ok = spi_test_wait_idle(); + } + spi_test_cs_high(); + return ok; +} + +// Tests read_reg frame construction, SPI full-duplex transfer, and CRC parsing. +// In loopback mode, rx mirrors tx; this still validates parser/CRC path end-to-end. +static bool spi_test_read_reg_exact(uint8_t reg_addr, uint8_t *data, uint8_t length) +{ + uint8_t tx[3U * 33U]; + uint8_t rx[3U * 33U]; + uint8_t frames; + + if ((length == 0U) || (length > 32U) || SERCOM0_SPI_IsBusy()) + { + return false; + } + + frames = (uint8_t)(length + 1U); + + { + uint8_t pair0[2] = {(uint8_t)(reg_addr & 0x7FU), 0x00U}; + tx[0] = pair0[0]; + tx[1] = pair0[1]; + tx[2] = spi_test_crc8_calc(pair0, 2U); + } + + for (uint8_t i = 1U; i < frames; i++) + { + uint8_t cmd = (i < (uint8_t)(frames - 1U)) ? (uint8_t)((reg_addr + i) & 0x7FU) : (uint8_t)0x00U; + uint8_t pair[2] = {cmd, 0x00U}; + tx[3U * i + 0U] = pair[0]; + tx[3U * i + 1U] = pair[1]; + tx[3U * i + 2U] = spi_test_crc8_calc(pair, 2U); + } + + spi_test_print_bytes("read_reg tx", tx, (size_t)(3U * frames)); + + spi_test_cs_low(); + bool ok = SERCOM0_SPI_WriteRead(tx, (size_t)(3U * frames), rx, (size_t)(3U * frames)); + if (ok) + { + ok = spi_test_wait_idle(); + } + spi_test_cs_high(); + if (!ok) + { + return false; + } + + spi_test_print_bytes("read_reg rx", rx, (size_t)(3U * frames)); + + for (uint8_t j = 1U; j <= length; j++) + { + uint8_t *chunk = &rx[3U * j]; + if (spi_test_crc8_calc(chunk, 2U) != chunk[2]) + { + return false; + } + data[j - 1U] = chunk[1]; + } + return true; +} + +void spi_driver_self_test_run(void) +{ + uint8_t wr_data[3] = {0x12U, 0x34U, 0x56U}; + uint8_t rd_data[3] = {0U}; + bool ok_write; + bool ok_read; + + PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_DIRSET = SPI_TEST_CS_MASK; + spi_test_cs_high(); + + printf("=== SPI read/write reg transport test (PA08->PA09 loopback) ===\n"); + + ok_write = spi_test_write_reg_exact(0x10U, wr_data, sizeof(wr_data)); + ok_read = spi_test_read_reg_exact(0x10U, rd_data, sizeof(rd_data)); + + printf("write_reg_exact(0x10, len=3): %s\n", ok_write ? "OK" : "FAIL"); + printf("read_reg_exact(0x10, len=3): %s\n", ok_read ? "OK" : "FAIL"); + spi_test_print_bytes("read_reg data", rd_data, sizeof(rd_data)); + printf("Note: this confirms MCU SPI framing/path only; real BQ register behavior needs the BQ IC connected.\n"); +} diff --git a/bms/bms/bms_config_e18a/src/ic_bms/spi_test.h b/bms/bms/bms_config_e18a/src/ic_bms/spi_test.h new file mode 100644 index 00000000..4710c0e2 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/ic_bms/spi_test.h @@ -0,0 +1,6 @@ +#ifndef SPI_TEST_H +#define SPI_TEST_H + +void spi_driver_self_test_run(void); + +#endif /* SPI_TEST_H */ diff --git a/bms/bms/bms_config_e18a/src/main.c b/bms/bms/bms_config_e18a/src/main.c new file mode 100644 index 00000000..44629f9c --- /dev/null +++ b/bms/bms/bms_config_e18a/src/main.c @@ -0,0 +1,98 @@ +/******************************************************************************* + Main Source File + + Company: + Microchip Technology Inc. + + File Name: + main.c + + Summary: + This file contains the "main" function for a project. + + Description: + This file contains the "main" function for a project. The + "main" function calls the "SYS_Initialize" function to initialize the state + machines of all modules in the system + *******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "definitions.h" // SYS function prototypes +#include "ic_bms/bms_spi.h" +#include "ic_bms/spi_test.h" +#include "app/can_facade.h" +#include "app/can_telemetry.h" +#include "app/pwr_mode.h" +#include "app/state_machine.h" +#include "peripheral/port/plib_port.h" +#include +#include + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Main Entry Point +// ***************************************************************************** +// ***************************************************************************** +static void CAN_Wake_EIC_Callback(uintptr_t context) // called when a CAN wake-up interrupt occurs on EIC pin 11 +{ + (void)context; + sm_on_can_wake(); +} + + +static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) // called every 100ms by the RTC timer interrupt +{ + (void)intCause; + (void)context; + sm_on_rtc_tick(); + CAN_telemetry_tickISR(); +} + + + +int main ( void ) +{ + /* Initialize all modules */ + SYS_Initialize ( NULL ); + pwr_mode_init(); + CAN_Init(); + CAN_telemetry_init(); + RTC_Timer32CallbackRegister(TelemetryRtcCb, 0); + RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK_CMP0); + RTC_Timer32Start(); + EIC_CallbackRegister(EIC_PIN_11, CAN_Wake_EIC_Callback, 0); + EIC_InterruptEnable(EIC_PIN_11); + + //spi_driver_self_test_run(); + bq76942_init(); + bothoff_init(); + sm_init(); + //bms_battery_status(); + + while ( true ) + { + /* Maintain state machines of all polled MPLAB Harmony modules. */ + SYS_Tasks ( ); + state_machine(); + } + + + /* Execution should not come here during normal operation */ + + return ( EXIT_FAILURE ); +} + + +/******************************************************************************* + End of File +*/ + diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ac.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ac.h new file mode 100644 index 00000000..96212c05 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ac.h @@ -0,0 +1,491 @@ +/* + * Component description for AC + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_AC_COMPONENT_H_ +#define _SAMC21_AC_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _UINT8_(0x00) /* (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _UINT8_(0) /* (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_UINT8_(0x1) << AC_CTRLA_SWRST_Pos) /* (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & (_UINT8_(value) << AC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the AC_CTRLA register */ +#define AC_CTRLA_ENABLE_Pos _UINT8_(1) /* (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << AC_CTRLA_ENABLE_Pos) /* (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & (_UINT8_(value) << AC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_CTRLA register */ +#define AC_CTRLA_Msk _UINT8_(0x03) /* (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _UINT8_(0x00) /* (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _UINT8_(0) /* (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_UINT8_(0x1) << AC_CTRLB_START0_Pos) /* (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & (_UINT8_(value) << AC_CTRLB_START0_Pos)) /* Assignment of value for START0 in the AC_CTRLB register */ +#define AC_CTRLB_START1_Pos _UINT8_(1) /* (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_UINT8_(0x1) << AC_CTRLB_START1_Pos) /* (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & (_UINT8_(value) << AC_CTRLB_START1_Pos)) /* Assignment of value for START1 in the AC_CTRLB register */ +#define AC_CTRLB_START2_Pos _UINT8_(2) /* (AC_CTRLB) Comparator 2 Start Comparison Position */ +#define AC_CTRLB_START2_Msk (_UINT8_(0x1) << AC_CTRLB_START2_Pos) /* (AC_CTRLB) Comparator 2 Start Comparison Mask */ +#define AC_CTRLB_START2(value) (AC_CTRLB_START2_Msk & (_UINT8_(value) << AC_CTRLB_START2_Pos)) /* Assignment of value for START2 in the AC_CTRLB register */ +#define AC_CTRLB_START3_Pos _UINT8_(3) /* (AC_CTRLB) Comparator 3 Start Comparison Position */ +#define AC_CTRLB_START3_Msk (_UINT8_(0x1) << AC_CTRLB_START3_Pos) /* (AC_CTRLB) Comparator 3 Start Comparison Mask */ +#define AC_CTRLB_START3(value) (AC_CTRLB_START3_Msk & (_UINT8_(value) << AC_CTRLB_START3_Pos)) /* Assignment of value for START3 in the AC_CTRLB register */ +#define AC_CTRLB_Msk _UINT8_(0x0F) /* (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _UINT8_(0) /* (AC_CTRLB Position) Comparator 3 Start Comparison */ +#define AC_CTRLB_START_Msk (_UINT8_(0xF) << AC_CTRLB_START_Pos) /* (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & (_UINT8_(value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _UINT16_(0) /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO0_Pos) /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assignment of value for COMPEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO1_Pos _UINT16_(1) /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO1_Pos) /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assignment of value for COMPEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO2_Pos _UINT16_(2) /* (AC_EVCTRL) Comparator 2 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO2_Pos) /* (AC_EVCTRL) Comparator 2 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO2(value) (AC_EVCTRL_COMPEO2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO2_Pos)) /* Assignment of value for COMPEO2 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO3_Pos _UINT16_(3) /* (AC_EVCTRL) Comparator 3 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO3_Pos) /* (AC_EVCTRL) Comparator 3 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO3(value) (AC_EVCTRL_COMPEO3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO3_Pos)) /* Assignment of value for COMPEO3 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO0_Pos _UINT16_(4) /* (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO0_Pos) /* (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assignment of value for WINEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO1_Pos _UINT16_(5) /* (AC_EVCTRL) Window 1 Event Output Enable Position */ +#define AC_EVCTRL_WINEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO1_Pos) /* (AC_EVCTRL) Window 1 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO1(value) (AC_EVCTRL_WINEO1_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO1_Pos)) /* Assignment of value for WINEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI0_Pos _UINT16_(8) /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI0_Pos) /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assignment of value for COMPEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI1_Pos _UINT16_(9) /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI1_Pos) /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assignment of value for COMPEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI2_Pos _UINT16_(10) /* (AC_EVCTRL) Comparator 2 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI2_Pos) /* (AC_EVCTRL) Comparator 2 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI2(value) (AC_EVCTRL_COMPEI2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI2_Pos)) /* Assignment of value for COMPEI2 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI3_Pos _UINT16_(11) /* (AC_EVCTRL) Comparator 3 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI3_Pos) /* (AC_EVCTRL) Comparator 3 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI3(value) (AC_EVCTRL_COMPEI3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI3_Pos)) /* Assignment of value for COMPEI3 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI0_Pos _UINT16_(12) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI0_Pos) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assignment of value for INVEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI1_Pos _UINT16_(13) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI1_Pos) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assignment of value for INVEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI2_Pos _UINT16_(14) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI2_Pos) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI2(value) (AC_EVCTRL_INVEI2_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI2_Pos)) /* Assignment of value for INVEI2 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI3_Pos _UINT16_(15) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI3_Pos) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI3(value) (AC_EVCTRL_INVEI3_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI3_Pos)) /* Assignment of value for INVEI3 in the AC_EVCTRL register */ +#define AC_EVCTRL_Msk _UINT16_(0xFF3F) /* (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _UINT16_(0) /* (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEO_Pos) /* (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _UINT16_(4) /* (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_UINT16_(0x3) << AC_EVCTRL_WINEO_Pos) /* (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _UINT16_(8) /* (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEI_Pos) /* (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _UINT16_(12) /* (AC_EVCTRL Position) Comparator 3 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_UINT16_(0xF) << AC_EVCTRL_INVEI_Pos) /* (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _UINT8_(0) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP0_Pos) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & (_UINT8_(value) << AC_INTENCLR_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP1_Pos _UINT8_(1) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP1_Pos) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & (_UINT8_(value) << AC_INTENCLR_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP2_Pos _UINT8_(2) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Position */ +#define AC_INTENCLR_COMP2_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP2_Pos) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP2(value) (AC_INTENCLR_COMP2_Msk & (_UINT8_(value) << AC_INTENCLR_COMP2_Pos)) /* Assignment of value for COMP2 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP3_Pos _UINT8_(3) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Position */ +#define AC_INTENCLR_COMP3_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP3_Pos) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP3(value) (AC_INTENCLR_COMP3_Msk & (_UINT8_(value) << AC_INTENCLR_COMP3_Pos)) /* Assignment of value for COMP3 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN0_Pos _UINT8_(4) /* (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN0_Pos) /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & (_UINT8_(value) << AC_INTENCLR_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN1_Pos _UINT8_(5) /* (AC_INTENCLR) Window 1 Interrupt Enable Position */ +#define AC_INTENCLR_WIN1_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN1_Pos) /* (AC_INTENCLR) Window 1 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN1(value) (AC_INTENCLR_WIN1_Msk & (_UINT8_(value) << AC_INTENCLR_WIN1_Pos)) /* Assignment of value for WIN1 in the AC_INTENCLR register */ +#define AC_INTENCLR_Msk _UINT8_(0x3F) /* (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _UINT8_(0) /* (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_UINT8_(0xF) << AC_INTENCLR_COMP_Pos) /* (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & (_UINT8_(value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _UINT8_(4) /* (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_UINT8_(0x3) << AC_INTENCLR_WIN_Pos) /* (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & (_UINT8_(value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _UINT8_(0x00) /* (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _UINT8_(0) /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_UINT8_(0x1) << AC_INTENSET_COMP0_Pos) /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & (_UINT8_(value) << AC_INTENSET_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTENSET register */ +#define AC_INTENSET_COMP1_Pos _UINT8_(1) /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_UINT8_(0x1) << AC_INTENSET_COMP1_Pos) /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & (_UINT8_(value) << AC_INTENSET_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTENSET register */ +#define AC_INTENSET_COMP2_Pos _UINT8_(2) /* (AC_INTENSET) Comparator 2 Interrupt Enable Position */ +#define AC_INTENSET_COMP2_Msk (_UINT8_(0x1) << AC_INTENSET_COMP2_Pos) /* (AC_INTENSET) Comparator 2 Interrupt Enable Mask */ +#define AC_INTENSET_COMP2(value) (AC_INTENSET_COMP2_Msk & (_UINT8_(value) << AC_INTENSET_COMP2_Pos)) /* Assignment of value for COMP2 in the AC_INTENSET register */ +#define AC_INTENSET_COMP3_Pos _UINT8_(3) /* (AC_INTENSET) Comparator 3 Interrupt Enable Position */ +#define AC_INTENSET_COMP3_Msk (_UINT8_(0x1) << AC_INTENSET_COMP3_Pos) /* (AC_INTENSET) Comparator 3 Interrupt Enable Mask */ +#define AC_INTENSET_COMP3(value) (AC_INTENSET_COMP3_Msk & (_UINT8_(value) << AC_INTENSET_COMP3_Pos)) /* Assignment of value for COMP3 in the AC_INTENSET register */ +#define AC_INTENSET_WIN0_Pos _UINT8_(4) /* (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_UINT8_(0x1) << AC_INTENSET_WIN0_Pos) /* (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & (_UINT8_(value) << AC_INTENSET_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTENSET register */ +#define AC_INTENSET_WIN1_Pos _UINT8_(5) /* (AC_INTENSET) Window 1 Interrupt Enable Position */ +#define AC_INTENSET_WIN1_Msk (_UINT8_(0x1) << AC_INTENSET_WIN1_Pos) /* (AC_INTENSET) Window 1 Interrupt Enable Mask */ +#define AC_INTENSET_WIN1(value) (AC_INTENSET_WIN1_Msk & (_UINT8_(value) << AC_INTENSET_WIN1_Pos)) /* Assignment of value for WIN1 in the AC_INTENSET register */ +#define AC_INTENSET_Msk _UINT8_(0x3F) /* (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _UINT8_(0) /* (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_UINT8_(0xF) << AC_INTENSET_COMP_Pos) /* (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & (_UINT8_(value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _UINT8_(4) /* (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_UINT8_(0x3) << AC_INTENSET_WIN_Pos) /* (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & (_UINT8_(value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _UINT8_(0) /* (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP0_Pos) /* (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & (_UINT8_(value) << AC_INTFLAG_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP1_Pos _UINT8_(1) /* (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP1_Pos) /* (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & (_UINT8_(value) << AC_INTFLAG_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP2_Pos _UINT8_(2) /* (AC_INTFLAG) Comparator 2 Position */ +#define AC_INTFLAG_COMP2_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP2_Pos) /* (AC_INTFLAG) Comparator 2 Mask */ +#define AC_INTFLAG_COMP2(value) (AC_INTFLAG_COMP2_Msk & (_UINT8_(value) << AC_INTFLAG_COMP2_Pos)) /* Assignment of value for COMP2 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP3_Pos _UINT8_(3) /* (AC_INTFLAG) Comparator 3 Position */ +#define AC_INTFLAG_COMP3_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP3_Pos) /* (AC_INTFLAG) Comparator 3 Mask */ +#define AC_INTFLAG_COMP3(value) (AC_INTFLAG_COMP3_Msk & (_UINT8_(value) << AC_INTFLAG_COMP3_Pos)) /* Assignment of value for COMP3 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN0_Pos _UINT8_(4) /* (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN0_Pos) /* (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & (_UINT8_(value) << AC_INTFLAG_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN1_Pos _UINT8_(5) /* (AC_INTFLAG) Window 1 Position */ +#define AC_INTFLAG_WIN1_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN1_Pos) /* (AC_INTFLAG) Window 1 Mask */ +#define AC_INTFLAG_WIN1(value) (AC_INTFLAG_WIN1_Msk & (_UINT8_(value) << AC_INTFLAG_WIN1_Pos)) /* Assignment of value for WIN1 in the AC_INTFLAG register */ +#define AC_INTFLAG_Msk _UINT8_(0x3F) /* (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _UINT8_(0) /* (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_UINT8_(0xF) << AC_INTFLAG_COMP_Pos) /* (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & (_UINT8_(value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _UINT8_(4) /* (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_UINT8_(0x3) << AC_INTFLAG_WIN_Pos) /* (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & (_UINT8_(value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _UINT8_(0x00) /* (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _UINT8_(0) /* (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_UINT8_(0x1) << AC_STATUSA_STATE0_Pos) /* (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & (_UINT8_(value) << AC_STATUSA_STATE0_Pos)) /* Assignment of value for STATE0 in the AC_STATUSA register */ +#define AC_STATUSA_STATE1_Pos _UINT8_(1) /* (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_UINT8_(0x1) << AC_STATUSA_STATE1_Pos) /* (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & (_UINT8_(value) << AC_STATUSA_STATE1_Pos)) /* Assignment of value for STATE1 in the AC_STATUSA register */ +#define AC_STATUSA_STATE2_Pos _UINT8_(2) /* (AC_STATUSA) Comparator 2 Current State Position */ +#define AC_STATUSA_STATE2_Msk (_UINT8_(0x1) << AC_STATUSA_STATE2_Pos) /* (AC_STATUSA) Comparator 2 Current State Mask */ +#define AC_STATUSA_STATE2(value) (AC_STATUSA_STATE2_Msk & (_UINT8_(value) << AC_STATUSA_STATE2_Pos)) /* Assignment of value for STATE2 in the AC_STATUSA register */ +#define AC_STATUSA_STATE3_Pos _UINT8_(3) /* (AC_STATUSA) Comparator 3 Current State Position */ +#define AC_STATUSA_STATE3_Msk (_UINT8_(0x1) << AC_STATUSA_STATE3_Pos) /* (AC_STATUSA) Comparator 3 Current State Mask */ +#define AC_STATUSA_STATE3(value) (AC_STATUSA_STATE3_Msk & (_UINT8_(value) << AC_STATUSA_STATE3_Pos)) /* Assignment of value for STATE3 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_Pos _UINT8_(4) /* (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assignment of value for WSTATE0 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_WSTATE1_Pos _UINT8_(6) /* (AC_STATUSA) Window 1 Current State Position */ +#define AC_STATUSA_WSTATE1_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Window 1 Current State Mask */ +#define AC_STATUSA_WSTATE1(value) (AC_STATUSA_WSTATE1_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE1_Pos)) /* Assignment of value for WSTATE1 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE1_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE1_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE1_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE1_ABOVE (AC_STATUSA_WSTATE1_ABOVE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE1_INSIDE (AC_STATUSA_WSTATE1_INSIDE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE1_BELOW (AC_STATUSA_WSTATE1_BELOW_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _UINT8_(0xFF) /* (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _UINT8_(0) /* (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_UINT8_(0xF) << AC_STATUSA_STATE_Pos) /* (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & (_UINT8_(value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _UINT8_(0x00) /* (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _UINT8_(0) /* (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_UINT8_(0x1) << AC_STATUSB_READY0_Pos) /* (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & (_UINT8_(value) << AC_STATUSB_READY0_Pos)) /* Assignment of value for READY0 in the AC_STATUSB register */ +#define AC_STATUSB_READY1_Pos _UINT8_(1) /* (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_UINT8_(0x1) << AC_STATUSB_READY1_Pos) /* (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & (_UINT8_(value) << AC_STATUSB_READY1_Pos)) /* Assignment of value for READY1 in the AC_STATUSB register */ +#define AC_STATUSB_READY2_Pos _UINT8_(2) /* (AC_STATUSB) Comparator 2 Ready Position */ +#define AC_STATUSB_READY2_Msk (_UINT8_(0x1) << AC_STATUSB_READY2_Pos) /* (AC_STATUSB) Comparator 2 Ready Mask */ +#define AC_STATUSB_READY2(value) (AC_STATUSB_READY2_Msk & (_UINT8_(value) << AC_STATUSB_READY2_Pos)) /* Assignment of value for READY2 in the AC_STATUSB register */ +#define AC_STATUSB_READY3_Pos _UINT8_(3) /* (AC_STATUSB) Comparator 3 Ready Position */ +#define AC_STATUSB_READY3_Msk (_UINT8_(0x1) << AC_STATUSB_READY3_Pos) /* (AC_STATUSB) Comparator 3 Ready Mask */ +#define AC_STATUSB_READY3(value) (AC_STATUSB_READY3_Msk & (_UINT8_(value) << AC_STATUSB_READY3_Pos)) /* Assignment of value for READY3 in the AC_STATUSB register */ +#define AC_STATUSB_Msk _UINT8_(0x0F) /* (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _UINT8_(0) /* (AC_STATUSB Position) Comparator 3 Ready */ +#define AC_STATUSB_READY_Msk (_UINT8_(0xF) << AC_STATUSB_READY_Pos) /* (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & (_UINT8_(value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /* (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the AC_DBGCTRL register */ +#define AC_DBGCTRL_Msk _UINT8_(0x01) /* (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _UINT8_(0x00) /* (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _UINT8_(0) /* (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN0_Pos) /* (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & (_UINT8_(value) << AC_WINCTRL_WEN0_Pos)) /* Assignment of value for WEN0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_Pos _UINT8_(1) /* (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL0_Pos)) /* Assignment of value for WINTSEL0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_WEN1_Pos _UINT8_(4) /* (AC_WINCTRL) Window 1 Mode Enable Position */ +#define AC_WINCTRL_WEN1_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN1_Pos) /* (AC_WINCTRL) Window 1 Mode Enable Mask */ +#define AC_WINCTRL_WEN1(value) (AC_WINCTRL_WEN1_Msk & (_UINT8_(value) << AC_WINCTRL_WEN1_Pos)) /* Assignment of value for WEN1 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL1_Pos _UINT8_(5) /* (AC_WINCTRL) Window 1 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL1_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Window 1 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL1(value) (AC_WINCTRL_WINTSEL1_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL1_Pos)) /* Assignment of value for WINTSEL1 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL1_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL1_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL1_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL1_ABOVE (AC_WINCTRL_WINTSEL1_ABOVE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL1_INSIDE (AC_WINCTRL_WINTSEL1_INSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL1_BELOW (AC_WINCTRL_WINTSEL1_BELOW_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE (AC_WINCTRL_WINTSEL1_OUTSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _UINT8_(0x77) /* (AC_WINCTRL) Register Mask */ + + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _UINT8_(0x00) /* (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _UINT8_(0) /* (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_UINT8_(0x3F) << AC_SCALER_VALUE_Pos) /* (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & (_UINT8_(value) << AC_SCALER_VALUE_Pos)) /* Assignment of value for VALUE in the AC_SCALER register */ +#define AC_SCALER_Msk _UINT8_(0x3F) /* (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _UINT32_(0x00) /* (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _UINT32_(1) /* (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos) /* (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SINGLE_Pos _UINT32_(2) /* (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos) /* (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assignment of value for SINGLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_Pos _UINT32_(3) /* (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assignment of value for INTSEL in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _UINT32_(0x0) /* (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _UINT32_(0x1) /* (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _UINT32_(0x2) /* (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _UINT32_(0x3) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _UINT32_(6) /* (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /* (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_Pos _UINT32_(8) /* (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assignment of value for MUXNEG in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _UINT32_(0x4) /* (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _UINT32_(0x5) /* (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _UINT32_(0x6) /* (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _UINT32_(0x7) /* (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _UINT32_(12) /* (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assignment of value for MUXPOS in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXPOS_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _UINT32_(0x4) /* (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _UINT32_(15) /* (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos) /* (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assignment of value for SWAP in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_Pos _UINT32_(16) /* (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_UINT32_(0x3) << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assignment of value for SPEED in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_LOW_Val _UINT32_(0x0) /* (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _UINT32_(0x3) /* (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Low speed Position */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _UINT32_(19) /* (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_UINT32_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /* (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & (_UINT32_(value) << AC_COMPCTRL_HYSTEN_Pos)) /* Assignment of value for HYSTEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_Pos _UINT32_(24) /* (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assignment of value for FLEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _UINT32_(0x1) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _UINT32_(0x2) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _UINT32_(28) /* (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assignment of value for OUT in the AC_COMPCTRL register */ +#define AC_COMPCTRL_OUT_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _UINT32_(0x1) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _UINT32_(0x2) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _UINT32_(0x370BF75E) /* (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_WINCTRL_Pos _UINT32_(2) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) /* Assignment of value for WINCTRL in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL0_Pos _UINT32_(3) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assignment of value for COMPCTRL0 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL1_Pos _UINT32_(4) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assignment of value for COMPCTRL1 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL2_Pos _UINT32_(5) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL2_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL2_Pos) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL2(value) (AC_SYNCBUSY_COMPCTRL2_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL2_Pos)) /* Assignment of value for COMPCTRL2 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL3_Pos _UINT32_(6) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL3_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL3_Pos) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL3(value) (AC_SYNCBUSY_COMPCTRL3_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL3_Pos)) /* Assignment of value for COMPCTRL3 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_Msk _UINT32_(0x0000007F) /* (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _UINT32_(3) /* (AC_SYNCBUSY Position) COMPCTRL 3 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_UINT32_(0xF) << AC_SYNCBUSY_COMPCTRL_Pos) /* (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/* AC register offsets definitions */ +#define AC_CTRLA_REG_OFST _UINT32_(0x00) /* (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST _UINT32_(0x01) /* (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST _UINT32_(0x02) /* (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST _UINT32_(0x04) /* (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST _UINT32_(0x05) /* (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST _UINT32_(0x06) /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST _UINT32_(0x07) /* (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST _UINT32_(0x08) /* (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST _UINT32_(0x0A) /* (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST _UINT32_(0x0C) /* (AC_SCALER) Scaler n Offset */ +#define AC_SCALER0_REG_OFST _UINT32_(0x0C) /* (AC_SCALER0) Scaler n Offset */ +#define AC_SCALER1_REG_OFST _UINT32_(0x0D) /* (AC_SCALER1) Scaler n Offset */ +#define AC_SCALER2_REG_OFST _UINT32_(0x0E) /* (AC_SCALER2) Scaler n Offset */ +#define AC_SCALER3_REG_OFST _UINT32_(0x0F) /* (AC_SCALER3) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_COMPCTRL0_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL0) Comparator Control n Offset */ +#define AC_COMPCTRL1_REG_OFST _UINT32_(0x14) /* (AC_COMPCTRL1) Comparator Control n Offset */ +#define AC_COMPCTRL2_REG_OFST _UINT32_(0x18) /* (AC_COMPCTRL2) Comparator Control n Offset */ +#define AC_COMPCTRL3_REG_OFST _UINT32_(0x1C) /* (AC_COMPCTRL3) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (AC_SYNCBUSY) Synchronization Busy Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /* Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /* Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /* Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /* Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /* Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /* Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[4]; /* Offset: 0x0C (R/W 8) Scaler n */ + __IO uint32_t AC_COMPCTRL[4]; /* Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint32_t AC_SYNCBUSY; /* Offset: 0x20 (R/ 32) Synchronization Busy */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_AC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/adc.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/adc.h new file mode 100644 index 00000000..7430110c --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/adc.h @@ -0,0 +1,524 @@ +/* + * Component description for ADC + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_ADC_COMPONENT_H_ +#define _SAMC21_ADC_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _UINT8_(0) /* (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_UINT8_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT8_(value) << ADC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_CTRLA register */ +#define ADC_CTRLA_ENABLE_Pos _UINT8_(1) /* (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT8_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_CTRLA register */ +#define ADC_CTRLA_SLAVEEN_Pos _UINT8_(5) /* (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_UINT8_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT8_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assignment of value for SLAVEEN in the ADC_CTRLA register */ +#define ADC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (ADC_CTRLA) Run During Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run During Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the ADC_CTRLA register */ +#define ADC_CTRLA_ONDEMAND_Pos _UINT8_(7) /* (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_UINT8_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT8_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the ADC_CTRLA register */ +#define ADC_CTRLA_Msk _UINT8_(0xE3) /* (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_PRESCALER_Pos _UINT8_(0) /* (ADC_CTRLB) Prescaler Configuration Position */ +#define ADC_CTRLB_PRESCALER_Msk (_UINT8_(0x7) << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Prescaler Configuration Mask */ +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & (_UINT8_(value) << ADC_CTRLB_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the ADC_CTRLB register */ +#define ADC_CTRLB_PRESCALER_DIV2_Val _UINT8_(0x0) /* (ADC_CTRLB) Peripheral clock / 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _UINT8_(0x1) /* (ADC_CTRLB) Peripheral clock / 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _UINT8_(0x2) /* (ADC_CTRLB) Peripheral clock / 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _UINT8_(0x3) /* (ADC_CTRLB) Peripheral clock / 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _UINT8_(0x4) /* (ADC_CTRLB) Peripheral clock / 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _UINT8_(0x5) /* (ADC_CTRLB) Peripheral clock / 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _UINT8_(0x6) /* (ADC_CTRLB) Peripheral clock / 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _UINT8_(0x7) /* (ADC_CTRLB) Peripheral clock / 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 2 Position */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 4 Position */ +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 8 Position */ +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 16 Position */ +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 32 Position */ +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 64 Position */ +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 128 Position */ +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 256 Position */ +#define ADC_CTRLB_Msk _UINT8_(0x07) /* (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assignment of value for REFSEL in the ADC_REFCTRL register */ +#define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x1) /* (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x3) /* (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_DAC_Val _UINT8_(0x4) /* (ADC_REFCTRL) DAC */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _UINT8_(0x5) /* (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/1.6 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference Position */ +#define ADC_REFCTRL_REFSEL_DAC (ADC_REFCTRL_REFSEL_DAC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) DAC Position */ +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assignment of value for REFCOMP in the ADC_REFCTRL register */ +#define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assignment of value for FLUSHEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assignment of value for FLUSHINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assignment of value for STARTINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assignment of value for RESRDYEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assignment of value for WINMONEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTENCLR register */ +#define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTENCLR register */ +#define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTENCLR register */ +#define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTENSET register */ +#define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTENSET register */ +#define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTENSET register */ +#define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTFLAG register */ +#define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTFLAG register */ +#define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTFLAG register */ +#define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) ( R/ 8) Sequence Status -------- */ +#define ADC_SEQSTATUS_RESETVALUE _UINT8_(0x00) /* (ADC_SEQSTATUS) Sequence Status Reset Value */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos _UINT8_(0) /* (ADC_SEQSTATUS) Sequence State Position */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_UINT8_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) /* (ADC_SEQSTATUS) Sequence State Mask */ +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQSTATE_Pos)) /* Assignment of value for SEQSTATE in the ADC_SEQSTATUS register */ +#define ADC_SEQSTATUS_SEQBUSY_Pos _UINT8_(7) /* (ADC_SEQSTATUS) Sequence Busy Position */ +#define ADC_SEQSTATUS_SEQBUSY_Msk (_UINT8_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) /* (ADC_SEQSTATUS) Sequence Busy Mask */ +#define ADC_SEQSTATUS_SEQBUSY(value) (ADC_SEQSTATUS_SEQBUSY_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQBUSY_Pos)) /* Assignment of value for SEQBUSY in the ADC_SEQSTATUS register */ +#define ADC_SEQSTATUS_Msk _UINT8_(0x9F) /* (ADC_SEQSTATUS) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assignment of value for MUXPOS in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _UINT16_(0x1C) /* (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assignment of value for MUXNEG in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_Msk _UINT16_(0x1F1F) /* (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#define ADC_CTRLC_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLC) Control C Reset Value */ + +#define ADC_CTRLC_DIFFMODE_Pos _UINT16_(0) /* (ADC_CTRLC) Differential Mode Position */ +#define ADC_CTRLC_DIFFMODE_Msk (_UINT16_(0x1) << ADC_CTRLC_DIFFMODE_Pos) /* (ADC_CTRLC) Differential Mode Mask */ +#define ADC_CTRLC_DIFFMODE(value) (ADC_CTRLC_DIFFMODE_Msk & (_UINT16_(value) << ADC_CTRLC_DIFFMODE_Pos)) /* Assignment of value for DIFFMODE in the ADC_CTRLC register */ +#define ADC_CTRLC_LEFTADJ_Pos _UINT16_(1) /* (ADC_CTRLC) Left-Adjusted Result Position */ +#define ADC_CTRLC_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLC_LEFTADJ_Pos) /* (ADC_CTRLC) Left-Adjusted Result Mask */ +#define ADC_CTRLC_LEFTADJ(value) (ADC_CTRLC_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLC_LEFTADJ_Pos)) /* Assignment of value for LEFTADJ in the ADC_CTRLC register */ +#define ADC_CTRLC_FREERUN_Pos _UINT16_(2) /* (ADC_CTRLC) Free Running Mode Position */ +#define ADC_CTRLC_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLC_FREERUN_Pos) /* (ADC_CTRLC) Free Running Mode Mask */ +#define ADC_CTRLC_FREERUN(value) (ADC_CTRLC_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLC_FREERUN_Pos)) /* Assignment of value for FREERUN in the ADC_CTRLC register */ +#define ADC_CTRLC_CORREN_Pos _UINT16_(3) /* (ADC_CTRLC) Digital Correction Logic Enable Position */ +#define ADC_CTRLC_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLC_CORREN_Pos) /* (ADC_CTRLC) Digital Correction Logic Enable Mask */ +#define ADC_CTRLC_CORREN(value) (ADC_CTRLC_CORREN_Msk & (_UINT16_(value) << ADC_CTRLC_CORREN_Pos)) /* Assignment of value for CORREN in the ADC_CTRLC register */ +#define ADC_CTRLC_RESSEL_Pos _UINT16_(4) /* (ADC_CTRLC) Conversion Result Resolution Position */ +#define ADC_CTRLC_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) Conversion Result Resolution Mask */ +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLC_RESSEL_Pos)) /* Assignment of value for RESSEL in the ADC_CTRLC register */ +#define ADC_CTRLC_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLC) 12-bit */ +#define ADC_CTRLC_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLC) 16-bit averaging mode */ +#define ADC_CTRLC_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLC) 10-bit */ +#define ADC_CTRLC_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLC) 8-bit */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 12-bit Position */ +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 16-bit averaging mode Position */ +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 10-bit Position */ +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 8-bit Position */ +#define ADC_CTRLC_R2R_Pos _UINT16_(7) /* (ADC_CTRLC) Rail-to-Rail mode enable Position */ +#define ADC_CTRLC_R2R_Msk (_UINT16_(0x1) << ADC_CTRLC_R2R_Pos) /* (ADC_CTRLC) Rail-to-Rail mode enable Mask */ +#define ADC_CTRLC_R2R(value) (ADC_CTRLC_R2R_Msk & (_UINT16_(value) << ADC_CTRLC_R2R_Pos)) /* Assignment of value for R2R in the ADC_CTRLC register */ +#define ADC_CTRLC_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLC) Window Monitor Mode Position */ +#define ADC_CTRLC_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) Window Monitor Mode Mask */ +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLC_WINMODE_Pos)) /* Assignment of value for WINMODE in the ADC_CTRLC register */ +#define ADC_CTRLC_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) No window mode (default) Position */ +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT > WINLT Position */ +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT < WINUT Position */ +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLC_DUALSEL_Pos _UINT16_(12) /* (ADC_CTRLC) Dual Mode Trigger Selection Position */ +#define ADC_CTRLC_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLC_DUALSEL_Pos)) /* Assignment of value for DUALSEL in the ADC_CTRLC register */ +#define ADC_CTRLC_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLC_Msk _UINT16_(0x37BF) /* (ADC_CTRLC) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assignment of value for SAMPLENUM in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assignment of value for ADJRES in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assignment of value for SAMPLEN in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assignment of value for OFFCOMP in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_WINLT register */ +#define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_WINUT register */ +#define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_GAINCORR register */ +#define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_OFFSETCORR register */ +#define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assignment of value for FLUSH in the ADC_SWTRIG register */ +#define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assignment of value for START in the ADC_SWTRIG register */ +#define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the ADC_DBGCTRL register */ +#define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) ( R/ 16) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _UINT16_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _UINT16_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_ENABLE_Pos _UINT16_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT16_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT16_(2) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assignment of value for INPUTCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_CTRLC_Pos _UINT16_(3) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLC_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLC(value) (ADC_SYNCBUSY_CTRLC_Msk & (_UINT16_(value) << ADC_SYNCBUSY_CTRLC_Pos)) /* Assignment of value for CTRLC in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_AVGCTRL_Pos _UINT16_(4) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assignment of value for AVGCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT16_(5) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assignment of value for SAMPCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINLT_Pos _UINT16_(6) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINUT_Pos _UINT16_(7) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_GAINCORR_Pos _UINT16_(8) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT16_(9) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SWTRIG_Pos _UINT16_(10) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assignment of value for SWTRIG in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_Msk _UINT16_(0x07FF) /* (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x24) ( R/ 16) Result -------- */ +#define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Reset Value */ + +#define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Value Position */ +#define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assignment of value for RESULT in the ADC_RESULT register */ +#define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ + + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#define ADC_SEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_SEQCTRL) Sequence Control Reset Value */ + +#define ADC_SEQCTRL_SEQEN_Pos _UINT32_(0) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Position */ +#define ADC_SEQCTRL_SEQEN_Msk (_UINT32_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Mask */ +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & (_UINT32_(value) << ADC_SEQCTRL_SEQEN_Pos)) /* Assignment of value for SEQEN in the ADC_SEQCTRL register */ +#define ADC_SEQCTRL_Msk _UINT32_(0xFFFFFFFF) /* (ADC_SEQCTRL) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assignment of value for BIASCOMP in the ADC_CALIB register */ +#define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assignment of value for BIASREFBUF in the ADC_CALIB register */ +#define ADC_CALIB_Msk _UINT16_(0x0707) /* (ADC_CALIB) Register Mask */ + + +/* ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ +#define ADC_CTRLB_REG_OFST _UINT32_(0x01) /* (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST _UINT32_(0x02) /* (ADC_REFCTRL) Reference Control Offset */ +#define ADC_EVCTRL_REG_OFST _UINT32_(0x03) /* (ADC_EVCTRL) Event Control Offset */ +#define ADC_INTENCLR_REG_OFST _UINT32_(0x04) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST _UINT32_(0x05) /* (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST _UINT32_(0x06) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_SEQSTATUS_REG_OFST _UINT32_(0x07) /* (ADC_SEQSTATUS) Sequence Status Offset */ +#define ADC_INPUTCTRL_REG_OFST _UINT32_(0x08) /* (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLC_REG_OFST _UINT32_(0x0A) /* (ADC_CTRLC) Control C Offset */ +#define ADC_AVGCTRL_REG_OFST _UINT32_(0x0C) /* (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0D) /* (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST _UINT32_(0x0E) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST _UINT32_(0x10) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST _UINT32_(0x12) /* (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST _UINT32_(0x14) /* (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST _UINT32_(0x18) /* (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_DBGCTRL_REG_OFST _UINT32_(0x1C) /* (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_RESULT_REG_OFST _UINT32_(0x24) /* (ADC_RESULT) Result Offset */ +#define ADC_SEQCTRL_REG_OFST _UINT32_(0x28) /* (ADC_SEQCTRL) Sequence Control Offset */ +#define ADC_CALIB_REG_OFST _UINT32_(0x2C) /* (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint8_t ADC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t ADC_CTRLB; /* Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t ADC_REFCTRL; /* Offset: 0x02 (R/W 8) Reference Control */ + __IO uint8_t ADC_EVCTRL; /* Offset: 0x03 (R/W 8) Event Control */ + __IO uint8_t ADC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_SEQSTATUS; /* Offset: 0x07 (R/ 8) Sequence Status */ + __IO uint16_t ADC_INPUTCTRL; /* Offset: 0x08 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLC; /* Offset: 0x0A (R/W 16) Control C */ + __IO uint8_t ADC_AVGCTRL; /* Offset: 0x0C (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /* Offset: 0x0D (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /* Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /* Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /* Offset: 0x12 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /* Offset: 0x14 (R/W 16) Offset Correction */ + __I uint8_t Reserved1[0x02]; + __IO uint8_t ADC_SWTRIG; /* Offset: 0x18 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x03]; + __IO uint8_t ADC_DBGCTRL; /* Offset: 0x1C (R/W 8) Debug Control */ + __I uint8_t Reserved3[0x03]; + __I uint16_t ADC_SYNCBUSY; /* Offset: 0x20 (R/ 16) Synchronization Busy */ + __I uint8_t Reserved4[0x02]; + __I uint16_t ADC_RESULT; /* Offset: 0x24 (R/ 16) Result */ + __I uint8_t Reserved5[0x02]; + __IO uint32_t ADC_SEQCTRL; /* Offset: 0x28 (R/W 32) Sequence Control */ + __IO uint16_t ADC_CALIB; /* Offset: 0x2C (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_ADC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/can.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/can.h new file mode 100644 index 00000000..f84adbc0 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/can.h @@ -0,0 +1,2528 @@ +/* + * Component description for CAN + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_CAN_COMPONENT_H_ +#define _SAMC21_CAN_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CAN */ +/* ************************************************************************** */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ +#define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ +#define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ +#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ +#define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ +#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ +#define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ +#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ + + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ +#define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ +#define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ +#define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ +#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ +#define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ +#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ +#define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ +#define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ + + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ +#define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ +#define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ +#define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ +#define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ + + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ +#define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ +#define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ +#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ +#define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ +#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ +#define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ +#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ + + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ +#define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ +#define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ +#define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ +#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ +#define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ +#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ +#define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ + + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ +#define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ +#define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ +#define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ +#define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ + + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ +#define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ +#define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ +#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ +#define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ +#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ +#define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ +#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ + + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ +#define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ +#define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ +#define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ +#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ +#define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ +#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ +#define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ + + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ +#define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ +#define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ +#define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ +#define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ + + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ +#define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assignment of value for ID in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ +#define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ +#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ +#define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ +#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ +#define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ +#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ + + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ +#define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ +#define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ +#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ +#define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ +#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ +#define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ +#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assignment of value for EFC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ +#define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assignment of value for MM in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ + + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ +#define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ +#define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ +#define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ +#define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ + + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ +#define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assignment of value for ID in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ +#define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ +#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ +#define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ +#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ +#define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ +#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ + + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ +#define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assignment of value for TXTS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ +#define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ +#define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ +#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ +#define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ +#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ +#define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assignment of value for ET in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ +#define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assignment of value for MM in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ + + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ +#define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assignment of value for SFID2 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ +#define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assignment of value for SFID1 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assignment of value for SFEC in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ +#define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ +#define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assignment of value for SFT in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ +#define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ +#define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assignment of value for EFID1 in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assignment of value for EFEC in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ +#define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ +#define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assignment of value for EFID2 in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ +#define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assignment of value for EFT in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ + + +/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ +#define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ + +#define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ +#define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assignment of value for SUBSTEP in the CAN_CREL register */ +#define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ +#define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assignment of value for STEP in the CAN_CREL register */ +#define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ +#define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assignment of value for REL in the CAN_CREL register */ +#define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ + + +/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ +#define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ + +#define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ +#define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assignment of value for ETV in the CAN_ENDN register */ +#define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ + + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ + +#define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ +#define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assignment of value for QOS in the CAN_MRCFG register */ +#define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ +#define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ + + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ + +#define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ +#define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assignment of value for DSJW in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ +#define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assignment of value for DTSEG2 in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ +#define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assignment of value for DTSEG1 in the CAN_DBTP register */ +#define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ +#define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assignment of value for DBRP in the CAN_DBTP register */ +#define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ +#define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ +#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assignment of value for TDC in the CAN_DBTP register */ +#define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ + + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ + +#define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ +#define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ +#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assignment of value for LBCK in the CAN_TEST register */ +#define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ +#define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assignment of value for TX in the CAN_TEST register */ +#define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ +#define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ +#define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ +#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assignment of value for RX in the CAN_TEST register */ +#define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ + + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ + +#define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ +#define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assignment of value for WDC in the CAN_RWD register */ +#define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ +#define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assignment of value for WDV in the CAN_RWD register */ +#define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ + + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ + +#define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ +#define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ +#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assignment of value for INIT in the CAN_CCCR register */ +#define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ +#define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ +#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assignment of value for CCE in the CAN_CCCR register */ +#define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ +#define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ +#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assignment of value for ASM in the CAN_CCCR register */ +#define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ +#define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ +#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assignment of value for CSA in the CAN_CCCR register */ +#define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ +#define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ +#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assignment of value for CSR in the CAN_CCCR register */ +#define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ +#define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ +#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assignment of value for MON in the CAN_CCCR register */ +#define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ +#define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ +#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assignment of value for DAR in the CAN_CCCR register */ +#define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ +#define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ +#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assignment of value for TEST in the CAN_CCCR register */ +#define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ +#define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ +#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assignment of value for FDOE in the CAN_CCCR register */ +#define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ +#define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ +#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assignment of value for BRSE in the CAN_CCCR register */ +#define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ +#define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ +#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assignment of value for PXHD in the CAN_CCCR register */ +#define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ +#define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ +#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assignment of value for EFBI in the CAN_CCCR register */ +#define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ +#define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ +#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assignment of value for TXP in the CAN_CCCR register */ +#define CAN_CCCR_NISO_Pos _UINT32_(15) /* (CAN_CCCR) Non ISO Operation Position */ +#define CAN_CCCR_NISO_Msk (_UINT32_(0x1) << CAN_CCCR_NISO_Pos) /* (CAN_CCCR) Non ISO Operation Mask */ +#define CAN_CCCR_NISO(value) (CAN_CCCR_NISO_Msk & (_UINT32_(value) << CAN_CCCR_NISO_Pos)) /* Assignment of value for NISO in the CAN_CCCR register */ +#define CAN_CCCR_Msk _UINT32_(0x0000F3FF) /* (CAN_CCCR) Register Mask */ + + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ + +#define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ +#define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assignment of value for NTSEG2 in the CAN_NBTP register */ +#define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ +#define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assignment of value for NTSEG1 in the CAN_NBTP register */ +#define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ +#define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assignment of value for NBRP in the CAN_NBTP register */ +#define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ +#define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assignment of value for NSJW in the CAN_NBTP register */ +#define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ + + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ + +#define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ +#define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assignment of value for TSS in the CAN_TSCC register */ +#define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _UINT32_(0x2) /* (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) External timestamp counter value used Position */ +#define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ +#define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assignment of value for TCP in the CAN_TSCC register */ +#define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ + + +/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ +#define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ + +#define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ +#define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assignment of value for TSC in the CAN_TSCV register */ +#define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ + + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ + +#define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ +#define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ +#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assignment of value for ETOC in the CAN_TOCC register */ +#define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ +#define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assignment of value for TOS in the CAN_TOCC register */ +#define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ +#define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ +#define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assignment of value for TOP in the CAN_TOCC register */ +#define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ + + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ + +#define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ +#define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assignment of value for TOC in the CAN_TOCV register */ +#define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ + + +/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ +#define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ + +#define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ +#define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assignment of value for TEC in the CAN_ECR register */ +#define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ +#define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assignment of value for REC in the CAN_ECR register */ +#define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ +#define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ +#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assignment of value for RP in the CAN_ECR register */ +#define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ +#define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assignment of value for CEL in the CAN_ECR register */ +#define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ + + +/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ +#define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ + +#define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ +#define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assignment of value for LEC in the CAN_PSR register */ +#define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ +#define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assignment of value for ACT in the CAN_PSR register */ +#define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ +#define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ +#define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ +#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assignment of value for EP in the CAN_PSR register */ +#define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ +#define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ +#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assignment of value for EW in the CAN_PSR register */ +#define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ +#define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ +#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assignment of value for BO in the CAN_PSR register */ +#define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ +#define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assignment of value for DLEC in the CAN_PSR register */ +#define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ +#define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ +#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assignment of value for RESI in the CAN_PSR register */ +#define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ +#define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ +#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assignment of value for RBRS in the CAN_PSR register */ +#define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ +#define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ +#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assignment of value for RFDF in the CAN_PSR register */ +#define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ +#define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ +#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assignment of value for PXE in the CAN_PSR register */ +#define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ +#define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assignment of value for TDCV in the CAN_PSR register */ +#define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ + + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ + +#define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ +#define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assignment of value for TDCF in the CAN_TDCR register */ +#define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assignment of value for TDCO in the CAN_TDCR register */ +#define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ + + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ + +#define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ +#define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ +#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assignment of value for RF0N in the CAN_IR register */ +#define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ +#define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ +#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assignment of value for RF0W in the CAN_IR register */ +#define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ +#define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ +#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assignment of value for RF0F in the CAN_IR register */ +#define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ +#define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ +#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_IR register */ +#define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ +#define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ +#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assignment of value for RF1N in the CAN_IR register */ +#define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ +#define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ +#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assignment of value for RF1W in the CAN_IR register */ +#define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ +#define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ +#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assignment of value for RF1F in the CAN_IR register */ +#define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ +#define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ +#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_IR register */ +#define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ +#define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ +#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assignment of value for HPM in the CAN_IR register */ +#define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ +#define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ +#define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assignment of value for TC in the CAN_IR register */ +#define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ +#define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ +#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assignment of value for TCF in the CAN_IR register */ +#define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ +#define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ +#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assignment of value for TFE in the CAN_IR register */ +#define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ +#define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ +#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assignment of value for TEFN in the CAN_IR register */ +#define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ +#define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assignment of value for TEFW in the CAN_IR register */ +#define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ +#define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ +#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assignment of value for TEFF in the CAN_IR register */ +#define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ +#define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ +#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_IR register */ +#define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ +#define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ +#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assignment of value for TSW in the CAN_IR register */ +#define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ +#define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ +#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assignment of value for MRAF in the CAN_IR register */ +#define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ +#define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ +#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assignment of value for TOO in the CAN_IR register */ +#define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ +#define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ +#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assignment of value for DRX in the CAN_IR register */ +#define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ +#define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ +#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assignment of value for BEC in the CAN_IR register */ +#define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ +#define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ +#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assignment of value for BEU in the CAN_IR register */ +#define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ +#define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ +#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assignment of value for ELO in the CAN_IR register */ +#define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ +#define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ +#define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assignment of value for EP in the CAN_IR register */ +#define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ +#define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ +#define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assignment of value for EW in the CAN_IR register */ +#define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ +#define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ +#define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assignment of value for BO in the CAN_IR register */ +#define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ +#define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ +#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assignment of value for WDI in the CAN_IR register */ +#define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ +#define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ +#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assignment of value for PEA in the CAN_IR register */ +#define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ +#define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ +#define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assignment of value for PED in the CAN_IR register */ +#define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ +#define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ +#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assignment of value for ARA in the CAN_IR register */ +#define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ + + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ + +#define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ +#define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ +#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assignment of value for RF0NE in the CAN_IE register */ +#define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assignment of value for RF0WE in the CAN_IE register */ +#define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ +#define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ +#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assignment of value for RF0FE in the CAN_IE register */ +#define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assignment of value for RF0LE in the CAN_IE register */ +#define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ +#define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ +#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assignment of value for RF1NE in the CAN_IE register */ +#define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assignment of value for RF1WE in the CAN_IE register */ +#define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ +#define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ +#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assignment of value for RF1FE in the CAN_IE register */ +#define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assignment of value for RF1LE in the CAN_IE register */ +#define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ +#define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ +#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assignment of value for HPME in the CAN_IE register */ +#define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ +#define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ +#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assignment of value for TCE in the CAN_IE register */ +#define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assignment of value for TCFE in the CAN_IE register */ +#define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assignment of value for TFEE in the CAN_IE register */ +#define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assignment of value for TEFNE in the CAN_IE register */ +#define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assignment of value for TEFWE in the CAN_IE register */ +#define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assignment of value for TEFFE in the CAN_IE register */ +#define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ +#define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ +#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assignment of value for TEFLE in the CAN_IE register */ +#define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assignment of value for TSWE in the CAN_IE register */ +#define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assignment of value for MRAFE in the CAN_IE register */ +#define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ +#define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assignment of value for TOOE in the CAN_IE register */ +#define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ +#define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ +#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assignment of value for DRXE in the CAN_IE register */ +#define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ +#define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ +#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assignment of value for BECE in the CAN_IE register */ +#define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ +#define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ +#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assignment of value for BEUE in the CAN_IE register */ +#define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assignment of value for ELOE in the CAN_IE register */ +#define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ +#define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ +#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assignment of value for EPE in the CAN_IE register */ +#define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ +#define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ +#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assignment of value for EWE in the CAN_IE register */ +#define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ +#define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assignment of value for BOE in the CAN_IE register */ +#define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ +#define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ +#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assignment of value for WDIE in the CAN_IE register */ +#define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assignment of value for PEAE in the CAN_IE register */ +#define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ +#define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ +#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assignment of value for PEDE in the CAN_IE register */ +#define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ +#define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ +#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assignment of value for ARAE in the CAN_IE register */ +#define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ + + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ + +#define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ +#define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ +#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assignment of value for RF0NL in the CAN_ILS register */ +#define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assignment of value for RF0WL in the CAN_ILS register */ +#define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ +#define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ +#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assignment of value for RF0FL in the CAN_ILS register */ +#define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assignment of value for RF0LL in the CAN_ILS register */ +#define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ +#define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ +#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assignment of value for RF1NL in the CAN_ILS register */ +#define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assignment of value for RF1WL in the CAN_ILS register */ +#define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ +#define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ +#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assignment of value for RF1FL in the CAN_ILS register */ +#define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assignment of value for RF1LL in the CAN_ILS register */ +#define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ +#define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ +#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assignment of value for HPML in the CAN_ILS register */ +#define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ +#define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ +#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assignment of value for TCL in the CAN_ILS register */ +#define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assignment of value for TCFL in the CAN_ILS register */ +#define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assignment of value for TFEL in the CAN_ILS register */ +#define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assignment of value for TEFNL in the CAN_ILS register */ +#define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assignment of value for TEFWL in the CAN_ILS register */ +#define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assignment of value for TEFFL in the CAN_ILS register */ +#define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ +#define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ +#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assignment of value for TEFLL in the CAN_ILS register */ +#define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assignment of value for TSWL in the CAN_ILS register */ +#define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assignment of value for MRAFL in the CAN_ILS register */ +#define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ +#define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assignment of value for TOOL in the CAN_ILS register */ +#define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ +#define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ +#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assignment of value for DRXL in the CAN_ILS register */ +#define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ +#define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ +#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assignment of value for BECL in the CAN_ILS register */ +#define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ +#define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ +#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assignment of value for BEUL in the CAN_ILS register */ +#define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assignment of value for ELOL in the CAN_ILS register */ +#define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ +#define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ +#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assignment of value for EPL in the CAN_ILS register */ +#define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ +#define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ +#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assignment of value for EWL in the CAN_ILS register */ +#define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ +#define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assignment of value for BOL in the CAN_ILS register */ +#define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ +#define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ +#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assignment of value for WDIL in the CAN_ILS register */ +#define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assignment of value for PEAL in the CAN_ILS register */ +#define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ +#define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ +#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assignment of value for PEDL in the CAN_ILS register */ +#define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ +#define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ +#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assignment of value for ARAL in the CAN_ILS register */ +#define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ + + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ + +#define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ +#define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ +#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assignment of value for EINT0 in the CAN_ILE register */ +#define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ +#define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ +#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assignment of value for EINT1 in the CAN_ILE register */ +#define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ + +#define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ +#define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ +#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ + +#define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ +#define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ +#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assignment of value for RRFE in the CAN_GFC register */ +#define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ +#define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ +#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assignment of value for RRFS in the CAN_GFC register */ +#define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ +#define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assignment of value for ANFE in the CAN_GFC register */ +#define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ +#define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assignment of value for ANFS in the CAN_GFC register */ +#define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ + + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ + +#define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ +#define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assignment of value for FLSSA in the CAN_SIDFC register */ +#define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ +#define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assignment of value for LSS in the CAN_SIDFC register */ +#define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ + + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ + +#define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ +#define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assignment of value for FLESA in the CAN_XIDFC register */ +#define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ +#define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assignment of value for LSE in the CAN_XIDFC register */ +#define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ + + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ + +#define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ +#define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assignment of value for EIDM in the CAN_XIDAM register */ +#define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ + + +/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ +#define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ + +#define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ +#define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assignment of value for BIDX in the CAN_HPMS register */ +#define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ +#define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assignment of value for MSI in the CAN_HPMS register */ +#define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ +#define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ +#define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_HPMS register */ +#define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ +#define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ +#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assignment of value for FLST in the CAN_HPMS register */ +#define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ + + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ + +#define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ +#define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ +#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assignment of value for ND0 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ +#define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ +#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assignment of value for ND1 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ +#define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ +#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assignment of value for ND2 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ +#define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ +#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assignment of value for ND3 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ +#define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ +#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assignment of value for ND4 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ +#define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ +#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assignment of value for ND5 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ +#define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ +#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assignment of value for ND6 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ +#define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ +#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assignment of value for ND7 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ +#define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ +#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assignment of value for ND8 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ +#define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ +#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assignment of value for ND9 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ +#define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ +#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assignment of value for ND10 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ +#define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ +#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assignment of value for ND11 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ +#define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ +#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assignment of value for ND12 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ +#define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ +#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assignment of value for ND13 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ +#define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ +#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assignment of value for ND14 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ +#define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ +#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assignment of value for ND15 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ +#define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ +#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assignment of value for ND16 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ +#define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ +#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assignment of value for ND17 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ +#define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ +#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assignment of value for ND18 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ +#define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ +#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assignment of value for ND19 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ +#define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ +#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assignment of value for ND20 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ +#define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ +#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assignment of value for ND21 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ +#define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ +#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assignment of value for ND22 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ +#define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ +#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assignment of value for ND23 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ +#define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ +#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assignment of value for ND24 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ +#define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ +#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assignment of value for ND25 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ +#define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ +#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assignment of value for ND26 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ +#define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ +#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assignment of value for ND27 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ +#define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ +#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assignment of value for ND28 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ +#define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ +#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assignment of value for ND29 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ +#define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ +#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assignment of value for ND30 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ +#define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ +#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assignment of value for ND31 in the CAN_NDAT1 register */ +#define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ + +#define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ +#define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ +#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ + +#define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ +#define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ +#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assignment of value for ND32 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ +#define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ +#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assignment of value for ND33 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ +#define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ +#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assignment of value for ND34 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ +#define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ +#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assignment of value for ND35 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ +#define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ +#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assignment of value for ND36 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ +#define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ +#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assignment of value for ND37 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ +#define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ +#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assignment of value for ND38 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ +#define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ +#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assignment of value for ND39 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ +#define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ +#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assignment of value for ND40 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ +#define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ +#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assignment of value for ND41 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ +#define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ +#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assignment of value for ND42 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ +#define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ +#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assignment of value for ND43 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ +#define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ +#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assignment of value for ND44 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ +#define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ +#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assignment of value for ND45 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ +#define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ +#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assignment of value for ND46 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ +#define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ +#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assignment of value for ND47 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ +#define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ +#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assignment of value for ND48 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ +#define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ +#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assignment of value for ND49 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ +#define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ +#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assignment of value for ND50 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ +#define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ +#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assignment of value for ND51 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ +#define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ +#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assignment of value for ND52 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ +#define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ +#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assignment of value for ND53 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ +#define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ +#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assignment of value for ND54 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ +#define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ +#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assignment of value for ND55 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ +#define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ +#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assignment of value for ND56 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ +#define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ +#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assignment of value for ND57 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ +#define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ +#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assignment of value for ND58 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ +#define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ +#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assignment of value for ND59 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ +#define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ +#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assignment of value for ND60 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ +#define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ +#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assignment of value for ND61 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ +#define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ +#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assignment of value for ND62 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ +#define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ +#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assignment of value for ND63 in the CAN_NDAT2 register */ +#define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ + +#define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ +#define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ +#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ + +#define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ +#define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assignment of value for F0SA in the CAN_RXF0C register */ +#define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ +#define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assignment of value for F0S in the CAN_RXF0C register */ +#define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ +#define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assignment of value for F0WM in the CAN_RXF0C register */ +#define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ +#define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assignment of value for F0OM in the CAN_RXF0C register */ +#define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ + + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ +#define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ + +#define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ +#define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assignment of value for F0FL in the CAN_RXF0S register */ +#define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ +#define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assignment of value for F0GI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ +#define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assignment of value for F0PI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ +#define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ +#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assignment of value for F0F in the CAN_RXF0S register */ +#define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ +#define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ +#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_RXF0S register */ +#define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ + + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ + +#define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ +#define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assignment of value for F0AI in the CAN_RXF0A register */ +#define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ + + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ + +#define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ +#define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assignment of value for RBSA in the CAN_RXBC register */ +#define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ + + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ + +#define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ +#define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assignment of value for F1SA in the CAN_RXF1C register */ +#define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ +#define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assignment of value for F1S in the CAN_RXF1C register */ +#define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ +#define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assignment of value for F1WM in the CAN_RXF1C register */ +#define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ +#define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assignment of value for F1OM in the CAN_RXF1C register */ +#define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ + + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ +#define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ + +#define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ +#define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assignment of value for F1FL in the CAN_RXF1S register */ +#define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ +#define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assignment of value for F1GI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ +#define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assignment of value for F1PI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ +#define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ +#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assignment of value for F1F in the CAN_RXF1S register */ +#define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ +#define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ +#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ +#define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assignment of value for DMS in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ +#define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ + + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ + +#define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ +#define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assignment of value for F1AI in the CAN_RXF1A register */ +#define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ + + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ + +#define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ +#define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assignment of value for F0DS in the CAN_RXESC register */ +#define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ +#define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assignment of value for F1DS in the CAN_RXESC register */ +#define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ +#define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assignment of value for RBDS in the CAN_RXESC register */ +#define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ + + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ + +#define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ +#define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assignment of value for TBSA in the CAN_TXBC register */ +#define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assignment of value for NDTB in the CAN_TXBC register */ +#define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ +#define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assignment of value for TFQS in the CAN_TXBC register */ +#define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ +#define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assignment of value for TFQM in the CAN_TXBC register */ +#define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ + + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ +#define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ + +#define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ +#define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assignment of value for TFFL in the CAN_TXFQS register */ +#define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ +#define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assignment of value for TFGI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assignment of value for TFQPI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ +#define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assignment of value for TFQF in the CAN_TXFQS register */ +#define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ + + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ + +#define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ +#define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assignment of value for TBDS in the CAN_TXESC register */ +#define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ +#define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ + + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ +#define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ + +#define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ +#define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ +#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assignment of value for TRP0 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ +#define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ +#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assignment of value for TRP1 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ +#define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ +#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assignment of value for TRP2 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ +#define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ +#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assignment of value for TRP3 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ +#define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ +#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assignment of value for TRP4 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ +#define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ +#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assignment of value for TRP5 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ +#define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ +#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assignment of value for TRP6 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ +#define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ +#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assignment of value for TRP7 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ +#define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ +#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assignment of value for TRP8 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ +#define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ +#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assignment of value for TRP9 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ +#define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ +#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assignment of value for TRP10 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ +#define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ +#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assignment of value for TRP11 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ +#define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ +#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assignment of value for TRP12 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ +#define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ +#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assignment of value for TRP13 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ +#define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ +#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assignment of value for TRP14 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ +#define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ +#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assignment of value for TRP15 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ +#define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ +#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assignment of value for TRP16 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ +#define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ +#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assignment of value for TRP17 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ +#define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ +#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assignment of value for TRP18 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ +#define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ +#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assignment of value for TRP19 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ +#define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ +#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assignment of value for TRP20 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ +#define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ +#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assignment of value for TRP21 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ +#define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ +#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assignment of value for TRP22 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ +#define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ +#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assignment of value for TRP23 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ +#define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ +#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assignment of value for TRP24 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ +#define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ +#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assignment of value for TRP25 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ +#define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ +#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assignment of value for TRP26 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ +#define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ +#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assignment of value for TRP27 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ +#define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ +#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assignment of value for TRP28 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ +#define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ +#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assignment of value for TRP29 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ +#define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ +#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assignment of value for TRP30 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ +#define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ +#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assignment of value for TRP31 in the CAN_TXBRP register */ +#define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ + +#define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ +#define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ +#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ + +#define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ +#define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ +#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assignment of value for AR0 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ +#define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ +#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assignment of value for AR1 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ +#define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ +#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assignment of value for AR2 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ +#define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ +#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assignment of value for AR3 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ +#define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ +#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assignment of value for AR4 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ +#define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ +#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assignment of value for AR5 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ +#define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ +#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assignment of value for AR6 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ +#define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ +#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assignment of value for AR7 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ +#define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ +#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assignment of value for AR8 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ +#define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ +#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assignment of value for AR9 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ +#define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ +#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assignment of value for AR10 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ +#define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ +#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assignment of value for AR11 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ +#define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ +#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assignment of value for AR12 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ +#define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ +#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assignment of value for AR13 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ +#define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ +#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assignment of value for AR14 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ +#define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ +#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assignment of value for AR15 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ +#define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ +#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assignment of value for AR16 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ +#define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ +#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assignment of value for AR17 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ +#define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ +#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assignment of value for AR18 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ +#define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ +#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assignment of value for AR19 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ +#define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ +#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assignment of value for AR20 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ +#define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ +#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assignment of value for AR21 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ +#define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ +#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assignment of value for AR22 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ +#define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ +#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assignment of value for AR23 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ +#define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ +#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assignment of value for AR24 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ +#define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ +#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assignment of value for AR25 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ +#define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ +#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assignment of value for AR26 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ +#define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ +#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assignment of value for AR27 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ +#define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ +#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assignment of value for AR28 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ +#define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ +#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assignment of value for AR29 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ +#define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ +#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assignment of value for AR30 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ +#define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ +#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assignment of value for AR31 in the CAN_TXBAR register */ +#define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ + +#define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ +#define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ +#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ + +#define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ +#define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ +#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assignment of value for CR0 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ +#define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ +#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assignment of value for CR1 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ +#define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ +#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assignment of value for CR2 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ +#define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ +#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assignment of value for CR3 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ +#define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ +#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assignment of value for CR4 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ +#define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ +#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assignment of value for CR5 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ +#define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ +#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assignment of value for CR6 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ +#define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ +#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assignment of value for CR7 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ +#define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ +#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assignment of value for CR8 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ +#define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ +#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assignment of value for CR9 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ +#define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ +#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assignment of value for CR10 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ +#define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ +#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assignment of value for CR11 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ +#define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ +#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assignment of value for CR12 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ +#define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ +#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assignment of value for CR13 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ +#define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ +#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assignment of value for CR14 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ +#define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ +#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assignment of value for CR15 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ +#define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ +#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assignment of value for CR16 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ +#define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ +#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assignment of value for CR17 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ +#define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ +#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assignment of value for CR18 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ +#define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ +#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assignment of value for CR19 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ +#define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ +#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assignment of value for CR20 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ +#define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ +#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assignment of value for CR21 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ +#define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ +#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assignment of value for CR22 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ +#define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ +#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assignment of value for CR23 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ +#define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ +#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assignment of value for CR24 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ +#define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ +#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assignment of value for CR25 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ +#define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ +#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assignment of value for CR26 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ +#define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ +#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assignment of value for CR27 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ +#define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ +#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assignment of value for CR28 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ +#define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ +#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assignment of value for CR29 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ +#define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ +#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assignment of value for CR30 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ +#define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ +#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assignment of value for CR31 in the CAN_TXBCR register */ +#define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ + +#define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ +#define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ +#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ +#define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ + +#define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ +#define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ +#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assignment of value for TO0 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ +#define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ +#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assignment of value for TO1 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ +#define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ +#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assignment of value for TO2 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ +#define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ +#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assignment of value for TO3 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ +#define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ +#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assignment of value for TO4 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ +#define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ +#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assignment of value for TO5 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ +#define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ +#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assignment of value for TO6 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ +#define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ +#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assignment of value for TO7 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ +#define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ +#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assignment of value for TO8 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ +#define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ +#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assignment of value for TO9 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ +#define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ +#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assignment of value for TO10 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ +#define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ +#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assignment of value for TO11 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ +#define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ +#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assignment of value for TO12 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ +#define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ +#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assignment of value for TO13 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ +#define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ +#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assignment of value for TO14 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ +#define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ +#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assignment of value for TO15 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ +#define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ +#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assignment of value for TO16 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ +#define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ +#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assignment of value for TO17 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ +#define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ +#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assignment of value for TO18 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ +#define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ +#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assignment of value for TO19 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ +#define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ +#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assignment of value for TO20 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ +#define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ +#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assignment of value for TO21 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ +#define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ +#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assignment of value for TO22 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ +#define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ +#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assignment of value for TO23 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ +#define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ +#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assignment of value for TO24 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ +#define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ +#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assignment of value for TO25 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ +#define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ +#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assignment of value for TO26 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ +#define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ +#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assignment of value for TO27 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ +#define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ +#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assignment of value for TO28 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ +#define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ +#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assignment of value for TO29 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ +#define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ +#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assignment of value for TO30 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ +#define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ +#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assignment of value for TO31 in the CAN_TXBTO register */ +#define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ + +#define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ +#define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ +#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ +#define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ + +#define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ +#define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ +#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assignment of value for CF0 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ +#define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ +#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assignment of value for CF1 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ +#define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ +#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assignment of value for CF2 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ +#define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ +#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assignment of value for CF3 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ +#define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ +#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assignment of value for CF4 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ +#define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ +#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assignment of value for CF5 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ +#define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ +#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assignment of value for CF6 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ +#define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ +#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assignment of value for CF7 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ +#define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ +#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assignment of value for CF8 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ +#define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ +#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assignment of value for CF9 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ +#define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ +#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assignment of value for CF10 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ +#define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ +#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assignment of value for CF11 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ +#define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ +#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assignment of value for CF12 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ +#define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ +#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assignment of value for CF13 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ +#define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ +#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assignment of value for CF14 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ +#define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ +#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assignment of value for CF15 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ +#define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ +#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assignment of value for CF16 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ +#define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ +#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assignment of value for CF17 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ +#define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ +#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assignment of value for CF18 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ +#define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ +#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assignment of value for CF19 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ +#define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ +#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assignment of value for CF20 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ +#define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ +#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assignment of value for CF21 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ +#define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ +#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assignment of value for CF22 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ +#define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ +#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assignment of value for CF23 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ +#define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ +#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assignment of value for CF24 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ +#define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ +#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assignment of value for CF25 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ +#define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ +#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assignment of value for CF26 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ +#define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ +#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assignment of value for CF27 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ +#define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ +#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assignment of value for CF28 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ +#define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ +#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assignment of value for CF29 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ +#define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ +#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assignment of value for CF30 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ +#define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ +#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assignment of value for CF31 in the CAN_TXBCF register */ +#define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ + +#define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ +#define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ +#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ + +#define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ +#define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ +#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assignment of value for TIE0 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ +#define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ +#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assignment of value for TIE1 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ +#define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ +#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assignment of value for TIE2 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ +#define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ +#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assignment of value for TIE3 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ +#define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ +#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assignment of value for TIE4 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ +#define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ +#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assignment of value for TIE5 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ +#define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ +#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assignment of value for TIE6 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ +#define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ +#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assignment of value for TIE7 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ +#define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ +#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assignment of value for TIE8 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ +#define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ +#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assignment of value for TIE9 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ +#define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ +#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assignment of value for TIE10 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ +#define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ +#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assignment of value for TIE11 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ +#define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ +#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assignment of value for TIE12 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ +#define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ +#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assignment of value for TIE13 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ +#define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ +#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assignment of value for TIE14 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ +#define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ +#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assignment of value for TIE15 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ +#define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ +#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assignment of value for TIE16 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ +#define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ +#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assignment of value for TIE17 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ +#define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ +#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assignment of value for TIE18 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ +#define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ +#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assignment of value for TIE19 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ +#define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ +#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assignment of value for TIE20 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ +#define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ +#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assignment of value for TIE21 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ +#define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ +#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assignment of value for TIE22 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ +#define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ +#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assignment of value for TIE23 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ +#define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ +#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assignment of value for TIE24 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ +#define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ +#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assignment of value for TIE25 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ +#define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ +#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assignment of value for TIE26 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ +#define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ +#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assignment of value for TIE27 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ +#define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ +#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assignment of value for TIE28 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ +#define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ +#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assignment of value for TIE29 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ +#define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ +#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assignment of value for TIE30 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ +#define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ +#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assignment of value for TIE31 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ + +#define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ +#define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ +#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ + +#define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ +#define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ +#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assignment of value for CFIE0 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ +#define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ +#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assignment of value for CFIE1 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ +#define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ +#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assignment of value for CFIE2 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ +#define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ +#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assignment of value for CFIE3 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ +#define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ +#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assignment of value for CFIE4 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ +#define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ +#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assignment of value for CFIE5 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ +#define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ +#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assignment of value for CFIE6 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ +#define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ +#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assignment of value for CFIE7 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ +#define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ +#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assignment of value for CFIE8 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ +#define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ +#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assignment of value for CFIE9 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ +#define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ +#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assignment of value for CFIE10 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ +#define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ +#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assignment of value for CFIE11 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ +#define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ +#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assignment of value for CFIE12 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ +#define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ +#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assignment of value for CFIE13 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ +#define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ +#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assignment of value for CFIE14 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ +#define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ +#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assignment of value for CFIE15 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ +#define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ +#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assignment of value for CFIE16 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ +#define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ +#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assignment of value for CFIE17 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ +#define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ +#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assignment of value for CFIE18 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ +#define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ +#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assignment of value for CFIE19 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ +#define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ +#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assignment of value for CFIE20 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ +#define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ +#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assignment of value for CFIE21 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ +#define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ +#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assignment of value for CFIE22 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ +#define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ +#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assignment of value for CFIE23 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ +#define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ +#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assignment of value for CFIE24 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ +#define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ +#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assignment of value for CFIE25 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ +#define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ +#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assignment of value for CFIE26 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ +#define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ +#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assignment of value for CFIE27 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ +#define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ +#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assignment of value for CFIE28 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ +#define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ +#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assignment of value for CFIE29 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ +#define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ +#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assignment of value for CFIE30 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ +#define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ +#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assignment of value for CFIE31 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ + +#define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ +#define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ +#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ + +#define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ +#define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assignment of value for EFSA in the CAN_TXEFC register */ +#define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ +#define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assignment of value for EFS in the CAN_TXEFC register */ +#define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ +#define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assignment of value for EFWM in the CAN_TXEFC register */ +#define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ + + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ +#define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ + +#define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ +#define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assignment of value for EFFL in the CAN_TXEFS register */ +#define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ +#define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assignment of value for EFGI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ +#define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assignment of value for EFPI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ +#define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ +#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assignment of value for EFF in the CAN_TXEFS register */ +#define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_TXEFS register */ +#define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ + + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ + +#define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assignment of value for EFAI in the CAN_TXEFA register */ +#define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ + + +/* CAN register offsets definitions */ +#define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ +#define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ +#define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ +#define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ +#define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ +#define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ +#define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ +#define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ +#define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ +#define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ +#define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ +#define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ +#define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ +#define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ +#define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ +#define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ +#define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ +#define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ +#define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ +#define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ +#define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ +#define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ +#define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ +#define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ +#define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ +#define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ +#define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ +#define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ +#define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ +#define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ +#define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ +#define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ +#define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ +#define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ +#define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ +#define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ +#define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ +#define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ +#define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ +#define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ +#define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ +#define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ +#define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ +#define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ +#define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ +#define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ +#define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* CAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t CAN_RXBE_0; /* Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t CAN_RXBE_1; /* Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t CAN_RXBE_DATA; /* Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} can_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t CAN_RXF0E_0; /* Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t CAN_RXF0E_1; /* Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t CAN_RXF0E_DATA; /* Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} can_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t CAN_RXF1E_0; /* Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t CAN_RXF1E_1; /* Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t CAN_RXF1E_DATA; /* Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} can_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t CAN_TXBE_0; /* Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t CAN_TXBE_1; /* Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t CAN_TXBE_DATA; /* Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} can_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t CAN_TXEFE_0; /* Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t CAN_TXEFE_1; /* Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} can_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t CAN_SIDFE_0; /* Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} can_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t CAN_XIDFE_0; /* Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t CAN_XIDFE_1; /* Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} can_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/* CAN register API structure */ +typedef struct +{ /* Control Area Network */ + __I uint32_t CAN_CREL; /* Offset: 0x00 (R/ 32) Core Release */ + __I uint32_t CAN_ENDN; /* Offset: 0x04 (R/ 32) Endian */ + __IO uint32_t CAN_MRCFG; /* Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO uint32_t CAN_DBTP; /* Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO uint32_t CAN_TEST; /* Offset: 0x10 (R/W 32) Test */ + __IO uint32_t CAN_RWD; /* Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO uint32_t CAN_CCCR; /* Offset: 0x18 (R/W 32) CC Control */ + __IO uint32_t CAN_NBTP; /* Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO uint32_t CAN_TSCC; /* Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I uint32_t CAN_TSCV; /* Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO uint32_t CAN_TOCC; /* Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO uint32_t CAN_TOCV; /* Offset: 0x2C (R/W 32) Timeout Counter Value */ + __I uint8_t Reserved1[0x10]; + __I uint32_t CAN_ECR; /* Offset: 0x40 (R/ 32) Error Counter */ + __I uint32_t CAN_PSR; /* Offset: 0x44 (R/ 32) Protocol Status */ + __IO uint32_t CAN_TDCR; /* Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t CAN_IR; /* Offset: 0x50 (R/W 32) Interrupt */ + __IO uint32_t CAN_IE; /* Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO uint32_t CAN_ILS; /* Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO uint32_t CAN_ILE; /* Offset: 0x5C (R/W 32) Interrupt Line Enable */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t CAN_GFC; /* Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO uint32_t CAN_SIDFC; /* Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO uint32_t CAN_XIDFC; /* Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t CAN_XIDAM; /* Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I uint32_t CAN_HPMS; /* Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO uint32_t CAN_NDAT1; /* Offset: 0x98 (R/W 32) New Data 1 */ + __IO uint32_t CAN_NDAT2; /* Offset: 0x9C (R/W 32) New Data 2 */ + __IO uint32_t CAN_RXF0C; /* Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I uint32_t CAN_RXF0S; /* Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO uint32_t CAN_RXF0A; /* Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO uint32_t CAN_RXBC; /* Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO uint32_t CAN_RXF1C; /* Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I uint32_t CAN_RXF1S; /* Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO uint32_t CAN_RXF1A; /* Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO uint32_t CAN_RXESC; /* Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t CAN_TXBC; /* Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I uint32_t CAN_TXFQS; /* Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO uint32_t CAN_TXESC; /* Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I uint32_t CAN_TXBRP; /* Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO uint32_t CAN_TXBAR; /* Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO uint32_t CAN_TXBCR; /* Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I uint32_t CAN_TXBTO; /* Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I uint32_t CAN_TXBCF; /* Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO uint32_t CAN_TXBTIE; /* Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t CAN_TXBCIE; /* Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t CAN_TXEFC; /* Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I uint32_t CAN_TXEFS; /* Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO uint32_t CAN_TXEFA; /* Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} can_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_CAN_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ccl.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ccl.h new file mode 100644 index 00000000..19211ee3 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ccl.h @@ -0,0 +1,218 @@ +/* + * Component description for CCL + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_CCL_COMPONENT_H_ +#define _SAMC21_CCL_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assignment of value for SWRST in the CCL_CTRL register */ +#define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the CCL_CTRL register */ +#define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the CCL_CTRL register */ +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assignment of value for SEQSEL in the CCL_SEQCTRL register */ +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assignment of value for FILTSEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assignment of value for EDGESEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assignment of value for INSEL0 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assignment of value for INSEL1 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assignment of value for INSEL2 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assignment of value for INVEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assignment of value for LUTEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assignment of value for LUTEO in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assignment of value for TRUTH in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ + + +/* CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ +#define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ +#define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ +#define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ +#define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ +#define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /* Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /* Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /* Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_CCL_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dac.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dac.h new file mode 100644 index 00000000..f55c9482 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dac.h @@ -0,0 +1,217 @@ +/* + * Component description for DAC + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_DAC_COMPONENT_H_ +#define _SAMC21_DAC_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the DAC_CTRLA register */ +#define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable Position */ +#define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_CTRLA register */ +#define DAC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (DAC_CTRLA) Run in Standby Position */ +#define DAC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) /* (DAC_CTRLA) Run in Standby Mask */ +#define DAC_CTRLA_RUNSTDBY(value) (DAC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << DAC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the DAC_CTRLA register */ +#define DAC_CTRLA_Msk _UINT8_(0x43) /* (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_EOEN_Pos _UINT8_(0) /* (DAC_CTRLB) External Output Enable Position */ +#define DAC_CTRLB_EOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_EOEN_Pos) /* (DAC_CTRLB) External Output Enable Mask */ +#define DAC_CTRLB_EOEN(value) (DAC_CTRLB_EOEN_Msk & (_UINT8_(value) << DAC_CTRLB_EOEN_Pos)) /* Assignment of value for EOEN in the DAC_CTRLB register */ +#define DAC_CTRLB_IOEN_Pos _UINT8_(1) /* (DAC_CTRLB) Internal Output Enable Position */ +#define DAC_CTRLB_IOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_IOEN_Pos) /* (DAC_CTRLB) Internal Output Enable Mask */ +#define DAC_CTRLB_IOEN(value) (DAC_CTRLB_IOEN_Msk & (_UINT8_(value) << DAC_CTRLB_IOEN_Pos)) /* Assignment of value for IOEN in the DAC_CTRLB register */ +#define DAC_CTRLB_LEFTADJ_Pos _UINT8_(2) /* (DAC_CTRLB) Left Adjusted Data Position */ +#define DAC_CTRLB_LEFTADJ_Msk (_UINT8_(0x1) << DAC_CTRLB_LEFTADJ_Pos) /* (DAC_CTRLB) Left Adjusted Data Mask */ +#define DAC_CTRLB_LEFTADJ(value) (DAC_CTRLB_LEFTADJ_Msk & (_UINT8_(value) << DAC_CTRLB_LEFTADJ_Pos)) /* Assignment of value for LEFTADJ in the DAC_CTRLB register */ +#define DAC_CTRLB_VPD_Pos _UINT8_(3) /* (DAC_CTRLB) Voltage Pump Disable Position */ +#define DAC_CTRLB_VPD_Msk (_UINT8_(0x1) << DAC_CTRLB_VPD_Pos) /* (DAC_CTRLB) Voltage Pump Disable Mask */ +#define DAC_CTRLB_VPD(value) (DAC_CTRLB_VPD_Msk & (_UINT8_(value) << DAC_CTRLB_VPD_Pos)) /* Assignment of value for VPD in the DAC_CTRLB register */ +#define DAC_CTRLB_DITHER_Pos _UINT8_(5) /* (DAC_CTRLB) Dither Enable Position */ +#define DAC_CTRLB_DITHER_Msk (_UINT8_(0x1) << DAC_CTRLB_DITHER_Pos) /* (DAC_CTRLB) Dither Enable Mask */ +#define DAC_CTRLB_DITHER(value) (DAC_CTRLB_DITHER_Msk & (_UINT8_(value) << DAC_CTRLB_DITHER_Pos)) /* Assignment of value for DITHER in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_Pos _UINT8_(6) /* (DAC_CTRLB) Reference Selection Position */ +#define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assignment of value for REFSEL in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_INT1V_Val _UINT8_(0x0) /* (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _UINT8_(0x1) /* (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal 1.0V reference Position */ +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) AVCC Position */ +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference Position */ +#define DAC_CTRLB_Msk _UINT8_(0xEF) /* (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input Position */ +#define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL) Start Conversion Event Input Mask */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(1) /* (DAC_EVCTRL) Data Buffer Empty Event Output Position */ +#define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output Mask */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) /* Assignment of value for EMPTYEO in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI_Pos _UINT8_(2) /* (DAC_EVCTRL) Invert Event Input Position */ +#define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL) Invert Event Input Mask */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) /* Assignment of value for INVEI in the DAC_EVCTRL register */ +#define DAC_EVCTRL_Msk _UINT8_(0x07) /* (DAC_EVCTRL) Register Mask */ + + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR) Underrun Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) /* Assignment of value for UNDERRUN in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY_Pos _UINT8_(1) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) /* Assignment of value for EMPTY in the DAC_INTENCLR register */ +#define DAC_INTENCLR_Msk _UINT8_(0x03) /* (DAC_INTENCLR) Register Mask */ + + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET) Underrun Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) /* Assignment of value for UNDERRUN in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY_Pos _UINT8_(1) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) /* Assignment of value for EMPTY in the DAC_INTENSET register */ +#define DAC_INTENSET_Msk _UINT8_(0x03) /* (DAC_INTENSET) Register Mask */ + + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG) Underrun Position */ +#define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG) Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) /* Assignment of value for UNDERRUN in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY_Pos _UINT8_(1) /* (DAC_INTFLAG) Data Buffer Empty Position */ +#define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG) Data Buffer Empty Mask */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) /* Assignment of value for EMPTY in the DAC_INTFLAG register */ +#define DAC_INTFLAG_Msk _UINT8_(0x03) /* (DAC_INTFLAG) Register Mask */ + + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS) Ready Position */ +#define DAC_STATUS_READY_Msk (_UINT8_(0x1) << DAC_STATUS_READY_Pos) /* (DAC_STATUS) Ready Mask */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) /* Assignment of value for READY in the DAC_STATUS register */ +#define DAC_STATUS_Msk _UINT8_(0x01) /* (DAC_STATUS) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */ +#define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) Data Reset Value */ + +#define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) Data value to be converted Position */ +#define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) Data value to be converted Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assignment of value for DATA in the DAC_DATA register */ +#define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assignment of value for DATABUF in the DAC_DATABUF register */ +#define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) Enable Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) Enable Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data Position */ +#define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY) Data Mask */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) /* Assignment of value for DATA in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data Buffer Position */ +#define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY) Data Buffer Mask */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) /* Assignment of value for DATABUF in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_Msk _UINT32_(0x0000000F) /* (DAC_SYNCBUSY) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the DAC_DBGCTRL register */ +#define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ + + +/* DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ +#define DAC_DATA_REG_OFST _UINT32_(0x08) /* (DAC_DATA) Data Offset */ +#define DAC_DATABUF_REG_OFST _UINT32_(0x0C) /* (DAC_DATABUF) Data Buffer Offset */ +#define DAC_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DBGCTRL_REG_OFST _UINT32_(0x14) /* (DAC_DBGCTRL) Debug Control Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* DAC register API structure */ +typedef struct +{ /* Digital Analog Converter */ + __IO uint8_t DAC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /* Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /* Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /* Offset: 0x07 (R/ 8) Status */ + __O uint16_t DAC_DATA; /* Offset: 0x08 ( /W 16) Data */ + __I uint8_t Reserved2[0x02]; + __O uint16_t DAC_DATABUF; /* Offset: 0x0C ( /W 16) Data Buffer */ + __I uint8_t Reserved3[0x02]; + __I uint32_t DAC_SYNCBUSY; /* Offset: 0x10 (R/ 32) Synchronization Busy */ + __IO uint8_t DAC_DBGCTRL; /* Offset: 0x14 (R/W 8) Debug Control */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_DAC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/divas.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/divas.h new file mode 100644 index 00000000..82413246 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/divas.h @@ -0,0 +1,127 @@ +/* + * Component description for DIVAS + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_DIVAS_COMPONENT_H_ +#define _SAMC21_DIVAS_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DIVAS */ +/* ************************************************************************** */ + +/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */ +#define DIVAS_CTRLA_RESETVALUE _UINT8_(0x00) /* (DIVAS_CTRLA) Control Reset Value */ + +#define DIVAS_CTRLA_SIGNED_Pos _UINT8_(0) /* (DIVAS_CTRLA) Signed Position */ +#define DIVAS_CTRLA_SIGNED_Msk (_UINT8_(0x1) << DIVAS_CTRLA_SIGNED_Pos) /* (DIVAS_CTRLA) Signed Mask */ +#define DIVAS_CTRLA_SIGNED(value) (DIVAS_CTRLA_SIGNED_Msk & (_UINT8_(value) << DIVAS_CTRLA_SIGNED_Pos)) /* Assignment of value for SIGNED in the DIVAS_CTRLA register */ +#define DIVAS_CTRLA_DLZ_Pos _UINT8_(1) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Position */ +#define DIVAS_CTRLA_DLZ_Msk (_UINT8_(0x1) << DIVAS_CTRLA_DLZ_Pos) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Mask */ +#define DIVAS_CTRLA_DLZ(value) (DIVAS_CTRLA_DLZ_Msk & (_UINT8_(value) << DIVAS_CTRLA_DLZ_Pos)) /* Assignment of value for DLZ in the DIVAS_CTRLA register */ +#define DIVAS_CTRLA_Msk _UINT8_(0x03) /* (DIVAS_CTRLA) Register Mask */ + + +/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */ +#define DIVAS_STATUS_RESETVALUE _UINT8_(0x00) /* (DIVAS_STATUS) Status Reset Value */ + +#define DIVAS_STATUS_BUSY_Pos _UINT8_(0) /* (DIVAS_STATUS) DIVAS Accelerator Busy Position */ +#define DIVAS_STATUS_BUSY_Msk (_UINT8_(0x1) << DIVAS_STATUS_BUSY_Pos) /* (DIVAS_STATUS) DIVAS Accelerator Busy Mask */ +#define DIVAS_STATUS_BUSY(value) (DIVAS_STATUS_BUSY_Msk & (_UINT8_(value) << DIVAS_STATUS_BUSY_Pos)) /* Assignment of value for BUSY in the DIVAS_STATUS register */ +#define DIVAS_STATUS_DBZ_Pos _UINT8_(1) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Position */ +#define DIVAS_STATUS_DBZ_Msk (_UINT8_(0x1) << DIVAS_STATUS_DBZ_Pos) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Mask */ +#define DIVAS_STATUS_DBZ(value) (DIVAS_STATUS_DBZ_Msk & (_UINT8_(value) << DIVAS_STATUS_DBZ_Pos)) /* Assignment of value for DBZ in the DIVAS_STATUS register */ +#define DIVAS_STATUS_Msk _UINT8_(0x03) /* (DIVAS_STATUS) Register Mask */ + + +/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */ +#define DIVAS_DIVIDEND_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVIDEND) Dividend Reset Value */ + +#define DIVAS_DIVIDEND_DIVIDEND_Pos _UINT32_(0) /* (DIVAS_DIVIDEND) DIVIDEND Position */ +#define DIVAS_DIVIDEND_DIVIDEND_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos) /* (DIVAS_DIVIDEND) DIVIDEND Mask */ +#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & (_UINT32_(value) << DIVAS_DIVIDEND_DIVIDEND_Pos)) /* Assignment of value for DIVIDEND in the DIVAS_DIVIDEND register */ +#define DIVAS_DIVIDEND_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVIDEND) Register Mask */ + + +/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */ +#define DIVAS_DIVISOR_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVISOR) Divisor Reset Value */ + +#define DIVAS_DIVISOR_DIVISOR_Pos _UINT32_(0) /* (DIVAS_DIVISOR) DIVISOR Position */ +#define DIVAS_DIVISOR_DIVISOR_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos) /* (DIVAS_DIVISOR) DIVISOR Mask */ +#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & (_UINT32_(value) << DIVAS_DIVISOR_DIVISOR_Pos)) /* Assignment of value for DIVISOR in the DIVAS_DIVISOR register */ +#define DIVAS_DIVISOR_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVISOR) Register Mask */ + + +/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) ( R/ 32) Result -------- */ +#define DIVAS_RESULT_RESETVALUE _UINT32_(0x00) /* (DIVAS_RESULT) Result Reset Value */ + +#define DIVAS_RESULT_RESULT_Pos _UINT32_(0) /* (DIVAS_RESULT) RESULT Position */ +#define DIVAS_RESULT_RESULT_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos) /* (DIVAS_RESULT) RESULT Mask */ +#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & (_UINT32_(value) << DIVAS_RESULT_RESULT_Pos)) /* Assignment of value for RESULT in the DIVAS_RESULT register */ +#define DIVAS_RESULT_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_RESULT) Register Mask */ + + +/* -------- DIVAS_REM : (DIVAS Offset: 0x14) ( R/ 32) Remainder -------- */ +#define DIVAS_REM_RESETVALUE _UINT32_(0x00) /* (DIVAS_REM) Remainder Reset Value */ + +#define DIVAS_REM_REM_Pos _UINT32_(0) /* (DIVAS_REM) REM Position */ +#define DIVAS_REM_REM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_REM_REM_Pos) /* (DIVAS_REM) REM Mask */ +#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & (_UINT32_(value) << DIVAS_REM_REM_Pos)) /* Assignment of value for REM in the DIVAS_REM register */ +#define DIVAS_REM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_REM) Register Mask */ + + +/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */ +#define DIVAS_SQRNUM_RESETVALUE _UINT32_(0x00) /* (DIVAS_SQRNUM) Square Root Input Reset Value */ + +#define DIVAS_SQRNUM_SQRNUM_Pos _UINT32_(0) /* (DIVAS_SQRNUM) Square Root Input Position */ +#define DIVAS_SQRNUM_SQRNUM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos) /* (DIVAS_SQRNUM) Square Root Input Mask */ +#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & (_UINT32_(value) << DIVAS_SQRNUM_SQRNUM_Pos)) /* Assignment of value for SQRNUM in the DIVAS_SQRNUM register */ +#define DIVAS_SQRNUM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_SQRNUM) Register Mask */ + + +/* DIVAS register offsets definitions */ +#define DIVAS_CTRLA_REG_OFST _UINT32_(0x00) /* (DIVAS_CTRLA) Control Offset */ +#define DIVAS_STATUS_REG_OFST _UINT32_(0x04) /* (DIVAS_STATUS) Status Offset */ +#define DIVAS_DIVIDEND_REG_OFST _UINT32_(0x08) /* (DIVAS_DIVIDEND) Dividend Offset */ +#define DIVAS_DIVISOR_REG_OFST _UINT32_(0x0C) /* (DIVAS_DIVISOR) Divisor Offset */ +#define DIVAS_RESULT_REG_OFST _UINT32_(0x10) /* (DIVAS_RESULT) Result Offset */ +#define DIVAS_REM_REG_OFST _UINT32_(0x14) /* (DIVAS_REM) Remainder Offset */ +#define DIVAS_SQRNUM_REG_OFST _UINT32_(0x18) /* (DIVAS_SQRNUM) Square Root Input Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* DIVAS register API structure */ +typedef struct +{ /* Divide and Square Root Accelerator */ + __IO uint8_t DIVAS_CTRLA; /* Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t DIVAS_STATUS; /* Offset: 0x04 (R/W 8) Status */ + __I uint8_t Reserved2[0x03]; + __IO uint32_t DIVAS_DIVIDEND; /* Offset: 0x08 (R/W 32) Dividend */ + __IO uint32_t DIVAS_DIVISOR; /* Offset: 0x0C (R/W 32) Divisor */ + __I uint32_t DIVAS_RESULT; /* Offset: 0x10 (R/ 32) Result */ + __I uint32_t DIVAS_REM; /* Offset: 0x14 (R/ 32) Remainder */ + __IO uint32_t DIVAS_SQRNUM; /* Offset: 0x18 (R/W 32) Square Root Input */ +} divas_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_DIVAS_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dmac.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dmac.h new file mode 100644 index 00000000..0a4a8640 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dmac.h @@ -0,0 +1,883 @@ +/* + * Component description for DMAC + * + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ +#ifndef _SAMC21_DMAC_COMPONENT_H_ +#define _SAMC21_DMAC_COMPONENT_H_ + +#include "core_cm0plus.h" + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _UINT16_(0x00) /* (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _UINT16_(0) /* (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos) /* (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assignment of value for VALID in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_Pos _UINT16_(1) /* (DMAC_BTCTRL) Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assignment of value for EVOSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when block transfer complete Position */ +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when beat transfer complete Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _UINT16_(3) /* (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assignment of value for BLOCKACT in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _UINT16_(0x2) /* (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _UINT16_(8) /* (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assignment of value for BEATSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _UINT16_(0x1) /* (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _UINT16_(0x2) /* (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _UINT16_(10) /* (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /* (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assignment of value for SRCINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_DSTINC_Pos _UINT16_(11) /* (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assignment of value for DSTINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_Pos _UINT16_(12) /* (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assignment of value for STEPSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_DST_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _UINT16_(13) /* (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assignment of value for STEPSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSIZE_X1_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M0PLUS Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/* ***************** SAMC21E18A specific Interrupt Numbers ****************** */ + MCLK_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (MCLK) */ + OSC32KCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSC32KCTRL) */ + OSCCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSCCTRL) */ + PAC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (PAC) */ + SUPC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (SUPC) */ + WDT_IRQn = 1, /* 1 Watchdog Timer (WDT) */ + RTC_IRQn = 2, /* 2 Real-Time Counter (RTC) */ + EIC_IRQn = 3, /* 3 External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /* 4 Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /* 5 Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /* 6 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /* 7 Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /* 8 Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /* 9 Serial Communication Interface (SERCOM0) */ + SERCOM1_IRQn = 10, /* 10 Serial Communication Interface (SERCOM1) */ + SERCOM2_IRQn = 11, /* 11 Serial Communication Interface (SERCOM2) */ + SERCOM3_IRQn = 12, /* 12 Serial Communication Interface (SERCOM3) */ + CAN0_IRQn = 15, /* 15 Control Area Network (CAN0) */ + TCC0_IRQn = 17, /* 17 Timer Counter Control (TCC0) */ + TCC1_IRQn = 18, /* 18 Timer Counter Control (TCC1) */ + TCC2_IRQn = 19, /* 19 Timer Counter Control (TCC2) */ + TC0_IRQn = 20, /* 20 Basic Timer Counter (TC0) */ + TC1_IRQn = 21, /* 21 Basic Timer Counter (TC1) */ + TC2_IRQn = 22, /* 22 Basic Timer Counter (TC2) */ + TC3_IRQn = 23, /* 23 Basic Timer Counter (TC3) */ + TC4_IRQn = 24, /* 24 Basic Timer Counter (TC4) */ + ADC0_IRQn = 25, /* 25 Analog Digital Converter (ADC0) */ + ADC1_IRQn = 26, /* 26 Analog Digital Converter (ADC1) */ + AC_IRQn = 27, /* 27 Analog Comparators (AC) */ + DAC_IRQn = 28, /* 28 Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /* 30 Peripheral Touch Controller (PTC) */ + + PERIPH_MAX_IRQn = 30 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M0PLUS handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pvReservedC12; + void* pvReservedC11; + void* pvReservedC10; + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pvReservedC4; + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt (MCLK OSCCTRL OSC32KCTRL PAC SUPC) */ + void* pfnWDT_Handler; /* 1 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 2 Real-Time Counter (RTC) */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 4 Frequency Meter (FREQM) */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor (TSENS) */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_Handler; /* 8 Event System Interface (EVSYS) */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface (SERCOM3) */ + void* pvReserved13; + void* pvReserved14; + void* pfnCAN0_Handler; /* 15 Control Area Network (CAN0) */ + void* pvReserved16; + void* pfnTCC0_Handler; /* 17 Timer Counter Control (TCC0) */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control (TCC1) */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control (TCC2) */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter (TC4) */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter (ADC0) */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 27 Analog Comparators (AC) */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter (DAC) */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller (PTC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M0PLUS exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void CAN0_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M0PLUS Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001 /* Cortex-M0+ Core Revision */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm0plus.h" +#if defined USE_CMSIS_INIT +#include "system_samc21e18a.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/ptc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /* Power Manager (PM) */ +#define ID_MCLK ( 2) /* Main Clock (MCLK) */ +#define ID_RSTC ( 3) /* Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /* Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /* Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /* Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /* Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /* External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /* Frequency Meter (FREQM) */ +#define ID_TSENS ( 12) /* Temperature Sensor (TSENS) */ +#define ID_PORT ( 32) /* Port Module (PORT) */ +#define ID_DSU ( 33) /* Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /* Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC ( 35) /* Direct Memory Access Controller (DMAC) */ +#define ID_MTB ( 36) /* Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS ( 37) /* HSB Matrix (HMATRIXHS) */ +#define ID_EVSYS ( 64) /* Event System Interface (EVSYS) */ +#define ID_SERCOM0 ( 65) /* Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 66) /* Serial Communication Interface (SERCOM1) */ +#define ID_SERCOM2 ( 67) /* Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 68) /* Serial Communication Interface (SERCOM3) */ +#define ID_CAN0 ( 71) /* Control Area Network (CAN0) */ +#define ID_TCC0 ( 73) /* Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 74) /* Timer Counter Control (TCC1) */ +#define ID_TCC2 ( 75) /* Timer Counter Control (TCC2) */ +#define ID_TC0 ( 76) /* Basic Timer Counter (TC0) */ +#define ID_TC1 ( 77) /* Basic Timer Counter (TC1) */ +#define ID_TC2 ( 78) /* Basic Timer Counter (TC2) */ +#define ID_TC3 ( 79) /* Basic Timer Counter (TC3) */ +#define ID_TC4 ( 80) /* Basic Timer Counter (TC4) */ +#define ID_ADC0 ( 81) /* Analog Digital Converter (ADC0) */ +#define ID_ADC1 ( 82) /* Analog Digital Converter (ADC1) */ +#define ID_SDADC ( 83) /* Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC ( 84) /* Analog Comparators (AC) */ +#define ID_DAC ( 85) /* Digital Analog Converter (DAC) */ +#define ID_PTC ( 86) /* Peripheral Touch Controller (PTC) */ +#define ID_CCL ( 87) /* Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_MAX ( 87) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42005000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x42004400) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x42004800) /* ADC1 Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42001c00) /* CAN0 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42005c00) /* CCL Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x42005400) /* DAC Registers Address */ +#define DIVAS_REGS ((divas_registers_t*)0x48000000) /* DIVAS Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x41006000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x42000000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define HMATRIXHS_REGS ((hmatrixb_registers_t*)0x4100a000) /* HMATRIXHS Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define MTB_REGS ((mtb_registers_t*)0x41008000) /* MTB Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define OTP5_FUSES_REGS ((fuses_otp5_fuses_registers_t*)0x00806020) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00806030) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41000000) /* PORT Registers Address */ +#define PORT_IOBUS_REGS ((port_registers_t*)0x60000000) /* PORT Registers Address */ +#define PTC_REGS ((ptc_registers_t*)0x42005800) /* PTC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDADC_REGS ((sdadc_registers_t*)0x42004c00) /* SDADC Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x42000400) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x42000800) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x42000c00) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x42001000) /* SERCOM3 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x42003000) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x42003400) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x42003800) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x42003c00) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42004000) /* TC4 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x42002400) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x42002800) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42002c00) /* TCC2 Registers Address */ +#define TSENS_REGS ((tsens_registers_t*)0x40003000) /* TSENS Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42005000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x42004400) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x42004800) /* ADC1 Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42001c00) /* CAN0 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42005c00) /* CCL Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x42005400) /* DAC Base Address */ +#define DIVAS_BASE_ADDRESS _UINT32_(0x48000000) /* DIVAS Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x41006000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x42000000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define HMATRIXHS_BASE_ADDRESS _UINT32_(0x4100a000) /* HMATRIXHS Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define MTB_BASE_ADDRESS _UINT32_(0x41008000) /* MTB Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define OTP5_FUSES_BASE_ADDRESS _UINT32_(0x00806020) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00806030) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41000000) /* PORT Base Address */ +#define PORT_IOBUS_BASE_ADDRESS _UINT32_(0x60000000) /* PORT Base Address */ +#define PTC_BASE_ADDRESS _UINT32_(0x42005800) /* PTC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDADC_BASE_ADDRESS _UINT32_(0x42004c00) /* SDADC Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x42000400) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x42000800) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x42000c00) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x42001000) /* SERCOM3 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x42003000) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x42003400) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x42003800) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x42003c00) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42004000) /* TC4 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x42002400) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x42002800) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42002c00) /* TCC2 Base Address */ +#define TSENS_BASE_ADDRESS _UINT32_(0x40003000) /* TSENS Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#include "pio/samc21e18a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 64) +#define FLASH_NB_OF_PAGES _UINT32_( 4096) + +#define OTP5_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ +#define USER_PAGE_SIZE _UINT32_(0x00000100) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 64) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 4) + +#define RWW_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: flash */ +#define RWW_PAGE_SIZE _UINT32_( 64) +#define RWW_NB_OF_PAGES _UINT32_( 128) + +#define HSRAM_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004000) /* 16kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00010000) /* 64kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: io */ +#define DIVAS_SIZE _UINT32_(0x00000020) /* 0kB Memory segment type: io */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define PERIPHERALS_SIZE _UINT32_(0x20000000) /* 524288kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define OTP5_ADDR _UINT32_(0x00806020) /* OTP5 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00806030) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define RWW_ADDR _UINT32_(0x00400000) /* RWW base address (type: flash)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define DIVAS_ADDR _UINT32_(0x48000000) /* DIVAS base address (type: io)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ +#define PERIPHERALS_ADDR _UINT32_(0x40000000) /* PERIPHERALS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAMC21E18A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X1101050A) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAMC21E18A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL 1 /* ID for OSCCTRL event generator XOSC_FAIL */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_CMP_0 3 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 4 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_OVF 5 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_RTC_PER_0 6 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 7 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 8 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 9 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 10 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 11 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 12 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 13 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_0 14 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 15 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 16 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 17 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 18 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 19 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 20 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 21 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 22 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 23 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 24 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 25 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 26 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 27 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 28 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 29 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_TSENS_WINMON 30 /* ID for TSENS event generator WINMON */ +#define EVENT_ID_GEN_DMAC_CH_0 31 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 32 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 33 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 34 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_TCC0_OVF 35 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 36 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 37 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 38 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 39 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 40 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 41 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC1_OVF 42 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 43 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 44 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 45 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 46 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_OVF 47 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 48 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 49 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 50 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 51 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 52 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 53 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 54 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 55 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 56 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 57 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 58 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 59 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 60 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 61 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 62 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 63 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 64 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 65 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 66 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 67 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 68 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 69 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 70 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_SDADC_RESRDY 71 /* ID for SDADC event generator RESRDY */ +#define EVENT_ID_GEN_SDADC_WINMON 72 /* ID for SDADC event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 73 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 74 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_COMP_2 75 /* ID for AC event generator COMP_2 */ +#define EVENT_ID_GEN_AC_COMP_3 76 /* ID for AC event generator COMP_3 */ +#define EVENT_ID_GEN_AC_WIN_0 77 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_AC_WIN_1 78 /* ID for AC event generator WIN_1 */ +#define EVENT_ID_GEN_DAC_EMPTY 79 /* ID for DAC event generator EMPTY */ +#define EVENT_ID_GEN_PTC_EOC 80 /* ID for PTC event generator EOC */ +#define EVENT_ID_GEN_PTC_WIN_COMP 81 /* ID for PTC event generator WIN_COMP */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 82 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 83 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 84 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 85 /* ID for CCL event generator LUTOUT_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 86 /* ID for PAC event generator ACCERR */ + +/* ************************************************************************** */ +/* Event User IDs for SAMC21E18A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_TSENS_START 0 /* ID for TSENS event user START */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_TCC0_EV_0 9 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 10 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 11 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 12 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 13 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 14 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC1_EV_0 15 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 16 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 17 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 18 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC2_EV_0 19 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 20 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 21 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 22 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 23 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 24 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 25 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 26 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 27 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_ADC0_START 28 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 29 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 30 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 31 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_SDADC_START 32 /* ID for SDADC event user START */ +#define EVENT_ID_USER_SDADC_FLUSH 33 /* ID for SDADC event user FLUSH */ +#define EVENT_ID_USER_AC_SOC_0 34 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 35 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_AC_SOC_2 36 /* ID for AC event user SOC_2 */ +#define EVENT_ID_USER_AC_SOC_3 37 /* ID for AC event user SOC_3 */ +#define EVENT_ID_USER_DAC_START 38 /* ID for DAC event user START */ +#define EVENT_ID_USER_CCL_LUTIN_0 40 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 41 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 42 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 43 /* ID for CCL event user LUTIN_3 */ +#define EVENT_ID_USER_MTB_START 45 /* ID for MTB event user START */ +#define EVENT_ID_USER_MTB_STOP 46 /* ID for MTB event user STOP */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAMC21E18A_H_ */ + diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000..9f4c4d77 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000..a2ad65fb --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000..74bc4a2d --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..6edd5096 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000..21a2c711 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000..045aaf19 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000..407b94ba --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000..6addcbb7 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000..ed961aa4 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000..3b268177 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bms/bms/bms_config_e18a/src/safety/current.c b/bms/bms/bms_config_e18a/src/safety/current.c new file mode 100644 index 00000000..813c31d1 --- /dev/null +++ b/bms/bms/bms_config_e18a/src/safety/current.c @@ -0,0 +1,77 @@ +#include "current.h" +#include "definitions.h" +#include "peripheral/adc/plib_adc0.h" +#include +#include + + +static int current_flags = 0; + +uint16_t adc_read_channel(uint8_t channel) +{ + // 1. Select ADC input (MUXPOS) + ADC0_REGS->ADC_INPUTCTRL = ADC_INPUTCTRL_MUXPOS(channel); + while (ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk); + + // 2. Start conversion + ADC0_REGS->ADC_SWTRIG |= ADC_SWTRIG_START_Msk; + + // 3. Wait for conversion to complete + while ((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) == 0); + + // 4. Read result + uint16_t result = ADC0_REGS->ADC_RESULT; + + // 5. Clear the RESRDY flag (write 1 to clear) + ADC0_REGS->ADC_INTFLAG = ADC_INTFLAG_RESRDY_Msk; + + return result; +} + + + +//static float read_current_amps(void){} + + +void current_init(){ + + ADC0_Initialize(); + ADC0_Enable(); + ADC0_ChannelSelect(ADC_POSINPUT_AIN0, ADC_NEGINPUT_GND); + ADC0_ConversionStart(); + + + +} + + + +void current_check(){ + + if (ADC0_REGS->ADC_RESULT > CURRENT_THRESHOLD_A){ + + + + current_flags++;} + + +} + + + + +void check_raise_flags(void){ + //check if current sense flags are raised + //if raised, take action + if (current_flags>5){ + //raise system fault + + } +} + + + + +//raise flags logic if current is out of range +//fault handling logic +//current limiting logic diff --git a/bms/bms/bms_config_e18a/src/safety/current.h b/bms/bms/bms_config_e18a/src/safety/current.h new file mode 100644 index 00000000..1942156b --- /dev/null +++ b/bms/bms/bms_config_e18a/src/safety/current.h @@ -0,0 +1,16 @@ + +#include "definitions.h" +#include "peripheral/adc/plib_adc0.h" +#include + + +#define CURRENT_THRESHOLD_A 25 +#define SENSOR_SENSITIVITY_V_A 0.04 +#define SENSOR_OFFSET_V 1.65 + + + +void current_init(void); +void current_check(void); +void current_raise_flags(void); + diff --git a/bms/bms/bms_config_e18a/src/safety/killswitch.c b/bms/bms/bms_config_e18a/src/safety/killswitch.c new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config_e18a/src/safety/killswitch.h b/bms/bms/bms_config_e18a/src/safety/killswitch.h new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config_e18a/src/safety/temperature.c b/bms/bms/bms_config_e18a/src/safety/temperature.c new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config_e18a/src/safety/temperature.h b/bms/bms/bms_config_e18a/src/safety/temperature.h new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config_e18a/src/safety/voltage.c b/bms/bms/bms_config_e18a/src/safety/voltage.c new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/bms_config_e18a/src/safety/voltage.h b/bms/bms/bms_config_e18a/src/safety/voltage.h new file mode 100644 index 00000000..e69de29b diff --git a/bms/bms/cmake/bms_config_e18a/default/CMakeLists.txt b/bms/bms/cmake/bms_config_e18a/default/CMakeLists.txt new file mode 100644 index 00000000..81cf0477 --- /dev/null +++ b/bms/bms/cmake/bms_config_e18a/default/CMakeLists.txt @@ -0,0 +1,23 @@ + +# This CMakeLists.txt is generated. +# Do not modify directly. +# If you want to customize cmake behavior create a user.cmake in this +# directory and add it to your version control system. + +# format v1.00 +# { + +cmake_minimum_required(VERSION 3.24.0) +set(CMAKE_SYSTEM_NAME "Generic") + +project(bms_config_e18a_default_project LANGUAGES C CXX ASM) + +include("${CMAKE_CURRENT_LIST_DIR}/.generated/main.cmake") + +if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/user.cmake) + include(user.cmake) +endif() + + +# } + diff --git a/bms/bms/cmake/bms_config_e18a/default/CMakePresets.json b/bms/bms/cmake/bms_config_e18a/default/CMakePresets.json new file mode 100644 index 00000000..a7f55b22 --- /dev/null +++ b/bms/bms/cmake/bms_config_e18a/default/CMakePresets.json @@ -0,0 +1,21 @@ +{ + "version": 6, + "configurePresets": [ + { + "name": "bms_config_e18a_default_conf", + "binaryDir": "${fileDir}/../../../_build/bms_config_e18a/default", + "generator": "Ninja", + "toolchainFile": "${fileDir}/.generated/toolchain.cmake", + "cacheVariables": { + "CMAKE_USER_MAKE_RULES_OVERRIDE": { + "type": "FILEPATH", + "value": "${fileDir}/.generated/overrides.cmake" + }, + "CMAKE_EXPORT_COMPILE_COMMANDS": { + "type": "BOOL", + "value": "ON" + } + } + } + ] +} \ No newline at end of file From 62db7251306fce57a29ec53f9a20600858ce78ec Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 12 Mar 2026 11:46:30 +0100 Subject: [PATCH 29/30] feat: remove config for e18a --- .../components/adc0.yml | 237 - .../components/adc1.yml | 207 - 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a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc0.yml +++ /dev/null @@ -1,237 +0,0 @@ -configVersion: 1.0.0 -componentName: adc0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: adc0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: adc0 - x: '30' - y: '216' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - ADC_CALLBACK_API: - attributes: - id: ADC_CALLBACK_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_CallbackRegister - type: Dynamic - type: Values - type: String - ADC_CHANNEL_SELECT_API: - attributes: - id: ADC_CHANNEL_SELECT_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ChannelSelect - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_U: - attributes: - id: ADC_CH_PHASE_U - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN2 - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_V: - attributes: - id: ADC_CH_PHASE_V - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN5 - type: Dynamic - type: Values - type: String - ADC_CH_POT: - attributes: - id: ADC_CH_POT - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_CH_VDC_BUS: - attributes: - id: ADC_CH_VDC_BUS - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_GET_RESULT_API: - attributes: - id: ADC_GET_RESULT_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ConversionResultGet - type: Dynamic - type: Values - type: String - ADC_GND: - attributes: - id: ADC_GND - children: - - children: - - attributes: - id: adc0 - value: ADC_NEGINPUT_GND - type: Dynamic - type: Values - type: String - ADC_INT_CLEAR_API: - attributes: - id: ADC_INT_CLEAR_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_InterruptsClear - type: Dynamic - type: Values - type: String - ADC_INT_DISABLE_API: - attributes: - id: ADC_INT_DISABLE_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_InterruptsDisable - type: Dynamic - type: Values - type: String - ADC_INT_ENABLE_API: - attributes: - id: ADC_INT_ENABLE_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_InterruptsEnable - type: Dynamic - type: Values - type: String - ADC_IS_RESULT_READY_API: - attributes: - id: ADC_IS_RESULT_READY_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ConversionStatusGet - type: Dynamic - type: Values - type: String - ADC_START_API: - attributes: - id: ADC_START_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_Enable - type: Dynamic - type: Values - type: String - ADC_START_CONV_API: - attributes: - id: ADC_START_CONV_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ConversionStart - type: Dynamic - type: Values - type: String - ADC_STOP_API: - attributes: - id: ADC_STOP_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_Disable - type: Dynamic - type: Values - type: String - INTERRUPT_ADC_RESULT: - attributes: - id: INTERRUPT_ADC_RESULT - children: - - children: - - attributes: - id: adc0 - value: ADC0_RESRDY_IRQn - type: Dynamic - type: Values - type: String - ADC_CTRLB_PRESCALER: - attributes: - id: ADC_CTRLB_PRESCALER - children: - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - ADC_CTRLC_DIFFMODE: - attributes: - id: ADC_CTRLC_DIFFMODE - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - ADC_CONV_TRIGGER: - attributes: - id: ADC_CONV_TRIGGER - children: - - children: - - attributes: - value: SW Trigger - type: User - type: Values - type: Combo - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc1.yml deleted file mode 100644 index b9ebd9ab..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/adc1.yml +++ /dev/null @@ -1,207 +0,0 @@ -configVersion: 1.0.0 -componentName: adc1 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: adc1 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: adc1 - x: '30' - y: '148' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - ADC_CALLBACK_API: - attributes: - id: ADC_CALLBACK_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_CallbackRegister - type: Dynamic - type: Values - type: String - ADC_CHANNEL_SELECT_API: - attributes: - id: ADC_CHANNEL_SELECT_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ChannelSelect - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_U: - attributes: - id: ADC_CH_PHASE_U - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN2 - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_V: - attributes: - id: ADC_CH_PHASE_V - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN5 - type: Dynamic - type: Values - type: String - ADC_CH_POT: - attributes: - id: ADC_CH_POT - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_CH_VDC_BUS: - attributes: - id: ADC_CH_VDC_BUS - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_GET_RESULT_API: - attributes: - id: ADC_GET_RESULT_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ConversionResultGet - type: Dynamic - type: Values - type: String - ADC_GND: - attributes: - id: ADC_GND - children: - - children: - - attributes: - id: adc1 - value: ADC_NEGINPUT_GND - type: Dynamic - type: Values - type: String - ADC_INT_CLEAR_API: - attributes: - id: ADC_INT_CLEAR_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_InterruptsClear - type: Dynamic - type: Values - type: String - ADC_INT_DISABLE_API: - attributes: - id: ADC_INT_DISABLE_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_InterruptsDisable - type: Dynamic - type: Values - type: String - ADC_INT_ENABLE_API: - attributes: - id: ADC_INT_ENABLE_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_InterruptsEnable - type: Dynamic - type: Values - type: String - ADC_IS_RESULT_READY_API: - attributes: - id: ADC_IS_RESULT_READY_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ConversionStatusGet - type: Dynamic - type: Values - type: String - ADC_START_API: - attributes: - id: ADC_START_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_Enable - type: Dynamic - type: Values - type: String - ADC_START_CONV_API: - attributes: - id: ADC_START_CONV_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ConversionStart - type: Dynamic - type: Values - type: String - ADC_STOP_API: - attributes: - id: ADC_STOP_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_Disable - type: Dynamic - type: Values - type: String - INTERRUPT_ADC_RESULT: - attributes: - id: INTERRUPT_ADC_RESULT - children: - - children: - - attributes: - id: adc1 - value: ADC1_RESRDY_IRQn - type: Dynamic - type: Values - type: String - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/can0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/can0.yml deleted file mode 100644 index 0b56dbc6..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/can0.yml +++ /dev/null @@ -1,526 +0,0 @@ -configVersion: 1.0.0 -componentName: can0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: can0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: can0 - x: '196' - y: '220' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - NBTP_NBRP: - attributes: - id: NBTP_NBRP - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '2' - type: Dynamic - - attributes: - value: '3' - type: User - type: Values - type: Integer - NOMINAL_SAMPLE_POINT: - attributes: - id: NOMINAL_SAMPLE_POINT - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '96.875' - type: Dynamic - - attributes: - value: '75.0' - type: User - type: Values - type: Float - NBTP_TOTAL_TIME_QUANTA: - attributes: - id: NBTP_TOTAL_TIME_QUANTA - children: - - children: - - attributes: - id: can0 - value: '24' - type: Dynamic - type: Values - type: Integer - NBTP_NTSEG1: - attributes: - id: NBTP_NTSEG1 - children: - - children: - - attributes: - id: can0 - value: '17' - type: Dynamic - type: Values - type: Integer - NBTP_NTSEG2: - attributes: - id: NBTP_NTSEG2 - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - type: Values - type: Integer - NBTP_NSJW: - attributes: - id: NBTP_NSJW - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - - attributes: - value: '5' - type: User - type: Values - type: Integer - CALCULATED_NOMINAL_BITRATE: - attributes: - id: CALCULATED_NOMINAL_BITRATE - children: - - children: - - attributes: - id: can0 - value: '500' - type: Dynamic - type: Values - type: Integer - NOMINAL_TIME_QUANTA_PERIOD: - attributes: - id: NOMINAL_TIME_QUANTA_PERIOD - children: - - children: - - attributes: - id: can0 - value: '83.333' - type: Dynamic - type: Values - type: String - CALCULATED_NOMINAL_ERRORRATE: - attributes: - id: CALCULATED_NOMINAL_ERRORRATE - children: - - children: - - attributes: - id: can0 - value: '0.000' - type: Dynamic - type: Values - type: String - AUTO_NOMINAL_BIT_TIMING_CALCULATION: - attributes: - id: AUTO_NOMINAL_BIT_TIMING_CALCULATION - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - DBTP_TOTAL_TIME_QUANTA: - attributes: - id: DBTP_TOTAL_TIME_QUANTA - children: - - children: - - attributes: - id: can0 - value: '24' - type: Dynamic - type: Values - type: Integer - DBTP_DTSEG1: - attributes: - id: DBTP_DTSEG1 - children: - - children: - - attributes: - id: can0 - value: '17' - type: Dynamic - type: Values - type: Integer - DBTP_DTSEG2: - attributes: - id: DBTP_DTSEG2 - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - type: Values - type: Integer - DBTP_DSJW: - attributes: - id: DBTP_DSJW - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - - attributes: - value: '5' - type: User - type: Values - type: Integer - CALCULATED_DATA_BITRATE: - attributes: - id: CALCULATED_DATA_BITRATE - children: - - children: - - attributes: - id: can0 - value: '2000' - type: Dynamic - type: Values - type: Integer - DATA_TIME_QUANTA_PERIOD: - attributes: - id: DATA_TIME_QUANTA_PERIOD - children: - - children: - - attributes: - id: can0 - value: '20.833' - type: Dynamic - type: Values - type: String - CALCULATED_DATA_ERRORRATE: - attributes: - id: CALCULATED_DATA_ERRORRATE - children: - - children: - - attributes: - id: can0 - value: '0.000' - type: Dynamic - type: Values - type: String - CAN_OPMODE: - attributes: - id: CAN_OPMODE - children: - - children: - - attributes: - value: CAN FD - type: User - type: Values - type: Combo - instHeaderFile: - attributes: - id: instHeaderFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_legacy.h.ftl - type: String - type: Attributes - type: File - sourceFile: - attributes: - id: sourceFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_legacy.c.ftl - type: String - type: Attributes - type: File - INTERRUPT_MODE: - attributes: - id: INTERRUPT_MODE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - DBTP_DBRP: - attributes: - id: DBTP_DBRP - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '2' - type: Dynamic - - attributes: - value: '0' - type: User - type: Values - type: Integer - DATA_SAMPLE_POINT: - attributes: - id: DATA_SAMPLE_POINT - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '87.5' - type: Dynamic - - attributes: - value: '75.0' - type: User - type: Values - type: Float - AUTO_DATA_BIT_TIMING_CALCULATION: - attributes: - id: AUTO_DATA_BIT_TIMING_CALCULATION - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - DATA_BITRATE: - attributes: - id: DATA_BITRATE - children: - - children: - - attributes: - value: '2000' - type: User - type: Values - type: Integer - NOMINAL_BITRATE: - attributes: - id: NOMINAL_BITRATE - children: - - children: - - attributes: - value: '500' - type: User - type: Values - type: Integer - headerFile: - attributes: - id: headerFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_common_legacy.h - type: String - type: Attributes - type: File - CAN_GENERATE_LEGACY_APIS: - attributes: - id: CAN_GENERATE_LEGACY_APIS - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RXF0_WATERMARK: - attributes: - id: RXF0_WATERMARK - children: - - children: - - attributes: - id: can0 - value: '0' - type: Dynamic - type: Values - type: Integer - RXF0_ELEMENTS: - attributes: - id: RXF0_ELEMENTS - children: - - children: - - attributes: - value: '8' - type: User - type: Values - type: Integer - RXF0_BYTES_CFG: - attributes: - id: RXF0_BYTES_CFG - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '7' - type: User - type: Values - type: KeyValueSet - RXF1_USE: - attributes: - id: RXF1_USE - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - RXBUF_USE: - attributes: - id: RXBUF_USE - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - TX_FIFO_WATERMARK: - attributes: - id: TX_FIFO_WATERMARK - children: - - children: - - attributes: - id: can0 - value: '0' - type: Dynamic - type: Values - type: Integer - TX_FIFO_ELEMENTS: - attributes: - id: TX_FIFO_ELEMENTS - children: - - children: - - attributes: - value: '8' - type: User - type: Values - type: Integer - TX_FIFO_BYTES_CFG: - attributes: - id: TX_FIFO_BYTES_CFG - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '7' - type: User - type: Values - type: KeyValueSet - FILTERS_STD_NOMATCH: - attributes: - id: FILTERS_STD_NOMATCH - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - FILTERS_EXT_NOMATCH: - attributes: - id: FILTERS_EXT_NOMATCH - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - TIMESTAMP_ENABLE: - attributes: - id: TIMESTAMP_ENABLE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RXF0_OVERWRITE: - attributes: - id: RXF0_OVERWRITE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/cmsis.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/cmsis.yml deleted file mode 100644 index f9f85905..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/cmsis.yml +++ /dev/null @@ -1,24 +0,0 @@ -configVersion: 1.0.0 -componentName: cmsis -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: cmsis - type: module - version: '' -- dependencyPackage: '' - name: CMSIS_5 - type: package - version: 5.9.1-dev -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: {} - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/core.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/core.yml deleted file mode 100644 index d6debb74..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/core.yml +++ /dev/null @@ -1,2640 +0,0 @@ -configVersion: 1.0.0 -componentName: core -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: core - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: core - x: '80' - y: '4' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - ADC0_CLOCK_ENABLE: - attributes: - id: ADC0_CLOCK_ENABLE - children: - - children: - - attributes: - id: adc0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - ADC0_CLOCK_FREQUENCY: - attributes: - id: ADC0_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - CAN0_CLOCK_ENABLE: - attributes: - id: CAN0_CLOCK_ENABLE - children: - - children: - - attributes: - id: can0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_CLOCK_FREQUENCY: - attributes: - id: CAN0_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_22_CHEN: - attributes: - id: GCLK_ID_22_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_22_FREQ: - attributes: - id: GCLK_ID_22_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_25_CHEN: - attributes: - id: GCLK_ID_25_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_25_FREQ: - attributes: - id: GCLK_ID_25_FREQ - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_26_CHEN: - attributes: - id: GCLK_ID_26_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_26_FREQ: - attributes: - id: GCLK_ID_26_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_33_CHEN: - attributes: - id: GCLK_ID_33_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_33_FREQ: - attributes: - id: GCLK_ID_33_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - MCLK_AHB_INITIAL_VALUE: - attributes: - id: MCLK_AHB_INITIAL_VALUE - children: - - children: - - attributes: - id: core - value: '0x1dff' - type: Dynamic - type: Values - type: String - MCLK_APBC_INITIAL_VALUE: - attributes: - id: MCLK_APBC_INITIAL_VALUE - children: - - children: - - attributes: - id: core - value: '0x60036' - type: Dynamic - type: Values - type: String - NVIC_12_0_ENABLE: - attributes: - id: NVIC_12_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_12_0_HANDLER: - attributes: - id: NVIC_12_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM3_Handler - type: Dynamic - type: Values - type: String - NVIC_12_0_HANDLER_LOCK: - attributes: - id: NVIC_12_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_14_0_ENABLE: - attributes: - id: NVIC_14_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_14_0_HANDLER: - attributes: - id: NVIC_14_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM5_Handler - type: Dynamic - type: Values - type: String - NVIC_14_0_HANDLER_LOCK: - attributes: - id: NVIC_14_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM3_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM3_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - SERCOM3_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM3_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM5_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM5_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - SERCOM5_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM5_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - ADC1_CLOCK_FREQUENCY: - attributes: - id: ADC1_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_34_FREQ: - attributes: - id: GCLK_ID_34_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_34_CHEN: - attributes: - id: GCLK_ID_34_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - ADC1_CLOCK_ENABLE: - attributes: - id: ADC1_CLOCK_ENABLE - children: - - children: - - attributes: - id: adc1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN1_CLOCK_FREQUENCY: - attributes: - id: CAN1_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_27_FREQ: - attributes: - id: GCLK_ID_27_FREQ - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_27_CHEN: - attributes: - id: GCLK_ID_27_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM1_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_20_FREQ: - attributes: - id: GCLK_ID_20_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_20_CHEN: - attributes: - id: GCLK_ID_20_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM1_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_10_0_ENABLE: - attributes: - id: NVIC_10_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_10_0_HANDLER_LOCK: - attributes: - id: NVIC_10_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_10_0_HANDLER: - attributes: - id: NVIC_10_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM1_I2C_InterruptHandler - type: Dynamic - type: Values - type: String - CAN1_INTERRUPT_ENABLE_UPDATE: - attributes: - id: CAN1_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_16_0_ENABLE: - attributes: - id: NVIC_16_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - NVIC_16_0_HANDLER: - attributes: - id: NVIC_16_0_HANDLER - children: - - children: - - attributes: - id: core - value: CAN1_Handler - type: Dynamic - type: Values - type: String - NVIC_16_0_HANDLER_LOCK: - attributes: - id: NVIC_16_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_INTERRUPT_ENABLE_UPDATE: - attributes: - id: CAN0_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_15_0_ENABLE: - attributes: - id: NVIC_15_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_INTERRUPT_ENABLE: - attributes: - id: CAN0_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: can0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_15_0_HANDLER: - attributes: - id: NVIC_15_0_HANDLER - children: - - children: - - attributes: - id: core - value: CAN0_InterruptHandler - type: Dynamic - type: Values - type: String - CAN0_INTERRUPT_HANDLER: - attributes: - id: CAN0_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: can0 - value: CAN0_InterruptHandler - type: Dynamic - type: Values - type: String - NVIC_15_0_HANDLER_LOCK: - attributes: - id: NVIC_15_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_INTERRUPT_HANDLER_LOCK: - attributes: - id: CAN0_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: can0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM4_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_23_FREQ: - attributes: - id: GCLK_ID_23_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_23_CHEN: - attributes: - id: GCLK_ID_23_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM4_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM4_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_13_0_ENABLE: - attributes: - id: NVIC_13_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_INTERRUPT_ENABLE: - attributes: - id: SERCOM4_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_13_0_HANDLER_LOCK: - attributes: - id: NVIC_13_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM4_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_13_0_HANDLER: - attributes: - id: NVIC_13_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM4_Handler - type: Dynamic - type: Values - type: String - SERCOM4_INTERRUPT_HANDLER: - attributes: - id: SERCOM4_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom4 - value: SERCOM4_Handler - type: Dynamic - type: Values - type: String - SERCOM1_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM1_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_ENABLE: - attributes: - id: SERCOM1_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM1_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_HANDLER: - attributes: - id: SERCOM1_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom1 - value: SERCOM1_I2C_InterruptHandler - type: Dynamic - type: Values - type: String - SERCOM0_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM0_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_19_FREQ: - attributes: - id: GCLK_ID_19_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_19_CHEN: - attributes: - id: GCLK_ID_19_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM0_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM0_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_9_0_ENABLE: - attributes: - id: NVIC_9_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_INTERRUPT_ENABLE: - attributes: - id: SERCOM0_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_9_0_HANDLER_LOCK: - attributes: - id: NVIC_9_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM0_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_9_0_HANDLER: - attributes: - id: NVIC_9_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM0_SPI_InterruptHandler - type: Dynamic - type: Values - type: String - SERCOM0_INTERRUPT_HANDLER: - attributes: - id: SERCOM0_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom0 - value: SERCOM0_SPI_InterruptHandler - type: Dynamic - type: Values - type: String - PORT_GROUP_1_DIR: - attributes: - id: PORT_GROUP_1_DIR - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_OUT: - attributes: - id: PORT_GROUP_1_OUT - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PINCFG8: - attributes: - id: PORT_GROUP_1_PINCFG8 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_8_USED: - attributes: - id: PORT_GROUP_1_PIN_8_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_1_PMUX4: - attributes: - id: PORT_GROUP_1_PMUX4 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PAD_8: - attributes: - id: PORT_GROUP_1_PAD_8 - children: - - children: - - attributes: - id: core - value: PB08 - type: Dynamic - type: Values - type: String - PIN_11_PERIPHERAL_FUNCTION: - attributes: - id: PIN_11_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PINCFG5: - attributes: - id: PORT_GROUP_1_PINCFG5 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_5_USED: - attributes: - id: PORT_GROUP_1_PIN_5_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_1_PMUX2: - attributes: - id: PORT_GROUP_1_PMUX2 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PAD_5: - attributes: - id: PORT_GROUP_1_PAD_5 - children: - - children: - - attributes: - id: core - value: PB05 - type: Dynamic - type: Values - type: String - PIN_6_PERIPHERAL_FUNCTION: - attributes: - id: PIN_6_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_0_DIR: - attributes: - id: PORT_GROUP_0_DIR - children: - - children: - - attributes: - id: core - value: '0x100c8080' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_OUT: - attributes: - id: PORT_GROUP_0_OUT - children: - - children: - - attributes: - id: core - value: '0x80' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG1: - attributes: - id: PORT_GROUP_0_PINCFG1 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_1_USED: - attributes: - id: PORT_GROUP_0_PIN_1_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX0: - attributes: - id: PORT_GROUP_0_PMUX0 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_1: - attributes: - id: PORT_GROUP_0_PAD_1 - children: - - children: - - attributes: - id: core - value: PA01 - type: Dynamic - type: Values - type: String - PIN_2_PERIPHERAL_FUNCTION: - attributes: - id: PIN_2_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG0: - attributes: - id: PORT_GROUP_0_PINCFG0 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_0_USED: - attributes: - id: PORT_GROUP_0_PIN_0_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PAD_0: - attributes: - id: PORT_GROUP_0_PAD_0 - children: - - children: - - attributes: - id: core - value: PA00 - type: Dynamic - type: Values - type: String - PIN_1_PERIPHERAL_FUNCTION: - attributes: - id: PIN_1_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PINCFG9: - attributes: - id: PORT_GROUP_1_PINCFG9 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_9_USED: - attributes: - id: PORT_GROUP_1_PIN_9_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PINCFG3: - attributes: - id: PORT_GROUP_0_PINCFG3 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_3_USED: - attributes: - id: PORT_GROUP_0_PIN_3_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX1: - attributes: - id: PORT_GROUP_0_PMUX1 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_3: - attributes: - id: PORT_GROUP_0_PAD_3 - children: - - children: - - attributes: - id: core - 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PIN_46_PERIPHERAL_FUNCTION: - attributes: - id: PIN_46_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - RTC_INTERRUPT_ENABLE_UPDATE: - attributes: - id: RTC_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_ENABLE: - attributes: - id: NVIC_2_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - RTC_INTERRUPT_ENABLE: - attributes: - id: RTC_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: rtc - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_HANDLER_LOCK: - attributes: - id: NVIC_2_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - RTC_INTERRUPT_HANDLER_LOCK: - attributes: - id: RTC_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: rtc - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_HANDLER: - attributes: - id: NVIC_2_0_HANDLER - children: - - children: - - attributes: - id: core - value: RTC_InterruptHandler - type: Dynamic - type: Values - type: String - RTC_INTERRUPT_HANDLER: - attributes: - id: RTC_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: rtc - value: RTC_InterruptHandler - type: Dynamic - type: Values - type: String - MCLK_APBA_INITIAL_VALUE: - attributes: - id: MCLK_APBA_INITIAL_VALUE - children: - - children: - - attributes: - id: core - value: '0xfff' - type: Dynamic - type: Values - type: String - EIC_CLOCK_FREQUENCY: - attributes: - id: EIC_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_2_FREQ: - attributes: - id: GCLK_ID_2_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_2_CHEN: - attributes: - id: GCLK_ID_2_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - EIC_CLOCK_ENABLE: - attributes: - id: EIC_CLOCK_ENABLE - children: - - children: - - attributes: - id: eic - value: 'true' - type: Dynamic - type: Values - type: Boolean - EIC_INTERRUPT_ENABLE_UPDATE: - attributes: - id: EIC_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_3_0_ENABLE: - attributes: - id: NVIC_3_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - EIC_INTERRUPT_ENABLE: - attributes: - id: EIC_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: eic - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_3_0_HANDLER_LOCK: - attributes: - id: NVIC_3_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - EIC_INTERRUPT_HANDLER_LOCK: - attributes: - id: EIC_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: eic - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_3_0_HANDLER: - attributes: - id: NVIC_3_0_HANDLER - children: - - children: - - attributes: - id: core - value: EIC_InterruptHandler - type: Dynamic - type: Values - type: String - EIC_INTERRUPT_HANDLER: - attributes: - id: EIC_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: eic - value: EIC_InterruptHandler - type: Dynamic - type: Values - type: String - userData: - children: - - attributes: - canvasHeight: '0' - canvasWidth: '0' - type: GraphSettings - - children: - - attributes: - id: profile0 - name: Main - type: Profile - type: PowerProfiles - type: UserData diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/dfp.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/dfp.yml deleted file mode 100644 index 5feb0638..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/dfp.yml +++ /dev/null @@ -1,31 +0,0 @@ -configVersion: 1.0.0 -componentName: dfp -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: dfp - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: dfp - x: '520' - y: '11' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/eic.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/eic.yml deleted file mode 100644 index 78428423..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/eic.yml +++ /dev/null @@ -1,112 +0,0 @@ -configVersion: 1.0.0 -componentName: eic -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: eic - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: eic - x: '214' - y: '141' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - EIC_ASYNCH: - attributes: - id: EIC_ASYNCH - children: - - children: - - attributes: - id: eic - value: '0' - type: Dynamic - type: Values - type: Hex - EIC_CHAN_14: - attributes: - id: EIC_CHAN_14 - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - EIC_CONFIG_FILTEN_14: - attributes: - id: EIC_CONFIG_FILTEN_14 - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - EIC_CONFIG_SENSE_14: - attributes: - id: EIC_CONFIG_SENSE_14 - children: - - children: - - attributes: - value: '3' - type: User - type: Values - type: KeyValueSet - EIC_EXTINTEO: - attributes: - id: EIC_EXTINTEO - children: - - children: - - attributes: - id: eic - value: '0' - type: Dynamic - type: Values - type: Hex - EIC_INT: - attributes: - id: EIC_INT - children: - - children: - - attributes: - id: eic - value: '16384' - type: Dynamic - type: Values - type: Hex - EIC_INT_14: - attributes: - id: EIC_INT_14 - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/evsys.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/evsys.yml deleted file mode 100644 index 0a0d68b7..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/evsys.yml +++ /dev/null @@ -1,174 +0,0 @@ -configVersion: 1.0.0 -componentName: evsys -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: evsys - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: evsys - x: '202' - y: '10' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - EVSYS_CHANNEL_8_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_8_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_2_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_2_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_3_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_3_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_7_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_7_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_9_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_9_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_6_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_6_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_5_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_5_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_1_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_1_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_4_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_4_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_10_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_10_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_0_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_0_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - EVSYS_CHANNEL_11_GENERATOR_ACTIVE: - attributes: - id: EVSYS_CHANNEL_11_GENERATOR_ACTIVE - children: - - children: - - attributes: - id: evsys - value: 'false' - type: Dynamic - type: Values - type: Boolean - GENERATOR_EIC_EXTINT_14_ACTIVE: - attributes: - id: GENERATOR_EIC_EXTINT_14_ACTIVE - children: - - children: - - attributes: - id: eic - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/nvmctrl.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/nvmctrl.yml deleted file mode 100644 index 1079fff4..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/nvmctrl.yml +++ /dev/null @@ -1,31 +0,0 @@ -configVersion: 1.0.0 -componentName: nvmctrl -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: nvmctrl - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: nvmctrl - x: '339' - y: '7' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/rtc.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/rtc.yml deleted file mode 100644 index 6b2747f8..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/rtc.yml +++ /dev/null @@ -1,51 +0,0 @@ -configVersion: 1.0.0 -componentName: rtc -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: rtc - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: rtc - x: '496' - y: '340' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - RTC_MODE0_MATCHCLR: - attributes: - id: RTC_MODE0_MATCHCLR - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RTC_MODE0_TIMER_COMPARE: - attributes: - id: RTC_MODE0_TIMER_COMPARE - children: - - children: - - attributes: - value: '101' - type: User - type: Values - type: Hex - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom0.yml deleted file mode 100644 index 018fb294..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom0.yml +++ /dev/null @@ -1,340 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom0 - x: '538' - y: '152' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom0 - value: '232' - type: Dynamic - type: Values - type: Hex - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom0 - value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - SERCOM_SPIM_COMMON_HEADER: - attributes: - id: SERCOM_SPIM_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_HEADER: - attributes: - id: SERCOM_SPIM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_SOURCE: - attributes: - id: SERCOM_SPIM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_7816_HEADER: - attributes: - id: SERCOM_USART_7816_HEADER - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_7816_SOURCE: - attributes: - id: SERCOM_USART_7816_SOURCE - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '23' - type: Dynamic - type: Values - type: Integer - SPI_CLOCK_PHASE: - attributes: - id: SPI_CLOCK_PHASE - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - SPI_DIPO: - attributes: - id: SPI_DIPO - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom0 - value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - USART_7816_BAUD_VALUE: - attributes: - id: USART_7816_BAUD_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '14' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_DATA_BITS: - attributes: - id: USART_DATA_BITS - children: - - children: - - attributes: - id: sercom0 - value: DRV_USART_DATA_8_BIT - type: Dynamic - type: Values - type: String - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom0 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom0 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom0 - value: 'false' - type: Dynamic - type: Values - type: Boolean - SPI_DOPO: - attributes: - id: SPI_DOPO - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '3' - type: User - type: Values - type: KeyValueSet - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom1.yml deleted file mode 100644 index 342a2f30..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom1.yml +++ /dev/null @@ -1,308 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom1 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom1 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom1 - x: '368' - y: '153' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom1 - value: '232' - type: Dynamic - type: Values - type: Hex - I2C_CLOCK_SPEED_HZ: - attributes: - id: I2C_CLOCK_SPEED_HZ - children: - - children: - - attributes: - id: sercom1 - value: '100000' - type: Dynamic - type: Values - type: Integer - I2C_SCLSM: - attributes: - id: I2C_SCLSM - children: - - children: - - attributes: - id: sercom1 - value: '0' - type: Dynamic - type: Values - type: Integer - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom1 - value: '' - type: Dynamic - type: Values - type: String - SERCOM_I2CM_HEADER: - attributes: - id: SERCOM_I2CM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_I2CM_MASTER_HEADER: - attributes: - id: SERCOM_I2CM_MASTER_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_I2CM_SOURCE: - attributes: - id: SERCOM_I2CM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - value: '2' - type: User - type: Values - type: KeyValueSet - SERCOM_USART_7816_HEADER: - attributes: - id: SERCOM_USART_7816_HEADER - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_7816_SOURCE: - attributes: - id: SERCOM_USART_7816_SOURCE - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '23' - type: Dynamic - type: Values - type: Integer - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom1 - value: '' - type: Dynamic - type: Values - type: String - USART_7816_BAUD_VALUE: - attributes: - id: USART_7816_BAUD_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '14' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_DATA_BITS: - attributes: - id: USART_DATA_BITS - children: - - children: - - attributes: - id: sercom1 - value: DRV_USART_DATA_8_BIT - type: Dynamic - type: Values - type: String - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom1 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom1 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom1 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom4.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom4.yml deleted file mode 100644 index a1b862a5..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/sercom4.yml +++ /dev/null @@ -1,275 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom4 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom4 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: - children: - - children: - - attributes: - id: SERCOM4_I2C - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: DirectCapability - - attributes: - id: SERCOM4_SPI - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: DirectCapability - - attributes: - id: SERCOM4_UART - children: - - children: - - attributes: - id: targetComponentID - children: - - type: Value - value: stdio - type: String - - attributes: - id: targetAttachmentID - children: - - type: Value - value: UART - type: String - type: Attributes - type: DirectCapability - type: Attachments - type: sercom4 - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom4 - x: '67' - y: '340' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom4 - value: '232' - type: Dynamic - type: Values - type: Hex - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom4 - value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - id: sercom4 - value: '0' - type: Dynamic - type: Values - type: KeyValueSet - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom4 - value: '23' - type: Dynamic - type: Values - type: Integer - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom4 - value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom4 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_OPERATING_MODE: - attributes: - id: USART_OPERATING_MODE - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - id: sercom4 - value: '0' - type: Dynamic - type: Values - type: KeyValueSet - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom4 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom4 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom4 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/stdio.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/stdio.yml deleted file mode 100644 index 5f8be0f2..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/components/stdio.yml +++ /dev/null @@ -1,64 +0,0 @@ -configVersion: 1.0.0 -componentName: stdio -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: stdio - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: - children: - - children: - - attributes: - id: UART - children: - - children: - - attributes: - id: targetComponentID - children: - - type: Value - value: sercom4 - type: String - - attributes: - id: targetAttachmentID - children: - - type: Value - value: SERCOM4_UART - type: String - type: Attributes - type: DirectDependency - type: Attachments - type: stdio - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: stdio - x: '307' - y: '339' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - DEBUG_PERIPHERAL: - attributes: - id: DEBUG_PERIPHERAL - children: - - children: - - attributes: - id: stdio - value: sercom4 - type: Dynamic - type: Values - type: String - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/mcc-config.mc4 b/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/mcc-config.mc4 deleted file mode 100644 index d350f268..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default.bak0/mcc-config.mc4 +++ /dev/null @@ -1,292 +0,0 @@ -configVersion: 1.0.0 -coreVersion: 5.8.4 -spaHostVersion: 1.2.1 -device: ATSAMC21E18A -deviceLibrary: {} -groupModules: [] -modules: -- adc0 -- adc1 -- can0 -- cmsis -- core -- dfp -- eic -- evsys -- nvmctrl -- rtc -- sercom0 -- sercom1 -- sercom4 -- stdio -generatedFileHashHistoryMap: -- file: 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PORT_GROUP_0_PAD_11 - children: - - children: - - attributes: - id: core - value: PA11 - type: Dynamic - type: Values - type: String - PIN_20_PERIPHERAL_FUNCTION: - attributes: - id: PIN_20_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_20_MODE: - attributes: - id: PIN_20_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_20_FUNCTION_TYPE: - attributes: - id: PIN_20_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_16_LAT: - attributes: - id: PIN_16_LAT - children: - - children: - - attributes: - value: High - type: User - type: Values - type: String - PIN_53_MODE: - attributes: - id: PIN_53_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_53_FUNCTION_TYPE: - attributes: - id: PIN_53_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG28: - attributes: - id: PORT_GROUP_0_PINCFG28 - children: - - children: - - attributes: - id: core - value: '0x2' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_28_USED: - attributes: - id: PORT_GROUP_0_PIN_28_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_53_INEN: - attributes: - id: PIN_53_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_53_DIR: - attributes: - id: PIN_53_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PMUX14: - attributes: - id: PORT_GROUP_0_PMUX14 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_28: - attributes: - id: PORT_GROUP_0_PAD_28 - children: - - children: - - attributes: - id: core - value: PA28 - type: Dynamic - type: Values - type: String - PIN_53_PERIPHERAL_FUNCTION: - attributes: - id: PIN_53_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_53_FUNCTION_NAME: - attributes: - id: PIN_53_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_G - type: User - type: Values - type: String - PIN_53_DRVSTR: - attributes: - id: PIN_53_DRVSTR - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - PIN_38_MODE: - attributes: - id: PIN_38_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_38_FUNCTION_TYPE: - attributes: - id: PIN_38_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG19: - attributes: - id: PORT_GROUP_0_PINCFG19 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_19_USED: - attributes: - id: PORT_GROUP_0_PIN_19_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_38_INEN: - attributes: - id: PIN_38_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_38_DIR: - attributes: - id: PIN_38_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PMUX9: - attributes: - id: PORT_GROUP_0_PMUX9 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_19: - attributes: - id: PORT_GROUP_0_PAD_19 - children: - - children: - - attributes: - id: core - value: PA19 - type: Dynamic - type: Values - type: String - PIN_38_PERIPHERAL_FUNCTION: - attributes: - id: PIN_38_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_38_FUNCTION_NAME: - attributes: - id: PIN_38_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_Y - type: User - type: Values - type: String - PIN_37_MODE: - attributes: - id: PIN_37_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_37_FUNCTION_TYPE: - attributes: - id: PIN_37_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG18: - attributes: - id: PORT_GROUP_0_PINCFG18 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_18_USED: - attributes: - id: PORT_GROUP_0_PIN_18_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_37_INEN: - attributes: - id: PIN_37_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_37_DIR: - attributes: - id: PIN_37_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_18: - attributes: - id: PORT_GROUP_0_PAD_18 - children: - - children: - - attributes: - id: core - value: PA18 - type: Dynamic - type: Values - type: String - PIN_37_PERIPHERAL_FUNCTION: - attributes: - id: PIN_37_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_37_FUNCTION_NAME: - attributes: - id: PIN_37_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_R - type: User - type: Values - type: String - PIN_31_MODE: - attributes: - id: PIN_31_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_31_FUNCTION_TYPE: - attributes: - id: PIN_31_FUNCTION_TYPE - children: - - children: - - attributes: - value: EIC_EXTINT14 - type: User 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type: Dynamic - type: Values - type: String - PIN_31_PERIPHERAL_FUNCTION: - attributes: - id: PIN_31_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: A - type: User - type: Values - type: String - PIN_31_FUNCTION_NAME: - attributes: - id: PIN_31_FUNCTION_NAME - children: - - children: - - attributes: - value: CAN_RX_WAKEUP - type: User - type: Values - type: String - PIN_32_MODE: - attributes: - id: PIN_32_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_32_FUNCTION_TYPE: - attributes: - id: PIN_32_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG15: - attributes: - id: PORT_GROUP_0_PINCFG15 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_15_USED: - attributes: - id: PORT_GROUP_0_PIN_15_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_32_INEN: - attributes: - id: PIN_32_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_32_DIR: - attributes: - id: PIN_32_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_15: - attributes: - id: PORT_GROUP_0_PAD_15 - children: - - children: - - attributes: - id: core - value: PA15 - type: Dynamic - type: Values - type: String - PIN_32_PERIPHERAL_FUNCTION: - attributes: - id: PIN_32_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_32_FUNCTION_NAME: - attributes: - id: PIN_32_FUNCTION_NAME - children: - - children: - - attributes: - value: STB - type: User - type: Values - type: String - PIN_31_PULLEN: - attributes: - id: PIN_31_PULLEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_31_DRVSTR: - attributes: - id: PIN_31_DRVSTR - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - PORT_GROUP_0_PINCFG21: - attributes: - id: PORT_GROUP_0_PINCFG21 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_21_USED: - attributes: - id: PORT_GROUP_0_PIN_21_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX10: - attributes: - id: PORT_GROUP_0_PMUX10 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_21: - attributes: - id: PORT_GROUP_0_PAD_21 - children: - - children: - - attributes: - id: core - value: PA21 - type: Dynamic - type: Values - type: String - PIN_42_PERIPHERAL_FUNCTION: - attributes: - id: PIN_42_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_45_MODE: - attributes: - id: PIN_45_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_45_FUNCTION_TYPE: - attributes: - id: PIN_45_FUNCTION_TYPE - children: - - children: - - attributes: - value: CAN0_TX - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG24: - attributes: - id: PORT_GROUP_0_PINCFG24 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_24_USED: - attributes: - id: PORT_GROUP_0_PIN_24_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX12: - attributes: - id: PORT_GROUP_0_PMUX12 - children: - - children: - - attributes: - id: core - value: '0x66' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_24: - attributes: - id: PORT_GROUP_0_PAD_24 - children: - - children: - - attributes: - id: core - value: PA24 - type: Dynamic - type: Values - type: String - PIN_45_PERIPHERAL_FUNCTION: - attributes: - id: PIN_45_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - PIN_46_MODE: - attributes: - id: PIN_46_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_46_FUNCTION_TYPE: - attributes: - id: PIN_46_FUNCTION_TYPE - children: - - children: - - attributes: - value: CAN0_RX - type: User - type: Values - type: String - PORT_GROUP_0_PAD_25: - attributes: - id: PORT_GROUP_0_PAD_25 - children: - - children: - - attributes: - id: core - value: PA25 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG25: - attributes: - id: PORT_GROUP_0_PINCFG25 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_25_USED: - attributes: - id: PORT_GROUP_0_PIN_25_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_46_PERIPHERAL_FUNCTION: - attributes: - id: PIN_46_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - RTC_INTERRUPT_ENABLE_UPDATE: - attributes: - id: RTC_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'false' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_ENABLE: - attributes: - id: NVIC_2_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - RTC_INTERRUPT_ENABLE: - attributes: - id: RTC_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: rtc - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_HANDLER_LOCK: - attributes: - id: NVIC_2_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - RTC_INTERRUPT_HANDLER_LOCK: - attributes: - id: RTC_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: rtc - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_HANDLER: - attributes: - id: NVIC_2_0_HANDLER - children: - - children: - - attributes: - id: core - value: RTC_InterruptHandler - type: Dynamic - type: Values - type: String - RTC_INTERRUPT_HANDLER: - attributes: - id: RTC_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: rtc - value: RTC_InterruptHandler - type: Dynamic - type: Values - type: String - MCLK_APBA_INITIAL_VALUE: - attributes: - id: MCLK_APBA_INITIAL_VALUE - children: - - children: - - attributes: - id: core - value: '0xfff' - type: Dynamic - type: Values - type: String - EIC_CLOCK_FREQUENCY: - attributes: - id: EIC_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_2_FREQ: - attributes: - id: GCLK_ID_2_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_2_CHEN: - attributes: - id: GCLK_ID_2_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - EIC_CLOCK_ENABLE: - attributes: - id: EIC_CLOCK_ENABLE - children: - - children: - - attributes: - id: eic - value: 'true' - type: Dynamic - type: Values - type: Boolean - EIC_INTERRUPT_ENABLE_UPDATE: - attributes: - id: EIC_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_3_0_ENABLE: - attributes: - id: NVIC_3_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'false' - type: Dynamic - type: Values - type: Boolean - EIC_INTERRUPT_ENABLE: - attributes: - id: EIC_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: eic - value: 'false' - type: Dynamic - type: Values - type: Boolean - NVIC_3_0_HANDLER_LOCK: - attributes: - id: NVIC_3_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'false' - type: Dynamic - type: Values - type: Boolean - EIC_INTERRUPT_HANDLER_LOCK: - attributes: - id: EIC_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: eic - value: 'false' - type: Dynamic - type: Values - type: Boolean - NVIC_3_0_HANDLER: - attributes: - id: NVIC_3_0_HANDLER - children: - - children: - - attributes: - id: core - value: EIC_Handler - type: Dynamic - type: Values - type: String - EIC_INTERRUPT_HANDLER: - attributes: - id: EIC_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: eic - value: EIC_Handler - type: Dynamic - type: Values - type: String - SERCOM3_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM3_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom3 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM3_INTERRUPT_ENABLE: - attributes: - id: SERCOM3_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom3 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM3_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM3_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom3 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM3_INTERRUPT_HANDLER: - attributes: - id: SERCOM3_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom3 - value: SERCOM3_USART_InterruptHandler - type: Dynamic - type: Values - type: String - SERCOM2_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM2_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_21_FREQ: - attributes: - id: GCLK_ID_21_FREQ - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_21_CHEN: - attributes: - id: GCLK_ID_21_CHEN - children: - - children: - - attributes: - id: core - value: 'false' - type: Dynamic - type: Values - type: Boolean - SERCOM2_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM2_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_11_0_ENABLE: - attributes: - id: NVIC_11_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'false' - type: Dynamic - type: Values - type: Boolean - NVIC_11_0_HANDLER_LOCK: - attributes: - id: NVIC_11_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'false' - type: Dynamic - type: Values - type: Boolean - NVIC_11_0_HANDLER: - attributes: - id: NVIC_11_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM2_Handler - type: Dynamic - type: Values - type: String - PIN_13_PERIPHERAL_FUNCTION: - attributes: - id: PIN_13_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_4_MODE: - attributes: - id: PIN_4_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_4_FUNCTION_TYPE: - attributes: - id: PIN_4_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_4_INEN: - attributes: - id: PIN_4_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_4_DIR: - attributes: - id: PIN_4_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PIN_4_FUNCTION_NAME: - attributes: - id: PIN_4_FUNCTION_NAME - children: - - children: - - attributes: - value: RST_SHUT - type: User - type: Values - type: String - PIN_5_MODE: - attributes: - id: PIN_5_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_5_FUNCTION_TYPE: - attributes: - id: PIN_5_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG4: - attributes: - id: PORT_GROUP_0_PINCFG4 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_4_USED: - attributes: - id: PORT_GROUP_0_PIN_4_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_5_INEN: - attributes: - id: PIN_5_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_5_DIR: - attributes: - id: PIN_5_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PMUX2: - attributes: - id: PORT_GROUP_0_PMUX2 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_4: - attributes: - id: PORT_GROUP_0_PAD_4 - children: - - children: - - attributes: - id: core - value: PA04 - type: Dynamic - type: Values - type: String - PIN_5_PERIPHERAL_FUNCTION: - attributes: - id: PIN_5_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_5_FUNCTION_NAME: - attributes: - id: PIN_5_FUNCTION_NAME - children: - - children: - - attributes: - value: DDSG - type: User - type: Values - type: String - PIN_6_MODE: - attributes: - id: PIN_6_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_6_FUNCTION_TYPE: - attributes: - id: PIN_6_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG5: - attributes: - id: PORT_GROUP_0_PINCFG5 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_5_USED: - attributes: - id: PORT_GROUP_0_PIN_5_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_6_INEN: - attributes: - id: PIN_6_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_6_DIR: - attributes: - id: PIN_6_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_5: - attributes: - id: PORT_GROUP_0_PAD_5 - children: - - children: - - attributes: - id: core - value: PA05 - type: Dynamic - type: Values - type: String - PIN_6_FUNCTION_NAME: - attributes: - id: PIN_6_FUNCTION_NAME - children: - - children: - - attributes: - value: DCHG - type: User - type: Values - type: String - PIN_7_MODE: - attributes: - id: PIN_7_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_7_FUNCTION_TYPE: - attributes: - id: PIN_7_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG6: - attributes: - id: PORT_GROUP_0_PINCFG6 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_6_USED: - attributes: - id: PORT_GROUP_0_PIN_6_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_7_INEN: - attributes: - id: PIN_7_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_7_DIR: - attributes: - id: PIN_7_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_6: - attributes: - id: PORT_GROUP_0_PAD_6 - children: - - children: - - attributes: - id: core - value: PA06 - type: Dynamic - type: Values - type: String - PIN_7_PERIPHERAL_FUNCTION: - attributes: - id: PIN_7_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_7_FUNCTION_NAME: - attributes: - id: PIN_7_FUNCTION_NAME - children: - - children: - - attributes: - value: BOTHOFF - type: User - type: Values - type: String - PIN_7_LAT: - attributes: - id: PIN_7_LAT - children: - - children: - - attributes: - value: High - type: User - type: Values - type: String - PIN_8_MODE: - attributes: - id: PIN_8_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_8_FUNCTION_TYPE: - attributes: - id: PIN_8_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM0_PAD3 - type: User - type: Values - type: String - PIN_8_PERIPHERAL_FUNCTION: - attributes: - id: PIN_8_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: D - type: User - type: Values - type: String - PIN_8_FUNCTION_NAME: - attributes: - id: PIN_8_FUNCTION_NAME - children: - - children: - - attributes: - value: SCK - type: User - type: Values - type: String - PIN_11_MODE: - attributes: - id: PIN_11_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_11_FUNCTION_TYPE: - attributes: - id: PIN_11_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM0_PAD0 - type: User - type: Values - type: String - PIN_11_FUNCTION_NAME: - attributes: - id: PIN_11_FUNCTION_NAME - children: - - children: - - attributes: - value: MOSI - type: User - type: Values - type: String - PIN_12_MODE: - attributes: - id: PIN_12_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_12_FUNCTION_TYPE: - attributes: - id: PIN_12_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM0_PAD1 - type: User - type: Values - type: String - PIN_12_FUNCTION_NAME: - attributes: - id: PIN_12_FUNCTION_NAME - children: - - children: - - attributes: - value: MISO - type: User - type: Values - type: String - PIN_13_MODE: - attributes: - id: PIN_13_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_13_FUNCTION_TYPE: - attributes: - id: PIN_13_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_13_INEN: - attributes: - id: PIN_13_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_13_DIR: - attributes: - id: PIN_13_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PIN_13_FUNCTION_NAME: - attributes: - id: PIN_13_FUNCTION_NAME - children: - - children: - - attributes: - value: CS - type: User - type: Values - type: String - PIN_13_LAT: - attributes: - id: PIN_13_LAT - children: - - children: - - attributes: - value: High - type: User - type: Values - type: String - PIN_14_MODE: - attributes: - id: PIN_14_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_14_FUNCTION_TYPE: - attributes: - id: PIN_14_FUNCTION_TYPE - children: - - children: - - attributes: - value: EIC_EXTINT11 - type: User - type: Values - type: String - PIN_14_PERIPHERAL_FUNCTION: - attributes: - id: PIN_14_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: A - type: User - type: Values - type: String - PIN_14_FUNCTION_NAME: - attributes: - id: PIN_14_FUNCTION_NAME - children: - - children: - - attributes: - value: ALERT - type: User - type: Values - type: String - PIN_15_MODE: - attributes: - id: PIN_15_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_15_FUNCTION_TYPE: - attributes: - id: PIN_15_FUNCTION_TYPE - children: - - children: - - attributes: - value: EIC_EXTINT14 - type: User - type: Values - type: String - PIN_15_PERIPHERAL_FUNCTION: - attributes: - id: PIN_15_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: A - type: User - type: Values - type: String - PIN_15_FUNCTION_NAME: - attributes: - id: PIN_15_FUNCTION_NAME - children: - - children: - - attributes: - value: CAN_WAKE - type: User - type: Values - type: String - PORT_GROUP_0_PMUX8: - attributes: - id: PORT_GROUP_0_PMUX8 - children: - - children: - - attributes: - id: core - value: '0x22' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_16: - attributes: - id: PORT_GROUP_0_PAD_16 - children: - - children: - - attributes: - id: core - value: PA16 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG16: - attributes: - id: PORT_GROUP_0_PINCFG16 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_16_USED: - attributes: - id: PORT_GROUP_0_PIN_16_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_17_FUNCTION_NAME: - attributes: - id: PIN_17_FUNCTION_NAME - children: - - children: - - attributes: - value: I2C SCL - type: User - type: Values - type: String - PORT_GROUP_0_PAD_17: - attributes: - id: PORT_GROUP_0_PAD_17 - children: - - children: - - attributes: - id: core - value: PA17 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG17: - attributes: - id: PORT_GROUP_0_PINCFG17 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_17_USED: - attributes: - id: PORT_GROUP_0_PIN_17_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_18_FUNCTION_NAME: - attributes: - id: PIN_18_FUNCTION_NAME - children: - - children: - - attributes: - value: I2C SDA - type: User - type: Values - type: String - PIN_19_MODE: - attributes: - id: PIN_19_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_19_FUNCTION_TYPE: - attributes: - id: PIN_19_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_19_INEN: - attributes: - id: PIN_19_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_19_DIR: - attributes: - id: PIN_19_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PIN_19_FUNCTION_NAME: - attributes: - id: PIN_19_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_R - type: User - type: Values - type: String - PIN_20_INEN: - attributes: - id: PIN_20_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_20_DIR: - attributes: - id: PIN_20_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PIN_20_FUNCTION_NAME: - attributes: - id: PIN_20_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_Y - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG22: - attributes: - id: PORT_GROUP_0_PINCFG22 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_22_USED: - attributes: - id: PORT_GROUP_0_PIN_22_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX11: - attributes: - id: PORT_GROUP_0_PMUX11 - children: - - children: - - attributes: - id: core - value: '0x22' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_22: - attributes: - id: PORT_GROUP_0_PAD_22 - children: - - children: - - attributes: - id: core - value: PA22 - type: Dynamic - type: Values - type: String - PIN_21_PERIPHERAL_FUNCTION: - attributes: - id: PIN_21_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: C - type: User - type: Values - type: String - PIN_27_MODE: - attributes: - id: PIN_27_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_27_FUNCTION_TYPE: - attributes: - id: PIN_27_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_27_INEN: - attributes: - id: PIN_27_INEN - children: - - children: - - attributes: - value: 'True' - type: User - type: Values - type: String - PIN_27_DIR: - attributes: - id: PIN_27_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PIN_27_PERIPHERAL_FUNCTION: - attributes: - id: PIN_27_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_27_FUNCTION_NAME: - attributes: - id: PIN_27_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_G - type: User - type: Values - type: String - PIN_23_MODE: - attributes: - id: PIN_23_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_23_FUNCTION_TYPE: - attributes: - id: PIN_23_FUNCTION_TYPE - children: - - children: - - attributes: - value: CAN0_TX - type: User - type: Values - type: String - PIN_23_PERIPHERAL_FUNCTION: - attributes: - id: PIN_23_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - PIN_24_MODE: - attributes: - id: PIN_24_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_24_FUNCTION_TYPE: - attributes: - id: PIN_24_FUNCTION_TYPE - children: - - children: - - attributes: - value: CAN0_RX - type: User - type: Values - type: String - PIN_24_PERIPHERAL_FUNCTION: - attributes: - id: PIN_24_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - PIN_23_FUNCTION_NAME: - attributes: - id: PIN_23_FUNCTION_NAME - children: - - children: - - attributes: - value: CAN0_TX - type: User - type: Values - type: String - PIN_24_FUNCTION_NAME: - attributes: - id: PIN_24_FUNCTION_NAME - children: - - children: - - attributes: - value: CAN0_RX - type: User - type: Values - type: String - PIN_21_MODE: - attributes: - id: PIN_21_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_21_FUNCTION_TYPE: - attributes: - id: PIN_21_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM3_PAD0 - type: User - type: Values - type: String - PIN_21_FUNCTION_NAME: - attributes: - id: PIN_21_FUNCTION_NAME - children: - - children: - - attributes: - value: DEBUG_TX - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG23: - attributes: - id: PORT_GROUP_0_PINCFG23 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_23_USED: - attributes: - id: PORT_GROUP_0_PIN_23_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PAD_23: - attributes: - id: PORT_GROUP_0_PAD_23 - children: - - children: - - attributes: - id: core - value: PA23 - type: Dynamic - type: Values - type: String - PIN_22_PERIPHERAL_FUNCTION: - attributes: - id: PIN_22_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: C - type: User - type: Values - type: String - PIN_22_MODE: - attributes: - id: PIN_22_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_22_FUNCTION_TYPE: - attributes: - id: PIN_22_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM3_PAD1 - type: User - type: Values - type: String - PIN_22_FUNCTION_NAME: - attributes: - id: PIN_22_FUNCTION_NAME - children: - - children: - - attributes: - value: DEBUD_RX - type: User - type: Values - type: String - PIN_3_MODE: - attributes: - id: PIN_3_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_3_FUNCTION_TYPE: - attributes: - id: PIN_3_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG2: - attributes: - id: PORT_GROUP_0_PINCFG2 - children: - - children: - - attributes: - id: core - value: '0x2' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_2_USED: - attributes: - id: PORT_GROUP_0_PIN_2_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_3_INEN: - attributes: - id: PIN_3_INEN - children: - - children: - - attributes: - value: 'True' - type: User - type: Values - type: String - PIN_3_DIR: - attributes: - id: PIN_3_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_2: - attributes: - id: PORT_GROUP_0_PAD_2 - children: - - children: - - attributes: - id: core - value: PA02 - type: Dynamic - type: Values - type: String - PIN_3_PERIPHERAL_FUNCTION: - attributes: - id: PIN_3_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_3_FUNCTION_NAME: - attributes: - id: PIN_3_FUNCTION_NAME - children: - - children: - - attributes: - value: GPIO_PA02 - type: User - type: Values - type: String - userData: - children: - - attributes: - canvasHeight: '0' - canvasWidth: '0' - type: GraphSettings - - children: - - attributes: - id: profile0 - name: Main - type: Profile - type: PowerProfiles - type: UserData diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/eic.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/eic.yml deleted file mode 100644 index 69603549..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/eic.yml +++ /dev/null @@ -1,84 +0,0 @@ -configVersion: 1.0.0 -componentName: eic -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: eic - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: eic - x: '162' - y: '115' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - EIC_ASYNCH: - attributes: - id: EIC_ASYNCH - children: - - children: - - attributes: - id: eic - value: '0' - type: Dynamic - type: Values - type: Hex - EIC_CHAN_11: - attributes: - id: EIC_CHAN_11 - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - EIC_CHAN_14: - attributes: - id: EIC_CHAN_14 - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - EIC_EXTINTEO: - attributes: - id: EIC_EXTINTEO - children: - - children: - - attributes: - id: eic - value: '0' - type: Dynamic - type: Values - type: Hex - EIC_INT: - attributes: - id: EIC_INT - children: - - children: - - attributes: - id: eic - value: '0' - type: Dynamic - type: Values - type: Hex - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/rtc.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/rtc.yml deleted file mode 100644 index 9074a38d..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/rtc.yml +++ /dev/null @@ -1,51 +0,0 @@ -configVersion: 1.0.0 -componentName: rtc -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: rtc - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: rtc - x: '324' - y: '104' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - RTC_MODE0_MATCHCLR: - attributes: - id: RTC_MODE0_MATCHCLR - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RTC_MODE0_TIMER_COMPARE: - attributes: - id: RTC_MODE0_TIMER_COMPARE - children: - - children: - - attributes: - value: '101' - type: User - type: Values - type: Hex - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom0.yml deleted file mode 100644 index d5abd014..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom0.yml +++ /dev/null @@ -1,340 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom0 - x: '501' - y: '106' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom0 - value: '232' - type: Dynamic - type: Values - type: Hex - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom0 - value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - SERCOM_SPIM_COMMON_HEADER: - attributes: - id: SERCOM_SPIM_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_HEADER: - attributes: - id: SERCOM_SPIM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_SOURCE: - attributes: - id: SERCOM_SPIM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_7816_HEADER: - attributes: - id: SERCOM_USART_7816_HEADER - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_7816_SOURCE: - attributes: - id: SERCOM_USART_7816_SOURCE - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SPI_BAUD_RATE: - attributes: - id: SPI_BAUD_RATE - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '10000' - type: User - type: Values - type: Integer - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '2399' - type: Dynamic - type: Values - type: Integer - SPI_DIPO: - attributes: - id: SPI_DIPO - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - SPI_DOPO: - attributes: - id: SPI_DOPO - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '3' - type: User - type: Values - type: KeyValueSet - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom0 - value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - USART_7816_BAUD_VALUE: - attributes: - id: USART_7816_BAUD_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '14' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_DATA_BITS: - attributes: - id: USART_DATA_BITS - children: - - children: - - attributes: - id: sercom0 - value: DRV_USART_DATA_8_BIT - type: Dynamic - type: Values - type: String - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom0 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom0 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom0 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom1.yml deleted file mode 100644 index d4fe5a1e..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom1.yml +++ /dev/null @@ -1,383 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom1 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom1 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom1 - x: '662' - y: '106' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom1 - value: '232' - type: Dynamic - type: Values - type: Hex - I2CM_TRISE: - attributes: - id: I2CM_TRISE - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '100' - type: User - type: Values - type: Integer - I2C_CLOCK_SPEED: - attributes: - id: I2C_CLOCK_SPEED - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '100' - type: User - type: Values - type: Integer - I2C_CLOCK_SPEED_HZ: - attributes: - id: I2C_CLOCK_SPEED_HZ - children: - - children: - - attributes: - id: sercom1 - value: '100000' - type: Dynamic - type: Values - type: Integer - I2C_SCLSM: - attributes: - id: I2C_SCLSM - children: - - children: - - attributes: - id: sercom1 - value: '0' - type: Dynamic - type: Values - type: Integer - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom1 - value: '' - type: Dynamic - type: Values - type: String - SERCOM_I2CM_HEADER: - attributes: - id: SERCOM_I2CM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_I2CM_MASTER_HEADER: - attributes: - id: SERCOM_I2CM_MASTER_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_I2CM_SOURCE: - attributes: - id: SERCOM_I2CM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - value: '2' - type: User - type: Values - type: KeyValueSet - SERCOM_SPIM_COMMON_HEADER: - attributes: - id: SERCOM_SPIM_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_HEADER: - attributes: - id: SERCOM_SPIM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_SOURCE: - attributes: - id: SERCOM_SPIM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_7816_HEADER: - attributes: - id: SERCOM_USART_7816_HEADER - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_7816_SOURCE: - attributes: - id: SERCOM_USART_7816_SOURCE - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '23' - type: Dynamic - type: Values - type: Integer - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom1 - value: '' - type: Dynamic - type: Values - type: String - USART_7816_BAUD_VALUE: - attributes: - id: USART_7816_BAUD_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '14' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_DATA_BITS: - attributes: - id: USART_DATA_BITS - children: - - children: - - attributes: - id: sercom1 - value: DRV_USART_DATA_8_BIT - type: Dynamic - type: Values - type: String - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom1 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom1 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom1 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom3.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom3.yml deleted file mode 100644 index 1f725209..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default/components/sercom3.yml +++ /dev/null @@ -1,118 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom3 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom3 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom3 - x: '821' - y: '105' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom3 - value: '232' - type: Dynamic - type: Values - type: Hex - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom3 - value: '23' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom3 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom3 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RXPO: - attributes: - id: USART_RXPO - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom3 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom3 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom3 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default/mcc-config.mc4 b/bms/bms/bms_config_e18a/mcc/bms_config_default/mcc-config.mc4 deleted file mode 100644 index 57a73294..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default/mcc-config.mc4 +++ /dev/null @@ -1,86 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a4f1774c6f1f8c6cd522567536c9e9d75ca63259b868015ac9b0fb0aeeffe1f4 -- file: ../src/main.c diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc0.yml deleted file mode 100644 index 5c50ac54..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc0.yml +++ /dev/null @@ -1,237 +0,0 @@ -configVersion: 1.0.0 -componentName: adc0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: adc0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: adc0 - x: '30' - y: '216' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - ADC_CALLBACK_API: - attributes: - id: ADC_CALLBACK_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_CallbackRegister - type: Dynamic - type: Values - type: String - ADC_CHANNEL_SELECT_API: - attributes: - id: ADC_CHANNEL_SELECT_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ChannelSelect - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_U: - attributes: - id: ADC_CH_PHASE_U - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN2 - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_V: - attributes: - id: ADC_CH_PHASE_V - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN5 - type: Dynamic - type: Values - type: String - ADC_CH_POT: - attributes: - id: ADC_CH_POT - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_CH_VDC_BUS: - attributes: - id: ADC_CH_VDC_BUS - children: - - children: - - attributes: - id: adc0 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_GET_RESULT_API: - attributes: - id: ADC_GET_RESULT_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ConversionResultGet - type: Dynamic - type: Values - type: String - ADC_GND: - attributes: - id: ADC_GND - children: - - children: - - attributes: - id: adc0 - value: ADC_NEGINPUT_GND - type: Dynamic - type: Values - type: String - ADC_INT_CLEAR_API: - attributes: - id: ADC_INT_CLEAR_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_InterruptsClear - type: Dynamic - type: Values - type: String - ADC_INT_DISABLE_API: - attributes: - id: ADC_INT_DISABLE_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_InterruptsDisable - type: Dynamic - type: Values - type: String - ADC_INT_ENABLE_API: - attributes: - id: ADC_INT_ENABLE_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_InterruptsEnable - type: Dynamic - type: Values - type: String - ADC_IS_RESULT_READY_API: - attributes: - id: ADC_IS_RESULT_READY_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ConversionStatusGet - type: Dynamic - type: Values - type: String - ADC_START_API: - attributes: - id: ADC_START_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_Enable - type: Dynamic - type: Values - type: String - ADC_START_CONV_API: - attributes: - id: ADC_START_CONV_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_ConversionStart - type: Dynamic - type: Values - type: String - ADC_STOP_API: - attributes: - id: ADC_STOP_API - children: - - children: - - attributes: - id: adc0 - value: ADC0_Disable - type: Dynamic - type: Values - type: String - INTERRUPT_ADC_RESULT: - attributes: - id: INTERRUPT_ADC_RESULT - children: - - children: - - attributes: - id: adc0 - value: ADC0_RESRDY_IRQn - type: Dynamic - type: Values - type: String - ADC_CTRLB_PRESCALER: - attributes: - id: ADC_CTRLB_PRESCALER - children: - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - ADC_CTRLC_DIFFMODE: - attributes: - id: ADC_CTRLC_DIFFMODE - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - ADC_CONV_TRIGGER: - attributes: - id: ADC_CONV_TRIGGER - children: - - children: - - attributes: - value: SW Trigger - type: User - type: Values - type: Combo - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc1.yml deleted file mode 100644 index b9ebd9ab..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/adc1.yml +++ /dev/null @@ -1,207 +0,0 @@ -configVersion: 1.0.0 -componentName: adc1 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: adc1 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: adc1 - x: '30' - y: '148' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - ADC_CALLBACK_API: - attributes: - id: ADC_CALLBACK_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_CallbackRegister - type: Dynamic - type: Values - type: String - ADC_CHANNEL_SELECT_API: - attributes: - id: ADC_CHANNEL_SELECT_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ChannelSelect - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_U: - attributes: - id: ADC_CH_PHASE_U - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN2 - type: Dynamic - type: Values - type: String - ADC_CH_PHASE_V: - attributes: - id: ADC_CH_PHASE_V - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN5 - type: Dynamic - type: Values - type: String - ADC_CH_POT: - attributes: - id: ADC_CH_POT - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_CH_VDC_BUS: - attributes: - id: ADC_CH_VDC_BUS - children: - - children: - - attributes: - id: adc1 - value: ADC_POSINPUT_AIN0 - type: Dynamic - type: Values - type: String - ADC_GET_RESULT_API: - attributes: - id: ADC_GET_RESULT_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ConversionResultGet - type: Dynamic - type: Values - type: String - ADC_GND: - attributes: - id: ADC_GND - children: - - children: - - attributes: - id: adc1 - value: ADC_NEGINPUT_GND - type: Dynamic - type: Values - type: String - ADC_INT_CLEAR_API: - attributes: - id: ADC_INT_CLEAR_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_InterruptsClear - type: Dynamic - type: Values - type: String - ADC_INT_DISABLE_API: - attributes: - id: ADC_INT_DISABLE_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_InterruptsDisable - type: Dynamic - type: Values - type: String - ADC_INT_ENABLE_API: - attributes: - id: ADC_INT_ENABLE_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_InterruptsEnable - type: Dynamic - type: Values - type: String - ADC_IS_RESULT_READY_API: - attributes: - id: ADC_IS_RESULT_READY_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ConversionStatusGet - type: Dynamic - type: Values - type: String - ADC_START_API: - attributes: - id: ADC_START_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_Enable - type: Dynamic - type: Values - type: String - ADC_START_CONV_API: - attributes: - id: ADC_START_CONV_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_ConversionStart - type: Dynamic - type: Values - type: String - ADC_STOP_API: - attributes: - id: ADC_STOP_API - children: - - children: - - attributes: - id: adc1 - value: ADC1_Disable - type: Dynamic - type: Values - type: String - INTERRUPT_ADC_RESULT: - attributes: - id: INTERRUPT_ADC_RESULT - children: - - children: - - attributes: - id: adc1 - value: ADC1_RESRDY_IRQn - type: Dynamic - type: Values - type: String - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/can0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/can0.yml deleted file mode 100644 index 0b56dbc6..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/can0.yml +++ /dev/null @@ -1,526 +0,0 @@ -configVersion: 1.0.0 -componentName: can0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: can0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: can0 - x: '196' - y: '220' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - NBTP_NBRP: - attributes: - id: NBTP_NBRP - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '2' - type: Dynamic - - attributes: - value: '3' - type: User - type: Values - type: Integer - NOMINAL_SAMPLE_POINT: - attributes: - id: NOMINAL_SAMPLE_POINT - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '96.875' - type: Dynamic - - attributes: - value: '75.0' - type: User - type: Values - type: Float - NBTP_TOTAL_TIME_QUANTA: - attributes: - id: NBTP_TOTAL_TIME_QUANTA - children: - - children: - - attributes: - id: can0 - value: '24' - type: Dynamic - type: Values - type: Integer - NBTP_NTSEG1: - attributes: - id: NBTP_NTSEG1 - children: - - children: - - attributes: - id: can0 - value: '17' - type: Dynamic - type: Values - type: Integer - NBTP_NTSEG2: - attributes: - id: NBTP_NTSEG2 - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - type: Values - type: Integer - NBTP_NSJW: - attributes: - id: NBTP_NSJW - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - - attributes: - value: '5' - type: User - type: Values - type: Integer - CALCULATED_NOMINAL_BITRATE: - attributes: - id: CALCULATED_NOMINAL_BITRATE - children: - - children: - - attributes: - id: can0 - value: '500' - type: Dynamic - type: Values - type: Integer - NOMINAL_TIME_QUANTA_PERIOD: - attributes: - id: NOMINAL_TIME_QUANTA_PERIOD - children: - - children: - - attributes: - id: can0 - value: '83.333' - type: Dynamic - type: Values - type: String - CALCULATED_NOMINAL_ERRORRATE: - attributes: - id: CALCULATED_NOMINAL_ERRORRATE - children: - - children: - - attributes: - id: can0 - value: '0.000' - type: Dynamic - type: Values - type: String - AUTO_NOMINAL_BIT_TIMING_CALCULATION: - attributes: - id: AUTO_NOMINAL_BIT_TIMING_CALCULATION - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - DBTP_TOTAL_TIME_QUANTA: - attributes: - id: DBTP_TOTAL_TIME_QUANTA - children: - - children: - - attributes: - id: can0 - value: '24' - type: Dynamic - type: Values - type: Integer - DBTP_DTSEG1: - attributes: - id: DBTP_DTSEG1 - children: - - children: - - attributes: - id: can0 - value: '17' - type: Dynamic - type: Values - type: Integer - DBTP_DTSEG2: - attributes: - id: DBTP_DTSEG2 - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - type: Values - type: Integer - DBTP_DSJW: - attributes: - id: DBTP_DSJW - children: - - children: - - attributes: - id: can0 - value: '6' - type: Dynamic - - attributes: - value: '5' - type: User - type: Values - type: Integer - CALCULATED_DATA_BITRATE: - attributes: - id: CALCULATED_DATA_BITRATE - children: - - children: - - attributes: - id: can0 - value: '2000' - type: Dynamic - type: Values - type: Integer - DATA_TIME_QUANTA_PERIOD: - attributes: - id: DATA_TIME_QUANTA_PERIOD - children: - - children: - - attributes: - id: can0 - value: '20.833' - type: Dynamic - type: Values - type: String - CALCULATED_DATA_ERRORRATE: - attributes: - id: CALCULATED_DATA_ERRORRATE - children: - - children: - - attributes: - id: can0 - value: '0.000' - type: Dynamic - type: Values - type: String - CAN_OPMODE: - attributes: - id: CAN_OPMODE - children: - - children: - - attributes: - value: CAN FD - type: User - type: Values - type: Combo - instHeaderFile: - attributes: - id: instHeaderFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_legacy.h.ftl - type: String - type: Attributes - type: File - sourceFile: - attributes: - id: sourceFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_legacy.c.ftl - type: String - type: Attributes - type: File - INTERRUPT_MODE: - attributes: - id: INTERRUPT_MODE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - DBTP_DBRP: - attributes: - id: DBTP_DBRP - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '2' - type: Dynamic - - attributes: - value: '0' - type: User - type: Values - type: Integer - DATA_SAMPLE_POINT: - attributes: - id: DATA_SAMPLE_POINT - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - - children: - - attributes: - id: can0 - value: '87.5' - type: Dynamic - - attributes: - value: '75.0' - type: User - type: Values - type: Float - AUTO_DATA_BIT_TIMING_CALCULATION: - attributes: - id: AUTO_DATA_BIT_TIMING_CALCULATION - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - DATA_BITRATE: - attributes: - id: DATA_BITRATE - children: - - children: - - attributes: - value: '2000' - type: User - type: Values - type: Integer - NOMINAL_BITRATE: - attributes: - id: NOMINAL_BITRATE - children: - - children: - - attributes: - value: '500' - type: User - type: Values - type: Integer - headerFile: - attributes: - id: headerFile - children: - - children: - - attributes: - id: source - children: - - type: Value - value: ../peripheral/can_u2003/templates/plib_can_common_legacy.h - type: String - type: Attributes - type: File - CAN_GENERATE_LEGACY_APIS: - attributes: - id: CAN_GENERATE_LEGACY_APIS - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RXF0_WATERMARK: - attributes: - id: RXF0_WATERMARK - children: - - children: - - attributes: - id: can0 - value: '0' - type: Dynamic - type: Values - type: Integer - RXF0_ELEMENTS: - attributes: - id: RXF0_ELEMENTS - children: - - children: - - attributes: - value: '8' - type: User - type: Values - type: Integer - RXF0_BYTES_CFG: - attributes: - id: RXF0_BYTES_CFG - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '7' - type: User - type: Values - type: KeyValueSet - RXF1_USE: - attributes: - id: RXF1_USE - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - RXBUF_USE: - attributes: - id: RXBUF_USE - children: - - children: - - attributes: - value: 'false' - type: User - type: Values - type: Boolean - TX_FIFO_WATERMARK: - attributes: - id: TX_FIFO_WATERMARK - children: - - children: - - attributes: - id: can0 - value: '0' - type: Dynamic - type: Values - type: Integer - TX_FIFO_ELEMENTS: - attributes: - id: TX_FIFO_ELEMENTS - children: - - children: - - attributes: - value: '8' - type: User - type: Values - type: Integer - TX_FIFO_BYTES_CFG: - attributes: - id: TX_FIFO_BYTES_CFG - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '7' - type: User - type: Values - type: KeyValueSet - FILTERS_STD_NOMATCH: - attributes: - id: FILTERS_STD_NOMATCH - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - FILTERS_EXT_NOMATCH: - attributes: - id: FILTERS_EXT_NOMATCH - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - TIMESTAMP_ENABLE: - attributes: - id: TIMESTAMP_ENABLE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RXF0_OVERWRITE: - attributes: - id: RXF0_OVERWRITE - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/cmsis.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/cmsis.yml deleted file mode 100644 index f9f85905..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/cmsis.yml +++ /dev/null @@ -1,24 +0,0 @@ -configVersion: 1.0.0 -componentName: cmsis -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: cmsis - type: module - version: '' -- dependencyPackage: '' - name: CMSIS_5 - type: package - version: 5.9.1-dev -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: {} - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/core.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/core.yml deleted file mode 100644 index 9c2cfa8e..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/core.yml +++ /dev/null @@ -1,2508 +0,0 @@ -configVersion: 1.0.0 -componentName: core -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: core - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: core - x: '80' - y: '4' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - ADC0_CLOCK_ENABLE: - attributes: - id: ADC0_CLOCK_ENABLE - children: - - children: - - attributes: - id: adc0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - ADC0_CLOCK_FREQUENCY: - attributes: - id: ADC0_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - CAN0_CLOCK_ENABLE: - attributes: - id: CAN0_CLOCK_ENABLE - children: - - children: - - attributes: - id: can0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_CLOCK_FREQUENCY: - attributes: - id: CAN0_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_22_CHEN: - attributes: - id: GCLK_ID_22_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_22_FREQ: - attributes: - id: GCLK_ID_22_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_25_CHEN: - attributes: - id: GCLK_ID_25_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_25_FREQ: - attributes: - id: GCLK_ID_25_FREQ - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_26_CHEN: - attributes: - id: GCLK_ID_26_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_26_FREQ: - attributes: - id: GCLK_ID_26_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_33_CHEN: - attributes: - id: GCLK_ID_33_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - GCLK_ID_33_FREQ: - attributes: - id: GCLK_ID_33_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - MCLK_AHB_INITIAL_VALUE: - attributes: - id: MCLK_AHB_INITIAL_VALUE - children: - - children: - - attributes: - id: core - value: '0x1dff' - type: Dynamic - type: Values - type: String - MCLK_APBC_INITIAL_VALUE: - attributes: - id: MCLK_APBC_INITIAL_VALUE - children: - - children: - - attributes: - id: core - value: '0x60036' - type: Dynamic - type: Values - type: String - NVIC_12_0_ENABLE: - attributes: - id: NVIC_12_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_12_0_HANDLER: - attributes: - id: NVIC_12_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM3_Handler - type: Dynamic - type: Values - type: String - NVIC_12_0_HANDLER_LOCK: - attributes: - id: NVIC_12_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_14_0_ENABLE: - attributes: - id: NVIC_14_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_14_0_HANDLER: - attributes: - id: NVIC_14_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM5_Handler - type: Dynamic - type: Values - type: String - NVIC_14_0_HANDLER_LOCK: - attributes: - id: NVIC_14_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM3_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM3_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - SERCOM3_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM3_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM5_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM5_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - SERCOM5_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM5_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - ADC1_CLOCK_FREQUENCY: - attributes: - id: ADC1_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_34_FREQ: - attributes: - id: GCLK_ID_34_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_34_CHEN: - attributes: - id: GCLK_ID_34_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - ADC1_CLOCK_ENABLE: - attributes: - id: ADC1_CLOCK_ENABLE - children: - - children: - - attributes: - id: adc1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN1_CLOCK_FREQUENCY: - attributes: - id: CAN1_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_27_FREQ: - attributes: - id: GCLK_ID_27_FREQ - children: - - children: - - attributes: - id: core - value: '0' - type: Dynamic - type: Values - type: Integer - GCLK_ID_27_CHEN: - attributes: - id: GCLK_ID_27_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM1_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_20_FREQ: - attributes: - id: GCLK_ID_20_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_20_CHEN: - attributes: - id: GCLK_ID_20_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM1_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_10_0_ENABLE: - attributes: - id: NVIC_10_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_10_0_HANDLER_LOCK: - attributes: - id: NVIC_10_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_10_0_HANDLER: - attributes: - id: NVIC_10_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM1_I2C_InterruptHandler - type: Dynamic - type: Values - type: String - CAN1_INTERRUPT_ENABLE_UPDATE: - attributes: - id: CAN1_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_16_0_ENABLE: - attributes: - id: NVIC_16_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - NVIC_16_0_HANDLER: - attributes: - id: NVIC_16_0_HANDLER - children: - - children: - - attributes: - id: core - value: CAN1_Handler - type: Dynamic - type: Values - type: String - NVIC_16_0_HANDLER_LOCK: - attributes: - id: NVIC_16_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_INTERRUPT_ENABLE_UPDATE: - attributes: - id: CAN0_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_15_0_ENABLE: - attributes: - id: NVIC_15_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_INTERRUPT_ENABLE: - attributes: - id: CAN0_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: can0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_15_0_HANDLER: - attributes: - id: NVIC_15_0_HANDLER - children: - - children: - - attributes: - id: core - value: CAN0_InterruptHandler - type: Dynamic - type: Values - type: String - CAN0_INTERRUPT_HANDLER: - attributes: - id: CAN0_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: can0 - value: CAN0_InterruptHandler - type: Dynamic - type: Values - type: String - NVIC_15_0_HANDLER_LOCK: - attributes: - id: NVIC_15_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - CAN0_INTERRUPT_HANDLER_LOCK: - attributes: - id: CAN0_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: can0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM4_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_23_FREQ: - attributes: - id: GCLK_ID_23_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_23_CHEN: - attributes: - id: GCLK_ID_23_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM4_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM4_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_13_0_ENABLE: - attributes: - id: NVIC_13_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_INTERRUPT_ENABLE: - attributes: - id: SERCOM4_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_13_0_HANDLER_LOCK: - attributes: - id: NVIC_13_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM4_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM4_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_13_0_HANDLER: - attributes: - id: NVIC_13_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM4_Handler - type: Dynamic - type: Values - type: String - SERCOM4_INTERRUPT_HANDLER: - attributes: - id: SERCOM4_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom4 - value: SERCOM4_Handler - type: Dynamic - type: Values - type: String - SERCOM1_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM1_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_ENABLE: - attributes: - id: SERCOM1_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM1_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM1_INTERRUPT_HANDLER: - attributes: - id: SERCOM1_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom1 - value: SERCOM1_I2C_InterruptHandler - type: Dynamic - type: Values - type: String - SERCOM0_CORE_CLOCK_FREQUENCY: - attributes: - id: SERCOM0_CORE_CLOCK_FREQUENCY - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_19_FREQ: - attributes: - id: GCLK_ID_19_FREQ - children: - - children: - - attributes: - id: core - value: '48000000' - type: Dynamic - type: Values - type: Integer - GCLK_ID_19_CHEN: - attributes: - id: GCLK_ID_19_CHEN - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_CORE_CLOCK_ENABLE: - attributes: - id: SERCOM0_CORE_CLOCK_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_INTERRUPT_ENABLE_UPDATE: - attributes: - id: SERCOM0_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_9_0_ENABLE: - attributes: - id: NVIC_9_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_INTERRUPT_ENABLE: - attributes: - id: SERCOM0_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_9_0_HANDLER_LOCK: - attributes: - id: NVIC_9_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - SERCOM0_INTERRUPT_HANDLER_LOCK: - attributes: - id: SERCOM0_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_9_0_HANDLER: - attributes: - id: NVIC_9_0_HANDLER - children: - - children: - - attributes: - id: core - value: SERCOM0_SPI_InterruptHandler - type: Dynamic - type: Values - type: String - SERCOM0_INTERRUPT_HANDLER: - attributes: - id: SERCOM0_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: sercom0 - value: SERCOM0_SPI_InterruptHandler - type: Dynamic - type: Values - type: String - PORT_GROUP_1_DIR: - attributes: - id: PORT_GROUP_1_DIR - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_OUT: - attributes: - id: PORT_GROUP_1_OUT - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PINCFG8: - attributes: - id: PORT_GROUP_1_PINCFG8 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_8_USED: - attributes: - id: PORT_GROUP_1_PIN_8_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_1_PMUX4: - attributes: - id: PORT_GROUP_1_PMUX4 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PAD_8: - attributes: - id: PORT_GROUP_1_PAD_8 - children: - - children: - - attributes: - id: core - value: PB08 - type: Dynamic - type: Values - type: String - PIN_11_PERIPHERAL_FUNCTION: - attributes: - id: PIN_11_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PINCFG5: - attributes: - id: PORT_GROUP_1_PINCFG5 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_5_USED: - attributes: - id: PORT_GROUP_1_PIN_5_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_1_PMUX2: - attributes: - id: PORT_GROUP_1_PMUX2 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PAD_5: - attributes: - id: PORT_GROUP_1_PAD_5 - children: - - children: - - attributes: - id: core - value: PB05 - type: Dynamic - type: Values - type: String - PIN_6_PERIPHERAL_FUNCTION: - attributes: - id: PIN_6_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_0_DIR: - attributes: - id: PORT_GROUP_0_DIR - children: - - children: - - attributes: - id: core - value: '0x100c8080' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_OUT: - attributes: - id: PORT_GROUP_0_OUT - children: - - children: - - attributes: - id: core - value: '0x80' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG1: - attributes: - id: PORT_GROUP_0_PINCFG1 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_1_USED: - attributes: - id: PORT_GROUP_0_PIN_1_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX0: - attributes: - id: PORT_GROUP_0_PMUX0 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_1: - attributes: - id: PORT_GROUP_0_PAD_1 - children: - - children: - - attributes: - id: core - value: PA01 - type: Dynamic - type: Values - type: String - PIN_2_PERIPHERAL_FUNCTION: - attributes: - id: PIN_2_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG0: - attributes: - id: PORT_GROUP_0_PINCFG0 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_0_USED: - attributes: - id: PORT_GROUP_0_PIN_0_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PAD_0: - attributes: - id: PORT_GROUP_0_PAD_0 - children: - - children: - - attributes: - id: core - value: PA00 - type: Dynamic - type: Values - type: String - PIN_1_PERIPHERAL_FUNCTION: - attributes: - id: PIN_1_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PINCFG9: - attributes: - id: PORT_GROUP_1_PINCFG9 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_9_USED: - attributes: - id: PORT_GROUP_1_PIN_9_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PINCFG3: - attributes: - id: PORT_GROUP_0_PINCFG3 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_3_USED: - attributes: - id: PORT_GROUP_0_PIN_3_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX1: - attributes: - id: PORT_GROUP_0_PMUX1 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_3: - attributes: - id: PORT_GROUP_0_PAD_3 - children: - - children: - - attributes: - id: core - value: PA03 - type: Dynamic - type: Values - type: String - PIN_4_PERIPHERAL_FUNCTION: - attributes: - id: PIN_4_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_2_DIR: - attributes: - id: PIN_2_DIR - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_2_PULLEN: - attributes: - id: PIN_2_PULLEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_2_INEN: - attributes: - id: PIN_2_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PINCFG6: - attributes: - id: PORT_GROUP_1_PINCFG6 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_6_USED: - attributes: - id: PORT_GROUP_1_PIN_6_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_1_PMUX3: - attributes: - id: PORT_GROUP_1_PMUX3 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PAD_6: - attributes: - id: PORT_GROUP_1_PAD_6 - children: - - children: - - attributes: - id: core - value: PB06 - type: Dynamic - type: Values - type: String - PIN_9_PERIPHERAL_FUNCTION: - attributes: - id: PIN_9_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PINCFG7: - attributes: - id: PORT_GROUP_1_PINCFG7 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_1_PIN_7_USED: - attributes: - id: PORT_GROUP_1_PIN_7_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_1_PAD_7: - attributes: - id: PORT_GROUP_1_PAD_7 - children: - - children: - - attributes: - id: core - value: PB07 - type: Dynamic - type: Values - type: String - PIN_10_PERIPHERAL_FUNCTION: - attributes: - id: PIN_10_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_1_PAD_9: - attributes: - id: PORT_GROUP_1_PAD_9 - children: - - children: - - attributes: - id: core - value: PB09 - type: Dynamic - type: Values - type: String - PIN_12_PERIPHERAL_FUNCTION: - attributes: - id: PIN_12_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG10: - attributes: - id: PORT_GROUP_0_PINCFG10 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_10_USED: - attributes: - id: PORT_GROUP_0_PIN_10_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX5: - attributes: - id: PORT_GROUP_0_PMUX5 - children: - - children: - - attributes: - id: core - value: '0x20' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_10: - attributes: - id: PORT_GROUP_0_PAD_10 - children: - - children: - - attributes: - id: core - value: PA10 - type: Dynamic - type: Values - type: String - PIN_19_PERIPHERAL_FUNCTION: - attributes: - id: PIN_19_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_16_MODE: - attributes: - id: PIN_16_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_16_FUNCTION_TYPE: - attributes: - id: PIN_16_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PMUX3: - attributes: - id: PORT_GROUP_0_PMUX3 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_7: - attributes: - id: PORT_GROUP_0_PAD_7 - children: - - children: - - attributes: - id: core - value: PA07 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG7: - attributes: - id: PORT_GROUP_0_PINCFG7 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_7_USED: - attributes: - id: PORT_GROUP_0_PIN_7_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_16_PERIPHERAL_FUNCTION: - attributes: - id: PIN_16_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_16_INEN: - attributes: - id: PIN_16_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_16_DIR: - attributes: - id: PIN_16_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PIN_16_FUNCTION_NAME: - attributes: - id: PIN_16_FUNCTION_NAME - children: - - children: - - attributes: - value: GPIO_PA07 - type: User - type: Values - type: String - PIN_17_MODE: - attributes: - id: PIN_17_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_17_FUNCTION_TYPE: - attributes: - id: PIN_17_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM0_PAD0 - type: User - type: Values - type: String - PORT_GROUP_0_PMUX4: - attributes: - id: PORT_GROUP_0_PMUX4 - children: - - children: - - attributes: - id: core - value: '0x22' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_8: - attributes: - id: PORT_GROUP_0_PAD_8 - children: - - children: - - attributes: - id: core - value: PA08 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG8: - attributes: - id: PORT_GROUP_0_PINCFG8 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_8_USED: - attributes: - id: PORT_GROUP_0_PIN_8_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_17_PERIPHERAL_FUNCTION: - attributes: - id: PIN_17_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: C - type: User - type: Values - type: String - PIN_18_MODE: - attributes: - id: PIN_18_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_18_FUNCTION_TYPE: - attributes: - id: PIN_18_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM0_PAD1 - type: User - type: Values - type: String - PORT_GROUP_0_PAD_9: - attributes: - id: PORT_GROUP_0_PAD_9 - children: - - children: - - attributes: - id: core - value: PA09 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG9: - attributes: - id: PORT_GROUP_0_PINCFG9 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_9_USED: - attributes: - id: PORT_GROUP_0_PIN_9_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_18_PERIPHERAL_FUNCTION: - attributes: - id: PIN_18_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: C - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG11: - attributes: - id: PORT_GROUP_0_PINCFG11 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_11_USED: - attributes: - id: PORT_GROUP_0_PIN_11_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PAD_11: - attributes: - id: PORT_GROUP_0_PAD_11 - children: - - children: - - attributes: - id: core - value: PA11 - type: Dynamic - type: Values - type: String - PIN_20_PERIPHERAL_FUNCTION: - attributes: - id: PIN_20_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: C - type: User - type: Values - type: String - PIN_20_MODE: - attributes: - id: PIN_20_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_20_FUNCTION_TYPE: - attributes: - id: PIN_20_FUNCTION_TYPE - children: - - children: - - attributes: - value: SERCOM0_PAD3 - type: User - type: Values - type: String - PIN_16_LAT: - attributes: - id: PIN_16_LAT - children: - - children: - - attributes: - value: High - type: User - type: Values - type: String - PIN_53_MODE: - attributes: - id: PIN_53_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_53_FUNCTION_TYPE: - attributes: - id: PIN_53_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG28: - attributes: - id: PORT_GROUP_0_PINCFG28 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_28_USED: - attributes: - id: PORT_GROUP_0_PIN_28_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_53_INEN: - attributes: - id: PIN_53_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_53_DIR: - attributes: - id: PIN_53_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PMUX14: - attributes: - id: PORT_GROUP_0_PMUX14 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_28: - attributes: - id: PORT_GROUP_0_PAD_28 - children: - - children: - - attributes: - id: core - value: PA28 - type: Dynamic - type: Values - type: String - PIN_53_PERIPHERAL_FUNCTION: - attributes: - id: PIN_53_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_53_FUNCTION_NAME: - attributes: - id: PIN_53_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_G - type: User - type: Values - type: String - PIN_53_DRVSTR: - attributes: - id: PIN_53_DRVSTR - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - PIN_38_MODE: - attributes: - id: PIN_38_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_38_FUNCTION_TYPE: - attributes: - id: PIN_38_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG19: - attributes: - id: PORT_GROUP_0_PINCFG19 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_19_USED: - attributes: - id: PORT_GROUP_0_PIN_19_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_38_INEN: - attributes: - id: PIN_38_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_38_DIR: - attributes: - id: PIN_38_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PMUX9: - attributes: - id: PORT_GROUP_0_PMUX9 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_19: - attributes: - id: PORT_GROUP_0_PAD_19 - children: - - children: - - attributes: - id: core - value: PA19 - type: Dynamic - type: Values - type: String - PIN_38_PERIPHERAL_FUNCTION: - attributes: - id: PIN_38_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_38_FUNCTION_NAME: - attributes: - id: PIN_38_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_Y - type: User - type: Values - type: String - PIN_37_MODE: - attributes: - id: PIN_37_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_37_FUNCTION_TYPE: - attributes: - id: PIN_37_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG18: - attributes: - id: PORT_GROUP_0_PINCFG18 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_18_USED: - attributes: - id: PORT_GROUP_0_PIN_18_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_37_INEN: - attributes: - id: PIN_37_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_37_DIR: - attributes: - id: PIN_37_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_18: - attributes: - id: PORT_GROUP_0_PAD_18 - children: - - children: - - attributes: - id: core - value: PA18 - type: Dynamic - type: Values - type: String - PIN_37_PERIPHERAL_FUNCTION: - attributes: - id: PIN_37_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_37_FUNCTION_NAME: - attributes: - id: PIN_37_FUNCTION_NAME - children: - - children: - - attributes: - value: LED_R - type: User - type: Values - type: String - PIN_31_MODE: - attributes: - id: PIN_31_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_31_FUNCTION_TYPE: - attributes: - id: PIN_31_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG14: - attributes: - id: PORT_GROUP_0_PINCFG14 - children: - - children: - - attributes: - id: core - value: '0x2' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_14_USED: - attributes: - id: PORT_GROUP_0_PIN_14_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_31_INEN: - attributes: - id: PIN_31_INEN - children: - - children: - - attributes: - value: 'True' - type: User - type: Values - type: String - PIN_31_DIR: - attributes: - id: PIN_31_DIR - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PORT_GROUP_0_PMUX7: - attributes: - id: PORT_GROUP_0_PMUX7 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_14: - attributes: - id: PORT_GROUP_0_PAD_14 - children: - - children: - - attributes: - id: core - value: PA14 - type: Dynamic - type: Values - type: String - PIN_31_PERIPHERAL_FUNCTION: - attributes: - id: PIN_31_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_31_FUNCTION_NAME: - attributes: - id: PIN_31_FUNCTION_NAME - children: - - children: - - attributes: - value: CAN_RX_WAKEUP - type: User - type: Values - type: String - PIN_32_MODE: - attributes: - id: PIN_32_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_32_FUNCTION_TYPE: - attributes: - id: PIN_32_FUNCTION_TYPE - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG15: - attributes: - id: PORT_GROUP_0_PINCFG15 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_15_USED: - attributes: - id: PORT_GROUP_0_PIN_15_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_32_INEN: - attributes: - id: PIN_32_INEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_32_DIR: - attributes: - id: PIN_32_DIR - children: - - children: - - attributes: - value: Out - type: User - type: Values - type: String - PORT_GROUP_0_PAD_15: - attributes: - id: PORT_GROUP_0_PAD_15 - children: - - children: - - attributes: - id: core - value: PA15 - type: Dynamic - type: Values - type: String - PIN_32_PERIPHERAL_FUNCTION: - attributes: - id: PIN_32_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: GPIO - type: User - type: Values - type: String - PIN_32_FUNCTION_NAME: - attributes: - id: PIN_32_FUNCTION_NAME - children: - - children: - - attributes: - value: STB - type: User - type: Values - type: String - PIN_31_PULLEN: - attributes: - id: PIN_31_PULLEN - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_31_DRVSTR: - attributes: - id: PIN_31_DRVSTR - children: - - children: - - attributes: - value: '0' - type: User - type: Values - type: KeyValueSet - PORT_GROUP_0_PINCFG21: - attributes: - id: PORT_GROUP_0_PINCFG21 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_21_USED: - attributes: - id: PORT_GROUP_0_PIN_21_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX10: - attributes: - id: PORT_GROUP_0_PMUX10 - children: - - children: - - attributes: - id: core - value: '0x0' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_21: - attributes: - id: PORT_GROUP_0_PAD_21 - children: - - children: - - attributes: - id: core - value: PA21 - type: Dynamic - type: Values - type: String - PIN_42_PERIPHERAL_FUNCTION: - attributes: - id: PIN_42_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_45_MODE: - attributes: - id: PIN_45_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_45_FUNCTION_TYPE: - attributes: - id: PIN_45_FUNCTION_TYPE - children: - - children: - - attributes: - value: CAN0_TX - type: User - type: Values - type: String - PORT_GROUP_0_PINCFG24: - attributes: - id: PORT_GROUP_0_PINCFG24 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_24_USED: - attributes: - id: PORT_GROUP_0_PIN_24_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PORT_GROUP_0_PMUX12: - attributes: - id: PORT_GROUP_0_PMUX12 - children: - - children: - - attributes: - id: core - value: '0x66' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PAD_24: - attributes: - id: PORT_GROUP_0_PAD_24 - children: - - children: - - attributes: - id: core - value: PA24 - type: Dynamic - type: Values - type: String - PIN_45_PERIPHERAL_FUNCTION: - attributes: - id: PIN_45_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - PIN_46_MODE: - attributes: - id: PIN_46_MODE - children: - - children: - - attributes: - value: '' - type: User - type: Values - type: String - PIN_46_FUNCTION_TYPE: - attributes: - id: PIN_46_FUNCTION_TYPE - children: - - children: - - attributes: - value: CAN0_RX - type: User - type: Values - type: String - PORT_GROUP_0_PAD_25: - attributes: - id: PORT_GROUP_0_PAD_25 - children: - - children: - - attributes: - id: core - value: PA25 - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PINCFG25: - attributes: - id: PORT_GROUP_0_PINCFG25 - children: - - children: - - attributes: - id: core - value: '0x1' - type: Dynamic - type: Values - type: String - PORT_GROUP_0_PIN_25_USED: - attributes: - id: PORT_GROUP_0_PIN_25_USED - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - PIN_46_PERIPHERAL_FUNCTION: - attributes: - id: PIN_46_PERIPHERAL_FUNCTION - children: - - children: - - attributes: - value: G - type: User - type: Values - type: String - RTC_INTERRUPT_ENABLE_UPDATE: - attributes: - id: RTC_INTERRUPT_ENABLE_UPDATE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_ENABLE: - attributes: - id: NVIC_2_0_ENABLE - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - RTC_INTERRUPT_ENABLE: - attributes: - id: RTC_INTERRUPT_ENABLE - children: - - children: - - attributes: - id: rtc - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_HANDLER_LOCK: - attributes: - id: NVIC_2_0_HANDLER_LOCK - children: - - children: - - attributes: - id: core - value: 'true' - type: Dynamic - type: Values - type: Boolean - RTC_INTERRUPT_HANDLER_LOCK: - attributes: - id: RTC_INTERRUPT_HANDLER_LOCK - children: - - children: - - attributes: - id: rtc - value: 'true' - type: Dynamic - type: Values - type: Boolean - NVIC_2_0_HANDLER: - attributes: - id: NVIC_2_0_HANDLER - children: - - children: - - attributes: - id: core - value: RTC_InterruptHandler - type: Dynamic - type: Values - type: String - RTC_INTERRUPT_HANDLER: - attributes: - id: RTC_INTERRUPT_HANDLER - children: - - children: - - attributes: - id: rtc - value: RTC_InterruptHandler - type: Dynamic - type: Values - type: String - userData: - children: - - attributes: - canvasHeight: '0' - canvasWidth: '0' - type: GraphSettings - - children: - - attributes: - id: profile0 - name: Main - type: Profile - type: PowerProfiles - type: UserData diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/dfp.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/dfp.yml deleted file mode 100644 index 5feb0638..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/dfp.yml +++ /dev/null @@ -1,31 +0,0 @@ -configVersion: 1.0.0 -componentName: dfp -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: dfp - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: dfp - x: '520' - y: '11' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/evsys.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/evsys.yml deleted file mode 100644 index a2ae033c..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/evsys.yml +++ /dev/null @@ -1,31 +0,0 @@ -configVersion: 1.0.0 -componentName: evsys -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: evsys - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: evsys - x: '202' - y: '10' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/nvmctrl.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/nvmctrl.yml deleted file mode 100644 index 1079fff4..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/nvmctrl.yml +++ /dev/null @@ -1,31 +0,0 @@ -configVersion: 1.0.0 -componentName: nvmctrl -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: nvmctrl - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: nvmctrl - x: '339' - y: '7' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: {} - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/rtc.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/rtc.yml deleted file mode 100644 index cae31175..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/rtc.yml +++ /dev/null @@ -1,51 +0,0 @@ -configVersion: 1.0.0 -componentName: rtc -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: rtc - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: rtc - x: '496' - y: '340' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - RTC_MODE0_MATCHCLR: - attributes: - id: RTC_MODE0_MATCHCLR - children: - - children: - - attributes: - value: 'true' - type: User - type: Values - type: Boolean - RTC_MODE0_TIMER_COMPARE: - attributes: - id: RTC_MODE0_TIMER_COMPARE - children: - - children: - - attributes: - value: '257' - type: User - type: Values - type: Hex - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom0.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom0.yml deleted file mode 100644 index 018fb294..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom0.yml +++ /dev/null @@ -1,340 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom0 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom0 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom0 - x: '538' - y: '152' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom0 - value: '232' - type: Dynamic - type: Values - type: Hex - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom0 - value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - SERCOM_SPIM_COMMON_HEADER: - attributes: - id: SERCOM_SPIM_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_HEADER: - attributes: - id: SERCOM_SPIM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_SPIM_SOURCE: - attributes: - id: SERCOM_SPIM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_7816_HEADER: - attributes: - id: SERCOM_USART_7816_HEADER - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_7816_SOURCE: - attributes: - id: SERCOM_USART_7816_SOURCE - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '23' - type: Dynamic - type: Values - type: Integer - SPI_CLOCK_PHASE: - attributes: - id: SPI_CLOCK_PHASE - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - SPI_DIPO: - attributes: - id: SPI_DIPO - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '1' - type: User - type: Values - type: KeyValueSet - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom0 - value: '&(SERCOM0_REGS->SPIM.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - USART_7816_BAUD_VALUE: - attributes: - id: USART_7816_BAUD_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '14' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom0 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_DATA_BITS: - attributes: - id: USART_DATA_BITS - children: - - children: - - attributes: - id: sercom0 - value: DRV_USART_DATA_8_BIT - type: Dynamic - type: Values - type: String - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom0 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom0 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom0 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom0 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom0 - value: 'false' - type: Dynamic - type: Values - type: Boolean - SPI_DOPO: - attributes: - id: SPI_DOPO - children: - - children: - - attributes: - id: visible - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - value: '3' - type: User - type: Values - type: KeyValueSet - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom1.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom1.yml deleted file mode 100644 index 342a2f30..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom1.yml +++ /dev/null @@ -1,308 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom1 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom1 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: {} - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom1 - x: '368' - y: '153' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom1 - value: '232' - type: Dynamic - type: Values - type: Hex - I2C_CLOCK_SPEED_HZ: - attributes: - id: I2C_CLOCK_SPEED_HZ - children: - - children: - - attributes: - id: sercom1 - value: '100000' - type: Dynamic - type: Values - type: Integer - I2C_SCLSM: - attributes: - id: I2C_SCLSM - children: - - children: - - attributes: - id: sercom1 - value: '0' - type: Dynamic - type: Values - type: Integer - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom1 - value: '' - type: Dynamic - type: Values - type: String - SERCOM_I2CM_HEADER: - attributes: - id: SERCOM_I2CM_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_I2CM_MASTER_HEADER: - attributes: - id: SERCOM_I2CM_MASTER_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_I2CM_SOURCE: - attributes: - id: SERCOM_I2CM_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - value: '2' - type: User - type: Values - type: KeyValueSet - SERCOM_USART_7816_HEADER: - attributes: - id: SERCOM_USART_7816_HEADER - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_7816_SOURCE: - attributes: - id: SERCOM_USART_7816_SOURCE - children: - - children: - - attributes: - id: source - children: - - type: Value - type: String - type: Attributes - type: File - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '23' - type: Dynamic - type: Values - type: Integer - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom1 - value: '' - type: Dynamic - type: Values - type: String - USART_7816_BAUD_VALUE: - attributes: - id: USART_7816_BAUD_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '14' - type: Dynamic - type: Values - type: Integer - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom1 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_DATA_BITS: - attributes: - id: USART_DATA_BITS - children: - - children: - - attributes: - id: sercom1 - value: DRV_USART_DATA_8_BIT - type: Dynamic - type: Values - type: String - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom1 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom1 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom1 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom1 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom1 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom4.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom4.yml deleted file mode 100644 index a1b862a5..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/sercom4.yml +++ /dev/null @@ -1,275 +0,0 @@ -configVersion: 1.0.0 -componentName: sercom4 -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: sercom4 - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: - children: - - children: - - attributes: - id: SERCOM4_I2C - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: DirectCapability - - attributes: - id: SERCOM4_SPI - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'false' - type: Boolean - type: Attributes - type: DirectCapability - - attributes: - id: SERCOM4_UART - children: - - children: - - attributes: - id: targetComponentID - children: - - type: Value - value: stdio - type: String - - attributes: - id: targetAttachmentID - children: - - type: Value - value: UART - type: String - type: Attributes - type: DirectCapability - type: Attachments - type: sercom4 - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: sercom4 - x: '67' - y: '340' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - I2CM_BAUD: - attributes: - id: I2CM_BAUD - children: - - children: - - attributes: - id: sercom4 - value: '232' - type: Dynamic - type: Values - type: Hex - RECEIVE_DATA_REGISTER: - attributes: - id: RECEIVE_DATA_REGISTER - children: - - children: - - attributes: - id: sercom4 - value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - SERCOM_MODE: - attributes: - id: SERCOM_MODE - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - id: sercom4 - value: '0' - type: Dynamic - type: Values - type: KeyValueSet - SERCOM_USART_COMMON_HEADER: - attributes: - id: SERCOM_USART_COMMON_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_HEADER: - attributes: - id: SERCOM_USART_HEADER - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SERCOM_USART_SOURCE: - attributes: - id: SERCOM_USART_SOURCE - children: - - children: - - attributes: - id: enabled - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - type: File - SPI_BAUD_REG_VALUE: - attributes: - id: SPI_BAUD_REG_VALUE - children: - - children: - - attributes: - id: sercom4 - value: '23' - type: Dynamic - type: Values - type: Integer - TRANSMIT_DATA_REGISTER: - attributes: - id: TRANSMIT_DATA_REGISTER - children: - - children: - - attributes: - id: sercom4 - value: '&(SERCOM3_REGS->USART_INT.SERCOM_DATA)' - type: Dynamic - type: Values - type: String - USART_BAUD_VALUE: - attributes: - id: USART_BAUD_VALUE - children: - - children: - - attributes: - id: sercom4 - value: '63019' - type: Dynamic - type: Values - type: Integer - USART_INTERRUPT_MODE_ENABLE: - attributes: - id: USART_INTERRUPT_MODE_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_LIN_MASTER_SUPPORTED: - attributes: - id: USART_LIN_MASTER_SUPPORTED - children: - - children: - - attributes: - id: sercom4 - value: 'true' - type: Dynamic - type: Values - type: Boolean - USART_OPERATING_MODE: - attributes: - id: USART_OPERATING_MODE - children: - - children: - - attributes: - id: readOnly - children: - - type: Value - value: 'true' - type: Boolean - type: Attributes - - children: - - attributes: - id: sercom4 - value: '0' - type: Dynamic - type: Values - type: KeyValueSet - USART_RING_BUFFER_MODE_ENABLE: - attributes: - id: USART_RING_BUFFER_MODE_ENABLE - children: - - children: - - attributes: - id: sercom4 - value: 'false' - type: Dynamic - type: Values - type: Boolean - USART_SAMPLE_COUNT: - attributes: - id: USART_SAMPLE_COUNT - children: - - children: - - attributes: - id: sercom4 - value: '16' - type: Dynamic - type: Values - type: Integer - USART_SAMPLE_RATE: - attributes: - id: USART_SAMPLE_RATE - children: - - children: - - attributes: - id: sercom4 - value: '0' - type: Dynamic - type: Values - type: Integer - USART_USE_FRACTIONAL_BAUD: - attributes: - id: USART_USE_FRACTIONAL_BAUD - children: - - children: - - attributes: - id: sercom4 - value: 'false' - type: Dynamic - type: Values - type: Boolean - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/stdio.yml b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/stdio.yml deleted file mode 100644 index 5f8be0f2..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/components/stdio.yml +++ /dev/null @@ -1,64 +0,0 @@ -configVersion: 1.0.0 -componentName: stdio -coreVersion: 5.8.4 -device: ATSAMC21E18A -library: [] -dependency: -- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule - name: stdio - type: module - version: '' -- dependencyPackage: '' - name: csp - type: package - version: v3.23.0 -customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData -data: - attachments: - children: - - children: - - attributes: - id: UART - children: - - children: - - attributes: - id: targetComponentID - children: - - type: Value - value: sercom4 - type: String - - attributes: - id: targetAttachmentID - children: - - type: Value - value: SERCOM4_UART - type: String - type: Attributes - type: DirectDependency - type: Attachments - type: stdio - elementPosition: - attributes: - id: __ROOTVIEW - children: - - children: - - attributes: - id: stdio - x: '307' - y: '339' - type: ElementPosition - type: ElementPositions - type: ComponentGraph - symbols: - DEBUG_PERIPHERAL: - attributes: - id: DEBUG_PERIPHERAL - children: - - children: - - attributes: - id: stdio - value: sercom4 - type: Dynamic - type: Values - type: String - userData: {} diff --git a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/mcc-config.mc4 b/bms/bms/bms_config_e18a/mcc/bms_config_default_default/mcc-config.mc4 deleted file mode 100644 index 2fbc2909..00000000 --- a/bms/bms/bms_config_e18a/mcc/bms_config_default_default/mcc-config.mc4 +++ /dev/null @@ -1,287 +0,0 @@ -configVersion: 1.0.0 -coreVersion: 5.8.4 -spaHostVersion: 1.2.1 -device: ATSAMC21E18A -deviceLibrary: {} -groupModules: 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Please do not edit this file. - -manifest_file_version: 1.0.0 -project: bms_config_default -creation_date: 2026-03-10T17:53:08.181+01:00[Europe/Oslo] -operating_system: Linux -mcc_mode: VSCodePlugin -mcc_mode_version: Unknown -device_name: ATSAMC21E18A -compiler: N/A -mcc_version: 5.6.4 -mcc_core_version: 5.8.4 -content_manager_version: 6.0.4 -is_mcc_offline: false -is_using_prerelease_versions: false -mcc_content_registries: https://registry.npmjs.org/ -device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, - version: Bundled} -packs: {name: SAMC21_DFP, version: 3.8.119} -modules: -- {name: csp, type: HARMONY, version: v3.23.0} diff --git a/bms/bms/bms_config_e18a/mcc/mcc-manifest-generated-success.yml b/bms/bms/bms_config_e18a/mcc/mcc-manifest-generated-success.yml deleted file mode 100644 index 3d34223a..00000000 --- a/bms/bms/bms_config_e18a/mcc/mcc-manifest-generated-success.yml +++ /dev/null @@ -1,21 +0,0 @@ -# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. - -manifest_file_version: 1.0.0 -project: bms_config_default -creation_date: 2026-03-10T17:53:08.146+01:00[Europe/Oslo] -operating_system: Linux -mcc_mode: VSCodePlugin -mcc_mode_version: Unknown -device_name: ATSAMC21E18A -compiler: N/A -mcc_version: 5.6.4 -mcc_core_version: 5.8.4 -content_manager_version: 6.0.4 -is_mcc_offline: false -is_using_prerelease_versions: false -mcc_content_registries: https://registry.npmjs.org/ -device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, - version: Bundled} -packs: {name: SAMC21_DFP, version: 3.8.119} -modules: -- {name: csp, type: HARMONY, version: v3.23.0} diff --git a/bms/bms/bms_config_e18a/mcc/mcc.vscode b/bms/bms/bms_config_e18a/mcc/mcc.vscode deleted file mode 100644 index 23a8857e..00000000 --- a/bms/bms/bms_config_e18a/mcc/mcc.vscode +++ /dev/null @@ -1,11 +0,0 @@ -# This file has been autogenerated by MCC. Please do not edit this file. - -configName: bms_config -fileVersion: 1.0.0 -device: ATSAMC21E18A -associatedIDEProjects: - MPLAB: - - name: bms_config_e18a - path: ../../.vscode - config: default - device: ATSAMC21E18A diff --git a/bms/bms/bms_config_e18a/src/app/can_facade.c b/bms/bms/bms_config_e18a/src/app/can_facade.c deleted file mode 100644 index 4cf68592..00000000 --- a/bms/bms/bms_config_e18a/src/app/can_facade.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - Platform: - ATSAMC21 - - Company: - Vortex NTNU. - - Author: - Markus Sandvik - - File Name: - can_facade.c - */ - -#include "definitions.h" -#include "peripheral/port/plib_port.h" -#include "can_facade.h" - - /* ===== RX variables ===== */ - volatile bool rxReady = false; - - uint32_t rx_messageID = 0; - uint8_t rx_message[64] = {0}; - uint8_t rx_messageLength = 0; - uint16_t timestamp = 0; - - static CAN_MSG_RX_FRAME_ATTRIBUTE msgFrameAttr = CAN_MSG_RX_DATA_FRAME; - - /* ===== CAN RAM ===== */ - static bool s_ram_bound = false; - static uint8_t s_can_msg_ram[CAN0_MESSAGE_RAM_CONFIG_SIZE]; - - /* ===== ISR callback ===== */ - void APP_CAN_Callback(uintptr_t context) - { - (void)context; - - rxReady = true; - - - - /* Re-arm RX */ - CAN0_MessageReceive(&rx_messageID, - &rx_messageLength, - rx_message, - ×tamp, - CAN_MSG_ATTR_RX_FIFO0, - &msgFrameAttr); - } - - /* ===== Init ===== */ - void CAN_Init(void) - { - - STB_OutputEnable(); - STB_Clear(); - ////////////////////// - - if (!s_ram_bound) - { - CAN0_MessageRAMConfigSet(s_can_msg_ram); // Bind the CAN message RAM to the driver - s_ram_bound = true; - } - - CAN0_RxCallbackRegister(APP_CAN_Callback, (uintptr_t)NULL, CAN_MSG_ATTR_RX_FIFO0); - - CAN0_MessageReceive(&rx_messageID, - &rx_messageLength, - rx_message, - ×tamp, - CAN_MSG_ATTR_RX_FIFO0, - &msgFrameAttr); - } - - /* ===== Send ===== */ - bool CAN_Send(uint32_t id, uint8_t *data, uint8_t len) - { - const CAN_MODE mode = CAN_MODE_FD_WITHOUT_BRS; - const CAN_MSG_TX_ATTRIBUTE attr = CAN_MSG_ATTR_TX_FIFO_DATA_FRAME; - - return CAN0_MessageTransmit(id, len, data, mode, attr); - } \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/app/can_facade.h b/bms/bms/bms_config_e18a/src/app/can_facade.h deleted file mode 100644 index 112829eb..00000000 --- a/bms/bms/bms_config_e18a/src/app/can_facade.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - Platform: - ATSAMC21 - - Company: - Vortex NTNU. - - Author: - Markus Sandvik - - File Name: - can_facade.h - */ - - #ifndef CAN_FACADE_H - #define CAN_FACADE_H - - #pragma once - #include - #include - #include "definitions.h" - - #ifdef __cplusplus - extern "C" { - #endif - - void CAN_Init(void); - bool CAN_Send(uint32_t id, uint8_t *data, uint8_t len); - void APP_CAN_Callback(uintptr_t context); - - - #ifdef __cplusplus - } - #endif - - #endif // CAN_FACADE_H - \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/app/can_telemetry.c b/bms/bms/bms_config_e18a/src/app/can_telemetry.c deleted file mode 100644 index 56fa21b7..00000000 --- a/bms/bms/bms_config_e18a/src/app/can_telemetry.c +++ /dev/null @@ -1,83 +0,0 @@ -#include "app/can_telemetry.h" -#include "app/can_facade.h" -#include "ic_bms/bms_spi.h" -#include -#include - - - -static volatile bool flag_vol_tx = false; -static volatile bool flag_temp_tx = false; - -void CAN_telemetry_init(void) -{ - flag_vol_tx = false; // Initialize voltage transmission flag -} - -void CAN_telemetry_tickISR(void) // Call this function every 100ms from a timer interrupt -{ - flag_vol_tx = true; - flag_temp_tx = true; // Set temperature transmission flag -} - -void CAN_voltage_send(void) -{ - uint16_t cell_mV[CELLS_COUNT] = {0}; - uint8_t payload[CELLS_PAYLOAD_LEN]; - uint8_t i; - bool ok; - - if (!flag_vol_tx) - return; - - flag_vol_tx = false; - - ok = read_cells_1to6(cell_mV); - if (!ok) - { - //handle read error - } - - for (i = 0; i < CELLS_COUNT; i++) - { - payload[2 * i] = (uint8_t)(cell_mV[i] & 0xFF); - payload[2 * i + 1] = (uint8_t)((cell_mV[i] >> 8) & 0xFF); - } - - ok = CAN_Send(CAN_VOLTAGE_ID, payload, CELLS_PAYLOAD_LEN); - if (!ok) - { - //handle send error - } -} -void CAN_temp_send(void) -{ - int16_t t1_dC, t2_dC, t3_dC; - uint8_t payload[6]; - bool ok; - - if (!flag_temp_tx) - return; - - flag_temp_tx = false; - - bms_read_ts_temp(TS1_TEMP, &t1_dC); - bms_read_ts_temp(TS2_TEMP, &t2_dC); - bms_read_ts_temp(TS3_TEMP, &t3_dC); - - //Divides temp data into 6 payloads (2 bytes per temp) and sends over CAN - payload[0] = (uint8_t)(t1_dC & 0xFF); - payload[1] = (uint8_t)((t1_dC >> 8) & 0xFF); - payload[2] = (uint8_t)(t2_dC & 0xFF); - payload[3] = (uint8_t)((t2_dC >> 8) & 0xFF); - payload[4] = (uint8_t)(t3_dC & 0xFF); - payload[5] = (uint8_t)((t3_dC >> 8) & 0xFF); - - ok = CAN_Send(CAN_TEMP_ID, payload, sizeof(payload)); - if (!ok) - { - //handle send error - } - - -} diff --git a/bms/bms/bms_config_e18a/src/app/can_telemetry.h b/bms/bms/bms_config_e18a/src/app/can_telemetry.h deleted file mode 100644 index ce6bd8a3..00000000 --- a/bms/bms/bms_config_e18a/src/app/can_telemetry.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef CAN_TELEMETRY_H -#define CAN_TELEMETRY_H - -#define CELLS_COUNT 6 -#define CELLS_PAYLOAD_LEN 12 -#define CAN_ID_BOTHOFF_CMD 0x200 //EXAMPLE VALUE -#define BOTHOFF_CMD_BYTE 0xA5 -#define CAN_TEMP_ID 0x100 //EXAMPLE VALUE -#define CAN_VOLTAGE_ID 0x101 //EXAMPLE VALUE - -//legg til func for current, pressure, standbymode, reset mcu - -#define CAN_PRESSURE_ID 0x102 //EXAMPLE VALUE -#define CAN_STANDBYMODE_ID 0x103 //EXAMPLE VALUE -#define CAN_RST_MCU 0x104 //EXAMPLE VALUE -#define CAN_CURRENT_ID 0x105 //EXAMPLE VALUE - - -void CAN_telemetry_init(void); -void CAN_telemetry_tickISR(void); // call from timer/RTC callback -void CAN_voltage_send(void); // call from main loop -void CAN_temp_send(void); - - - -#endif diff --git a/bms/bms/bms_config_e18a/src/app/pwr_mode.c b/bms/bms/bms_config_e18a/src/app/pwr_mode.c deleted file mode 100644 index 80f50126..00000000 --- a/bms/bms/bms_config_e18a/src/app/pwr_mode.c +++ /dev/null @@ -1,51 +0,0 @@ -#include "app/pwr_mode.h" -#include "definitions.h" -#include "sam.h" - -static pwr_mode_state_t g_pwr_state= PWR_MODE_ACTIVE; - - -void pwr_mode_init(void) -{ - /* Start in the lightest sleep mode */ - pwr_set_idle0(); -} - -void pwr_set_idle0(void) -{ - - PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_IDLE0; - - while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != - PM_SLEEPCFG_SLEEPMODE_IDLE0) - { - } -} - -void pwr_set_stb_lowpower(void) -{ - /* Enter MCU standby; wake-up comes from an enabled interrupt. */ - PM_REGS->PM_STDBYCFG = PM_STDBYCFG_VREGSMOD_LP; - PM_REGS->PM_SLEEPCFG = PM_SLEEPCFG_SLEEPMODE_STANDBY; - - while ((PM_REGS->PM_SLEEPCFG & PM_SLEEPCFG_SLEEPMODE_Msk) != - PM_SLEEPCFG_SLEEPMODE_STANDBY) - { - } -} - -void pwr_enter_sleep(void) -{ - /* Sleep until the next interrupt. */ - __WFI(); // Wait For Interrupt instruction to enter sleep mode - //not sure if correct method -} - -void pwr_set_state(pwr_mode_state_t state){ - g_pwr_state = state; // Update the global state variable -} - -pwr_mode_state_t pwr_get_state(void) -{ - return g_pwr_state; // Return the current power mode state -} diff --git a/bms/bms/bms_config_e18a/src/app/pwr_mode.h b/bms/bms/bms_config_e18a/src/app/pwr_mode.h deleted file mode 100644 index f0abef31..00000000 --- a/bms/bms/bms_config_e18a/src/app/pwr_mode.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef PWR_MODE_H -#define PWR_MODE_H - -typedef enum{ - PWR_MODE_ACTIVE=0, - PWR_MODE_STANDBY=1 -} pwr_mode_state_t; - -void pwr_mode_init(void); -void pwr_set_idle0(void); -void pwr_set_stb_lowpower(void); -void pwr_enter_sleep(void); - -void pwr_set_state(pwr_mode_state_t state); -pwr_mode_state_t pwr_get_state(void); - -#endif \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/app/state_machine.c b/bms/bms/bms_config_e18a/src/app/state_machine.c deleted file mode 100644 index 456f7db7..00000000 --- a/bms/bms/bms_config_e18a/src/app/state_machine.c +++ /dev/null @@ -1,118 +0,0 @@ -#include "app/state_machine.h" - -#include -#include - -#include "definitions.h" -#include "app/can_telemetry.h" -#include "app/pwr_mode.h" -#include "peripheral/port/plib_port.h" -#include "app/can_facade.h" -#include "ic_bms/bms_spi.h" - -extern volatile bool rxReady; -extern uint32_t rx_messageID; -extern uint8_t rx_message[64]; -extern uint8_t rx_messageLength; - -static volatile bool s_can_wake_irq = false; -static volatile uint32_t s_rtc_tick = 0U; -static uint32_t s_last_can_tick = 0U; - -#define STBY_TO_TICKS 6000U - -void sm_init(void) -{ - s_rtc_tick = 0U; - s_last_can_tick = 0U; - s_can_wake_irq = false; -} - -void sm_on_can_wake(void) -{ - s_can_wake_irq = true; -} - -void sm_on_rtc_tick(void) -{ - s_rtc_tick++; -} - -void state_machine(void) -{ - switch (pwr_get_state()) - { - case PWR_MODE_ACTIVE: - { - uint32_t now; - bool can_alive = s_can_wake_irq; - - CAN_voltage_send(); - CAN_temp_send(); - now = s_rtc_tick; - - if (rxReady) - { - uint32_t id = rx_messageID; - uint8_t len = rx_messageLength; - uint8_t b0 = (len > 0U) ? rx_message[0] : 0U; - - rxReady = false; - can_alive = true; - - switch (id) - { - case CAN_ID_BOTHOFF_CMD: - if ((len > 0U) && (b0 == BOTHOFF_CMD_BYTE)) - { - bothoff_high(); - } - break; - - case CAN_RST_MCU: - NVIC_SystemReset(); - break; - - default: - break; - } - } - - if (can_alive) - { - s_last_can_tick = now; - s_can_wake_irq = false; - } - - if ((uint32_t)(now - s_last_can_tick) >= STBY_TO_TICKS) // Check if the time since the last CAN activity exceeds the threshold - { - STB_Set(); - pwr_set_stb_lowpower(); - pwr_set_state(PWR_MODE_STANDBY); - } - break; - } - - case PWR_MODE_STANDBY: - if (s_can_wake_irq) - { - s_can_wake_irq = false; - s_last_can_tick = s_rtc_tick; - - STB_Clear(); - pwr_set_idle0(); - CAN_Init(); - pwr_set_state(PWR_MODE_ACTIVE); - } - break; - - default: - s_last_can_tick = s_rtc_tick; - STB_Clear(); - pwr_set_idle0(); - pwr_set_state(PWR_MODE_ACTIVE); - break; - } - - pwr_enter_sleep(); -} diff --git a/bms/bms/bms_config_e18a/src/app/state_machine.h b/bms/bms/bms_config_e18a/src/app/state_machine.h deleted file mode 100644 index 7ce3cd11..00000000 --- a/bms/bms/bms_config_e18a/src/app/state_machine.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef STATE_MACHINE_H -#define STATE_MACHINE_H - -void sm_init(void); -void state_machine(void); -void sm_on_can_wake(void); -void sm_on_rtc_tick(void); - -#endif diff --git a/bms/bms/bms_config_e18a/src/config/default/ATSAMC21E18A.ld b/bms/bms/bms_config_e18a/src/config/default/ATSAMC21E18A.ld deleted file mode 100644 index 6e2de873..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/ATSAMC21E18A.ld +++ /dev/null @@ -1,241 +0,0 @@ -/*-------------------------------------------------------------------------- - * MPLAB XC32 Compiler - ATSAMC21E18A linker script - * - * Copyright (c) 2022, Microchip Technology Inc. and its subsidiaries ("Microchip") - * All rights reserved. - * - * This software is developed by Microchip Technology Inc. and its - * subsidiaries ("Microchip"). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. Microchip's name may not be used to endorse or promote products - * derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* - * Define the __XC32_RESET_HANDLER_NAME macro on the command line when you - * want to use a different name for the Reset Handler function. - */ -#ifndef __XC32_RESET_HANDLER_NAME -#define __XC32_RESET_HANDLER_NAME Reset_Handler -#endif /* __XC32_RESET_HANDLER_NAME */ - -/* Set the entry point in the ELF file. Once the entry point is in the ELF - * file, you can then use the --write-sla option to xc32-bin2hex to place - * the address into the hex file using the SLA field (RECTYPE 5). This hex - * record may be useful for a bootloader that needs to determine the entry - * point to the application. - */ -ENTRY(__XC32_RESET_HANDLER_NAME) - -/************************************************************************* - * Memory-Region Macro Definitions - * The XC32 linker preprocesses linker scripts. You may define these - * macros in the MPLAB X project properties or on the command line when - * calling the linker via the xc32-gcc shell. - *************************************************************************/ - -#ifndef ROM_ORIGIN -# define ROM_ORIGIN 0x0 -#endif -#ifndef ROM_LENGTH -# define ROM_LENGTH 0x40000 -#elif (ROM_LENGTH > 0x40000) -# error ROM_LENGTH is greater than the max size of 0x40000 -#endif -#ifndef RAM_ORIGIN -# define RAM_ORIGIN 0x20000000 -#endif -#ifndef RAM_LENGTH -# define RAM_LENGTH 0x8000 -#elif (RAM_LENGTH > 0x8000) -# error RAM_LENGTH is greater than the max size of 0x8000 -#endif - - -/************************************************************************* - * Memory-Region Definitions - * The MEMORY command describes the location and size of blocks of memory - * on the target device. The command below uses the macros defined above. - *************************************************************************/ -MEMORY -{ - rom (LRX) : ORIGIN = ROM_ORIGIN, LENGTH = ROM_LENGTH - ram (WX!R) : ORIGIN = RAM_ORIGIN, LENGTH = RAM_LENGTH - config_00804000 : ORIGIN = 0x00804000, LENGTH = 0x4 - config_00804004 : ORIGIN = 0x00804004, LENGTH = 0x4 - -} -/************************************************************************* - * Output region definitions. - * CODE_REGION defines the output region for .text/.rodata. - * DATA_REGION defines the output region for .data/.bss - * VECTOR_REGION defines the output region for .vectors. - * - * CODE_REGION defaults to 'rom', if rom is present (non-zero length), - * and 'ram' otherwise. - * DATA_REGION defaults to 'ram', which must be present. - * VECTOR_REGION defaults to CODE_REGION, unless 'boot_rom' is present. - */ -#ifndef CODE_REGION -# if ROM_LENGTH > 0 -# define CODE_REGION rom -# else -# define CODE_REGION ram -# endif -#endif -#ifndef DATA_REGION -# define DATA_REGION ram -#endif -#ifndef VECTOR_REGION -# define VECTOR_REGION CODE_REGION -#endif - -__rom_end = ORIGIN(rom) + LENGTH(rom); -__ram_end = ORIGIN(ram) + LENGTH(ram); - -/************************************************************************* - * Section Definitions - Map input sections to output sections - *************************************************************************/ -SECTIONS -{ - .config_00804000 : { - KEEP(*(.config_00804000)) - } > config_00804000 - .config_00804004 : { - KEEP(*(.config_00804004)) - } > config_00804004 - - /* - * The linker moves the .vectors section into itcm when itcm is - * enabled via the -mitcm option, but only when this .vectors output - * section exists in the linker script. - */ - .vectors : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.* .vectors_default .vectors_default.*)) - KEEP(*(.isr_vector)) - KEEP(*(.reset*)) - KEEP(*(.after_vectors)) - } > VECTOR_REGION - /* - * Code Sections - Note that standard input sections such as - * *(.text), *(.text.*), *(.rodata), & *(.rodata.*) - * are not mapped here. The best-fit allocator locates them, - * so that input sections may flow around absolute sections - * as needed. - */ - .text : - { - . = ALIGN(4); - *(.glue_7t) *(.glue_7) - *(.gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > CODE_REGION - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > CODE_REGION - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - - /* - * Align here to ensure that the .bss section occupies space up to - * _end. Align after .bss to ensure correct alignment even if the - * .bss section disappears because there are no input sections. - * - * Note that input sections named .bss* are no longer mapped here. - * The best-fit allocator locates them, so that they may flow - * around absolute sections as needed. - */ - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - _sbss = . ; - _szero = .; - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - _ebss = . ; - _ezero = .; - } > DATA_REGION - - . = ALIGN(4); - _end = . ; - _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; - -} - diff --git a/bms/bms/bms_config_e18a/src/config/default/definitions.h b/bms/bms/bms_config_e18a/src/config/default/definitions.h deleted file mode 100644 index 9d8b4e29..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/definitions.h +++ /dev/null @@ -1,147 +0,0 @@ -/******************************************************************************* - System Definitions - - File Name: - definitions.h - - Summary: - project system definitions. - - Description: - This file contains the system-wide prototypes and definitions for a project. - - *******************************************************************************/ - -//DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - *******************************************************************************/ -//DOM-IGNORE-END - -#ifndef DEFINITIONS_H -#define DEFINITIONS_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include -#include -#include -#include "peripheral/sercom/usart/plib_sercom3_usart.h" -#include "peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h" -#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" -#include "peripheral/port/plib_port.h" -#include "peripheral/clock/plib_clock.h" -#include "peripheral/nvic/plib_nvic.h" -#include "peripheral/can/plib_can0.h" -#include "peripheral/eic/plib_eic.h" -#include "peripheral/rtc/plib_rtc.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - -extern "C" { - -#endif -// DOM-IGNORE-END - -/* Device Information */ -#define DEVICE_NAME "ATSAMC21E18A" -#define DEVICE_ARCH "CORTEX-M0PLUS" -#define DEVICE_FAMILY "SAMC" -#define DEVICE_SERIES "SAMC21" - -/* CPU clock frequency */ -#define CPU_CLOCK_FREQUENCY 48000000U - -// ***************************************************************************** -// ***************************************************************************** -// Section: System Functions -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* System Initialization Function - - Function: - void SYS_Initialize( void *data ) - - Summary: - Function that initializes all modules in the system. - - Description: - This function initializes all modules in the system, including any drivers, - services, middleware, and applications. - - Precondition: - None. - - Parameters: - data - Pointer to the data structure containing any data - necessary to initialize the module. This pointer may - be null if no data is required and default initialization - is to be used. - - Returns: - None. - - Example: - - SYS_Initialize ( NULL ); - - while ( true ) - { - SYS_Tasks ( ); - } - - - Remarks: - This function will only be called once, after system reset. -*/ - -void SYS_Initialize( void *data ); - -/* Nullify SYS_Tasks() if only PLIBs are used. */ -#define SYS_Tasks() - -// ***************************************************************************** -// ***************************************************************************** -// Section: extern declarations -// ***************************************************************************** -// ***************************************************************************** - - - - -//DOM-IGNORE-BEGIN -#ifdef __cplusplus -} -#endif -//DOM-IGNORE-END - -#endif /* DEFINITIONS_H */ -/******************************************************************************* - End of File -*/ - diff --git a/bms/bms/bms_config_e18a/src/config/default/device.h b/bms/bms/bms_config_e18a/src/config/default/device.h deleted file mode 100644 index 669c7985..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/device.h +++ /dev/null @@ -1,65 +0,0 @@ -/******************************************************************************* - Device Header File - - Company: - Microchip Technology Inc. - - File Name: - device.h - - Summary: - This file includes the selected device from within the project. - The device will provide access to respective device packs. - - Description: - None - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef DEVICE_H -#define DEVICE_H - -#pragma GCC diagnostic push -#ifndef __cplusplus -#pragma GCC diagnostic ignored "-Wnested-externs" -#endif -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wattributes" -#pragma GCC diagnostic ignored "-Wundef" -#ifndef DONT_USE_PREDEFINED_CORE_HANDLERS - #define DONT_USE_PREDEFINED_CORE_HANDLERS -#endif //DONT_USE_PREDEFINED_CORE_HANDLERS -#ifndef DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -#endif //DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -#include "samc21e18a.h" -#pragma GCC diagnostic pop -#include "device_cache.h" -#include "toolchain_specifics.h" - -#endif //DEVICE_H diff --git a/bms/bms/bms_config_e18a/src/config/default/device_cache.h b/bms/bms/bms_config_e18a/src/config/default/device_cache.h deleted file mode 100644 index 802e5dc5..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/device_cache.h +++ /dev/null @@ -1,94 +0,0 @@ -/******************************************************************************* - Cortex-M L1 Cache Header - - File Name: - device_cache.h - - Summary: - Preprocessor definitions to provide L1 Cache control. - - Description: - An MPLAB PLIB or Project can include this header to perform cache cleans, - invalidates etc. For the DCache and ICache. - - Remarks: - This header should not define any prototypes or data definitions, or - include any files that do. The file only provides macro definitions for - build-time. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef DEVICE_CACHE_H -#define DEVICE_CACHE_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section Includes other configuration headers necessary to completely - define this configuration. -*/ - -#include "device.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - -extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: L1 Cache Configuration -// ***************************************************************************** -// ***************************************************************************** - - -#define ICACHE_ENABLE() -#define ICACHE_DISABLE() -#define ICACHE_INVALIDATE() - -#define DCACHE_ENABLE() -#define DCACHE_DISABLE() -#define DCACHE_INVALIDATE() -#define DCACHE_CLEAN() -#define DCACHE_CLEAN_INVALIDATE() -#define DCACHE_CLEAN_BY_ADDR(addr,sz) -#define DCACHE_INVALIDATE_BY_ADDR(addr,sz) -#define DCACHE_CLEAN_INVALIDATE_BY_ADDR(addr,sz) - -//DOM-IGNORE-BEGIN -#ifdef __cplusplus -} -#endif -//DOM-IGNORE-END - -#endif // #ifndef DEVICE_CACHE_H diff --git a/bms/bms/bms_config_e18a/src/config/default/device_vectors.h b/bms/bms/bms_config_e18a/src/config/default/device_vectors.h deleted file mode 100644 index a584fcdf..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/device_vectors.h +++ /dev/null @@ -1,118 +0,0 @@ -/******************************************************************************* - Cortex-M device vectors file - - Company: - Microchip Technology Inc. - - File Name: - device_vectors.h - - Summary: - Harmony3 device handler structure for cortex-M devices - - Description: - This file contains Harmony3 device handler structure for cortex-M devices - *******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - *******************************************************************************/ -// DOM-IGNORE-END - -#ifndef DEVICE_VECTORS_H -#define DEVICE_VECTORS_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** - -/* Function pointer type for vector handlers */ -typedef void (*pfn_handler_t)(void); - -/* Structure defining device vector types */ -typedef struct H3DeviceVectorsTag -{ - /* Stack pointer */ - uint32_t* pvStack; - - /* CORTEX-M0PLUS handlers */ - pfn_handler_t pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ - pfn_handler_t pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - pfn_handler_t pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ - pfn_handler_t pfnReservedC12; - pfn_handler_t pfnReservedC11; - pfn_handler_t pfnReservedC10; - pfn_handler_t pfnReservedC9; - pfn_handler_t pfnReservedC8; - pfn_handler_t pfnReservedC7; - pfn_handler_t pfnReservedC6; - pfn_handler_t pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ - pfn_handler_t pfnReservedC4; - pfn_handler_t pfnReservedC3; - pfn_handler_t pfnPendSV_Handler; /* -2 Pendable request for system service */ - pfn_handler_t pfnSysTick_Handler; /* -1 System Tick Timer */ - - /* Peripheral handlers */ - pfn_handler_t pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt */ - pfn_handler_t pfnWDT_Handler; /* 1 Watchdog Timer */ - pfn_handler_t pfnRTC_Handler; /* 2 Real Time Counter */ - pfn_handler_t pfnEIC_Handler; /* 3 External Interrupt Controller */ - pfn_handler_t pfnFREQM_Handler; /* 4 Frequency Meter */ - pfn_handler_t pfnTSENS_Handler; /* 5 Temperature Sensor */ - pfn_handler_t pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - pfn_handler_t pfnDMAC_Handler; /* 7 Direct Memory Controller */ - pfn_handler_t pfnEVSYS_Handler; /* 8 Event Systems */ - pfn_handler_t pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - pfn_handler_t pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - pfn_handler_t pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - pfn_handler_t pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - pfn_handler_t pfnReserved13; - pfn_handler_t pfnReserved14; - pfn_handler_t pfnCAN0_Handler; /* 15 Control Area Network 0 */ - pfn_handler_t pfnReserved16; - pfn_handler_t pfnTCC0_Handler; /* 17 Timer/Counter for Control Applications 0 */ - pfn_handler_t pfnTCC1_Handler; /* 18 Timer/Counter for Control Applications 1 */ - pfn_handler_t pfnTCC2_Handler; /* 19 Timer/Counter for Control Applications 2 */ - pfn_handler_t pfnTC0_Handler; /* 20 Timer/Counter 0 */ - pfn_handler_t pfnTC1_Handler; /* 21 Timer/Counter 1 */ - pfn_handler_t pfnTC2_Handler; /* 22 Timer/Counter 2 */ - pfn_handler_t pfnTC3_Handler; /* 23 Timer/Counter 3 */ - pfn_handler_t pfnTC4_Handler; /* 24 Timer/Counter 4 */ - pfn_handler_t pfnADC0_Handler; /* 25 Analog-to-Digital Converter 0 */ - pfn_handler_t pfnADC1_Handler; /* 26 Analog-to-Digital Converter 1 */ - pfn_handler_t pfnAC_Handler; /* 27 Analog Comparators */ - pfn_handler_t pfnDAC_Handler; /* 28 Digital-to-Analog Converter */ - pfn_handler_t pfnSDADC_Handler; /* 29 Sigma-Delat Analog-to-Digital Converter */ - pfn_handler_t pfnPTC_Handler; /* 30 Peripheral Touch Controller */ -}H3DeviceVectors; - -#endif //DEVICE_VECTORS_H diff --git a/bms/bms/bms_config_e18a/src/config/default/exceptions.c b/bms/bms/bms_config_e18a/src/config/default/exceptions.c deleted file mode 100644 index 664dd4ad..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/exceptions.c +++ /dev/null @@ -1,89 +0,0 @@ -/******************************************************************************* - System Exceptions File - - File Name: - exceptions.c - - Summary: - This file contains a function which overrides the default _weak_ exception - handlers provided by the interrupt.c file. - - Description: - This file redefines the default _weak_ exception handler with a more debug - friendly one. If an unexpected exception occurs the code will stop in a - while(1) loop. - *******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include "interrupts.h" -#include "definitions.h" - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Exception Handling Routine -// ***************************************************************************** -// ***************************************************************************** -/* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 8.6 might be violated here if the users provide a strong - implementations to these weak handler functions. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 -*/ - - -/* Brief default interrupt handlers for core IRQs.*/ -void __attribute__((noreturn, weak)) NonMaskableInt_Handler(void) -{ -#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) - __builtin_software_breakpoint(); -#endif - while (true) - { - } -} - -void __attribute__((noreturn, weak)) HardFault_Handler(void) -{ -#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) - __builtin_software_breakpoint(); -#endif - while (true) - { - } -} - - -/* MISRAC 2012 deviation block end for rule 8.6 */ - -/******************************************************************************* - End of File - */ diff --git a/bms/bms/bms_config_e18a/src/config/default/harmony-manifest-success.yml b/bms/bms/bms_config_e18a/src/config/default/harmony-manifest-success.yml deleted file mode 100644 index 6192c769..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/harmony-manifest-success.yml +++ /dev/null @@ -1,21 +0,0 @@ - -# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. -# Project "bms_config_default" has been created by using mentioned Harmony 3 packages - - -project: bms_config_default -creation_date: 2026-03-10T17:53:08.152+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime -operating_system: Linux -mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] -mcc_version: v5.6.4 -mcc_core_version: v5.8.4 -mplabx_version: NA # if MPLAB X plugin only -harmony_version: v5.6.4 -compiler: NA - -modules: - - {name: "csp", version: "v3.23.0"} - -packs: - - {name: "SAMC21_DFP", version: "3.8.119"} - diff --git a/bms/bms/bms_config_e18a/src/config/default/initialization.c b/bms/bms/bms_config_e18a/src/config/default/initialization.c deleted file mode 100644 index 25bf9740..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/initialization.c +++ /dev/null @@ -1,161 +0,0 @@ -/******************************************************************************* - System Initialization File - - File Name: - initialization.c - - Summary: - This file contains source code necessary to initialize the system. - - Description: - This file contains source code necessary to initialize the system. It - implements the "SYS_Initialize" function, defines the configuration bits, - and allocates any necessary global system resources, - *******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - *******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include "definitions.h" -#include "device.h" - - -// **************************************************************************** -// **************************************************************************** -// Section: Configuration Bits -// **************************************************************************** -// **************************************************************************** -#pragma config NVMCTRL_BOOTPROT = SIZE_0BYTES -#pragma config NVMCTRL_EEPROM_SIZE = SIZE_0BYTES -#pragma config BODVDDUSERLEVEL = 0x8U // Enter Hexadecimal value -#pragma config BODVDD_DIS = DISABLED -#pragma config BODVDD_ACTION = NONE - -#pragma config BODVDD_HYST = DISABLED -#pragma config NVMCTRL_REGION_LOCKS = 0xffffU // Enter Hexadecimal value - -#pragma config WDT_ENABLE = DISABLED -#pragma config WDT_ALWAYSON = DISABLED -#pragma config WDT_PER = CYC8 - -#pragma config WDT_WINDOW = CYC8 -#pragma config WDT_EWOFFSET = CYC8 -#pragma config WDT_WEN = DISABLED - - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Driver Initialization Data -// ***************************************************************************** -// ***************************************************************************** -/* Following MISRA-C rules are deviated in the below code block */ -/* MISRA C-2012 Rule 7.2 - Deviation record ID - H3_MISRAC_2012_R_7_2_DR_1 */ -/* MISRA C-2012 Rule 11.1 - Deviation record ID - H3_MISRAC_2012_R_11_1_DR_1 */ -/* MISRA C-2012 Rule 11.3 - Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1 */ -/* MISRA C-2012 Rule 11.8 - Deviation record ID - H3_MISRAC_2012_R_11_8_DR_1 */ - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: System Data -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -// ***************************************************************************** -// Section: Library/Stack Initialization Data -// ***************************************************************************** -// ***************************************************************************** - - -// ***************************************************************************** -// ***************************************************************************** -// Section: System Initialization -// ***************************************************************************** -// ***************************************************************************** - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Local initialization functions -// ***************************************************************************** -// ***************************************************************************** - -/* MISRAC 2012 deviation block end */ - -/******************************************************************************* - Function: - void SYS_Initialize ( void *data ) - - Summary: - Initializes the board, services, drivers, application and other modules. - - Remarks: - */ - -void SYS_Initialize ( void* data ) -{ - - /* MISRAC 2012 deviation block start */ - /* MISRA C-2012 Rule 2.2 deviated in this file. Deviation record ID - H3_MISRAC_2012_R_2_2_DR_1 */ - - - - CLOCK_Initialize(); - - - - - SERCOM3_USART_Initialize(); - - SERCOM1_I2C_Initialize(); - - SERCOM0_SPI_Initialize(); - - CAN0_Initialize(); - - EIC_Initialize(); - - RTC_Initialize(); - - - NVIC_Initialize(); - - - /* MISRAC 2012 deviation block end */ -} - -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/interrupts.c b/bms/bms/bms_config_e18a/src/config/default/interrupts.c deleted file mode 100644 index b5c24153..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/interrupts.c +++ /dev/null @@ -1,160 +0,0 @@ -/******************************************************************************* - System Interrupts File - - Company: - Microchip Technology Inc. - - File Name: - interrupt.c - - Summary: - Interrupt vectors mapping - - Description: - This file maps all the interrupt vectors to their corresponding - implementations. If a particular module interrupt is used, then its ISR - definition can be found in corresponding PLIB source file. If a module - interrupt is not used, then its ISR implementation is mapped to dummy - handler. - *******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - *******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include "device_vectors.h" -#include "interrupts.h" -#include "definitions.h" - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: System Interrupt Vector Functions -// ***************************************************************************** -// ***************************************************************************** - -/* MISRA C-2012 Rule 8.6 deviated below. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ -extern uint32_t _stack; -extern const H3DeviceVectors exception_table; - -extern void Dummy_Handler(void); - -/* Brief default interrupt handler for unused IRQs.*/ -void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(void) -{ - while (true) - { - } -} - -/* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 8.6 deviated 26 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ -/* Device vectors list dummy definition*/ -extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void SysTick_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void SYSTEM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void WDT_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void EIC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void NVMCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void DMAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void EVSYS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void SERCOM2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TCC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TCC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TCC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void TC4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void ADC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void ADC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void AC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void DAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void SDADC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); -extern void PTC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); - - -/* MISRAC 2012 deviation block end */ - -/* Multiple handlers for vector */ - - - -__attribute__ ((section(".vectors"), used)) -const H3DeviceVectors exception_table= -{ - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = &_stack, - - .pfnReset_Handler = Reset_Handler, - .pfnNonMaskableInt_Handler = NonMaskableInt_Handler, - .pfnHardFault_Handler = HardFault_Handler, - .pfnSVCall_Handler = SVCall_Handler, - .pfnPendSV_Handler = PendSV_Handler, - .pfnSysTick_Handler = SysTick_Handler, - .pfnSYSTEM_Handler = SYSTEM_Handler, - .pfnWDT_Handler = WDT_Handler, - .pfnRTC_Handler = RTC_InterruptHandler, - .pfnEIC_Handler = EIC_Handler, - .pfnFREQM_Handler = FREQM_Handler, - .pfnTSENS_Handler = TSENS_Handler, - .pfnNVMCTRL_Handler = NVMCTRL_Handler, - .pfnDMAC_Handler = DMAC_Handler, - .pfnEVSYS_Handler = EVSYS_Handler, - .pfnSERCOM0_Handler = SERCOM0_SPI_InterruptHandler, - .pfnSERCOM1_Handler = SERCOM1_I2C_InterruptHandler, - .pfnSERCOM2_Handler = SERCOM2_Handler, - .pfnSERCOM3_Handler = SERCOM3_USART_InterruptHandler, - .pfnCAN0_Handler = CAN0_InterruptHandler, - .pfnTCC0_Handler = TCC0_Handler, - .pfnTCC1_Handler = TCC1_Handler, - .pfnTCC2_Handler = TCC2_Handler, - .pfnTC0_Handler = TC0_Handler, - .pfnTC1_Handler = TC1_Handler, - .pfnTC2_Handler = TC2_Handler, - .pfnTC3_Handler = TC3_Handler, - .pfnTC4_Handler = TC4_Handler, - .pfnADC0_Handler = ADC0_Handler, - .pfnADC1_Handler = ADC1_Handler, - .pfnAC_Handler = AC_Handler, - .pfnDAC_Handler = DAC_Handler, - .pfnSDADC_Handler = SDADC_Handler, - .pfnPTC_Handler = PTC_Handler, - - -}; - -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/interrupts.h b/bms/bms/bms_config_e18a/src/config/default/interrupts.h deleted file mode 100644 index 11816788..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/interrupts.h +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* - System Interrupts File - - Company: - Microchip Technology Inc. - - File Name: - interrupt.h - - Summary: - Interrupt vectors mapping - - Description: - This file contains declarations of device vectors used by Harmony 3 - *******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - *******************************************************************************/ -// DOM-IGNORE-END - -#ifndef INTERRUPTS_H -#define INTERRUPTS_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Handler Routines -// ***************************************************************************** -// ***************************************************************************** -void Reset_Handler (void); -void NonMaskableInt_Handler (void); -void HardFault_Handler (void); -void RTC_InterruptHandler (void); -void SERCOM0_SPI_InterruptHandler (void); -void SERCOM1_I2C_InterruptHandler (void); -void SERCOM3_USART_InterruptHandler (void); -void CAN0_InterruptHandler (void); - - - -#endif // INTERRUPTS_H diff --git a/bms/bms/bms_config_e18a/src/config/default/libc_syscalls.c b/bms/bms/bms_config_e18a/src/config/default/libc_syscalls.c deleted file mode 100644 index ae819a61..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/libc_syscalls.c +++ /dev/null @@ -1,61 +0,0 @@ -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#include -#include -#include -#include -#include "device.h" /* for ARM CMSIS __BKPT() */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 21.2 deviated twice. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ -/* Harmony specific - * We implement only the syscalls we want over the stubs provided by libpic32c - */ -extern void _exit(int status); - -void _exit(int status) -{ - /* Software breakpoint */ -#ifdef __DEBUG - __BKPT(0); -#endif - - /* halt CPU */ - while (true) - { - } -} - -#ifdef __cplusplus -} -#endif - -/* MISRAC 2012 deviation block end */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.c deleted file mode 100644 index 5b38d23d..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.c +++ /dev/null @@ -1,230 +0,0 @@ -/******************************************************************************* - Analog-to-Digital Converter(ADC0) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_adc0.c - - Summary - ADC0 PLIB Implementation File. - - Description - This file defines the interface to the ADC peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "interrupts.h" -#include "plib_adc0.h" - -// ***************************************************************************** -// ***************************************************************************** -// Section: Global Data -// ***************************************************************************** -// ***************************************************************************** - -#define ADC0_LINEARITY_POS (0U) -#define ADC0_LINEARITY_Msk (0x7UL << ADC0_LINEARITY_POS) - -#define ADC0_BIASCAL_POS (3U) -#define ADC0_BIASCAL_Msk (0x7UL << ADC0_BIASCAL_POS) - - -// ***************************************************************************** -// ***************************************************************************** -// Section: ADC0 Implementation -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* Initialize ADC module */ -void ADC0_Initialize( void ) -{ - /* Reset ADC */ - ADC0_REGS->ADC_CTRLA = (uint8_t)ADC_CTRLA_SWRST_Msk; - - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) - { - /* Wait for Synchronization */ - } - /* Write linearity calibration in BIASREFBUF and bias calibration in BIASCOMP */ - uint32_t calib_low_word = (uint32_t)(*(uint64_t*)OTP5_ADDR); - ADC0_REGS->ADC_CALIB = (uint16_t)((ADC_CALIB_BIASREFBUF((calib_low_word & ADC0_LINEARITY_Msk) >> ADC0_LINEARITY_POS)) | - (ADC_CALIB_BIASCOMP((calib_low_word & ADC0_BIASCAL_Msk) >> ADC0_BIASCAL_POS))); - - /* Prescaler */ - ADC0_REGS->ADC_CTRLB = (uint8_t)ADC_CTRLB_PRESCALER_DIV4; - /* Sampling length */ - ADC0_REGS->ADC_SAMPCTRL = (uint8_t)ADC_SAMPCTRL_SAMPLEN(3UL); - - /* Reference */ - ADC0_REGS->ADC_REFCTRL = (uint8_t)ADC_REFCTRL_REFSEL_INTVCC2 | ADC_REFCTRL_REFCOMP_Msk; - - /* Input pin */ - ADC0_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0; - - /* Resolution & Operation Mode */ - ADC0_REGS->ADC_CTRLC = (uint16_t)(ADC_CTRLC_RESSEL_12BIT | ADC_CTRLC_WINMODE(0UL) ); - - - /* Clear all interrupt flags */ - ADC0_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; - - while(0U != ADC0_REGS->ADC_SYNCBUSY) - { - /* Wait for Synchronization */ - } -} - -/* Enable ADC module */ -void ADC0_Enable( void ) -{ - ADC0_REGS->ADC_CTRLA |= (uint8_t)ADC_CTRLA_ENABLE_Msk; - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Disable ADC module */ -void ADC0_Disable( void ) -{ - ADC0_REGS->ADC_CTRLA &= (uint8_t)(~ADC_CTRLA_ENABLE_Msk); - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Configure channel input */ -void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) -{ - /* Configure pin scan mode and positive and negative input pins */ - ADC0_REGS->ADC_INPUTCTRL = (uint16_t) positiveInput | (uint16_t) negativeInput; - - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Start the ADC conversion by SW */ -void ADC0_ConversionStart( void ) -{ - /* Start conversion */ - ADC0_REGS->ADC_SWTRIG |= (uint8_t)ADC_SWTRIG_START_Msk; - - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Check whether auto sequence conversion is done */ -bool ADC0_ConversionSequenceIsFinished(void) -{ - bool seq_status = false; - if ((ADC0_REGS->ADC_SEQSTATUS & ADC_SEQSTATUS_SEQBUSY_Msk) != ADC_SEQSTATUS_SEQBUSY_Msk) - { - seq_status = true; - } - return seq_status; -} - -/* Configure window comparison threshold values */ -void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) -{ - ADC0_REGS->ADC_WINLT = low_threshold; - ADC0_REGS->ADC_WINUT = high_threshold; - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) - { - /* Wait for Synchronization */ - } - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) - { - /* Wait for Synchronization */ - } -} - -void ADC0_WindowModeSet(ADC_WINMODE mode) -{ - ADC0_REGS->ADC_CTRLC = (ADC0_REGS->ADC_CTRLC & (uint16_t)(~ADC_CTRLC_WINMODE_Msk)) | (uint16_t)((uint32_t)mode << ADC_CTRLC_WINMODE_Pos); - while((ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_CTRLC_Msk) == ADC_SYNCBUSY_CTRLC_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Read the conversion result */ -uint16_t ADC0_ConversionResultGet( void ) -{ - return (uint16_t)ADC0_REGS->ADC_RESULT; -} - -void ADC0_InterruptsClear(ADC_STATUS interruptMask) -{ - ADC0_REGS->ADC_INTFLAG = (uint8_t)interruptMask; -} - -void ADC0_InterruptsEnable(ADC_STATUS interruptMask) -{ - ADC0_REGS->ADC_INTENSET = (uint8_t)interruptMask; -} - -void ADC0_InterruptsDisable(ADC_STATUS interruptMask) -{ - ADC0_REGS->ADC_INTENCLR = (uint8_t)interruptMask; -} - -/* Check whether result is ready */ -bool ADC0_ConversionStatusGet( void ) -{ - bool status; - status = (((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); - if (status == true) - { - ADC0_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_RESRDY_Msk; - } - return status; -} - - diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.h deleted file mode 100644 index 49ca4421..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc0.h +++ /dev/null @@ -1,127 +0,0 @@ -/******************************************************************************* - Analog-to-Digital Converter(ADC0) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_adc0.h - - Summary - ADC0 PLIB Header File. - - Description - This file defines the interface to the ADC peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_ADC0_H // Guards against multiple inclusion -#define PLIB_ADC0_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "device.h" -#include "plib_adc_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -/* The following data type definitions are used by the functions in this - interface and should be considered part it. -*/ - -// ***************************************************************************** - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** -/* The following functions make up the methods (set of possible operations) of - this interface. -*/ - -void ADC0_Initialize( void ); - -void ADC0_Enable( void ); - -void ADC0_Disable( void ); - -void ADC0_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); - -void ADC0_ConversionStart( void ); - -uint16_t ADC0_ConversionResultGet( void ); - -void ADC0_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); - -void ADC0_WindowModeSet(ADC_WINMODE mode); - -bool ADC0_ConversionSequenceIsFinished(void); - -void ADC0_InterruptsClear(ADC_STATUS interruptMask); - -void ADC0_InterruptsEnable(ADC_STATUS interruptMask); - -void ADC0_InterruptsDisable(ADC_STATUS interruptMask); - - -bool ADC0_ConversionStatusGet( void ); - - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif /* PLIB_ADC0_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.c deleted file mode 100644 index 868eff15..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.c +++ /dev/null @@ -1,228 +0,0 @@ -/******************************************************************************* - Analog-to-Digital Converter(ADC1) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_adc1.c - - Summary - ADC1 PLIB Implementation File. - - Description - This file defines the interface to the ADC peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "interrupts.h" -#include "plib_adc1.h" - -// ***************************************************************************** -// ***************************************************************************** -// Section: Global Data -// ***************************************************************************** -// ***************************************************************************** - -#define ADC1_LINEARITY_POS (6U) -#define ADC1_LINEARITY_Msk (0x7UL << ADC1_LINEARITY_POS) - -#define ADC1_BIASCAL_POS (9U) -#define ADC1_BIASCAL_Msk (0x7UL << ADC1_BIASCAL_POS) - - -// ***************************************************************************** -// ***************************************************************************** -// Section: ADC1 Implementation -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* Initialize ADC module */ -void ADC1_Initialize( void ) -{ - /* Reset ADC */ - ADC1_REGS->ADC_CTRLA = (uint8_t)ADC_CTRLA_SWRST_Msk; - - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWRST_Msk) == ADC_SYNCBUSY_SWRST_Msk) - { - /* Wait for Synchronization */ - } - /* Write linearity calibration in BIASREFBUF and bias calibration in BIASCOMP */ - uint32_t calib_low_word = (uint32_t)(*(uint64_t*)OTP5_ADDR); - ADC1_REGS->ADC_CALIB = (uint16_t)((ADC_CALIB_BIASREFBUF((calib_low_word & ADC1_LINEARITY_Msk) >> ADC1_LINEARITY_POS)) | - (ADC_CALIB_BIASCOMP((calib_low_word & ADC1_BIASCAL_Msk) >> ADC1_BIASCAL_POS))); - - /* Prescaler */ - ADC1_REGS->ADC_CTRLB = (uint8_t)ADC_CTRLB_PRESCALER_DIV8; - /* Sampling length */ - ADC1_REGS->ADC_SAMPCTRL = (uint8_t)ADC_SAMPCTRL_SAMPLEN(3UL); - - /* Reference */ - ADC1_REGS->ADC_REFCTRL = (uint8_t)ADC_REFCTRL_REFSEL_INTVCC2 | ADC_REFCTRL_REFCOMP_Msk; - - /* Input pin */ - ADC1_REGS->ADC_INPUTCTRL = (uint16_t) ADC_POSINPUT_AIN0; - - /* Resolution & Operation Mode */ - ADC1_REGS->ADC_CTRLC = (uint16_t)(ADC_CTRLC_RESSEL_12BIT | ADC_CTRLC_WINMODE(0UL) | ADC_CTRLC_FREERUN_Msk); - - - /* Clear all interrupt flags */ - ADC1_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; - - while(0U != ADC1_REGS->ADC_SYNCBUSY) - { - /* Wait for Synchronization */ - } -} - -/* Enable ADC module */ -void ADC1_Enable( void ) -{ - ADC1_REGS->ADC_CTRLA |= (uint8_t)ADC_CTRLA_ENABLE_Msk; - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Disable ADC module */ -void ADC1_Disable( void ) -{ - ADC1_REGS->ADC_CTRLA &= (uint8_t)(~ADC_CTRLA_ENABLE_Msk); - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_ENABLE_Msk) == ADC_SYNCBUSY_ENABLE_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Configure channel input */ -void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ) -{ - /* Configure pin scan mode and positive and negative input pins */ - ADC1_REGS->ADC_INPUTCTRL = (uint16_t) positiveInput | (uint16_t) negativeInput; - - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk) == ADC_SYNCBUSY_INPUTCTRL_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Start the ADC conversion by SW */ -void ADC1_ConversionStart( void ) -{ - /* Start conversion */ - ADC1_REGS->ADC_SWTRIG |= (uint8_t)ADC_SWTRIG_START_Msk; - - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_SWTRIG_Msk) == ADC_SYNCBUSY_SWTRIG_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Check whether auto sequence conversion is done */ -bool ADC1_ConversionSequenceIsFinished(void) -{ - bool seq_status = false; - if ((ADC1_REGS->ADC_SEQSTATUS & ADC_SEQSTATUS_SEQBUSY_Msk) != ADC_SEQSTATUS_SEQBUSY_Msk) - { - seq_status = true; - } - return seq_status; -} - -/* Configure window comparison threshold values */ -void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold) -{ - ADC1_REGS->ADC_WINLT = low_threshold; - ADC1_REGS->ADC_WINUT = high_threshold; - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINLT_Msk) == ADC_SYNCBUSY_WINLT_Msk) - { - /* Wait for Synchronization */ - } - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_WINUT_Msk) == ADC_SYNCBUSY_WINUT_Msk) - { - /* Wait for Synchronization */ - } -} - -void ADC1_WindowModeSet(ADC_WINMODE mode) -{ - ADC1_REGS->ADC_CTRLC = (ADC1_REGS->ADC_CTRLC & (uint16_t)(~ADC_CTRLC_WINMODE_Msk)) | (uint16_t)((uint32_t)mode << ADC_CTRLC_WINMODE_Pos); - while((ADC1_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_CTRLC_Msk) == ADC_SYNCBUSY_CTRLC_Msk) - { - /* Wait for Synchronization */ - } -} - -/* Read the conversion result */ -uint16_t ADC1_ConversionResultGet( void ) -{ - return (uint16_t)ADC1_REGS->ADC_RESULT; -} - -void ADC1_InterruptsClear(ADC_STATUS interruptMask) -{ - ADC1_REGS->ADC_INTFLAG = (uint8_t)interruptMask; -} - -void ADC1_InterruptsEnable(ADC_STATUS interruptMask) -{ - ADC1_REGS->ADC_INTENSET = (uint8_t)interruptMask; -} - -void ADC1_InterruptsDisable(ADC_STATUS interruptMask) -{ - ADC1_REGS->ADC_INTENCLR = (uint8_t)interruptMask; -} - -/* Check whether result is ready */ -bool ADC1_ConversionStatusGet( void ) -{ - bool status; - status = (((ADC1_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) >> ADC_INTFLAG_RESRDY_Pos) != 0U); - if (status == true) - { - ADC1_REGS->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_RESRDY_Msk; - } - return status; -} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.h deleted file mode 100644 index a0fa8afd..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc1.h +++ /dev/null @@ -1,127 +0,0 @@ -/******************************************************************************* - Analog-to-Digital Converter(ADC1) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_adc1.h - - Summary - ADC1 PLIB Header File. - - Description - This file defines the interface to the ADC peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_ADC1_H // Guards against multiple inclusion -#define PLIB_ADC1_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "device.h" -#include "plib_adc_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -/* The following data type definitions are used by the functions in this - interface and should be considered part it. -*/ - -// ***************************************************************************** - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** -/* The following functions make up the methods (set of possible operations) of - this interface. -*/ - -void ADC1_Initialize( void ); - -void ADC1_Enable( void ); - -void ADC1_Disable( void ); - -void ADC1_ChannelSelect( ADC_POSINPUT positiveInput, ADC_NEGINPUT negativeInput ); - -void ADC1_ConversionStart( void ); - -uint16_t ADC1_ConversionResultGet( void ); - -void ADC1_ComparisonWindowSet(uint16_t low_threshold, uint16_t high_threshold); - -void ADC1_WindowModeSet(ADC_WINMODE mode); - -bool ADC1_ConversionSequenceIsFinished(void); - -void ADC1_InterruptsClear(ADC_STATUS interruptMask); - -void ADC1_InterruptsEnable(ADC_STATUS interruptMask); - -void ADC1_InterruptsDisable(ADC_STATUS interruptMask); - - -bool ADC1_ConversionStatusGet( void ); - - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif /* PLIB_ADC1_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc_common.h deleted file mode 100644 index c1dfe852..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/adc/plib_adc_common.h +++ /dev/null @@ -1,156 +0,0 @@ -/******************************************************************************* - Analog-to-Digital Converter(ADC) Peripheral Library Interface Header File - - Company - Microchip Technology Inc. - - File Name - plib_adc_common.h - - Summary - ADC Peripheral Library Interface Header File. - - Description - This file defines the common types for the ADC peripheral library. This - library provides access to and control of the associated peripheral - instance. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_ADC_COMMON_H // Guards against multiple inclusion -#define PLIB_ADC_COMMON_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Preprocessor macros -// ***************************************************************************** -// ***************************************************************************** -#define ADC_STATUS_NONE 0U -#define ADC_STATUS_RESRDY ADC_INTFLAG_RESRDY_Msk -#define ADC_STATUS_WINMON ADC_INTFLAG_WINMON_Msk -#define ADC_STATUS_OVERRUN ADC_INTFLAG_OVERRUN_Msk -#define ADC_STATUS_MASK (ADC_STATUS_RESRDY | ADC_STATUS_OVERRUN | ADC_STATUS_WINMON) -#define ADC_STATUS_INVALID 0xFFFFFFFFU - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -/* The following data type definitions are used by the functions in this - interface and should be considered part it. -*/ - -typedef enum -{ - ADC_POSINPUT_AIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, - ADC_POSINPUT_AIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, - ADC_POSINPUT_AIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, - ADC_POSINPUT_AIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, - ADC_POSINPUT_AIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, - ADC_POSINPUT_AIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, - ADC_POSINPUT_AIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, - ADC_POSINPUT_AIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, - ADC_POSINPUT_AIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, - ADC_POSINPUT_AIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, - ADC_POSINPUT_AIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, - ADC_POSINPUT_AIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, - ADC_POSINPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, - ADC_POSINPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, - ADC_POSINPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, - ADC_POSINPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, -}ADC_POSINPUT; - -// ***************************************************************************** - -typedef enum -{ - ADC_NEGINPUT_AIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, - ADC_NEGINPUT_AIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, - ADC_NEGINPUT_AIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, - ADC_NEGINPUT_AIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, - ADC_NEGINPUT_AIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, - ADC_NEGINPUT_AIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, - ADC_NEGINPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, -}ADC_NEGINPUT; - -typedef uint32_t ADC_STATUS; -typedef enum -{ - ADC_WINMODE_DISABLED = ADC_CTRLC_WINMODE_DISABLE_Val, - ADC_WINMODE_GREATER_THAN_WINLT = ADC_CTRLC_WINMODE_MODE1_Val, - ADC_WINMODE_LESS_THAN_WINUT = ADC_CTRLC_WINMODE_MODE2_Val, - ADC_WINMODE_BETWEEN_WINLT_AND_WINUT = ADC_CTRLC_WINMODE_MODE3_Val, - ADC_WINMODE_OUTSIDE_WINLT_AND_WINUT = ADC_CTRLC_WINMODE_MODE4_Val -}ADC_WINMODE; - - -// ***************************************************************************** - - -typedef void (*ADC_CALLBACK)(ADC_STATUS status, uintptr_t context); - - -typedef struct -{ - ADC_CALLBACK callback; - - uintptr_t context; - -} ADC_CALLBACK_OBJ; - - - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif /* PLIB_ADC_COMMON_H*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.c deleted file mode 100644 index 19b5de3a..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.c +++ /dev/null @@ -1,911 +0,0 @@ -/******************************************************************************* - Controller Area Network (CAN) Peripheral Library Source File - - Company: - Microchip Technology Inc. - - File Name: - plib_can0.c - - Summary: - CAN peripheral library interface. - - Description: - This file defines the interface to the CAN peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -//DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -//DOM-IGNORE-END -// ***************************************************************************** -// ***************************************************************************** -// Header Includes -// ***************************************************************************** -// ***************************************************************************** - -#include "device.h" -#include "interrupts.h" -#include "plib_can0.h" - -// ***************************************************************************** -// ***************************************************************************** -// Global Data -// ***************************************************************************** -// ***************************************************************************** -#define CAN_STD_ID_Msk 0x7FFU - -static volatile CAN_TX_FIFO_CALLBACK_OBJ can0TxFifoCallbackObj; -static volatile CAN_TX_EVENT_FIFO_CALLBACK_OBJ can0TxEventFifoCallbackObj; -static volatile CAN_RX_FIFO_CALLBACK_OBJ can0RxFifoCallbackObj[2]; -static volatile CAN_CALLBACK_OBJ can0CallbackObj; -static volatile CAN_OBJ can0Obj; - -static inline void CAN0_ZeroInitialize(volatile void* pData, size_t dataSize) -{ - volatile uint8_t* data = (volatile uint8_t*)pData; - for (uint32_t index = 0; index < dataSize; index++) - { - data[index] = 0U; - } -} - -// ***************************************************************************** -// ***************************************************************************** -// CAN0 PLib Interface Routines -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** -/* Function: - void CAN0_Initialize(void) - - Summary: - Initializes given instance of the CAN peripheral. - - Precondition: - None. - - Parameters: - None. - - Returns: - None -*/ -void CAN0_Initialize(void) -{ - /* Start CAN initialization */ - CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - /* Set Data Bit Timing and Prescaler Register */ - CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(15UL) | CAN_DBTP_DTSEG1(31UL) | CAN_DBTP_DBRP(0UL) | CAN_DBTP_DSJW(7UL); - - /* Set Nominal Bit timing and Prescaler Register */ - CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(23UL) | CAN_NBTP_NTSEG1(70UL) | CAN_NBTP_NBRP(0UL) | CAN_NBTP_NSJW(23UL); - - /* Receive Buffer / FIFO Element Size Configuration Register */ - CAN0_REGS->CAN_RXESC = 0UL | CAN_RXESC_F0DS(0UL) | CAN_RXESC_F1DS(0UL); - /* Transmit Buffer/FIFO Element Size Configuration Register */ - CAN0_REGS->CAN_TXESC = CAN_TXESC_TBDS(0UL); - - /* Global Filter Configuration Register */ - CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; - - /* Set the operation mode */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; - - - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Select interrupt line */ - CAN0_REGS->CAN_ILS = 0x0U; - - /* Enable interrupt line */ - CAN0_REGS->CAN_ILE = CAN_ILE_EINT0_Msk; - - /* Enable CAN interrupts */ - CAN0_REGS->CAN_IE = CAN_IE_BOE_Msk | CAN_IE_ARAE_Msk | CAN_IE_PEDE_Msk | CAN_IE_PEAE_Msk | CAN_IE_WDIE_Msk - | CAN_IE_EWE_Msk | CAN_IE_EPE_Msk | CAN_IE_ELOE_Msk | CAN_IE_BEUE_Msk | CAN_IE_BECE_Msk - | CAN_IE_TFEE_Msk - | CAN_IE_TEFNE_Msk | CAN_IE_TEFLE_Msk | CAN_IE_TEFFE_Msk | CAN_IE_TCFE_Msk | CAN_IE_HPME_Msk - | CAN_IE_RF0NE_Msk | CAN_IE_RF0LE_Msk | CAN_IE_RF0FE_Msk - | CAN_IE_RF1NE_Msk | CAN_IE_RF1LE_Msk | CAN_IE_RF1FE_Msk - - | CAN_IE_MRAFE_Msk; - - CAN0_ZeroInitialize(&can0Obj.msgRAMConfig, sizeof(CAN_MSG_RAM_CONFIG)); -} - - -// ***************************************************************************** -/* Function: - bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) - - Summary: - Transmit multiple messages into CAN bus from Tx FIFO. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - numberOfMessage - Total number of message. - txBuffer - Pointer to Tx buffer - - Returns: - Request status. - true - Request was successful. - false - Request has failed. -*/ -bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) -{ - uint8_t *txFifo = NULL; - uint8_t *txBuf = (uint8_t *)txBuffer; - uint32_t bufferNumber = 0U; - uint8_t tfqpi = 0U; - uint8_t count = 0U; - bool transmitFifo_event = false; - - if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) - { - tfqpi = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); - - for (count = 0U; count < numberOfMessage; count++) - { - txFifo = (uint8_t *)((uint8_t*)can0Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE)); - - (void) memcpy(txFifo, txBuf, CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE); - - txBuf += CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE; - bufferNumber |= (1UL << tfqpi); - tfqpi++; - if (tfqpi == 1U) - { - tfqpi = 0U; - } - } - - __DSB(); - - /* Set Transmission request */ - CAN0_REGS->CAN_TXBAR = bufferNumber; - - transmitFifo_event = true; - } - return transmitFifo_event; -} - -// ***************************************************************************** -/* Function: - uint8_t CAN0_TxFifoFreeLevelGet(void) - - Summary: - Returns Tx FIFO Free Level. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - None. - - Returns: - Tx FIFO Free Level. -*/ -uint8_t CAN0_TxFifoFreeLevelGet(void) -{ - return (uint8_t)(CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); -} - -// ***************************************************************************** -/* Function: - bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) - - Summary: - Check if Transmission request is pending for the specific Tx buffer. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - None. - - Returns: - true - Transmission request is pending. - false - Transmission request is not pending. -*/ -bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) -{ - return ((CAN0_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); -} - -// ***************************************************************************** -/* Function: - bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) - - Summary: - Read Tx Event FIFO for the transmitted messages. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - numberOfTxEvent - Total number of Tx Event - txEventFifo - Pointer to Tx Event FIFO - - Returns: - Request status. - true - Request was successful. - false - Request has failed. -*/ -bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) -{ - uint8_t txefgi = 0U; - uint8_t count = 0U; - uint8_t *txEvent = NULL; - uint8_t *txEvtFifo = (uint8_t *)txEventFifo; - bool txFifo_event = false; - - if (txEventFifo != NULL) - { - /* Read data from the Rx FIFO0 */ - txefgi = (uint8_t)((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); - for (count = 0U; count < numberOfTxEvent; count++) - { - txEvent = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); - - (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); - - if ((count + 1U) == numberOfTxEvent) - { - break; - } - txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); - txefgi++; - if (txefgi == 1U) - { - txefgi = 0U; - } - } - - /* Ack the Tx Event FIFO position */ - CAN0_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); - - txFifo_event = true; - } - return txFifo_event; -} - - -// ***************************************************************************** -/* Function: - bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) - - Summary: - Read messages from Rx FIFO0/FIFO1. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - rxFifoNum - Rx FIFO number - numberOfMessage - Total number of message - rxBuffer - Pointer to Rx buffer - - Returns: - Request status. - true - Request was successful. - false - Request has failed. -*/ -bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) -{ - uint8_t rxgi = 0U; - uint8_t count = 0U; - uint8_t *rxFifo = NULL; - uint8_t *rxBuf = (uint8_t *)rxBuffer; - bool status = false; - - if (rxBuffer != NULL) - { - switch (rxFifoNum) - { - case CAN_RX_FIFO_0: - /* Read data from the Rx FIFO0 */ - rxgi = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); - for (count = 0U; count < numberOfMessage; count++) - { - rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN0_RX_FIFO0_ELEMENT_SIZE)); - - (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO0_ELEMENT_SIZE); - - if ((count + 1U) == numberOfMessage) - { - break; - } - rxBuf += CAN0_RX_FIFO0_ELEMENT_SIZE; - rxgi++; - if (rxgi == 1U) - { - rxgi = 0U; - } - } - - /* Ack the fifo position */ - CAN0_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); - - status = true; - break; - case CAN_RX_FIFO_1: - /* Read data from the Rx FIFO1 */ - rxgi = (uint8_t)((CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); - for (count = 0U; count < numberOfMessage; count++) - { - rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN0_RX_FIFO1_ELEMENT_SIZE)); - - (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO1_ELEMENT_SIZE); - - if ((count + 1U) == numberOfMessage) - { - break; - } - rxBuf += CAN0_RX_FIFO1_ELEMENT_SIZE; - rxgi++; - if (rxgi == 1U) - { - rxgi = 0U; - } - } - /* Ack the fifo position */ - CAN0_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); - - status = true; - break; - default: - /* Do nothing */ - break; - } - } - return status; -} - -// ***************************************************************************** -/* Function: - CAN_ERROR CAN0_ErrorGet(void) - - Summary: - Returns the error during transfer. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - None. - - Returns: - Error during transfer. -*/ -CAN_ERROR CAN0_ErrorGet(void) -{ - CAN_ERROR error; - uint32_t errorStatus = CAN0_REGS->CAN_PSR; - - error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) - | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); - - if ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - } - - return error; -} - -// ***************************************************************************** -/* Function: - void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) - - Summary: - Returns the transmit and receive error count during transfer. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - txErrorCount - Transmit Error Count to be received - rxErrorCount - Receive Error Count to be received - - Returns: - None. -*/ -void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) -{ - *txErrorCount = (uint8_t)(CAN0_REGS->CAN_ECR & CAN_ECR_TEC_Msk); - *rxErrorCount = (uint8_t)((CAN0_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); -} - -// ***************************************************************************** -/* Function: - void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) - - Summary: - Set the Message RAM Configuration. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. - Application must allocate buffer from non-cached - contiguous memory and buffer size must be - CAN0_MESSAGE_RAM_CONFIG_SIZE - - Returns: - None -*/ -/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ -void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) -{ - uint32_t offset = 0U; - uint32_t msgRAMConfigBaseAddr = (uint32_t)msgRAMConfigBaseAddress; - - (void) memset(msgRAMConfigBaseAddress, 0x00, CAN0_MESSAGE_RAM_CONFIG_SIZE); - - /* Set CAN CCCR Init for Message RAM Configuration */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - can0Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; - offset = CAN0_RX_FIFO0_SIZE; - /* Receive FIFO 0 Configuration Register */ - CAN0_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | - CAN_RXF0C_F0SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO0Address); - - can0Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN0_RX_FIFO1_SIZE; - /* Receive FIFO 1 Configuration Register */ - CAN0_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | - CAN_RXF1C_F1SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO1Address); - - can0Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN0_TX_FIFO_BUFFER_SIZE; - /* Transmit Buffer/FIFO Configuration Register */ - CAN0_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | - CAN_TXBC_TBSA((uint32_t)can0Obj.msgRAMConfig.txBuffersAddress); - - can0Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); - offset += CAN0_TX_EVENT_FIFO_SIZE; - /* Transmit Event FIFO Configuration Register */ - CAN0_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | - CAN_TXEFC_EFSA((uint32_t)can0Obj.msgRAMConfig.txEventFIFOAddress); - - - /* Reference offset variable once to remove warning about the variable not being used after increment */ - (void)offset; - - /* Complete Message RAM Configuration by clearing CAN CCCR Init */ - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for configuration complete */ - } -} -/* MISRAC 2012 deviation block end for Rule 11.3*/ - - - - -void CAN0_SleepModeEnter(void) -{ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) - { - /* Wait for clock stop request to complete */ - } -} - -void CAN0_SleepModeExit(void) -{ - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) - { - /* Wait for no clock stop */ - } - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } -} - -bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) -{ - bool status = false; - uint32_t numOfTimeQuanta; - uint8_t tseg1; - float temp1; - float temp2; - - if ((setup != NULL) && (bitTiming != NULL)) - { - if (setup->nominalBitTimingSet == true) - { - numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); - if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) - { - if (setup->nominalSamplePoint < 50.0f) - { - setup->nominalSamplePoint = 50.0f; - } - temp1 = (float)numOfTimeQuanta; - temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; - tseg1 = (uint8_t)temp2; - bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); - bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; - bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; - bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; - bitTiming->nominalBitTimingSet = true; - status = true; - } - else - { - bitTiming->nominalBitTimingSet = false; - } - } - if (setup->dataBitTimingSet == true) - { - numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->dataBitRate * ((uint32_t)setup->dataPrescaler + 1U)); - if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 49U)) - { - if (setup->dataSamplePoint < 50.0f) - { - setup->dataSamplePoint = 50.0f; - } - temp1 = (float)numOfTimeQuanta; - temp2 = (temp1 * setup->dataSamplePoint) / 100.0f; - tseg1 = (uint8_t)temp2; - bitTiming->dataBitTiming.dataTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); - bitTiming->dataBitTiming.dataTimeSegment1 = tseg1 - 2U; - bitTiming->dataBitTiming.dataSJW = bitTiming->dataBitTiming.dataTimeSegment2; - bitTiming->dataBitTiming.dataPrescaler = setup->dataPrescaler; - bitTiming->dataBitTimingSet = true; - status = true; - } - else - { - bitTiming->dataBitTimingSet = false; - status = false; - } - } - } - - return status; -} - -bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) -{ - bool status = false; - bool nominalBitTimingSet = false; - bool dataBitTimingSet = false; - - if ((bitTiming->nominalBitTimingSet == true) - && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) - && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) - && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) - && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) - { - nominalBitTimingSet = true; - } - - if ((bitTiming->dataBitTimingSet == true) - && ((bitTiming->dataBitTiming.dataTimeSegment1 >= 0x1U) && (bitTiming->dataBitTiming.dataTimeSegment1 <= 0x1FU)) - && (bitTiming->dataBitTiming.dataTimeSegment2 <= 0xFU) - && (bitTiming->dataBitTiming.dataPrescaler <= 0x1FU) - && (bitTiming->dataBitTiming.dataSJW <= 0xFU)) - { - dataBitTimingSet = true; - } - - if ((nominalBitTimingSet == true) || (dataBitTimingSet == true)) - { - /* Start CAN initialization */ - CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - - /* Set CCE to unlock the configuration registers */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; - - if (dataBitTimingSet == true) - { - /* Set Data Bit Timing and Prescaler Register */ - CAN0_REGS->CAN_DBTP = CAN_DBTP_DTSEG2(bitTiming->dataBitTiming.dataTimeSegment2) | CAN_DBTP_DTSEG1(bitTiming->dataBitTiming.dataTimeSegment1) | CAN_DBTP_DBRP(bitTiming->dataBitTiming.dataPrescaler) | CAN_DBTP_DSJW(bitTiming->dataBitTiming.dataSJW); - } - if (nominalBitTimingSet == true) - { - /* Set Nominal Bit timing and Prescaler Register */ - CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); - } - - /* Set the operation mode */ - CAN0_REGS->CAN_CCCR |= CAN_CCCR_FDOE_Msk | CAN_CCCR_BRSE_Msk; - - - CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; - while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) - { - /* Wait for initialization complete */ - } - status = true; - } - return status; -} - - -// ***************************************************************************** -/* Function: - void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined - by the CAN_TX_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can0TxFifoCallbackObj.callback = callback; - can0TxFifoCallbackObj.context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined - by the CAN_TX_EVENT_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can0TxEventFifoCallbackObj.callback = callback; - can0TxEventFifoCallbackObj.context = contextHandle; - - } -} - - -// ***************************************************************************** -/* Function: - void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - rxFifoNum - Rx FIFO Number - - callback - A pointer to a function with a calling signature defined - by the CAN_RX_FIFO_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can0RxFifoCallbackObj[rxFifoNum].callback = callback; - can0RxFifoCallbackObj[rxFifoNum].context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) - - Summary: - Sets the pointer to the function (and it's context) to be called when the - given CAN's transfer events occur. - - Precondition: - CAN0_Initialize must have been called for the associated CAN instance. - - Parameters: - callback - A pointer to a function with a calling signature defined - by the CAN_CALLBACK data type. - - contextHandle - A value (usually a pointer) passed (unused) into the function - identified by the callback parameter. - - Returns: - None. -*/ -void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle) -{ - if (callback != NULL) - { - can0CallbackObj.callback = callback; - can0CallbackObj.context = contextHandle; - } -} - -// ***************************************************************************** -/* Function: - void CAN0_InterruptHandler(void) - - Summary: - CAN0 Peripheral Interrupt Handler. - - Description: - This function is CAN0 Peripheral Interrupt Handler and will - called on every CAN0 interrupt. - - Precondition: - None. - - Parameters: - None. - - Returns: - None. - - Remarks: - The function is called as peripheral instance's interrupt handler if the - instance interrupt is enabled. If peripheral instance's interrupt is not - enabled user need to call it from the main while loop of the application. -*/ -void __attribute__((used)) CAN0_InterruptHandler(void) -{ - uint8_t numberOfMessage = 0; - uint8_t numberOfTxEvent = 0; - - uint32_t ir = CAN0_REGS->CAN_IR; - - /* Additional temporary variable used to prevent MISRA violations (Rule 13.x) */ - uintptr_t context; - - if ((ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))) != 0U) - { - CAN0_REGS->CAN_IR = (ir & (~(CAN_IR_RF0N_Msk | CAN_IR_RF1N_Msk | CAN_IR_TFE_Msk | CAN_IR_TEFN_Msk))); - if (can0CallbackObj.callback != NULL) - { - context = can0CallbackObj.context; - can0CallbackObj.callback(ir, context); - } - } - /* New Message in Rx FIFO 0 */ - if ((ir & CAN_IR_RF0N_Msk) != 0U) - { - CAN0_REGS->CAN_IR = CAN_IR_RF0N_Msk; - - numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); - - if (can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback != NULL) - { - context = can0RxFifoCallbackObj[CAN_RX_FIFO_0].context; - can0RxFifoCallbackObj[CAN_RX_FIFO_0].callback(numberOfMessage, context); - } - } - /* New Message in Rx FIFO 1 */ - if ((ir & CAN_IR_RF1N_Msk) != 0U) - { - CAN0_REGS->CAN_IR = CAN_IR_RF1N_Msk; - - numberOfMessage = (uint8_t)(CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); - - if (can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback != NULL) - { - context = can0RxFifoCallbackObj[CAN_RX_FIFO_1].context; - can0RxFifoCallbackObj[CAN_RX_FIFO_1].callback(numberOfMessage, context); - } - } - - /* TX FIFO is empty */ - if ((ir & CAN_IR_TFE_Msk) != 0U) - { - CAN0_REGS->CAN_IR = CAN_IR_TFE_Msk; - if (can0TxFifoCallbackObj.callback != NULL) - { - context = can0TxFifoCallbackObj.context; - can0TxFifoCallbackObj.callback(context); - } - } - /* Tx Event FIFO new entry */ - if ((ir & CAN_IR_TEFN_Msk) != 0U) - { - CAN0_REGS->CAN_IR = CAN_IR_TEFN_Msk; - - numberOfTxEvent = (uint8_t)(CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); - - if (can0TxEventFifoCallbackObj.callback != NULL) - { - context = can0TxEventFifoCallbackObj.context; - can0TxEventFifoCallbackObj.callback(numberOfTxEvent, context); - } - } -} - -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.h deleted file mode 100644 index 63404486..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can0.h +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* - CAN Peripheral Library Interface Header File - - Company: - Microchip Technology Inc. - - File Name: - plib_can0.h - - Summary: - CAN PLIB interface declarations. - - Description: - The CAN plib provides a simple interface to manage the CAN modules on - Microchip microcontrollers. This file defines the interface declarations - for the CAN plib. - - Remarks: - None. - -*******************************************************************************/ -//DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -//DOM-IGNORE-END - -#ifndef PLIB_CAN0_H -#define PLIB_CAN0_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -/* - * This section lists the other files that are included in this file. - */ -#include -#include - -#include "device.h" -#include "plib_can_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - extern "C" { -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -#define CAN0_CLOCK_FREQUENCY 48000000U - -/* CAN0 Message RAM Configuration Size */ -#define CAN0_RX_FIFO0_ELEMENT_SIZE 16U -#define CAN0_RX_FIFO0_SIZE 16U -#define CAN0_RX_FIFO1_ELEMENT_SIZE 16U -#define CAN0_RX_FIFO1_SIZE 16U -#define CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE 16U -#define CAN0_TX_FIFO_BUFFER_SIZE 16U -#define CAN0_TX_EVENT_FIFO_SIZE 8U - -/* CAN0_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver - for allocating buffer from non-cached contiguous memory */ -#define CAN0_MESSAGE_RAM_CONFIG_SIZE 56U - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** -void CAN0_Initialize(void); -bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); -uint8_t CAN0_TxFifoFreeLevelGet(void); -bool CAN0_TxBufferIsBusy(uint8_t bufferNumber); -bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); -bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); -CAN_ERROR CAN0_ErrorGet(void); -void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); -void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); -void CAN0_SleepModeEnter(void); -void CAN0_SleepModeExit(void); -bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); -bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming); -void CAN0_TxFifoCallbackRegister(CAN_TX_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN0_TxEventFifoCallbackRegister(CAN_TX_EVENT_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN0_RxFifoCallbackRegister(CAN_RX_FIFO_NUM rxFifoNum, CAN_RX_FIFO_CALLBACK callback, uintptr_t contextHandle); -void CAN0_CallbackRegister(CAN_CALLBACK callback, uintptr_t contextHandle); -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - } -#endif -// DOM-IGNORE-END - -#endif // PLIB_CAN0_H - -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can_common.h deleted file mode 100644 index b5f9f963..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/can/plib_can_common.h +++ /dev/null @@ -1,668 +0,0 @@ -/******************************************************************************* - CAN Peripheral Library Interface Header File - - Company - Microchip Technology Inc. - - File Name - plib_can_common.h - - Summary - CAN peripheral library interface. - - Description - This file defines the interface to the CAN peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_CAN_COMMON_H -#define PLIB_CAN_COMMON_H - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Preprocessor macros -// ***************************************************************************** -// ***************************************************************************** - - // ***************************************************************************** -/* CAN Transfer Errors - - Summary: - CAN Transfer Error macros. - - Description: - Helper macros to identify CAN errors. - - Remarks: - None. -*/ - -#define CAN_ERROR_NONE 0x0U -#define CAN_ERROR_LEC_STUFF 0x1U -#define CAN_ERROR_LEC_FORM 0x2U -#define CAN_ERROR_LEC_ACK 0x3U -#define CAN_ERROR_LEC_BIT1 0x4U -#define CAN_ERROR_LEC_BIT0 0x5U -#define CAN_ERROR_LEC_CRC 0x6U -#define CAN_ERROR_LEC_NC 0x7U -#define CAN_ERROR_PASSIVE 0x20U -#define CAN_ERROR_WARNING_STATUS 0x40U -#define CAN_ERROR_BUS_OFF 0x80U -#define CAN_ERROR_DLEC_STUFF 0x100U -#define CAN_ERROR_DLEC_FORM 0x200U -#define CAN_ERROR_DLEC_ACK 0x300U -#define CAN_ERROR_DLEC_BIT1 0x400U -#define CAN_ERROR_DLEC_BIT0 0x500U -#define CAN_ERROR_DLEC_CRC 0x600U -#define CAN_ERROR_DLEC_NC 0x700U -#define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U -#define CAN_ERROR_INVALID 0xFFFFFFFFU - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* CAN Rx FIFO Number - - Summary: - CAN Rx FIFO Number. - - Description: - This data type defines CAN Rx FIFO number for Rx FIFO0 and FIFO1. - - Remarks: - None. -*/ -typedef enum -{ - CAN_RX_FIFO_0 = 0U, - CAN_RX_FIFO_1 -} CAN_RX_FIFO_NUM; - -// ***************************************************************************** -/* CAN Interrupt Mask - - Summary: - CAN Interrupt Mask. - - Description: - This data type defines the CAN Interrupt sources number. - - Remarks: - None. -*/ -typedef enum -{ - CAN_INTERRUPT_RF0N_MASK = (1UL << 0U), - CAN_INTERRUPT_RF0W_MASK = (1UL << 1U), - CAN_INTERRUPT_RF0F_MASK = (1UL << 2U), - CAN_INTERRUPT_RF0L_MASK = (1UL << 3U), - CAN_INTERRUPT_RF1N_MASK = (1UL << 4U), - CAN_INTERRUPT_RF1W_MASK = (1UL << 5U), - CAN_INTERRUPT_RF1F_MASK = (1UL << 6U), - CAN_INTERRUPT_RF1L_MASK = (1UL << 7U), - CAN_INTERRUPT_HPM_MASK = (1UL << 8U), - CAN_INTERRUPT_TC_MASK = (1UL << 9U), - CAN_INTERRUPT_TCF_MASK = (1UL << 10U), - CAN_INTERRUPT_TFE_MASK = (1UL << 11U), - CAN_INTERRUPT_TEFN_MASK = (1UL << 12U), - CAN_INTERRUPT_TEFW_MASK = (1UL << 13U), - CAN_INTERRUPT_TEFF_MASK = (1UL << 14U), - CAN_INTERRUPT_TEFL_MASK = (1UL << 15U), - CAN_INTERRUPT_TSW_MASK = (1UL << 16U), - CAN_INTERRUPT_MRAF_MASK = (1UL << 17U), - CAN_INTERRUPT_TOO_MASK = (1UL << 18U), - CAN_INTERRUPT_DRX_MASK = (1UL << 19U), - CAN_INTERRUPT_ELO_MASK = (1UL << 22U), - CAN_INTERRUPT_EP_MASK = (1UL << 23U), - CAN_INTERRUPT_EW_MASK = (1UL << 24U), - CAN_INTERRUPT_BO_MASK = (1UL << 25U), - CAN_INTERRUPT_WDI_MASK = (1UL << 26U), - CAN_INTERRUPT_PEA_MASK = (1UL << 27U), - CAN_INTERRUPT_PED_MASK = (1UL << 28U), - CAN_INTERRUPT_ARA_MASK = (1UL << 29U) -}CAN_INTERRUPT_MASK; - -// ***************************************************************************** -/* CAN Transfer Error - - Summary: - CAN Transfer Error data type. - - Description: - This data type defines the CAN Transfer Error. - - Remarks: - None. -*/ -typedef uint32_t CAN_ERROR; - -// ***************************************************************************** -/* CAN Tx FIFO Callback - - Summary: - CAN Callback Function Pointer for Tx FIFO. - - Description: - This data type defines the CAN Callback Function Pointer for Tx FIFO. - - Remarks: - None. -*/ -typedef void (*CAN_TX_FIFO_CALLBACK) (uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN TX/RX Buffers Callback - - Summary: - CAN Callback Function Pointer for TX/RX Buffers. - - Description: - This data type defines the CAN Callback Function Pointer for TX/RX Buffers. - - Remarks: - None. -*/ -typedef void (*CAN_TXRX_BUFFERS_CALLBACK) (uint8_t bufferNumber, uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN Tx Event FIFO Callback - - Summary: - CAN Callback Function Pointer for Tx Event FIFO. - - Description: - This data type defines the CAN Callback Function Pointer for Tx Event FIFO. - - Remarks: - None. -*/ -typedef void (*CAN_TX_EVENT_FIFO_CALLBACK) (uint8_t numberOfTxEvent, uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN Rx FIFO0/FIFO1 Callback - - Summary: - CAN Callback Function Pointer for Rx FIFO0/FIFO1. - - Description: - This data type defines the CAN Callback Function Pointer for Rx FIFO0/FIFO1. - - Remarks: - None. -*/ -typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN Callback - - Summary: - CAN Callback Function Pointer. - - Description: - This data type defines the CAN Callback Function Pointer. - - Remarks: - None. -*/ -typedef void (*CAN_CALLBACK) (uint32_t interruptStatus, uintptr_t contextHandle); - -// ***************************************************************************** -/* CAN Message RAM Configuration - - Summary: - CAN Message RAM Configuration structure. - - Description: - This data structure defines the CAN Message RAM Base address for Rx FIFO0, - Rx FIFO1, Rx Buffers, Tx Buffers/FIFO, Tx Event FIFO, Standard Message ID Filter and - Extended Message ID Filter configuration. - - Remarks: - None. -*/ -typedef struct -{ - /* Rx FIFO0 base address */ - can_rxf0e_registers_t *rxFIFO0Address; - - /* Rx FIFO1 base address */ - can_rxf1e_registers_t *rxFIFO1Address; - - /* Rx Buffer base address */ - can_rxbe_registers_t *rxBuffersAddress; - - /* Tx Buffers/FIFO base address */ - can_txbe_registers_t *txBuffersAddress; - - /* Tx Event FIFO base address */ - can_txefe_registers_t *txEventFIFOAddress; - - /* Standard Message ID Filter base address */ - can_sidfe_registers_t *stdMsgIDFilterAddress; - - /* Extended Message ID Filter base address */ - can_xidfe_registers_t *extMsgIDFilterAddress; -} CAN_MSG_RAM_CONFIG; - -// ***************************************************************************** -/* CAN Rx Buffer and FIFO Element - - Summary: - CAN Rx Buffer and FIFO Element Structure. - - Description: - This data structure defines CAN Rx Buffer and FIFO Element. - - Remarks: - None. -*/ -typedef struct -{ - /* Identifier */ - unsigned int id:29; - /* Remote Transmission Request */ - unsigned int rtr:1; - /* Extended Identifier */ - unsigned int xtd:1; - /* Error State Indicator */ - unsigned int esi:1; - - /* Rx Timestamp */ - unsigned int rxts:16; - /* Data Length Code */ - unsigned int dlc:4; - /* Bit Rate Switching */ - unsigned int brs:1; - /* FD Format */ - unsigned int fdf:1; - /* Reserved */ - unsigned int :2; - /* Filter Index */ - unsigned int fidx:7; - /* Accepted Non-matching Frame */ - unsigned int anmf:1; - - /* Data field */ - uint8_t data[8]; - -} CAN_RX_BUFFER; - -// ***************************************************************************** -/* CAN Tx Buffer Element - - Summary: - CAN Tx Buffer Element Structure. - - Description: - This data structure defines CAN Tx Buffer Element. - - Remarks: - None. -*/ -typedef struct -{ - /* Identifier */ - unsigned int id:29; - /* Remote Transmission Request */ - unsigned int rtr:1; - /* Extended Identifier */ - unsigned int xtd:1; - /* Error State Indicator */ - unsigned int esi:1; - - /* Reserved */ - unsigned int :16; - /* Data Length Code */ - unsigned int dlc:4; - /* Bit Rate Switching */ - unsigned int brs:1; - /* FD Format */ - unsigned int fdf:1; - /* Reserved */ - unsigned int :1; - /* Event FIFO Control */ - unsigned int efc:1; - /* Message Marker */ - unsigned int mm:8; - - /* Data field */ - uint8_t data[8]; - -} CAN_TX_BUFFER; - -// ***************************************************************************** -/* CAN Tx Event FIFO Element - - Summary: - CAN Tx Event FIFO Element Structure. - - Description: - This data structure defines CAN Tx Event FIFO Element. - - Remarks: - None. -*/ -typedef struct -{ - /* Identifier */ - unsigned int id:29; - /* Remote Transmission Request */ - unsigned int rtr:1; - /* Extended Identifier */ - unsigned int xtd:1; - /* Error State Indicator */ - unsigned int esi:1; - - /* Tx Timestamp */ - unsigned int txts:16; - /* Data Length Code */ - unsigned int dlc:4; - /* Bit Rate Switch */ - unsigned int brs:1; - /* FD Format */ - unsigned int fdf:1; - /* Event Type */ - unsigned int et:2; - /* Message Marker */ - unsigned int mm:8; - -} CAN_TX_EVENT_FIFO; - -// ***************************************************************************** -/* CAN Nominal Bit Timing Parameters - - Summary: - CAN Nominal Bit Timing Parameter structure. - - Description: - This data structure defines Nominal Bit Timing Parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Nominal Time segment after sample point */ - uint8_t nominalTimeSegment2; - - /* Nominal Time segment before sample point */ - uint8_t nominalTimeSegment1; - - /* Nominal Baud Rate Prescaler */ - uint16_t nominalPrescaler; - - /* Nominal Syncronization Jump Width */ - uint8_t nominalSJW; - -} CAN_NOMINAL_BIT_TIMING; - -// ***************************************************************************** -/* CAN Data Bit Timing Parameters - - Summary: - CAN Data Bit Timing Parameter structure. - - Description: - This data structure defines Data Bit Timing Parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Data Time segment after sample point */ - uint8_t dataTimeSegment2; - - /* Data Time segment before sample point */ - uint8_t dataTimeSegment1; - - /* Data Baud Rate Prescaler */ - uint8_t dataPrescaler; - - /* Data Syncronization Jump Width */ - uint8_t dataSJW; - -} CAN_DATA_BIT_TIMING; - -// ***************************************************************************** -/* CAN Bit Timing Parameters - - Summary: - CAN Bit Timing Parameter structure. - - Description: - This data structure defines Bit Timing Parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Nominal bit timing set flag */ - bool nominalBitTimingSet; - - /* Nominal bit timing parameters */ - CAN_NOMINAL_BIT_TIMING nominalBitTiming; - - /* Data bit timing set flag */ - bool dataBitTimingSet; - - /* Data bit timing parameters */ - CAN_DATA_BIT_TIMING dataBitTiming; -} CAN_BIT_TIMING; - -// ***************************************************************************** -/* CAN Bit Timing Setup - - Summary: - CAN Bit Timing Setup structure. - - Description: - This data structure defines Bit Timing Setup parameters. - - Remarks: - None. -*/ -typedef struct -{ - /* Nominal bit timing set flag */ - bool nominalBitTimingSet; - - /* Nominal bit rate */ - uint32_t nominalBitRate; - - /* Nominal Sample Point */ - float nominalSamplePoint; - - /* Nominal Baud Rate Prescaler */ - uint16_t nominalPrescaler; - - /* Data bit timing set flag */ - bool dataBitTimingSet; - - /* Data bit rate */ - uint32_t dataBitRate; - - /* Data Sample Point */ - float dataSamplePoint; - - /* Data Baud Rate Prescaler */ - uint8_t dataPrescaler; - -} CAN_BIT_TIMING_SETUP; - -// ***************************************************************************** -/* CAN Tx FIFO Callback Object - - Summary: - CAN transfer event callback structure for Tx FIFO. - - Description: - This data structure stores transfer event callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* Transfer Event Callback */ - CAN_TX_FIFO_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_TX_FIFO_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Tx/Rx Buffers Callback Object - - Summary: - CAN transfer event callback structure for Tx/Rx Buffers. - - Description: - This data structure stores transfer event callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* Transfer Event Callback */ - CAN_TXRX_BUFFERS_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_TXRX_BUFFERS_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Tx Event FIFO Callback Object - - Summary: - CAN transfer event callback structure for Tx Event FIFO. - - Description: - This data structure stores transfer event callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* Transfer Event Callback */ - CAN_TX_EVENT_FIFO_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_TX_EVENT_FIFO_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Rx FIFO0/FIFO1 Callback Object - - Summary: - CAN transfer event callback structure for Rx FIFO0/FIFO1. - - Description: - This data structure stores transfer event callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* Transfer Event Callback */ - CAN_RX_FIFO_CALLBACK callback; - - /* Transfer Event Callback Context */ - uintptr_t context; -} CAN_RX_FIFO_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN Callback Object - - Summary: - CAN interrupt status callback structure. - - Description: - This data structure stores interrupt status callback and it's context. - - Remarks: - None. -*/ -typedef struct -{ - /* CAN Interrupt Status Callback */ - CAN_CALLBACK callback; - - /* CAN Interrupt Status Callback Context */ - uintptr_t context; -} CAN_CALLBACK_OBJ; - -// ***************************************************************************** -/* CAN PLib Instance Object - - Summary: - CAN PLib Object structure. - - Description: - This data structure defines the CAN PLib Instance Object. - - Remarks: - None. -*/ -typedef struct -{ - /* Message RAM Configuration */ - CAN_MSG_RAM_CONFIG msgRAMConfig; - -} CAN_OBJ; - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif -// DOM-IGNORE-END - -#endif //PLIB_CAN_COMMON_H -/******************************************************************************* - End of File -*/ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.c deleted file mode 100644 index 2403a77b..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.c +++ /dev/null @@ -1,148 +0,0 @@ -/******************************************************************************* - CLOCK PLIB - - Company: - Microchip Technology Inc. - - File Name: - plib_clock.c - - Summary: - CLOCK PLIB Implementation File. - - Description: - None - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#include "plib_clock.h" -#include "device.h" -#include "interrupts.h" - - - - -static void OSCCTRL_Initialize(void) -{ - uint32_t calibValue = (uint32_t)(((*(uint64_t*)0x00806020UL) >> 19 ) & 0x3fffffUL); - OSCCTRL_REGS->OSCCTRL_CAL48M = calibValue; - - - /* Selection of the Division Value */ - OSCCTRL_REGS->OSCCTRL_OSC48MDIV = (uint8_t)OSCCTRL_OSC48MDIV_DIV(0UL); - - while((OSCCTRL_REGS->OSCCTRL_OSC48MSYNCBUSY & OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) == OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) - { - /* Waiting for the synchronization */ - } - - while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_OSC48MRDY_Msk) != OSCCTRL_STATUS_OSC48MRDY_Msk) - { - /* Waiting for the OSC48M Ready state */ - } - OSCCTRL_REGS->OSCCTRL_OSC48MCTRL |= OSCCTRL_OSC48MCTRL_ONDEMAND_Msk; - -} - -static void OSC32KCTRL_Initialize(void) -{ - OSC32KCTRL_REGS->OSC32KCTRL_OSC32K = 0x0UL; - - OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0UL); -} - - - -static void GCLK0_Initialize(void) -{ - - GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1UL) | GCLK_GENCTRL_SRC(6UL) | GCLK_GENCTRL_GENEN_Msk; - - while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL0_Msk) == GCLK_SYNCBUSY_GENCTRL0_Msk) - { - /* wait for the Generator 0 synchronization */ - } -} - -void CLOCK_Initialize (void) -{ - /* Function to Initialize the Oscillators */ - OSCCTRL_Initialize(); - - /* Function to Initialize the 32KHz Oscillators */ - OSC32KCTRL_Initialize(); - - GCLK0_Initialize(); - - - /* Selection of the Generator and write Lock for EIC */ - GCLK_REGS->GCLK_PCHCTRL[2] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; - - while ((GCLK_REGS->GCLK_PCHCTRL[2] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) - { - /* Wait for synchronization */ - } - /* Selection of the Generator and write Lock for SERCOM0_CORE */ - GCLK_REGS->GCLK_PCHCTRL[19] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; - - while ((GCLK_REGS->GCLK_PCHCTRL[19] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) - { - /* Wait for synchronization */ - } - /* Selection of the Generator and write Lock for SERCOM1_CORE */ - GCLK_REGS->GCLK_PCHCTRL[20] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; - - while ((GCLK_REGS->GCLK_PCHCTRL[20] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) - { - /* Wait for synchronization */ - } - /* Selection of the Generator and write Lock for SERCOM3_CORE */ - GCLK_REGS->GCLK_PCHCTRL[22] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; - - while ((GCLK_REGS->GCLK_PCHCTRL[22] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) - { - /* Wait for synchronization */ - } - /* Selection of the Generator and write Lock for CAN0 */ - GCLK_REGS->GCLK_PCHCTRL[26] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; - - while ((GCLK_REGS->GCLK_PCHCTRL[26] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) - { - /* Wait for synchronization */ - } - /* Configure the AHB Bridge Clocks */ - MCLK_REGS->MCLK_AHBMASK = 0x1dffU; - - - - /* Configure the APBC Bridge Clocks */ - MCLK_REGS->MCLK_APBCMASK = 0x16U; - - -} - - - diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.h deleted file mode 100644 index 71d6690a..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/clock/plib_clock.h +++ /dev/null @@ -1,143 +0,0 @@ -/******************************************************************************* - CLOCK PLIB - - Company: - Microchip Technology Inc. - - File Name: - plib_clock.h - - Summary: - CLOCK PLIB Header File. - - Description: - The Clock PLIB initializes all the oscillators based on the - requirements. - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef PLIB_CLOCK_H -#define PLIB_CLOCK_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ -#include -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility -extern "C" { -#endif - -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** -/* The following functions make up the methods (set of possible operations) of -this interface. -*/ - -// ***************************************************************************** -/* Function: - void CLOCK_Initialize (void); - - Summary: - Initializes all the modules related to the system clock. - - Description: - This function initializes the clock as defined by the MHC and Clock Manager - selections. The function will configure the NVM Flash Wait states based on - the configured CPU operational frequency. It will then configure the - oscillators. - - For each of the clock sources (External Oscillator, Digital Phase Locked - Loop, Internal 48MHz Oscillator, External 32KHz oscillator and the Internal - 32KHz oscillator) enabled in MHC, the function will configure the clock - settings and will then wait till the clock is ready. In case of DPLL, the - function will wait till a lock is obtained. - - The function will then configure the Generic clock generators based on MHC - configurations. If a Generic Clock is enabled in MHC, this will be enabled - in the CLOCK_Initialize() function. The function will apply the CPU clock - divider and will wait for the Main Clock module to get ready. If the Main - Clock to the Peripheral APB and AHB interfaces was enabled in MHC, these - will be enabled in the CLOCK_Initialize() function. If the Peripheral Clock - Channels were enabled in MHC, these will be enabled in the - CLOCK_Initialize() function. - - The peripheral AHB and APB main clock and peripheral channel clocks will be - enabled when the peripheral specific initialize functions are called. This - will override the setting in MHC. The Generic Clock Generator source for - desired peripheral channel must be configured in MHC. - - Precondition: - MHC GUI should be configured with the right values. Incorrect configuration - of the Clock will result in incorrect peripheral behavior or a non - functional device. - - Parameters: - None. - - Returns: - None. - - Example: - - CLOCK_Initialize(); - - - Remarks: - This function should be called before calling other Clock library functions. -*/ - -void CLOCK_Initialize (void); - - - - -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif - -#endif /* PLIB_CLOCK_H */ - diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.c deleted file mode 100644 index e87bf923..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.c +++ /dev/null @@ -1,114 +0,0 @@ -/******************************************************************************* - External Interrupt Controller (EIC) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_eic.c - - Summary - Source for EIC peripheral library interface Implementation. - - Description - This file defines the interface to the EIC peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "plib_eic.h" -#include "interrupts.h" - -// ***************************************************************************** -// ***************************************************************************** -// Section: Global Data -// ***************************************************************************** -// ***************************************************************************** - - - -void EIC_Initialize (void) -{ - /* Reset all registers in the EIC module to their initial state and - EIC will be disabled. */ - EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_SWRST_Msk; - - while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_SWRST_Msk) == EIC_SYNCBUSY_SWRST_Msk) - { - /* Wait for sync */ - } - - /* EIC is by default clocked by GCLK */ - - /* NMI Control register */ - - /* Interrupt sense type and filter control for EXTINT channels 0 to 7*/ - EIC_REGS->EIC_CONFIG[0] = EIC_CONFIG_SENSE0_NONE | - EIC_CONFIG_SENSE1_NONE | - EIC_CONFIG_SENSE2_NONE | - EIC_CONFIG_SENSE3_NONE | - EIC_CONFIG_SENSE4_NONE | - EIC_CONFIG_SENSE5_NONE | - EIC_CONFIG_SENSE6_NONE | - EIC_CONFIG_SENSE7_NONE ; - - /* Interrupt sense type and filter control for EXTINT channels 8 to 15 */ - EIC_REGS->EIC_CONFIG[1] = EIC_CONFIG_SENSE0_NONE - | EIC_CONFIG_SENSE1_NONE - | EIC_CONFIG_SENSE2_NONE - | EIC_CONFIG_SENSE3_NONE - | EIC_CONFIG_SENSE4_NONE - | EIC_CONFIG_SENSE5_NONE - | EIC_CONFIG_SENSE6_NONE - | EIC_CONFIG_SENSE7_NONE ; - - - - - - - /* Enable the EIC */ - EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_ENABLE_Msk; - - while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_ENABLE_Msk) == EIC_SYNCBUSY_ENABLE_Msk) - { - /* Wait for sync */ - } -} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.h deleted file mode 100644 index 3e50f6bf..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/eic/plib_eic.h +++ /dev/null @@ -1,189 +0,0 @@ -/******************************************************************************* External Interrupt Controller (EIC) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_eic.h - - Summary - EIC PLIB Header File. - - Description - This file defines the interface to the EIC peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -/* Guards against multiple inclusion */ -#ifndef PLIB_EIC_H -#define PLIB_EIC_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "device.h" -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -/* The following data type definitions are used by the functions in this - interface and should be considered part of it. -*/ - -/* EIC Pin Count */ -#define EXTINT_COUNT (16U) - -// ***************************************************************************** -/* EIC Pins - - Summary: - Identifies the available EIC pins. - - Description: - This enumeration identifies all the available EIC pins. Not all pins will be - implemented in a device. The pins described here are for documentation - purposes only. The MHC will generate this enumeration with the enabled EIC - pins only. The application should not use the constant value that are - assigned to enumeration constants as this may vary between devices. - - Remarks: - None. -*/ - - - /* External Interrupt Controller Pin 11 */ -#define EIC_PIN_11 (11U) - - /* External Interrupt Controller Pin 14 */ -#define EIC_PIN_14 (14U) - -#define EIC_PIN_MAX (16U) - -typedef uint16_t EIC_PIN; - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** -/* The following functions make up the methods (set of possible operations) of - this interface. -*/ - -// ***************************************************************************** -/* Function: - void EIC_Initialize (void); - - Summary: - Initializes given instance of EIC peripheral. - - Description: - This function initializes given instance of EIC peripheral of the device - with the values configured in MHC GUI. - - Precondition: - MHC GUI should be configured with the right values. - - Parameters: - None. - - Returns: - None. - - Example: - - EIC_Initialize(); - - - Remarks: - This function should only be called once during system initialization - before any other EIC function is called. -*/ - -void EIC_Initialize (void); - -// ***************************************************************************** -/* Function: - void EIC_InterruptEnable (EIC_PIN pin) - - Summary: - Enables interrupts on a pin. - - Description - This function enables interrupts on an external interrupt pin. - When enabled, the interrupt pin sense will be configured as per the - configuration set in MHC. - - Precondition: - EIC_Initialize() function must have been called for the - associated instance. - - Parameters: - pin - EIC Pin number - - Returns: - None - - Example: - - EIC_Initialize(); - EIC_InterruptEnable(EIC_PIN_3); - - - Remarks: - None. -*/ - - -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif -#endif /* PLIB_EIC_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.c deleted file mode 100644 index 0876df57..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.c +++ /dev/null @@ -1,52 +0,0 @@ -/******************************************************************************* - EVSYS Peripheral Library - - Company: - Microchip Technology Inc. - - File Name: - plib_evsys.c - - Summary: - EVSYS Source File - - Description: - None - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#include "plib_evsys.h" -#include "interrupts.h" - - -void EVSYS_Initialize( void ) -{ /*Event Channel User Configuration*/ - - -} - - - diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.h deleted file mode 100644 index 9ea8b02b..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/evsys/plib_evsys.h +++ /dev/null @@ -1,68 +0,0 @@ -/******************************************************************************* - Interface definition of EVSYS PLIB. - - Company: - Microchip Technology Inc. - - File Name: - plib_evsys.h - - Summary: - Interface definition of the Event System Plib (EVSYS). - - Description: - This file defines the interface for the EVSYS Plib. - It allows user to setup event generators and users. -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef EVSYS_H // Guards against multiple inclusion -#define EVSYS_H - -#include "device.h" -#include -#include - -#ifdef __cplusplus // Provide C++ Compatibility - extern "C" { -#endif - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface -// ***************************************************************************** -// ***************************************************************************** - - - -/***************************** EVSYS API *******************************/ -void EVSYS_Initialize( void ); - -#ifdef __cplusplus // Provide C++ Compatibility - } -#endif - -#endif diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.c deleted file mode 100644 index d0a400c4..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.c +++ /dev/null @@ -1,127 +0,0 @@ -/******************************************************************************* - NVIC PLIB Implementation - - Company: - Microchip Technology Inc. - - File Name: - plib_nvic.c - - Summary: - NVIC PLIB Source File - - Description: - None - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#include "device.h" -#include "plib_nvic.h" - - -// ***************************************************************************** -// ***************************************************************************** -// Section: NVIC Implementation -// ***************************************************************************** -// ***************************************************************************** - -void NVIC_Initialize( void ) -{ - - /* Enable NVIC Controller */ - __DMB(); - __enable_irq(); - - /* Enable the interrupt sources and configure the priorities as configured - * from within the "Interrupt Manager" of MHC. */ - NVIC_SetPriority(RTC_IRQn, 3); - NVIC_EnableIRQ(RTC_IRQn); - NVIC_SetPriority(SERCOM0_IRQn, 3); - NVIC_EnableIRQ(SERCOM0_IRQn); - NVIC_SetPriority(SERCOM1_IRQn, 3); - NVIC_EnableIRQ(SERCOM1_IRQn); - NVIC_SetPriority(SERCOM3_IRQn, 3); - NVIC_EnableIRQ(SERCOM3_IRQn); - NVIC_SetPriority(CAN0_IRQn, 3); - NVIC_EnableIRQ(CAN0_IRQn); - - - - -} - -void NVIC_INT_Enable( void ) -{ - __DMB(); - __enable_irq(); -} - -bool NVIC_INT_Disable( void ) -{ - bool processorStatus = (__get_PRIMASK() == 0U); - - __disable_irq(); - __DMB(); - - return processorStatus; -} - -void NVIC_INT_Restore( bool state ) -{ - if( state == true ) - { - __DMB(); - __enable_irq(); - } - else - { - __disable_irq(); - __DMB(); - } -} - -bool NVIC_INT_SourceDisable( IRQn_Type source ) -{ - bool processorStatus; - bool intSrcStatus; - - processorStatus = NVIC_INT_Disable(); - intSrcStatus = (NVIC_GetEnableIRQ(source) != 0U); - NVIC_DisableIRQ( source ); - NVIC_INT_Restore( processorStatus ); - - /* return the source status */ - return intSrcStatus; -} - -void NVIC_INT_SourceRestore( IRQn_Type source, bool status ) -{ - if( status ) { - NVIC_EnableIRQ( source ); - } - - return; -} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.h deleted file mode 100644 index 6d36bd14..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvic/plib_nvic.h +++ /dev/null @@ -1,72 +0,0 @@ -/******************************************************************************* - NVIC PLIB Header - - Company: - Microchip Technology Inc. - - File Name: - plib_nvic.h - - Summary: - NVIC PLIB Header File - - Description: - None - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef PLIB_NVIC_H -#define PLIB_NVIC_H - -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - - -/***************************** NVIC Inline *******************************/ - -void NVIC_Initialize( void ); -void NVIC_INT_Enable( void ); -bool NVIC_INT_Disable( void ); -void NVIC_INT_Restore( bool state ); -bool NVIC_INT_SourceDisable( IRQn_Type source ); -void NVIC_INT_SourceRestore( IRQn_Type source, bool status ); - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END -#endif // PLIB_NVIC_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c deleted file mode 100644 index 36679253..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c +++ /dev/null @@ -1,260 +0,0 @@ -/******************************************************************************* - Non-Volatile Memory Controller(NVMCTRL) PLIB. - - Company: - Microchip Technology Inc. - - File Name: - plib_nvmctrl.c - - Summary: - Interface definition of NVMCTRL Plib. - - Description: - This file defines the interface for the NVMCTRL Plib. - It allows user to Program, Erase and lock the on-chip Non Volatile Flash - Memory. -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include -#include "interrupts.h" -#include "plib_nvmctrl.h" - - -// ***************************************************************************** -// ***************************************************************************** -// Section: NVMCTRL Implementation -// ***************************************************************************** -// ***************************************************************************** - - -void NVMCTRL_Initialize(void) -{ - NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY | NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS | NVMCTRL_CTRLB_RWS(2UL) | NVMCTRL_CTRLB_MANW_Msk; -} - -void NVMCTRL_CacheInvalidate(void) -{ - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_INVALL | NVMCTRL_CTRLA_CMDEX_KEY); -} -bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ) -{ - uint32_t *paddress = (uint32_t*)address; - (void)memcpy(data, paddress, length); - return true; -} - -bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ) -{ - uint32_t i; - uint32_t * paddress = (uint32_t *)address; - - /* Writing 32-bit words in the given address */ - for ( i = 0U; i < (NVMCTRL_RWWEEPROM_PAGESIZE/4U); i++) - { - *paddress = *(data + i); - paddress++; - } - - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEWP | NVMCTRL_CTRLA_CMDEX_KEY); - - return true; -} - -bool NVMCTRL_RWWEEPROM_RowErase( uint32_t address ) -{ - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEER | NVMCTRL_CTRLA_CMDEX_KEY); - - return true; -} -bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ) -{ - uint32_t *paddress = (uint32_t*)address; - (void)memcpy(data, paddress, length); - return true; -} - -bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address) -{ - uint32_t i; - uint32_t * paddress = (uint32_t *)address; - - /* writing 32-bit data into the given address */ - for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) - { - *paddress = *(data + i); - paddress++; - } - - return true; -} - -bool NVMCTRL_PageBufferCommit( const uint32_t address) -{ - uint16_t command = NVMCTRL_CTRLA_CMD_WP_Val; - - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - if (address >= NVMCTRL_RWWEEPROM_START_ADDRESS) - { - command = NVMCTRL_CTRLA_CMD_RWWEEWP; - } - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(command | NVMCTRL_CTRLA_CMDEX_KEY); - - - return true; -} - -bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ) -{ - uint32_t i; - uint32_t * paddress = (uint32_t *)address; - - /* writing 32-bit data into the given address */ - for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) - { - *paddress = *(data + i); - paddress++; - } - - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_WP_Val | NVMCTRL_CTRLA_CMDEX_KEY); - - return true; -} - -bool NVMCTRL_RowErase( uint32_t address ) -{ - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_ER_Val | NVMCTRL_CTRLA_CMDEX_KEY); - - return true; -} - -bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ) -{ - uint32_t i; - uint32_t * paddress = (uint32_t *)address; - bool pagewrite_val = false; - - if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= ((NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE) - NVMCTRL_USERROW_PAGESIZE))) - { - /* writing 32-bit data into the given address */ - for (i = 0U; i < (NVMCTRL_USERROW_PAGESIZE/4U); i++) - { - *paddress = data[i]; - paddress++; - } - - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_WAP_Val | NVMCTRL_CTRLA_CMDEX_KEY; - - - pagewrite_val = true; - } - - return pagewrite_val; -} - -bool NVMCTRL_USER_ROW_RowErase( uint32_t address ) -{ - bool rowerase = false; - if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= (NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE))) - { - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_EAR_Val | NVMCTRL_CTRLA_CMDEX_KEY; - - - rowerase = true; - } - - return rowerase; -} - -NVMCTRL_ERROR NVMCTRL_ErrorGet( void ) -{ - uint16_t nvm_error; - - /* Get the error bits set */ - nvm_error = (NVMCTRL_REGS->NVMCTRL_STATUS & (NVMCTRL_STATUS_NVME_Msk | NVMCTRL_STATUS_LOCKE_Msk | NVMCTRL_STATUS_PROGE_Msk)); - - /* Clear the error bits in both STATUS and INTFLAG register */ - NVMCTRL_REGS->NVMCTRL_STATUS |= nvm_error; - - NVMCTRL_REGS->NVMCTRL_INTFLAG = NVMCTRL_INTFLAG_ERROR_Msk; - - return ((NVMCTRL_ERROR) nvm_error); -} - -bool NVMCTRL_IsBusy(void) -{ - return ((NVMCTRL_REGS->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_READY_Msk)!= NVMCTRL_INTFLAG_READY_Msk); -} - -void NVMCTRL_RegionLock(uint32_t address) -{ - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_LR_Val | NVMCTRL_CTRLA_CMDEX_KEY); -} - -void NVMCTRL_RegionUnlock(uint32_t address) -{ - /* Set address and command */ - NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; - - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_UR_Val | NVMCTRL_CTRLA_CMDEX_KEY); -} - -void NVMCTRL_SecurityBitSet(void) -{ - NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_SSB_Val | NVMCTRL_CTRLA_CMDEX_KEY); -} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h deleted file mode 100644 index 365c2866..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h +++ /dev/null @@ -1,137 +0,0 @@ -/******************************************************************************* - Non-Volatile Memory Controller(NVMCTRL) PLIB. - - Company: - Microchip Technology Inc. - - File Name: - plib_nvmctrl.h - - Summary: - Interface definition of NVMCTRL Plib. - - Description: - This file defines the interface for the NVMCTRL Plib. - It allows user to Program, Erase and lock the on-chip Non Volatile Flash - Memory. -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_NVMCTRL_H -#define PLIB_NVMCTRL_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include "device.h" -#include -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - extern "C" { -#endif - -// DOM-IGNORE-END -// ***************************************************************************** -// ***************************************************************************** -// Section: Preprocessor macros -// ***************************************************************************** -// ***************************************************************************** - -#define NVMCTRL_FLASH_START_ADDRESS (0x00000000U) -#define NVMCTRL_FLASH_PAGESIZE (64U) -#define NVMCTRL_FLASH_ROWSIZE (256U) - -#define NVMCTRL_EMULATED_EEPROM_START_ADDRESS (0x40000U) -#define NVMCTRL_EMULATED_EEPROM_PAGESIZE (64U) -#define NVMCTRL_EMULATED_EEPROM_SIZE (0U) - -#define NVMCTRL_RWWEEPROM_START_ADDRESS (0x00400000U) -#define NVMCTRL_RWWEEPROM_SIZE (0x2000U) -#define NVMCTRL_RWWEEPROM_PAGESIZE (64U) -#define NVMCTRL_RWWEEPROM_ROWSIZE (256U) - -#define NVMCTRL_USERROW_START_ADDRESS (0x00804000U) -#define NVMCTRL_USERROW_SIZE (0x100U) -#define NVMCTRL_USERROW_PAGESIZE (64U) - -#define NVMCTRL_ERROR_NONE 0x0U -#define NVMCTRL_ERROR_PROG 0x4U -#define NVMCTRL_ERROR_LOCK 0x8U -#define NVMCTRL_ERROR_NVM 0x10U - -typedef uint16_t NVMCTRL_ERROR; - - -void NVMCTRL_Initialize(void); - -bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ); - -bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ); - - -bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address); - -bool NVMCTRL_PageBufferCommit( const uint32_t address); - - -bool NVMCTRL_RowErase( uint32_t address ); - -bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ); - -bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ); - -bool NVMCTRL_RWWEEPROM_RowErase ( uint32_t address ); - -NVMCTRL_ERROR NVMCTRL_ErrorGet( void ); - -bool NVMCTRL_IsBusy( void ); - -void NVMCTRL_RegionLock (uint32_t address); - -void NVMCTRL_RegionUnlock (uint32_t address); - -void NVMCTRL_SecurityBitSet(void); - - -bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ); - -bool NVMCTRL_USER_ROW_RowErase( uint32_t address ); - -void NVMCTRL_CacheInvalidate ( void ); - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif -// DOM-IGNORE-END -#endif // PLIB_NVMCTRL_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.c deleted file mode 100644 index 53c22749..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.c +++ /dev/null @@ -1,309 +0,0 @@ -/******************************************************************************* - PORT PLIB - - Company: - Microchip Technology Inc. - - File Name: - plib_port.c - - Summary: - Interface definition of PORT PLIB - - Description: - This file provides an interface to control and interact with PORT-I/O - Pin controller module. - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include "plib_port.h" - -// ***************************************************************************** -// ***************************************************************************** -// Section: PORT Implementation -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** -/* Function: - uint32_t PORT_GroupRead(PORT_GROUP group) - - Summary: - Read all the I/O pins in the specified port group. - - Description: - The function reads the hardware pin state of all pins in the specified group - and returns this as a 32 bit value. Each bit in the 32 bit value represent a - pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will - represent PA1 and so on. The application should only consider the value of - the port group pins which are implemented on the device. - - Remarks: - Refer plib_port.h file for more information. -*/ - -uint32_t PORT_GroupRead(PORT_GROUP group) -{ - return (((port_group_registers_t*)group)->PORT_IN); -} - -// ***************************************************************************** -/* Function: - void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); - - Summary: - Write value on the masked pins of the selected port group. - - Description: - This function writes the value contained in the value parameter to the - port group. Port group pins which are configured for output will be updated. - The mask parameter provides additional control on the bits in the group to - be affected. Setting a bit to 1 in the mask will cause the corresponding - bit in the port group to be updated. Clearing a bit in the mask will cause - that corresponding bit in the group to stay unaffected. For example, - setting a mask value 0xFFFFFFFF will cause all bits in the port group - to be updated. Setting a value 0x3 will only cause port group bit 0 and - bit 1 to be updated. - - For port pins which are not configured for output and have the pull feature - enabled, this function will affect pull value (pull up or pull down). A bit - value of 1 will enable the pull up. A bit value of 0 will enable the pull - down. - - Remarks: - Refer plib_port.h file for more information. -*/ - -void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value) -{ - /* Write the desired value */ - ((port_group_registers_t*)group)->PORT_OUT = (((port_group_registers_t*)group)->PORT_OUT & (~mask)) | (mask & value); -} - -// ***************************************************************************** -/* Function: - uint32_t PORT_GroupLatchRead(PORT_GROUP group) - - Summary: - Read the data driven on all the I/O pins of the selected port group. - - Description: - The function will return a 32-bit value representing the logic levels being - driven on the output pins within the group. The function will not sample the - actual hardware state of the output pin. Each bit in the 32-bit return value - will represent one of the 32 port pins within the group. The application - should only consider the value of the pins which are available on the - device. - - Remarks: - Refer plib_port.h file for more information. -*/ - -uint32_t PORT_GroupLatchRead(PORT_GROUP group) -{ - return (((port_group_registers_t*)group)->PORT_OUT); -} - -// ***************************************************************************** -/* Function: - void PORT_GroupSet(PORT_GROUP group, uint32_t mask) - - Summary: - Set the selected IO pins of a group. - - Description: - This function sets (drives a logic high) on the selected output pins of a - group. The mask parameter control the pins to be updated. A mask bit - position with a value 1 will cause that corresponding port pin to be set. A - mask bit position with a value 0 will cause the corresponding port pin to - stay un-affected. - - Remarks: - Refer plib_port.h file for more information. -*/ - -void PORT_GroupSet(PORT_GROUP group, uint32_t mask) -{ - ((port_group_registers_t*)group)->PORT_OUTSET = mask; -} - -// ***************************************************************************** -/* Function: - void PORT_GroupClear(PORT_GROUP group, uint32_t mask) - - Summary: - Clears the selected IO pins of a group. - - Description: - This function clears (drives a logic 0) on the selected output pins of a - group. The mask parameter control the pins to be updated. A mask bit - position with a value 1 will cause that corresponding port pin to be clear. - A mask bit position with a value 0 will cause the corresponding port pin to - stay un-affected. - - Remarks: - Refer plib_port.h file for more information. -*/ - -void PORT_GroupClear(PORT_GROUP group, uint32_t mask) -{ - ((port_group_registers_t*)group)->PORT_OUTCLR = mask; -} - -// ***************************************************************************** -/* Function: - void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) - - Summary: - Toggles the selected IO pins of a group. - - Description: - This function toggles the selected output pins of a group. The mask - parameter control the pins to be updated. A mask bit position with a value 1 - will cause that corresponding port pin to be toggled. A mask bit position - with a value 0 will cause the corresponding port pin to stay un-affected. - - Remarks: - Refer plib_port.h file for more information. -*/ - -void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) -{ - ((port_group_registers_t*)group)->PORT_OUTTGL = mask; -} - -// ***************************************************************************** -/* Function: - void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) - - Summary: - Configures the selected IO pins of a group as input. - - Description: - This function configures the selected IO pins of a group as input. The pins - to be configured as input are selected by setting the corresponding bits in - the mask parameter to 1. - - Remarks: - Refer plib_port.h file for more information. -*/ - -void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) -{ - ((port_group_registers_t*)group)->PORT_DIRCLR = mask; - - for(uint32_t i = 0U; i < 32U; i++) - { - if((mask & ((uint32_t)1U << i)) != 0U) - { - ((port_group_registers_t*)group)->PORT_PINCFG[i] |= PORT_PINCFG_INEN_Msk; - } - } -} - -// ***************************************************************************** -/* Function: - void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) - - Summary: - Configures the selected IO pins of a group as output. - - Description: - This function configures the selected IO pins of a group as output. The pins - to be configured as output are selected by setting the corresponding bits in - the mask parameter to 1. - - Remarks: - Refer plib_port.h file for more information. -*/ - -void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) -{ - ((port_group_registers_t*)group)->PORT_DIRSET = mask; -} - -// ***************************************************************************** -/* Function: - void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) - - Summary: - Configures the peripheral function on the selected port pin - - Description: - This function configures the selected peripheral function on the given port pin. - - Remarks: - Refer plib_port.h file for more information. -*/ -void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) -{ - uint32_t periph_func = (uint32_t) function; - PORT_GROUP group = GET_PORT_GROUP(pin); - uint32_t pin_num = ((uint32_t)pin) & 0x1FU; - uint32_t pinmux_val = (uint32_t)((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)]; - - /* For odd pins */ - if (0U != (pin_num & 0x01U)) - { - pinmux_val = (pinmux_val & ~0xF0U) | (periph_func << 4); - } - else - { - pinmux_val = (pinmux_val & ~0x0FU) | periph_func; - } - ((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)] = (uint8_t)pinmux_val; - - /* Enable peripheral control of the pin */ - ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] |= (uint8_t)PORT_PINCFG_PMUXEN_Msk; -} - -// ***************************************************************************** -/* Function: - void PORT_PinGPIOConfig(PORT_PIN pin) - - Summary: - Configures the selected pin as GPIO - - Description: - This function configures the given pin as GPIO. - - Remarks: - Refer plib_port.h file for more information. -*/ -void PORT_PinGPIOConfig(PORT_PIN pin) -{ - PORT_GROUP group = GET_PORT_GROUP(pin); - uint32_t pin_num = ((uint32_t)pin) & 0x1FU; - - /* Disable peripheral control of the pin */ - ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); -} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.h deleted file mode 100644 index b52fe9c4..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/port/plib_port.h +++ /dev/null @@ -1,918 +0,0 @@ -/******************************************************************************* - PORT PLIB - - Company: - Microchip Technology Inc. - - File Name: - plib_port.h - - Summary: - PORT PLIB Header File - - Description: - This file provides an interface to control and interact with PORT-I/O - Pin controller module. - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef PLIB_PORT_H -#define PLIB_PORT_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include "device.h" -#include -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - extern "C" { -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data types and constants -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* PORT Group - - Summary: - Identifies the port groups available on the device. - - Description: - These macros identifies all the ports groups that are available on this - device. - - Remarks: - The caller should not use the constant expressions assigned to any of - the preprocessor macros as these may vary between devices. - - Port groups shown here are the ones available on the selected device. Not - all ports groups are implemented. Refer to the device specific datasheet - for more details. The MHC will generate these macros with the port - groups that are available on the device. -*/ - -/* Group 0 */ -#define PORT_GROUP_0 (PORT_BASE_ADDRESS + (0U * 0x80U)) - - -/* Helper macros to get port information from the pin */ -#define GET_PORT_GROUP(pin) ((PORT_GROUP)(PORT_BASE_ADDRESS + (0x80U * (((uint32_t)pin) >> 5U)))) -#define GET_PIN_MASK(pin) (((uint32_t)(0x1U)) << (((uint32_t)pin) & 0x1FU)) - -/* Named type for port group */ -typedef uint32_t PORT_GROUP; - - -typedef enum -{ -PERIPHERAL_FUNCTION_A = 0x0, -PERIPHERAL_FUNCTION_B = 0x1, -PERIPHERAL_FUNCTION_C = 0x2, -PERIPHERAL_FUNCTION_D = 0x3, -PERIPHERAL_FUNCTION_E = 0x4, -PERIPHERAL_FUNCTION_F = 0x5, -PERIPHERAL_FUNCTION_G = 0x6, -PERIPHERAL_FUNCTION_H = 0x7, -PERIPHERAL_FUNCTION_I = 0x8, - -}PERIPHERAL_FUNCTION; - -// ***************************************************************************** -/* PORT Pins - - Summary: - Identifies the available Ports pins. - - Description: - This enumeration identifies all the ports pins that are available on this - device. - - Remarks: - The caller should not use the constant expressions assigned to any of - the enumeration constants as these may vary between devices. - - Port pins shown here are the ones available on the selected device. Not - all ports pins within a port group are implemented. Refer to the device - specific datasheet for more details. -*/ - -typedef enum -{ - /* PA00 pin */ - PORT_PIN_PA00 = 0U, - - /* PA01 pin */ - PORT_PIN_PA01 = 1U, - - /* PA02 pin */ - PORT_PIN_PA02 = 2U, - - /* PA03 pin */ - PORT_PIN_PA03 = 3U, - - /* PA04 pin */ - PORT_PIN_PA04 = 4U, - - /* PA05 pin */ - PORT_PIN_PA05 = 5U, - - /* PA06 pin */ - PORT_PIN_PA06 = 6U, - - /* PA07 pin */ - PORT_PIN_PA07 = 7U, - - /* PA08 pin */ - PORT_PIN_PA08 = 8U, - - /* PA09 pin */ - PORT_PIN_PA09 = 9U, - - /* PA10 pin */ - PORT_PIN_PA10 = 10U, - - /* PA11 pin */ - PORT_PIN_PA11 = 11U, - - /* PA14 pin */ - PORT_PIN_PA14 = 14U, - - /* PA15 pin */ - PORT_PIN_PA15 = 15U, - - /* PA16 pin */ - PORT_PIN_PA16 = 16U, - - /* PA17 pin */ - PORT_PIN_PA17 = 17U, - - /* PA18 pin */ - PORT_PIN_PA18 = 18U, - - /* PA19 pin */ - PORT_PIN_PA19 = 19U, - - /* PA22 pin */ - PORT_PIN_PA22 = 22U, - - /* PA23 pin */ - PORT_PIN_PA23 = 23U, - - /* PA24 pin */ - PORT_PIN_PA24 = 24U, - - /* PA25 pin */ - PORT_PIN_PA25 = 25U, - - /* PA27 pin */ - PORT_PIN_PA27 = 27U, - - /* PA28 pin */ - PORT_PIN_PA28 = 28U, - - /* PA30 pin */ - PORT_PIN_PA30 = 30U, - - /* PA31 pin */ - PORT_PIN_PA31 = 31U, - - /* This element should not be used in any of the PORT APIs. - * It will be used by other modules or application to denote that none of - * the PORT Pin is used */ - PORT_PIN_NONE = 65535U, - -} PORT_PIN; - -// ***************************************************************************** -// ***************************************************************************** -// Section: Generated API based on pin configurations done in Pin Manager -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** -// Section: PORT APIs which operates on multiple pins of a group -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* Function: - uint32_t PORT_GroupRead(PORT_GROUP group) - - Summary: - Read all the I/O pins in the specified port group. - - Description: - The function reads the hardware pin state of all pins in the specified group - and returns this as a 32 bit value. Each bit in the 32 bit value represent a - pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will - represent PA1 and so on. The application should only consider the value of - the port group pins which are implemented on the device. - - Precondition: - The PORT_Initialize() function should have been called. Input buffer - (INEN bit in the Pin Configuration register) should be enabled in MHC. - - Parameters: - group - One of the IO groups from the enum PORT_GROUP. - - Returns: - A 32-bit value representing the hardware state of of all the I/O pins in the - selected port group. - - Example: - - - uint32_t value; - value = PORT_Read(PORT_GROUP_C); - - - - Remarks: - None. -*/ - -uint32_t PORT_GroupRead(PORT_GROUP group); - -// ***************************************************************************** -/* Function: - uint32_t PORT_GroupLatchRead(PORT_GROUP group) - - Summary: - Read the data driven on all the I/O pins of the selected port group. - - Description: - The function will return a 32-bit value representing the logic levels being - driven on the output pins within the group. The function will not sample the - actual hardware state of the output pin. Each bit in the 32-bit return value - will represent one of the 32 port pins within the group. The application - should only consider the value of the pins which are available on the - device. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One of the IO groups from the enum PORT_GROUP. - - Returns: - A 32-bit value representing the output state of of all the I/O pins in the - selected port group. - - Example: - - - uint32_t value; - value = PORT_GroupLatchRead(PORT_GROUP_C); - - - - Remarks: - None. -*/ - -uint32_t PORT_GroupLatchRead(PORT_GROUP group); - -// ***************************************************************************** -/* Function: - void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); - - Summary: - Write value on the masked pins of the selected port group. - - Description: - This function writes the value contained in the value parameter to the - port group. Port group pins which are configured for output will be updated. - The mask parameter provides additional control on the bits in the group to - be affected. Setting a bit to 1 in the mask will cause the corresponding - bit in the port group to be updated. Clearing a bit in the mask will cause - that corresponding bit in the group to stay unaffected. For example, - setting a mask value 0xFFFFFFFF will cause all bits in the port group - to be updated. Setting a value 0x3 will only cause port group bit 0 and - bit 1 to be updated. - - For port pins which are not configured for output and have the pull feature - enabled, this function will affect pull value (pull up or pull down). A bit - value of 1 will enable the pull up. A bit value of 0 will enable the pull - down. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One of the IO groups from the enum PORT_GROUP. - - mask - A 32 bit value in which positions of 0s and 1s decide - which IO pins of the selected port group will be written. - 1's - Will write to corresponding IO pins. - 0's - Will remain unchanged. - - value - Value which has to be written/driven on the I/O - lines of the selected port for which mask bits are '1'. - Values for the corresponding mask bit '0' will be ignored. - Refer to the function description for effect on pins - which are not configured for output. - - Returns: - None. - - Example: - - - PORT_GroupWrite(PORT_GROUP_C, 0x0F, 0xF563D453); - - - - Remarks: - None. -*/ - -void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); - -// ***************************************************************************** -/* Function: - void PORT_GroupSet(PORT_GROUP group, uint32_t mask) - - Summary: - Set the selected IO pins of a group. - - Description: - This function sets (drives a logic high) on the selected output pins of a - group. The mask parameter control the pins to be updated. A mask bit - position with a value 1 will cause that corresponding port pin to be set. A - mask bit position with a value 0 will cause the corresponding port pin to - stay un-affected. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One of the IO ports from the enum PORT_GROUP. - mask - A 32 bit value in which a bit represent a pin in the group. If the - value of the bit is 1, the corresponding port pin will driven to logic 1. If - the value of the bit is 0. the corresponding port pin will stay un-affected. - - Returns: - None. - - Example: - - - PORT_GroupSet(PORT_GROUP_C, 0x00A0); - - - - Remarks: - If the port pin within the the group is not configured for output and has - the pull feature enabled, driving a logic 1 on this pin will cause the pull - up to be enabled. -*/ - -void PORT_GroupSet(PORT_GROUP group, uint32_t mask); - -// ***************************************************************************** -/* Function: - void PORT_GroupClear(PORT_GROUP group, uint32_t mask) - - Summary: - Clears the selected IO pins of a group. - - Description: - This function clears (drives a logic 0) on the selected output pins of a - group. The mask parameter control the pins to be updated. A mask bit - position with a value 1 will cause that corresponding port pin to be clear. - A mask bit position with a value 0 will cause the corresponding port pin to - stay un-affected. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One of the IO ports from the enum PORT_GROUP. - mask - A 32 bit value in which a bit represent a pin in the group. If the - value of the bit is 1, the corresponding port pin will driven to logic 0. If - the value of the bit is 0. the corresponding port pin will stay un-affected. - - Returns: - None. - - Example: - - - PORT_GroupClear(PORT_GROUP_C, 0x00A0); - - - - Remarks: - If the port pin within the the group is not configured for output and has - the pull feature enabled, driving a logic 0 on this pin will cause the pull - down to be enabled. -*/ - -void PORT_GroupClear(PORT_GROUP group, uint32_t mask); - -// ***************************************************************************** -/* Function: - void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) - - Summary: - Toggles the selected IO pins of a group. - - Description: - This function toggles the selected output pins of a group. The mask - parameter control the pins to be updated. A mask bit position with a value 1 - will cause that corresponding port pin to be toggled. A mask bit position - with a value 0 will cause the corresponding port pin to stay un-affected. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One of the IO ports from the enum PORT_GROUP. - mask - A 32 bit value in which a bit represent a pin in the group. If the - value of the bit is 1, the corresponding port pin will be toggled. If the - value of the bit is 0. the corresponding port pin will stay un-affected. - - Returns: - None. - - Example: - - - PORT_GroupToggle(PORT_GROUP_C, 0x00A0); - - - - Remarks: - If the port pin within the the group is not configured for output and has - the pull feature enabled, driving a logic 0 on this pin will cause the pull - down to be enabled. Driving a logic 1 on this pin will cause the pull up to - be enabled. -*/ - -void PORT_GroupToggle(PORT_GROUP group, uint32_t mask); - -// ***************************************************************************** -/* Function: - void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) - - Summary: - Configures the selected IO pins of a group as input. - - Description: - This function configures the selected IO pins of a group as input. The pins - to be configured as input are selected by setting the corresponding bits in - the mask parameter to 1. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One or more of the of the IO ports from the enum PORT_GROUP. - mask - A 32 bit value in which a bit represents a pin in the group. If the - value of the bit is 1, the corresponding port pin will be configured as - input. If the value of the bit is 0. the corresponding port pin will stay - un-affected. - - Returns: - None. - - Example: - - - PORT_GroupInputEnable(PORT_GROUP_C, 0x00A0); - - - - Remarks: - None. -*/ - -void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask); - -// ***************************************************************************** -/* Function: - void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) - - Summary: - Configures the selected IO pins of a group as output. - - Description: - This function configures the selected IO pins of a group as output. The pins - to be configured as output are selected by setting the corresponding bits in - the mask parameter to 1. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - group - One or more of the of the IO ports from the enum PORT_GROUP. - mask - A 32 bit value in which a bit represents a pin in the group. If the - value of the bit is 1, the corresponding port pin will be configured as - output. If the value of the bit is 0. the corresponding port pin will stay - un-affected. - - Returns: - None. - - Example: - - - PORT_GroupOutputEnable(PORT_GROUP_C, 0x00A0); - - - - Remarks: - None. -*/ - -void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask); - -// ***************************************************************************** -/* Function: - void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) - - Summary: - Configures the peripheral function on the selected port pin - - Description: - This function configures the selected peripheral function on the given port pin. - - Remarks: - None -*/ -void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function); - -// ***************************************************************************** -/* Function: - void PORT_PinGPIOConfig(PORT_PIN pin) - - Summary: - Configures the selected pin as GPIO - - Description: - This function configures the given pin as GPIO. - - Remarks: - None -*/ -void PORT_PinGPIOConfig(PORT_PIN pin); - -// ***************************************************************************** -// ***************************************************************************** -// Section: PORT APIs which operates on one pin at a time -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* Function: - void PORT_PinWrite(PORT_PIN pin, bool value) - - Summary: - Writes the specified value to the selected pin. - - Description: - This function writes/drives the "value" on the selected I/O line/pin. - - Precondition: - The PORT_Initialize() function should have been called once. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - value - value to be written on the selected pin. - true = set pin to high (1). - false = clear pin to low (0). - - Returns: - None. - - Example: - - - bool value = true; - PORT_PinWrite(PORT_PIN_PB3, value); - - - - Remarks: - Calling this function with an input pin with the pull-up/pull-down feature - enabled will affect the pull-up/pull-down configuration. If the value is - false, the pull-down will be enabled. If the value is true, the pull-up will - be enabled. -*/ - -static inline void PORT_PinWrite(PORT_PIN pin, bool value) -{ - PORT_GroupWrite(GET_PORT_GROUP(pin), - GET_PIN_MASK(pin), - (value ? GET_PIN_MASK(pin) : 0U)); -} - - -// ***************************************************************************** -/* Function: - bool PORT_PinRead(PORT_PIN pin) - - Summary: - Read the selected pin value. - - Description: - This function reads the present state at the selected input pin. The - function can also be called to read the value of an output pin if input - sampling on the output pin is enabled in MHC. If input synchronization on - the pin is disabled in MHC, the function will cause a 2 PORT Clock cycles - delay. Enabling the synchronization eliminates the delay but will increase - power consumption. - - Precondition: - The PORT_Initialize() function should have been called. Input buffer - (INEN bit in the Pin Configuration register) should be enabled in MHC. - - Parameters: - pin - the port pin whose state needs to be read. - - Returns: - true - the state at the pin is a logic high. - false - the state at the pin is a logic low. - - Example: - - - bool value; - value = PORT_PinRead(PORT_PIN_PB3); - - - - Remarks: - None. -*/ - -static inline bool PORT_PinRead(PORT_PIN pin) -{ - return ((PORT_GroupRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); -} - - -// ***************************************************************************** -/* Function: - bool PORT_PinLatchRead(PORT_PIN pin) - - Summary: - Read the value driven on the selected pin. - - Description: - This function reads the data driven on the selected I/O line/pin. The - function does not sample the state of the hardware pin. It only returns the - value that is written to output register. Refer to the PORT_PinRead() - function if the state of the output pin needs to be read. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - - Returns: - true - the present value in the output latch is a logic high. - false - the present value in the output latch is a logic low. - - Example: - - - bool value; - value = PORT_PinLatchRead(PORT_PIN_PB3); - - - - Remarks: - To read actual pin value, PIN_Read API should be used. -*/ - -static inline bool PORT_PinLatchRead(PORT_PIN pin) -{ - return ((PORT_GroupLatchRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); -} - - -// ***************************************************************************** -/* Function: - void PORT_PinToggle(PORT_PIN pin) - - Summary: - Toggles the selected pin. - - Description: - This function toggles/inverts the present value on the selected I/O line/pin. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - - Returns: - None. - - Example: - - - PORT_PinToggle(PORT_PIN_PB3); - - - - Remarks: - None. -*/ - -static inline void PORT_PinToggle(PORT_PIN pin) -{ - PORT_GroupToggle(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); -} - - -// ***************************************************************************** -/* Function: - void PORT_PinSet(PORT_PIN pin) - - Summary: - Sets the selected pin. - - Description: - This function drives a logic 1 on the selected I/O line/pin. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - - Returns: - None. - - Example: - - - PORT_PinSet(PORT_PIN_PB3); - - - - Remarks: - None. -*/ - -static inline void PORT_PinSet(PORT_PIN pin) -{ - PORT_GroupSet(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); -} - - -// ***************************************************************************** -/* Function: - void PORT_PinClear(PORT_PIN pin) - - Summary: - Clears the selected pin. - - Description: - This function drives a logic 0 on the selected I/O line/pin. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - - Returns: - None. - - Example: - - - PORT_PinClear(PORT_PIN_PB3); - - - - Remarks: - None. -*/ - -static inline void PORT_PinClear(PORT_PIN pin) -{ - PORT_GroupClear(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); -} - - -// ***************************************************************************** -/* Function: - void PORT_PinInputEnable(PORT_PIN pin) - - Summary: - Configures the selected IO pin as input. - - Description: - This function configures the selected IO pin as input. This function - override the MHC input output pin settings. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - - Returns: - None. - - Example: - - - PORT_PinInputEnable(PORT_PIN_PB3); - - - - Remarks: - None. -*/ - -static inline void PORT_PinInputEnable(PORT_PIN pin) -{ - PORT_GroupInputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); -} - - -// ***************************************************************************** -/* Function: - void PORT_PinOutputEnable(PORT_PIN pin) - - Summary: - Enables selected IO pin as output. - - Description: - This function enables selected IO pin as output. Calling this function will - override the MHC input output pin configuration. - - Precondition: - The PORT_Initialize() function should have been called. - - Parameters: - pin - One of the IO pins from the enum PORT_PIN. - - Returns: - None. - - Example: - - - PORT_PinOutputEnable(PORT_PIN_PB3); - - - - Remarks: - None. -*/ - -static inline void PORT_PinOutputEnable(PORT_PIN pin) -{ - PORT_GroupOutputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); -} - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - -} - -#endif -// DOM-IGNORE-END -#endif // PLIB_PORT_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc.h deleted file mode 100644 index a68c0c25..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc.h +++ /dev/null @@ -1,116 +0,0 @@ -/******************************************************************************* - Real Time Counter (RTC) PLIB - - Company: - Microchip Technology Inc. - - File Name: - plib_rtc.h - - Summary: - RTC PLIB Header file - - Description: - This file defines the interface to the RTC peripheral library. This - library provides access to and control of the associated peripheral - instance. - -*******************************************************************************/ -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_RTC_H -#define PLIB_RTC_H - -#include "device.h" -#include -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility -extern "C" { -#endif -// DOM-IGNORE-END -// ***************************************************************************** -// ***************************************************************************** -// Section:Preprocessor macros -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** - -/* Frequency of Counter Clock for RTC */ -#define RTC_COUNTER_CLOCK_FREQUENCY (1024U / (1UL << (0x1U - 1U))) - -#define RTC_TIMER32_INT_MASK_PER0 RTC_MODE0_INTENSET_PER0_Msk -#define RTC_TIMER32_INT_MASK_PER1 RTC_MODE0_INTENSET_PER1_Msk -#define RTC_TIMER32_INT_MASK_PER2 RTC_MODE0_INTENSET_PER2_Msk -#define RTC_TIMER32_INT_MASK_PER3 RTC_MODE0_INTENSET_PER3_Msk -#define RTC_TIMER32_INT_MASK_PER4 RTC_MODE0_INTENSET_PER4_Msk -#define RTC_TIMER32_INT_MASK_PER5 RTC_MODE0_INTENSET_PER5_Msk -#define RTC_TIMER32_INT_MASK_PER6 RTC_MODE0_INTENSET_PER6_Msk -#define RTC_TIMER32_INT_MASK_PER7 RTC_MODE0_INTENSET_PER7_Msk -#define RTC_TIMER32_INT_MASK_CMP0 RTC_MODE0_INTENSET_CMP0_Msk -#define RTC_TIMER32_INT_MASK_OVF RTC_MODE0_INTENSET_OVF_Msk -#define RTC_TIMER32_INT_MASK_INVALID 0xFFFFFFFFU -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** - -typedef uint32_t RTC_TIMER32_INT_MASK; -typedef void (*RTC_TIMER32_CALLBACK)( RTC_TIMER32_INT_MASK intCause, uintptr_t context ); - -typedef struct -{ - /* Timer 32Bit */ - RTC_TIMER32_CALLBACK timer32BitCallback; - RTC_TIMER32_INT_MASK timer32intCause; - uintptr_t context; -} RTC_OBJECT; - -void RTC_Initialize(void); -void RTC_Timer32CountSyncEnable ( void ); -void RTC_Timer32CountSyncDisable ( void ); -void RTC_Timer32Start ( void ); -void RTC_Timer32Stop ( void ); -void RTC_Timer32CounterSet ( uint32_t count ); -uint32_t RTC_Timer32CounterGet ( void ); -uint32_t RTC_Timer32FrequencyGet ( void ); -void RTC_Timer32CompareSet ( uint32_t compareValue ); -uint32_t RTC_Timer32PeriodGet ( void ); -void RTC_Timer32InterruptEnable( RTC_TIMER32_INT_MASK interruptMask ); -void RTC_Timer32InterruptDisable( RTC_TIMER32_INT_MASK interruptMask ); -void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ); - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif -// DOM-IGNORE-END - -#endif /* PLIB_RTC_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc_timer.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc_timer.c deleted file mode 100644 index d6566db1..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/rtc/plib_rtc_timer.c +++ /dev/null @@ -1,196 +0,0 @@ -/******************************************************************************* - Real Time Counter (RTC) PLIB - - Company: - Microchip Technology Inc. - - File Name: - plib_rtc_timer.c - - Summary: - RTC PLIB Implementation file - - Description: - This file defines the interface to the RTC peripheral library. This - library provides access to and control of the associated peripheral - instance in timer mode. - -*******************************************************************************/ -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#include "interrupts.h" -#include "plib_rtc.h" -#include - -static volatile RTC_OBJECT rtcObj; - - -void RTC_Initialize(void) -{ - RTC_REGS->MODE0.RTC_CTRLA = RTC_MODE0_CTRLA_SWRST_Msk; - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_SWRST_Msk) == RTC_MODE0_SYNCBUSY_SWRST_Msk) - { - /* Wait for Synchronization after Software Reset */ - } - - - RTC_REGS->MODE0.RTC_CTRLA = (uint16_t)(RTC_MODE0_CTRLA_MODE(0UL) | RTC_MODE0_CTRLA_PRESCALER(0x1UL) | RTC_MODE0_CTRLA_COUNTSYNC_Msk |RTC_MODE0_CTRLA_MATCHCLR_Msk ); - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) - { - /* Wait for Synchronization */ - } - RTC_REGS->MODE0.RTC_COMP = 0x65U; - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) - { - /* Wait for Synchronization after writing Compare Value */ - } - -} - - -void RTC_Timer32CountSyncEnable ( void ) -{ - RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) - { - /* Wait for Synchronization */ - } -} - -void RTC_Timer32CountSyncDisable ( void ) -{ - RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_COUNTSYNC_Msk); - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) - { - /* Wait for Synchronization */ - } -} - -void RTC_Timer32Start ( void ) -{ - RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_ENABLE_Msk; - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) - { - /* Wait for synchronization after Enabling RTC */ - } -} - - -void RTC_Timer32Stop ( void ) -{ - RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_ENABLE_Msk); - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) - { - /* Wait for Synchronization after Disabling RTC */ - } -} - -void RTC_Timer32CounterSet ( uint32_t count ) -{ - RTC_REGS->MODE0.RTC_COUNT = count; - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) - { - /* Wait for Synchronization after writing value to Count Register */ - } -} - -void RTC_Timer32CompareSet ( uint32_t compareValue ) -{ - RTC_REGS->MODE0.RTC_COMP = compareValue; - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) - { - /* Wait for Synchronization after writing Compare Value */ - } -} -uint32_t RTC_Timer32CounterGet ( void ) -{ - if ((RTC_REGS->MODE0.RTC_CTRLA & RTC_MODE0_CTRLA_COUNTSYNC_Msk) == 0U) - { - RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; - - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) - { - /* Wait for Synchronization */ - } - } - while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) - { - /* Wait for Synchronization before reading value from Count Register */ - } - return(RTC_REGS->MODE0.RTC_COUNT); -} - -uint32_t RTC_Timer32PeriodGet ( void ) -{ - /* Get 32Bit Compare Value */ - /*lint -e{9048} PC lint incorrectly reports a missing 'U' Suffix */ - return (RTC_MODE0_COUNT_COUNT_Msk); -} - -uint32_t RTC_Timer32FrequencyGet ( void ) -{ - /* Return Frequency of RTC Clock */ - return RTC_COUNTER_CLOCK_FREQUENCY; -} - -void RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK interruptMask) -{ - RTC_REGS->MODE0.RTC_INTENSET = (uint16_t)interruptMask; -} - -void RTC_Timer32InterruptDisable(RTC_TIMER32_INT_MASK interruptMask) -{ - RTC_REGS->MODE0.RTC_INTENCLR = (uint16_t)interruptMask; -} - - -void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ) -{ - rtcObj.timer32BitCallback = callback; - rtcObj.context = context; -} - -void __attribute__((used)) RTC_InterruptHandler( void ) -{ - rtcObj.timer32intCause = (RTC_TIMER32_INT_MASK) RTC_REGS->MODE0.RTC_INTFLAG; - RTC_REGS->MODE0.RTC_INTFLAG = (uint16_t)RTC_MODE0_INTFLAG_Msk; - (void)RTC_REGS->MODE0.RTC_INTFLAG; - - /* Invoke registered Callback function */ - if(rtcObj.timer32BitCallback != NULL) - { - RTC_TIMER32_INT_MASK timer32intCause = rtcObj.timer32intCause; - uintptr_t context = rtcObj.context; - rtcObj.timer32BitCallback( timer32intCause, context ); - } -} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c deleted file mode 100644 index 6774f2e5..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.c +++ /dev/null @@ -1,680 +0,0 @@ -/******************************************************************************* - Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library - Source File - - Company: - Microchip Technology Inc. - - File Name: - plib_sercom1_i2c.c - - Summary: - SERCOM I2C PLIB Implementation file - - Description: - This file defines the interface to the SERCOM I2C peripheral library. - This library provides access to and control of the associated peripheral - instance. - -*******************************************************************************/ -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include "interrupts.h" -#include "plib_sercom1_i2c_master.h" - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Global Data -// ***************************************************************************** -// ***************************************************************************** - - -#define SERCOM1_I2CM_SPEED_HZ 100000 - -/* SERCOM1 I2C baud value */ -#define SERCOM1_I2CM_BAUD_VALUE (0xE8U) - - -static volatile SERCOM_I2C_OBJ sercom1I2CObj; - -// ***************************************************************************** -// ***************************************************************************** -// Section: SERCOM1 I2C Implementation -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** - -void SERCOM1_I2C_Initialize(void) -{ - /* Reset the module */ - SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk ; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Enable smart mode */ - SERCOM1_REGS->I2CM.SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Baud rate - Master Baud Rate*/ - SERCOM1_REGS->I2CM.SERCOM_BAUD = SERCOM1_I2CM_BAUD_VALUE; - - /* Set Operation Mode (Master), SDA Hold time, run in stand by and i2c master enable */ - SERCOM1_REGS->I2CM.SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | SERCOM_I2CM_CTRLA_SDAHOLD_75NS | SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE | SERCOM_I2CM_CTRLA_SCLSM(0UL) | SERCOM_I2CM_CTRLA_ENABLE_Msk ; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Initial Bus State: IDLE */ - SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Initialize the SERCOM1 PLib Object */ - sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; - sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; - - /* Enable all Interrupts */ - SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; -} - -static bool SERCOM1_I2C_CalculateBaudValue(uint32_t srcClkFreq, uint32_t i2cClkSpeed, uint32_t* baudVal) -{ - uint32_t baudValue = 0U; - float fSrcClkFreq = (float)srcClkFreq; - float fI2cClkSpeed = (float)i2cClkSpeed; - float fBaudValue = 0.0f; - - /* Reference clock frequency must be atleast two times the baud rate */ - if (srcClkFreq < (2U * i2cClkSpeed)) - { - return false; - } - - if (i2cClkSpeed <= 1000000U) - { - /* Standard, FM and FM+ baud calculation */ - fBaudValue = (fSrcClkFreq / fI2cClkSpeed) - ((fSrcClkFreq * (100.0f / 1000000000.0f)) + 10.0f); - baudValue = (uint32_t)fBaudValue; - } - else - { - return false; - } - if (i2cClkSpeed <= 400000U) - { - /* For I2C clock speed upto 400 kHz, the value of BAUD<7:0> determines both SCL_L and SCL_H with SCL_L = SCL_H */ - if (baudValue > (0xFFU * 2U)) - { - /* Set baud rate to the minimum possible value */ - baudValue = 0xFFU; - } - else if (baudValue <= 1U) - { - /* Baud value cannot be 0. Set baud rate to maximum possible value */ - baudValue = 1U; - } - else - { - baudValue /= 2U; - } - } - else - { - /* To maintain the ratio of SCL_L:SCL_H to 2:1, the max value of BAUD_LOW<15:8>:BAUD<7:0> can be 0xFF:0x7F. Hence BAUD_LOW + BAUD can not exceed 255+127 = 382 */ - if (baudValue >= 382U) - { - /* Set baud rate to the minimum possible value while maintaining SCL_L:SCL_H to 2:1 */ - baudValue = (0xFFUL << 8U) | (0x7FU); - } - else if (baudValue <= 3U) - { - /* Baud value cannot be 0. Set baud rate to maximum possible value while maintaining SCL_L:SCL_H to 2:1 */ - baudValue = (2UL << 8U) | 1U; - } - else - { - /* For Fm+ mode, I2C SCL_L:SCL_H to 2:1 */ - baudValue = ((((baudValue * 2U)/3U) << 8U) | (baudValue/3U)); - } - } - *baudVal = baudValue; - return true; -} - -bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ) -{ - uint32_t baudValue; - uint32_t i2cClkSpeed; - uint32_t i2cSpeedMode = 0; - - if (setup == NULL) - { - return false; - } - - i2cClkSpeed = setup->clkSpeed; - - if( srcClkFreq == 0U) - { - srcClkFreq = 48000000UL; - } - - if (SERCOM1_I2C_CalculateBaudValue(srcClkFreq, i2cClkSpeed, &baudValue) == false) - { - return false; - } - - if (i2cClkSpeed > 400000U) - { - i2cSpeedMode = 1U; - } - - /* Disable the I2C before changing the I2C clock speed */ - SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - /* Baud rate - Master Baud Rate*/ - SERCOM1_REGS->I2CM.SERCOM_BAUD = baudValue; - - SERCOM1_REGS->I2CM.SERCOM_CTRLA = ((SERCOM1_REGS->I2CM.SERCOM_CTRLA & ~SERCOM_I2CM_CTRLA_SPEED_Msk) | (SERCOM_I2CM_CTRLA_SPEED(i2cSpeedMode))); - - /* Re-enable the I2C module */ - SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ - SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - return true; -} - -void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle) -{ - sercom1I2CObj.callback = callback; - - sercom1I2CObj.context = contextHandle; -} - - -static void SERCOM1_I2C_SendAddress(uint16_t address, bool dir) -{ - /* If operation is I2C read */ - if(dir) - { - /*

*/ - - /* Next state will be to read data */ - sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; - } - else - { - /*

*/ - - /* Next state will be to write data */ - sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_WRITE; - } - - - SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)address << 1U) | (dir ? 1UL :0UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - -} - -static void SERCOM1_I2C_InitiateTransfer(uint16_t address, bool dir) -{ - sercom1I2CObj.writeCount = 0U; - sercom1I2CObj.readCount = 0U; - - /* Clear all flags */ - SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; - - /* Smart mode enabled with SCLSM = 0, - ACK is set to send while receiving the data */ - SERCOM1_REGS->I2CM.SERCOM_CTRLB &= ~SERCOM_I2CM_CTRLB_ACKACT_Msk; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - SERCOM1_I2C_SendAddress(address, dir); -} - -static bool SERCOM1_I2C_XferSetup( - uint16_t address, - uint8_t* wrData, - uint32_t wrLength, - uint8_t* rdData, - uint32_t rdLength, - bool dir, - bool isHighSpeed -) -{ - /* Check for ongoing transfer */ - if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) - { - return false; - } - - sercom1I2CObj.address = address; - sercom1I2CObj.readBuffer = rdData; - sercom1I2CObj.readSize = rdLength; - sercom1I2CObj.writeBuffer = wrData; - sercom1I2CObj.writeSize = wrLength; - sercom1I2CObj.transferDir = dir; - sercom1I2CObj.isHighSpeed = isHighSpeed; - sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; - - - SERCOM1_I2C_InitiateTransfer(address, dir); - - return true; -} - -bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength) -{ - return SERCOM1_I2C_XferSetup(address, NULL, 0, rdData, rdLength, true, false); -} - -bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength) -{ - return SERCOM1_I2C_XferSetup(address, wrData, wrLength, NULL, 0, false, false); -} - -bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength) -{ - return SERCOM1_I2C_XferSetup(address, wrData, wrLength, rdData, rdLength, false, false); -} - - -bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound) -{ - uint8_t* pDevList = (uint8_t*)pDevicesList; - uint8_t nDevFound = 0; - - /* Check for ongoing transfer */ - if(sercom1I2CObj.state != SERCOM_I2C_STATE_IDLE) - { - return false; - } - - if ((pDevicesList == NULL) || (nDevicesFound == NULL)) - { - return false; - } - - *nDevicesFound = 0; - - /* Clear all flags */ - SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; - - /* Disable all interrupts */ - SERCOM1_REGS->I2CM.SERCOM_INTENCLR = (uint8_t)SERCOM_I2CM_INTENCLR_Msk; - - for (uint16_t dev_addr = start_addr; dev_addr <= end_addr; dev_addr++) - { - while(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) - { - /* Wait for the bus to become IDLE */ - } - - /* Put the 7-bit device address on the bus with WR bit */ - SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)dev_addr << 1U); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - while ((SERCOM1_REGS->I2CM.SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_MB_Msk) == 0U) - { - /* Wait for the address transfer to complete */ - } - - if ((SERCOM1_REGS->I2CM.SERCOM_STATUS & (SERCOM_I2CM_STATUS_ARBLOST_Msk | SERCOM_I2CM_STATUS_BUSERR_Msk | SERCOM_I2CM_STATUS_RXNACK_Msk)) == 0U) - { - /* No error and device responded with an ACK. Add the device to the list of found devices. */ - pDevList[nDevFound] = (uint8_t)dev_addr; - - nDevFound += 1U; - } - - /* Issue stop condition */ - SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - } - - *nDevicesFound = nDevFound; - - /* Re-enable all interrupts */ - SERCOM1_REGS->I2CM.SERCOM_INTENSET = (uint8_t)SERCOM_I2CM_INTENSET_Msk; - - return true; -} - -bool SERCOM1_I2C_IsBusy(void) -{ - bool isBusy = true; - if((sercom1I2CObj.state == SERCOM_I2C_STATE_IDLE)) - { - if(((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) - { - isBusy = false; - } - } - return isBusy; -} - -SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void) -{ - return sercom1I2CObj.error; -} - -void SERCOM1_I2C_TransferAbort( void ) -{ - sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; - - // Reset the plib to IDLE state - sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; - - /* Disable the I2C module */ - SERCOM1_REGS->I2CM.SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Re-enable the I2C module */ - SERCOM1_REGS->I2CM.SERCOM_CTRLA |= SERCOM_I2CM_CTRLA_ENABLE_Msk; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Since the I2C module was disabled, re-initialize the bus state to IDLE */ - SERCOM1_REGS->I2CM.SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -void __attribute__((used)) SERCOM1_I2C_InterruptHandler(void) -{ - if(SERCOM1_REGS->I2CM.SERCOM_INTENSET != 0U) - { - uintptr_t context = sercom1I2CObj.context; - - /* Checks if the arbitration lost in multi-master scenario */ - if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_ARBLOST_Msk) == SERCOM_I2CM_STATUS_ARBLOST_Msk) - { - /* Set Error status */ - sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; - sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; - - } - /* Check for Bus Error during transmission */ - else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSERR_Msk) == SERCOM_I2CM_STATUS_BUSERR_Msk) - { - /* Set Error status */ - sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; - sercom1I2CObj.error = SERCOM_I2C_ERROR_BUS; - } - /* Checks slave acknowledge for address or data */ - else if((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_RXNACK_Msk) == SERCOM_I2CM_STATUS_RXNACK_Msk) - { - sercom1I2CObj.state = SERCOM_I2C_STATE_ERROR; - sercom1I2CObj.error = SERCOM_I2C_ERROR_NAK; - } - else - { - switch(sercom1I2CObj.state) - { - case SERCOM_I2C_REINITIATE_TRANSFER: - - if (sercom1I2CObj.writeSize != 0U) - { - /* Initiate Write transfer */ - SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, false); - } - else - { - /* Initiate Read transfer */ - SERCOM1_I2C_InitiateTransfer(sercom1I2CObj.address, true); - } - - break; - - - case SERCOM_I2C_STATE_IDLE: - - break; - - - - case SERCOM_I2C_STATE_TRANSFER_WRITE: - { - size_t writeCount = sercom1I2CObj.writeCount; - - if (writeCount == (sercom1I2CObj.writeSize)) - { - if(sercom1I2CObj.readSize != 0U) - { - - /* Write 7bit address with direction (ADDR.ADDR[0]) equal to 1*/ - SERCOM1_REGS->I2CM.SERCOM_ADDR = ((uint32_t)(sercom1I2CObj.address) << 1U) | (uint32_t)I2C_TRANSFER_READ; - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_READ; - - } - else - { - SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; - } - } - /* Write next byte */ - else - { - SERCOM1_REGS->I2CM.SERCOM_DATA = sercom1I2CObj.writeBuffer[writeCount]; - writeCount++; - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - sercom1I2CObj.writeCount = writeCount; - } - } - - break; - - case SERCOM_I2C_STATE_TRANSFER_READ: - { - size_t readCount = sercom1I2CObj.readCount; - - - if(readCount == (sercom1I2CObj.readSize - 1U)) - { - /* Set NACK and send stop condition to the slave from master */ - SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_ACKACT_Msk | SERCOM_I2CM_CTRLB_CMD(3UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - sercom1I2CObj.state = SERCOM_I2C_STATE_TRANSFER_DONE; - } - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Read the received data */ - sercom1I2CObj.readBuffer[readCount] = (uint8_t) SERCOM1_REGS->I2CM.SERCOM_DATA; - readCount++; - - sercom1I2CObj.readCount = readCount; - } - - break; - - default: - - /* Do nothing */ - break; - } - } - - /* Error Status */ - if(sercom1I2CObj.state == SERCOM_I2C_STATE_ERROR) - { - /* Reset the PLib objects and Interrupts */ - sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; - - /* Generate STOP condition */ - SERCOM1_REGS->I2CM.SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); - - /* Wait for synchronization */ - while((SERCOM1_REGS->I2CM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; - - if (sercom1I2CObj.callback != NULL) - { - sercom1I2CObj.callback(context); - } - } - /* Transfer Complete */ - else if(sercom1I2CObj.state == SERCOM_I2C_STATE_TRANSFER_DONE) - { - /* Reset the PLib objects and interrupts */ - sercom1I2CObj.state = SERCOM_I2C_STATE_IDLE; - sercom1I2CObj.error = SERCOM_I2C_ERROR_NONE; - - SERCOM1_REGS->I2CM.SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; - - /* Wait for the NAK and STOP bit to be transmitted out and I2C state machine to rest in IDLE state */ - while((SERCOM1_REGS->I2CM.SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U)) - { - /* Do nothing */ - } - - if(sercom1I2CObj.callback != NULL) - { - sercom1I2CObj.callback(context); - } - - } - else - { - /* Do nothing */ - } - } - - return; -} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h deleted file mode 100644 index d20fd0e2..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom1_i2c_master.h +++ /dev/null @@ -1,104 +0,0 @@ -/******************************************************************************* - Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library - Instance Header File - - Company: - Microchip Technology Inc. - - File Name: - plib_sercom1_i2c.h - - Summary: - SERCOM I2C PLIB Header file - - Description: - This file defines the interface to the SERCOM I2C peripheral library. This - library provides access to and control of the associated peripheral - instance. -*******************************************************************************/ -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_SERCOM1_I2C_H -#define PLIB_SERCOM1_I2C_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "plib_sercom_i2c_master_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -/* - * The following functions make up the methods (set of possible operations) of - * this interface. - */ - -void SERCOM1_I2C_Initialize(void); - -bool SERCOM1_I2C_Read(uint16_t address, uint8_t* rdData, uint32_t rdLength); - -bool SERCOM1_I2C_Write(uint16_t address, uint8_t* wrData, uint32_t wrLength); - -bool SERCOM1_I2C_WriteRead(uint16_t address, uint8_t* wrData, uint32_t wrLength, uint8_t* rdData, uint32_t rdLength); - -bool SERCOM1_I2C_IsBusy(void); - -SERCOM_I2C_ERROR SERCOM1_I2C_ErrorGet(void); - -void SERCOM1_I2C_CallbackRegister(SERCOM_I2C_CALLBACK callback, uintptr_t contextHandle); - -bool SERCOM1_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClkFreq ); - - -void SERCOM1_I2C_TransferAbort( void ); - -bool SERCOM1_I2C_BusScan(uint16_t start_addr, uint16_t end_addr, void* pDevicesList, uint8_t* nDevicesFound); - - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif -// DOM-IGNORE-END - -#endif /* PLIB_SERCOM1_I2C_H */ diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h deleted file mode 100644 index 904a768b..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/i2c_master/plib_sercom_i2c_master_common.h +++ /dev/null @@ -1,260 +0,0 @@ -/******************************************************************************* - Serial Communication Interface Inter-Integrated Circuit (SERCOM I2C) Library - Instance Header File - - Company - Microchip Technology Inc. - - File Name - plib_sercom_i2c_master.h - - Summary - SERCOM I2C peripheral library interface. - - Description - This file defines the interface to the SERCOM I2C peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_SERCOM_I2C_MASTER_H -#define PLIB_SERCOM_I2C_MASTER_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include -#include -#include -#include "device.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* SERCOM I2C Transfer type - - Summary: - List of transfer direction. - - Description: - This enum defines the I2C transfer direction. - - Remarks: - None. -*/ - -enum -{ - I2C_TRANSFER_WRITE = 0, - I2C_TRANSFER_READ = 1, -}; - -// ***************************************************************************** -/* SERCOM I2C Error. - - Summary: - Defines the possible errors that the SERCOM I2C peripheral can generate. - - Description: - This enum defines the possible error the SERCOM I2C peripheral can generate. - An error of this type is returned by the SERCOMx_I2C_ErrorGet() function. - - Remarks: - None. -*/ - -typedef enum -{ - /* No error has occurred. */ - SERCOM_I2C_ERROR_NONE, - - /* A bus transaction was NAK'ed */ - SERCOM_I2C_ERROR_NAK, - - /* A bus error has occurred. */ - SERCOM_I2C_ERROR_BUS, - -} SERCOM_I2C_ERROR; - -// ***************************************************************************** -/* SERCOM I2C State. - - Summary: - SERCOM I2C PLib Task State. - - Description: - This data type defines the SERCOM I2C PLib Task State. - - Remarks: - None. -*/ - -typedef enum -{ - /* SERCOM PLib Task Error State */ - SERCOM_I2C_STATE_ERROR = -1, - - /* SERCOM PLib Task Idle State */ - SERCOM_I2C_STATE_IDLE, - - /* SERCOM PLib Task Address Send State */ - SERCOM_I2C_STATE_ADDR_SEND, - - SERCOM_I2C_REINITIATE_TRANSFER, - /* SERCOM PLib Task Read Transfer State */ - SERCOM_I2C_STATE_TRANSFER_READ, - - /* SERCOM PLib Task Write Transfer State */ - SERCOM_I2C_STATE_TRANSFER_WRITE, - - /* SERCOM PLib Task High Speed Slave Address Send State */ - SERCOM_I2C_STATE_TRANSFER_ADDR_HS, - - /* SERCOM PLib Task Transfer Done State */ - SERCOM_I2C_STATE_TRANSFER_DONE, - -} SERCOM_I2C_STATE; - -// ***************************************************************************** -/* SERCOM I2C Callback - - Summary: - SERCOM I2C Callback Function Pointer. - - Description: - This data type defines the SERCOM I2C Callback Function Pointer. - - Remarks: - None. -*/ - -typedef void (*SERCOM_I2C_CALLBACK) -( - /*Transfer context*/ - uintptr_t contextHandle - -); - -// ***************************************************************************** -/* SERCOM I2C PLib Instance Object - - Summary: - SERCOM I2C PLib Object structure. - - Description: - This data structure defines the SERCOM I2C PLib Instance Object. - - Remarks: - None. -*/ - -typedef struct -{ - bool isHighSpeed; - - bool txMasterCode; - - bool transferDir; - - uint16_t address; - - uint8_t masterCode; - - uint8_t* writeBuffer; - - uint8_t* readBuffer; - - size_t writeSize; - - size_t readSize; - - size_t writeCount; - - size_t readCount; - - /* State */ - SERCOM_I2C_STATE state; - - /* Transfer status */ - SERCOM_I2C_ERROR error; - - /* Transfer Event Callback */ - SERCOM_I2C_CALLBACK callback; - - /* Transfer context */ - uintptr_t context; - -} SERCOM_I2C_OBJ; - -// ***************************************************************************** -/* Transaction Request Block - - Summary: - Transaction Request Block Structure. - - Description: - This data structure defines the Transaction Request Block. - - Remarks: - None. -*/ - -typedef struct -{ - /* SERCOM I2C Clock Speed */ - uint32_t clkSpeed; - -} SERCOM_I2C_TRANSFER_SETUP; - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif /* PLIB_SERCOM_I2C_MASTER_H */ \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c deleted file mode 100644 index 3ade6cfa..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.c +++ /dev/null @@ -1,622 +0,0 @@ -/******************************************************************************* - SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE(SERCOM0_SPI) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom0_spi_master.c - - Summary - SERCOM0_SPI Master PLIB Implementation File. - - Description - This file defines the interface to the SERCOM SPI peripheral library. - This library provides access to and control of the associated - peripheral instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#include "interrupts.h" -#include "plib_sercom0_spi_master.h" - -// ***************************************************************************** -// ***************************************************************************** -// Section: MACROS Definitions -// ***************************************************************************** -// ***************************************************************************** - - -/* SERCOM0 clk freq value for the baud calculation */ -#define SERCOM0_Frequency (48000000UL) - -/* SERCOM0 SPI baud value for 10000 Hz baud rate */ -#define SERCOM0_SPIM_BAUD_VALUE (2399UL) - -/*Global object to save SPI Exchange related data */ -static volatile SPI_OBJECT sercom0SPIObj; - -// ***************************************************************************** -// ***************************************************************************** -// Section: SERCOM0_SPI Implementation -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* Function: - void SERCOM0_SPI_Initialize(void); - - Summary: - Initializes instance SERCOM0 of the SERCOM module operating in SPI mode. - - Description: - This function initializes instance SERCOM0 of SERCOM module operating in SPI mode. - This function should be called before any other library function. The SERCOM - module will be configured as per the MHC settings. - - Remarks: - Refer plib_sercom0_spi.h file for more information. -*/ - -void SERCOM0_SPI_Initialize(void) -{ - /* Instantiate the SERCOM0 SPI object */ - sercom0SPIObj.callback = NULL ; - sercom0SPIObj.transferIsBusy = false ; - sercom0SPIObj.txSize = 0U; - sercom0SPIObj.rxSize = 0U; - - /* Selection of the Character Size and Receiver Enable */ - SERCOM0_REGS->SPIM.SERCOM_CTRLB = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT | SERCOM_SPIM_CTRLB_RXEN_Msk ; - - /* Wait for synchronization */ - while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Selection of the Baud Value */ - SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)SERCOM_SPIM_BAUD_BAUD(SERCOM0_SPIM_BAUD_VALUE); - - /* Configure Data Out Pin Out , Master Mode, - * Data In and Pin Out,Data Order and Standby mode if configured - * and Selection of the Clock Phase and Polarity and Enable the SPI Module - */ - SERCOM0_REGS->SPIM.SERCOM_CTRLA = SERCOM_SPIM_CTRLA_MODE_SPI_MASTER | SERCOM_SPIM_CTRLA_DOPO_PAD3 | SERCOM_SPIM_CTRLA_DIPO_PAD1 | SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW | SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE | SERCOM_SPIM_CTRLA_DORD_MSB | SERCOM_SPIM_CTRLA_ENABLE_Msk ; - - - /* Wait for synchronization */ - while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, - uint32_t spiSourceClock); - - Summary: - Configure SERCOM SPI operational parameters at run time. - - Description: - This function allows the application to change the SERCOM SPI operational - parameter at run time. The application can thus override the MHC defined - configuration for these parameters. The parameter are specified via the - SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter - should be initialized to the desired value. - - The application may feel need to call this function in situation where - multiple SPI slaves, each with different operation parameters, are connected - to one SPI master. This function can thus be used to setup the SPI Master to - meet the communication needs of the slave. - - Calling this function will affect any ongoing communication. The application - must thus ensure that there is no on-going communication on the SPI before - calling this function. - - Remarks: - Refer plib_sercom0_spi.h file for more information. -*/ - -bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock) -{ - uint32_t baudValue = 0U; - - bool statusValue = false; - - if(spiSourceClock == 0U) - { - /* Fetch Master Clock Frequency directly */ - spiSourceClock = SERCOM0_Frequency; - } - - /* Disable the SPI Module */ - SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_ENABLE_Msk); - - /* Disabling SPI module, also clears the TXC (Transmit Complete) bit to 0. TXC = 0 means transfer is not complete (busy). - As a result, calling SERCOM0_SPI_IsBusy() after a call to SERCOM0_SPI_TransferSetup() always returns busy. - Since, application must call the SERCOM0_SPI_TransferSetup() API only after ensuring that no transfer is in progress, - it is safe to clear the rxSize and txSize to 0, so as to let the SERCOM0_SPI_IsBusy() return false (not busy). - */ - sercom0SPIObj.rxSize = 0; - sercom0SPIObj.txSize = 0; - - /* Wait for synchronization */ - while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - if(setup != NULL) - { - if (setup->clockFrequency <= spiSourceClock/2U) - { - baudValue = (spiSourceClock/(2U*(setup->clockFrequency))) - 1U; - - /* Set the lowest possible baud */ - if (baudValue >= 255U) - { - baudValue = 255U; - } - - /* Selection of the Clock Polarity and Clock Phase */ - SERCOM0_REGS->SPIM.SERCOM_CTRLA &= ~(SERCOM_SPIM_CTRLA_CPOL_Msk | SERCOM_SPIM_CTRLA_CPHA_Msk); - SERCOM0_REGS->SPIM.SERCOM_CTRLA |= (uint32_t)setup->clockPolarity | (uint32_t)setup->clockPhase; - - /* Selection of the Baud Value */ - SERCOM0_REGS->SPIM.SERCOM_BAUD = (uint8_t)baudValue; - - /* Selection of the Character Size */ - SERCOM0_REGS->SPIM.SERCOM_CTRLB &= ~SERCOM_SPIM_CTRLB_CHSIZE_Msk; - SERCOM0_REGS->SPIM.SERCOM_CTRLB |= (uint32_t)setup->dataBits; - - /* Wait for synchronization */ - while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - statusValue = true; - } - } - - /* Enabling the SPI Module */ - SERCOM0_REGS->SPIM.SERCOM_CTRLA |= SERCOM_SPIM_CTRLA_ENABLE_Msk; - - /* Wait for synchronization */ - while((SERCOM0_REGS->SPIM.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - return statusValue; -} - - -// ***************************************************************************** -/* Function: - void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, - uintptr_t context); - - Summary: - Allows application to register callback with PLIB. - - Description: - This function allows application to register an event handling function - for the PLIB to call back when requested data exchange operation has - completed or any error has occurred. - The callback should be registered before the client performs exchange - operation. - At any point if application wants to stop the callback, it can use this - function with "callBack" value as NULL. - - Remarks: - Refer plib_sercom0_spi.h file for more information. -*/ - -void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context ) -{ - sercom0SPIObj.callback = callBack; - - sercom0SPIObj.context = context; -} - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_IsBusy(void); - - Summary: - Returns transfer status of SERCOM SERCOM0SPI. - - Description: - This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The - application can use the function to check if SERCOM SERCOM0SPI module is busy - before calling any of the data transfer functions. The library does not - allow a data transfer operation if another transfer operation is already in - progress. - - This function can be used as an alternative to the callback function when - the library is operating interrupt mode. The allow the application to - implement a synchronous interface to the library. - - Remarks: - Refer plib_sercom0_spi.h file for more information. -*/ - -bool SERCOM0_SPI_IsBusy(void) -{ - bool isBusy = false; - size_t txSize = sercom0SPIObj.txSize; - bool transferIsBusy = sercom0SPIObj.transferIsBusy; - - if ((sercom0SPIObj.rxSize == 0U) && (txSize == 0U)) - { - /* This means no transfer has been requested yet; hence SPI is not busy. */ - isBusy = false; - } - else - { - /* if transmit is not complete or if the state flag is not set, SPI is busy */ - isBusy = (((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U) || transferIsBusy); - } - return isBusy; -} - -bool SERCOM0_SPI_IsTransmitterBusy(void) -{ - return ((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == 0U)? true : false; -} - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize - void* pReceiveData, size_t rxSize); - - Summary: - Write and Read data on SERCOM SERCOM0 SPI peripheral. - - Description: - This function transmits "txSize" number of bytes and receives "rxSize" - number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is - transmitted and received data is saved in the location pointed by - pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" - data units towards completion. - - When "Interrupt Mode" option is unchecked in MHC, this function will be - blocking in nature. In this mode, the function will not return until all - the requested data is transferred. The function returns true after - transferring all the data. This indicates that the operation has been - completed. - - When "Interrupt Mode" option is selected in MHC, the function will be - non-blocking in nature. The function returns immediately. The data transfer - process continues in the peripheral interrupt. The application specified - transmit and receive buffer are ownerd by the library until the data - transfer is complete and should not be modified by the application till the - transfer is complete. Only one transfer is allowed at any time. The - Application can use a callback function or a polling function to check for - completion of the transfer. If a callback is required, this should be - registered prior to calling the SERCOM0_SPI_WriteRead() function. The - application can use the SERCOM0_SPI_IsBusy() to poll for completion. - - Remarks: - Refer plib_sercom0_spi.h file for more information. -*/ - -bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize) -{ - bool isRequestAccepted = false; - uint32_t dummyData = 0U; - size_t txSz; - - if (sercom0SPIObj.transferIsBusy == false) - { - /* Verify the request */ - if(((txSize > 0U) && (pTransmitData != NULL)) || ((rxSize > 0U) && (pReceiveData != NULL))) - { - if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_9) - { - /* For 9-bit transmission, the txSize and rxSize must be an even number. */ - if(((txSize > 0U) && ((txSize & 0x01U) != 0U)) || ((rxSize > 0U) && ((rxSize & 0x01U) != 0U))) - { - return isRequestAccepted; - } - } - - isRequestAccepted = true; - sercom0SPIObj.txBuffer = pTransmitData; - sercom0SPIObj.rxBuffer = pReceiveData; - sercom0SPIObj.rxCount = 0U; - sercom0SPIObj.txCount = 0U; - sercom0SPIObj.dummySize = 0U; - - if(pTransmitData != NULL) - { - sercom0SPIObj.txSize = txSize; - } - else - { - sercom0SPIObj.txSize = 0U; - } - - if(pReceiveData != NULL) - { - sercom0SPIObj.rxSize = rxSize; - } - else - { - sercom0SPIObj.rxSize = 0U; - } - - sercom0SPIObj.transferIsBusy = true; - - /* Flush out any unread data in SPI read buffer */ - while((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) - { - dummyData = SERCOM0_REGS->SPIM.SERCOM_DATA; - (void)dummyData; - } - - SERCOM0_REGS->SPIM.SERCOM_STATUS |= SERCOM_SPIM_STATUS_BUFOVF_Msk; - - SERCOM0_REGS->SPIM.SERCOM_INTFLAG |= (uint8_t)SERCOM_SPIM_INTFLAG_ERROR_Msk; - - txSz = sercom0SPIObj.txSize; - - if(sercom0SPIObj.rxSize > txSz) - { - sercom0SPIObj.dummySize = sercom0SPIObj.rxSize - txSz; - } - - /* Start the first write here itself, rest will happen in ISR context */ - if((SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == (uint32_t)SPI_DATA_BITS_8) - { - if(sercom0SPIObj.txCount < txSz) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint8_t*)sercom0SPIObj.txBuffer); - - sercom0SPIObj.txCount++; - } - else if(sercom0SPIObj.dummySize > 0U) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; - - sercom0SPIObj.dummySize--; - } - else - { - /* Do nothing */ - } - } - else - { - sercom0SPIObj.txSize >>= 1U; - sercom0SPIObj.dummySize >>= 1U; - sercom0SPIObj.rxSize >>= 1U; - - txSz = sercom0SPIObj.txSize; - - if(sercom0SPIObj.txCount < txSz) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = *((uint16_t*)sercom0SPIObj.txBuffer) & SERCOM_SPIM_DATA_Msk; - - sercom0SPIObj.txCount++; - } - else if(sercom0SPIObj.dummySize > 0U) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU & SERCOM_SPIM_DATA_Msk; - - sercom0SPIObj.dummySize--; - } - else - { - /* Do nothing */ - } - } - - if(rxSize > 0U) - { - /* Enable ReceiveComplete */ - SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_RXC_Msk; - } - else - { - /* Enable the DataRegisterEmpty */ - SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; - } - } - } - - return isRequestAccepted; -} - -bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize) -{ - return SERCOM0_SPI_WriteRead(pTransmitData, txSize, NULL, 0U); -} - -bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize) -{ - return SERCOM0_SPI_WriteRead(NULL, 0U, pReceiveData, rxSize); -} - -// ***************************************************************************** -/* Function: - void SERCOM0_SPI_InterruptHandler(void); - - Summary: - Handler that handles the SPI interrupts - - Description: - This Function is called from the handler to handle the exchange based on the - Interrupts. - - Remarks: - Refer plib_sercom0_spi.h file for more information. -*/ - -void __attribute__((used)) SERCOM0_SPI_InterruptHandler(void) -{ - uint32_t dataBits = 0U; - uint32_t receivedData = 0U; - static bool isLastByteTransferInProgress = false; - uintptr_t context = sercom0SPIObj.context; - - if(SERCOM0_REGS->SPIM.SERCOM_INTENSET != 0U) - { - dataBits = SERCOM0_REGS->SPIM.SERCOM_CTRLB & SERCOM_SPIM_CTRLB_CHSIZE_Msk; - - size_t rxCount = sercom0SPIObj.rxCount; - size_t txCount = sercom0SPIObj.txCount; - size_t txSize = sercom0SPIObj.txSize; - - if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == SERCOM_SPIM_INTFLAG_RXC_Msk) - { - receivedData = SERCOM0_REGS->SPIM.SERCOM_DATA; - - if(rxCount < sercom0SPIObj.rxSize) - { - if(dataBits == (uint32_t)SPI_DATA_BITS_8) - { - ((uint8_t*)sercom0SPIObj.rxBuffer)[rxCount] = (uint8_t)receivedData; - rxCount++; - } - else - { - ((uint16_t*)sercom0SPIObj.rxBuffer)[rxCount] = (uint16_t)receivedData; - rxCount++; - } - } - } - - /* If there are more words to be transmitted, then transmit them here and keep track of the count */ - if((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_DRE_Msk) == SERCOM_SPIM_INTFLAG_DRE_Msk) - { - /* Disable the DRE interrupt. This will be enabled back if more than - * one byte is pending to be transmitted */ - SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_DRE_Msk; - - if(dataBits == (uint32_t)SPI_DATA_BITS_8) - { - if(txCount < sercom0SPIObj.txSize) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint8_t*)sercom0SPIObj.txBuffer)[txCount]; - txCount++; - } - else if(sercom0SPIObj.dummySize > 0U) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFU; - - sercom0SPIObj.dummySize--; - } - else - { - /* Do nothing */ - } - } - else - { - if(txCount < sercom0SPIObj.txSize) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = ((uint16_t*)sercom0SPIObj.txBuffer)[txCount]; - txCount++; - } - else if(sercom0SPIObj.dummySize > 0U) - { - SERCOM0_REGS->SPIM.SERCOM_DATA = 0xFFFFU; - - sercom0SPIObj.dummySize--; - } - else - { - /* Do nothing */ - } - } - - if((sercom0SPIObj.dummySize == 0U) && (txCount == txSize)) - { - /* At higher baud rates, the data in the shift register can be - * shifted out and TXC flag can get set resulting in a - * callback been given to the application with the SPI interrupt - * pending with the application. This will then result in the - * interrupt handler being called again with nothing to transmit. - * To avoid this, a software flag is set, but - * the TXC interrupt is not enabled until the very end. - */ - - isLastByteTransferInProgress = true; - } - else if(rxCount == sercom0SPIObj.rxSize) - { - SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_DRE_Msk; - - SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)SERCOM_SPIM_INTENCLR_RXC_Msk; - } - else - { - /* Do nothing */ - } - } - - sercom0SPIObj.rxCount = rxCount; - sercom0SPIObj.txCount = txCount; - - if(((SERCOM0_REGS->SPIM.SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk) == SERCOM_SPIM_INTFLAG_TXC_Msk) && (isLastByteTransferInProgress == true)) - { - if(rxCount == sercom0SPIObj.rxSize) - { - sercom0SPIObj.transferIsBusy = false; - - /* Disable the Data Register empty and Receive Complete Interrupt flags */ - SERCOM0_REGS->SPIM.SERCOM_INTENCLR = (uint8_t)(SERCOM_SPIM_INTENCLR_DRE_Msk | SERCOM_SPIM_INTENCLR_RXC_Msk | SERCOM_SPIM_INTENSET_TXC_Msk); - - isLastByteTransferInProgress = false; - - if(sercom0SPIObj.callback != NULL) - { - sercom0SPIObj.callback(context); - } - } - } - - if(isLastByteTransferInProgress == true) - { - /* For the last byte transfer, the DRE interrupt is already disabled. - * Enable TXC interrupt to ensure no data is present in the shift - * register before application callback is called. - */ - SERCOM0_REGS->SPIM.SERCOM_INTENSET = (uint8_t)SERCOM_SPIM_INTENSET_TXC_Msk; - } - } -} diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h deleted file mode 100644 index ac5d988c..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom0_spi_master.h +++ /dev/null @@ -1,624 +0,0 @@ -/******************************************************************************* - SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE (SERCOM0_SPI ) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom0_spi_master.h - - Summary - SERCOM0_SPI Master PLIB Header File. - - Description - This file defines the interface to the SERCOM SPI peripheral library. - This library provides access to and control of the associated - peripheral instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_SERCOM0_SPI_MASTER_H // Guards against multiple inclusion -#define PLIB_SERCOM0_SPI_MASTER_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -/* This section lists the other files that are included in this file. -*/ - -#include "plib_sercom_spi_master_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - -extern "C" { - -#endif - -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -/* The following functions make up the methods (set of possible operations) of -this interface. -*/ - -// ***************************************************************************** -/* Function: - void SERCOM0_SPI_Initialize (void); - - Summary: - Initializes instance SERCOM0 operating in SPI mode. - - Description: - This function initializes instance SERCOM0 operating in SPI mode. - This function should be called before any other library function. The SERCOM - module will be configured as per the MHC settings. - - Precondition: - MCC GUI should be configured with the right values. The Generic Clock - configuration and the SERCOM Peripheral Clock channel should have been - configured in the clock manager GUI.The function will itself enable the - required peripheral clock channel and main clock. - - Parameters: - None. - - Returns: - None. - - Example: - - SERCOM0_SPI_Initialize(); - - - Remarks: - This function must be called once before any other SPI function is called. -*/ - -void SERCOM0_SPI_Initialize (void); - - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, - uint32_t spiSourceClock); - - Summary: - Configure SERCOM SPI operational parameters at run time. - - Description: - This function allows the application to change the SERCOM SPI operational - parameter at run time. The application can thus override the MHC defined - configuration for these parameters. The parameter are specified via the - SPI_TRANSFER_SETUP type setup parameter. Each member of this parameter - should be initialized to the desired value. - - The application may feel need to call this function in situation where - multiple SPI slaves, each with different operation paramertes, are connected - to one SPI master. This function can thus be used to setup the SPI Master to - meet the communication needs of the slave. - - Calling this function will affect any ongoing communication. The application - must thus ensure that there is no on-going communication on the SPI before - calling this function. - - Precondition: - SERCOM SERCOM0 SPI must first be initialized using SERCOM0_SPI_Initialize(). - - Parameters : - setup - pointer to the data structure of type SPI_TRANSFER_SETUP containing - the operation parameters. Each operation parameter must be specified even if - the parameter does not need to change. - - spiSourceClock - Current value of GCLK frequency feeding the SERCOM0 core. - - Returns: - true - setup was successful. - - false - if spiSourceClock and spi clock frequencies are such that resultant - baud value is out of the possible range. - - Example: Assuming 20 MHz as peripheral Master clock frequency - - SPI_TRANSFER_SETUP setup; - setup.clockFrequency = 1000000; - setup.clockPhase = SPI_CLOCK_PHASE_TRAILING_EDGE; - setup.clockPolarity = SPI_CLOCK_POLARITY_IDLE_LOW; - setup.dataBits = SPI_DATA_BITS_8; - - if (SERCOM0_SPI_TransferSetup (&setup, 20000000) == false) - { - this means setup could not be done, debug the reason. - } - - - - Remarks: - The application would need to call this function only if the operational - parameter need to be different than the ones configured in MHC. -*/ - -bool SERCOM0_SPI_TransferSetup(SPI_TRANSFER_SETUP *setup, uint32_t spiSourceClock); - - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize - void* pReceiveData, size_t rxSize); - - Summary: - Write and Read data on SERCOM SERCOM0 SPI peripheral. - - Description: - This function transmits "txSize" number of bytes and receives "rxSize" - number of bytes on SERCOM SERCOM0 SPI module. Data pointed by pTransmitData is - transmitted and received data is saved in the location pointed by - pReceiveData. The function will transfer the maximum of "txSize" or "rxSize" - data units towards completion. - - When "Interrupt Mode" option is unchecked in MHC, this function will be - blocking in nature. In this mode, the function will not return until all - the requested data is transferred. The function returns true after - transferring all the data. This indicates that the operation has been - completed. - - When "Interrupt Mode" option is selected in MHC, the function will be - non-blocking in nature. The function returns immediately. The data transfer - process continues in the peripheral interrupt. The application specified - transmit and receive buffer are ownerd by the library until the data - transfer is complete and should not be modified by the application till the - transfer is complete. Only one transfer is allowed at any time. The - Application can use a callback function or a polling function to check for - completion of the transfer. If a callback is required, this should be - registered prior to calling the SERCOM0_SPI_WriteRead() function. The - application can use the SERCOM0_SPI_IsBusy() to poll for completion. - - Precondition: - The SERCOM0_SPI_Initialize function must have been called. If the - peripheral instance has been configured for Interrupt mode and transfer - completion status needs to be communicated back to application via callback, - a callback should have been registered using SERCOM0_SPI_CallbackRegister() - function. - - Parameters: - pTransmitData - Pointer to the data which has to be transmitted. In a case - where only data reception is required, this pointer can be set to NULL. If - the module is configured for 9 bit data length, the data should be right - aligned in a 16 bit memory location. The size of this buffer should be - txSize. - - txSize - Number of bytes to be transmitted. For 9 but data length, a count - of 1 counts 2 bytes. This value can be different from rxSize. - - pReceiveData - Pointer to the location where the received data has to be - stored. It is user's responsibility to ensure that this location has - sufficient memory to store rxSize amount of data. In a case where only data - transmission is required, this pointer can be set to NULL. If the module is - configured for 9 bit data length, received data will be right aligned and - will be stored in a 16 bit memory location. - - rxSize - Number of bytes to be received. This value can be different from - txSize. For 9 bit data length, a size count of 1 indicates 2 bytes required - to store 9 bits of data. - - Returns: - true - If configured for Non-interrupt mode, the function has recevied and - transmitted the requested number of bytes. If configured for Interrupt mode, - the request was accepted successfully and will be processed in the - interrupt. - - false - If both pTransmitData and pReceiveData are NULL, or if both txSize - and rxSize are 0 or if txSize is non-zero but the pTransmitData is set to - NULL or rxSize is non-zero but pReceiveData is NULL. In Interrupt mode, the - function returns false if there is an on-going data transfer at the time of - calling the function. - - Example: - - - The following code snippet shows an example using the - SERCOM0_SPI_WriteRead() function in interrupt mode operation using the - callback function. - - uint8_t txBuffer[4]; - uint8_t rxBuffer[10]; - size_t txSize = 4; - size_t rxSize = 10; - - void APP_SPITransferHandler(uintptr_t context) - { - Transfer was completed without error, do something else now. - } - - SERCOM0_SPI_Initialize(); - SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); - if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize)) - { - request got accepted - } - else - { - request didn't get accepted, try again later with correct arguments - } - The following code snippet shows non-interrupt or blocking mode - operation. - - uint8_t txBuffer[4]; - uint8_t rxBuffer[10]; - size_t txSize = 4; - size_t rxSize = 10; - - SERCOM0_SPI_Initialize(); - - This function call will block. - SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize); - - - - Remarks: - None. -*/ - -bool SERCOM0_SPI_WriteRead (void* pTransmitData, size_t txSize, void* pReceiveData, size_t rxSize); - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); - - Summary: - Writes data to SERCOM SERCOM0 SPI peripheral. - - Description: - This function writes "txSize" number of bytes on SERCOM SERCOM0 SPI module. Data - pointed by pTransmitData is transmitted. - - When "Interrupt Mode" option is unchecked in MHC, this function will be - blocking in nature. In this mode, the function will not return until all - the requested data is transferred. The function returns true after - transferring all the data. This indicates that the operation has been - completed. - - When "Interrupt Mode" option is selected in MHC, the function will be - non-blocking in nature. The function returns immediately. The data transfer - process continues in the peripheral interrupt. The application specified - transmit buffer is ownerd by the library until the data transfer is - complete and should not be modified by the application till the transfer is - complete. Only one transfer is allowed at any time. The application can use - a callback function or a polling function to check for completion of the - transfer. If a callback is required, this should be registered prior to - calling the SERCOM0_SPI_WriteRead() function. The application can use the - SERCOM0_SPI_IsBusy() to poll for completion. - - Precondition: - The SERCOM0_SPI_Initialize function must have been called. - - Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the - peripheral instance has been configured in Interrupt mode and - transfer completion status needs to be communicated back to application via - callback. - - Parameters: - pTransmitData - Pointer to the buffer containing the data which has to be - transmitted. For 9 bit mode, data should be right aligned in the 16 bit - memory location. In "Interrupt Mode", this buffer should not be modified - after calling the function and before the callback function has been called - or the SERCOM0_SPI_IsBusy() function returns false. - - txSize - Number of bytes to be transmitted. For 9 bit mode, 2 bytes make up - a count of 1. - - Returns: - true - If configured for Non-interrupt mode, the function has transmitted - the requested number of bytes. If configured for Interrupt mode, the request - was accepted successfully and will be processed in the interrupt. - - false - If pTransmitData is NULL. In Interrupt mode, the function will - additionally return false if there is an on-going data transfer at the time - of calling the function. - - Example: - - uint8_t txBuffer[4]; - size_t txSize = 4; - - void APP_SPITransferHandler(uintptr_t context) - { - Transfer was completed without error, do something else now. - } - - SERCOM0_SPI_Initialize(); - SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); - if(SERCOM0_SPI_Write(&txBuffer, txSize)) - { - request got accepted - } - else - { - request didn't get accepted, try again later with correct arguments - } - - - - Remarks: - None. - -*/ - -bool SERCOM0_SPI_Write(void* pTransmitData, size_t txSize); - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); - - Summary: - Reads data on the SERCOM SERCOM0 SPI peripheral. - - Description: - This function reads "rxSize" number of bytes on SERCOM SERCOM0 SPI module. The - received data is stored in the buffer pointed by pReceiveData. - - When "Interrupt Mode" option is unchecked in MHC, this function will be - blocking in nature. In this mode, the function will not return until all - the requested data is transferred. The function returns true after - receiving "rxSize" number of bytes. This indicates that the operation has - been completed. - - When "Interrupt Mode" option is selected in MHC, the function will be - non-blocking in nature. The function returns immediately. The data transfer - process continues in the peripheral interrupt. The application specified - receive buffer is ownerd by the library until the data transfer is - complete and should not be modified by the application till the transfer is - complete. Only one transfer is allowed at any time. The application can use - a callback function or a polling function to check for completion of the - transfer. If a callback is required, this should be registered prior to - calling the SERCOM0_SPI_WriteRead() function. The application can use the - SERCOM0_SPI_IsBusy() to poll for completion. - - Precondition: - The SERCOM0_SPI_Initialize function must have been called. - - Callback has to be registered using SERCOM0_SPI_CallbackRegister API if the - peripheral instance has been configured in Interrupt mode and - transfer completion status needs to be communicated back to application via - callback. - - Parameters: - pReceiveData - Pointer to the buffer where the received data will be stored. - For 9 bit mode, data should be right aligned in the 16 bit memory location. - In "Interrupt Mode", this buffer should not be modified after calling the - function and before the callback function has been called or the - SERCOM0_SPI_IsBusy() function returns false. - - rxSize - Number of bytes to be received. For 9 bit mode, 2 bytes make up a - count of 1. - - Returns: - true - If configured for Non-interrupt mode, the function has received the - requested number of bytes. If configured for Interrupt mode, the request was - accepted successfully and will be processed in the interrupt. - - false - If pReceiveData is NULL. In Interrupt mode, the function will - additionally return false if there is an on-going data transfer at the time - of calling the function. - - Example: - - uint8_t rxBuffer[10]; - size_t rxSize = 10; - - void APP_SPITransferHandler(uintptr_t context) - { - Transfer was completed without error, do something else now. - } - - SERCOM0_SPI_Initialize(); - SERCOM0_SPI_CallbackRegister(&APP_SPITransferHandler, (uintptr_t)NULL); - if(SERCOM0_SPI_Read(&rxBuffer, rxSize)) - { - request got accepted - } - else - { - request didn't get accepted, try again later with correct arguments - } - - - Remarks: - None. -*/ - -bool SERCOM0_SPI_Read(void* pReceiveData, size_t rxSize); - -// ***************************************************************************** -/* Function: - void SERCOM0_SPI_CallbackRegister(const SERCOM_SPI_CALLBACK* callBack, - uintptr_t context); - - Summary: - Allows application to register callback with PLIB. - - Description: - This function allows application to register an event handling function - for the PLIB to call back when requested data exchange operation has - completed or any error has occurred. - The callback should be registered before the client performs exchange - operation. - At any point if application wants to stop the callback, it can use this - function with "callBack" value as NULL. - - Precondition: - The SERCOM0_SPI_Initialize function must have been called. - - Parameters: - callBack - Pointer to the event handler function implemented by the - user . - - context - The value of parameter will be passed back to the application - unchanged, when the callBack function is called. It can - be used to identify any application specific data object that - identifies the instance of the client module (for example, - it may be a pointer to the client module's state structure). - - Returns: - None. - - Example: - - uint8_t txBuffer[10]; - uint8_t rxBuffer[10]; - size_t txSize = 10; - size_t rxSize = 10; - - SERCOM0_SPI_Initialize(); - - SERCOM0_SPI_CallbackRegister(&APP_SPICallBack, (uintptr_t)NULL); - - if(SERCOM0_SPI_WriteRead(&txBuffer, txSize, &rxBuffer, rxSize )) - { - request got accepted - } - else - { - request didn't get accepted, try again later with correct arguments - } - - void APP_SPICallBack(uintptr_t contextHandle) - { - Exchange was completed without error, do something else. - } - - - Remarks: - If the client does not want to be notified when the queued operation - has completed, it does not need to register a callback. -*/ - -void SERCOM0_SPI_CallbackRegister(SERCOM_SPI_CALLBACK callBack, uintptr_t context); - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_IsBusy (void); - - Summary: - Returns transfer status of SERCOM SERCOM0SPI. - - Description: - This function ture if the SERCOM SERCOM0SPI module is busy with a transfer. The - application can use the function to check if SERCOM SERCOM0SPI module is busy - before calling any of the data transfer functions. The library does not - allow a data transfer operation if another transfer operation is already in - progress. This function returns true when the SPI PLIB software state machine is idle and - all the bytes are transmitted out on the bus (shift register is empty). - - This function can be used as an alternative to the callback function when - the library is operating interrupt mode. The allow the application to - implement a synchronous interface to the library. - - Precondition: - The SERCOM0_SPI_Initialize() should have been called once. The module should - have been configured for interrupt mode operation in MHC. - - Parameters: - None. - - Returns: - true - Transfer is still in progress - false - Transfer is completed or no transfer is currently in progress. - - Example: - - The following code example demonstrates the use of the - SERCOM0_SPI_IsBusy() function. This example shows a blocking while - loop. The function can also be called periodically. - - uint8_t dataBuffer[20]; - - SERCOM0_SPI_Initialize(); - SERCOM0_SPI_Write(dataBuffer, 20); - - while (SERCOM0_SPI_IsBusy() == true) - { - Wait here till the transfer is done. - } - - - Remarks: - None. -*/ - -bool SERCOM0_SPI_IsBusy (void); - -// ***************************************************************************** -/* Function: - bool SERCOM0_SPI_IsTransmitterBusy (void); - - Summary: - Returns hardware transfer status of the SPI transmit shift register - - Description: - This function returns the hardware status of the transmit shift register. - The status is returned true after all the bytes have been shifted out on the - SPI bus. This function should be used when using DMA with SPI PLIB to make - sure that all the bytes have been transmitted out on the bus. For SPI - transfers without DMA, the SERCOM0_SPI_IsBusy() API must be used. - - Precondition: - The SERCOM0_SPI_Initialize() should have been called once. - - Parameters: - None. - - Returns: - true - Data is being shifted out on the SPI bus - false - All the data bytes have been shifted out on the SPI bus - - Example: - - - - - Remarks: - None. -*/ -bool SERCOM0_SPI_IsTransmitterBusy(void); - -#ifdef __cplusplus // Provide C++ Compatibility -} -#endif - -#endif /* PLIB_SERCOM0_SPI_MASTER_H */ \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h deleted file mode 100644 index fcdc9dc8..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/spi_master/plib_sercom_spi_master_common.h +++ /dev/null @@ -1,296 +0,0 @@ -/******************************************************************************* - SERCOM_SPI(SERIAL COMMUNICATION SERIAL PERIPHERAL INTERFACE) PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom_spi_master_common.h - - Summary - SERCOM_SPI PLIB Master Local Header File. - - Description - This file defines the interface to the SERCOM SPI peripheral library. - This library provides access to and control of the associated - peripheral instance. - - Remarks: - None. - -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_SERCOM_SPI_MASTER_COMMON_H // Guards against multiple inclusion -#define PLIB_SERCOM_SPI_MASTER_COMMON_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include -#include -#include -#include - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* SPI Clock Phase - - Summary: - Identifies SPI Clock Phase Options - - Description: - This enumeration identifies possible SPI Clock Phase Options. - - Remarks: - None. -*/ - -typedef enum -{ - SPI_CLOCK_PHASE_LEADING_EDGE = SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE, - SPI_CLOCK_PHASE_TRAILING_EDGE = SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE, - - - /* Force the compiler to reserve 32-bit space for each enum value */ - SPI_CLOCK_PHASE_INVALID = 0xFFFFFFFFU - -} SPI_CLOCK_PHASE; - -// ***************************************************************************** -/* SPI Clock Polarity - - Summary: - Identifies SPI Clock Polarity Options - - Description: - This enumeration identifies possible SPI Clock Polarity Options. - - Remarks: - None. -*/ - -typedef enum -{ - SPI_CLOCK_POLARITY_IDLE_LOW = SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW, - SPI_CLOCK_POLARITY_IDLE_HIGH = SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH, - - - /* Force the compiler to reserve 32-bit space for each enum value */ - SPI_CLOCK_POLARITY_INVALID = 0xFFFFFFFFU - -} SPI_CLOCK_POLARITY; - -// ***************************************************************************** -/* SPI Data Bits - - Summary: - Identifies SPI bits per transfer - - Description: - This enumeration identifies number of bits per SPI transfer. - - Remarks: - For 9 bit mode, data should be right aligned in the 16 bit - memory location. -*/ - -typedef enum -{ - SPI_DATA_BITS_8 = SERCOM_SPIM_CTRLB_CHSIZE_8_BIT, - SPI_DATA_BITS_9 = SERCOM_SPIM_CTRLB_CHSIZE_9_BIT, - - - /* Force the compiler to reserve 32-bit space for each enum value */ - SPI_DATA_BITS_INVALID = 0xFFFFFFFFU - -} SPI_DATA_BITS; - -// ***************************************************************************** -/* SPI Transfer Setup Parameters - - Summary: - Identifies the setup parameters which can be changed dynamically. - - Description - This structure identifies the possible setup parameters for SPI - which can be changed dynamically if needed. - - Remarks: - None. -*/ - -typedef struct -{ - /* Baud Rate or clock frequency */ - uint32_t clockFrequency; - - /* Clock Phase */ - SPI_CLOCK_PHASE clockPhase; - - /* Clock Polarity */ - SPI_CLOCK_POLARITY clockPolarity; - - /* Number of bits per transfer */ - SPI_DATA_BITS dataBits; - -} SPI_TRANSFER_SETUP; - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* SPI CallBack Function Pointer - - Summary: - Pointer to a SPI Call back function. - - Description: - This data type defines the required function signature for the - SPI event handling callback function. Application must register - a pointer to an event handling function whose function signature (parameter - and return value types) match the types specified by this function pointer - in order to receive event calls back from the PLIB. - - The parameters and return values are described here and a partial example - implementation is provided. - - Parameters: - context - Value identifying the context of the application that - registered the event handling function - - Returns: - None. - - Example: - - - SPI1_CallbackRegister(&APP_SPICallBack, NULL); - void APP_SPICallBack(uintptr_t contextHandle) - { - if( SPI_ERROR_NONE == SPI1_ErrorGet()) - { - Exchange was completed without error, do something else now. - } - } - - - Remarks: - The context parameter contains the a handle to the client context, - provided at the time the event handling function was registered using the - SPIx_CallbackRegister function. This context handle value is - passed back to the client as the "context" parameter. It can be any value - (such as a pointer to the client's data) necessary to identify the client - context or instance of the client that made the data exchange - request. - - The event handler function executes in the PLIB's interrupt context. It is - recommended of the application to not perform process intensive or blocking - operations with in this function. -*/ - -typedef void (*SERCOM_SPI_CALLBACK)(uintptr_t context); - -// ***************************************************************************** -// ***************************************************************************** -// Section: Local: **** Local SPI Object**** -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* SPI Object - - Summary: - Defines the data type for the data structures used for peripheral - operations. - - Description: - This may be for used for peripheral operations. - - Remarks: - None. -*/ - -typedef struct -{ - /* Pointer to the transmitter buffer */ - void * txBuffer; - - /* Pointer to the received buffer */ - void * rxBuffer; - - size_t txSize; - - size_t rxSize; - - size_t dummySize; - - /* Size of the receive processed exchange size */ - size_t rxCount; - - /* Size of the transmit processed exchange size */ - size_t txCount; - - /* Exchange busy status of the SPI */ - bool transferIsBusy; - - /* SPI Event handler */ - SERCOM_SPI_CALLBACK callback; - - /* Context */ - uintptr_t context; - - uint32_t status; - -} SPI_OBJECT; - -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif - -#endif //PLIB_SERCOM_SPI_MASTER_COMMON_H \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c deleted file mode 100644 index ca5c9b13..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c +++ /dev/null @@ -1,615 +0,0 @@ -/******************************************************************************* - SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom3_usart.c - - Summary - USART peripheral library interface. - - Description - This file defines the interface to the USART peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include "interrupts.h" -#include "plib_sercom3_usart.h" -// ***************************************************************************** -// ***************************************************************************** -// Section: Global Data -// ***************************************************************************** -// ***************************************************************************** -/* SERCOM3 USART baud value for 115200 Hz baud rate */ -#define SERCOM3_USART_INT_BAUD_VALUE (63019UL) - -static volatile SERCOM_USART_OBJECT sercom3USARTObj; - - -// ***************************************************************************** -// ***************************************************************************** -// Section: SERCOM3 USART Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -static void SERCOM3_USART_ErrorClear( void ) -{ - uint8_t u8dummyData = 0U; - USART_ERROR errorStatus = (USART_ERROR) (SERCOM3_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); - - if(errorStatus != USART_ERROR_NONE) - { - /* Clear error flag */ - SERCOM3_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; - /* Clear all errors */ - SERCOM3_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); - - /* Flush existing error bytes from the RX FIFO */ - while((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) - { - u8dummyData = (uint8_t)SERCOM3_REGS->USART_INT.SERCOM_DATA; - } - } - - /* Ignore the warning */ - (void)u8dummyData; -} - -void SERCOM3_USART_Initialize( void ) -{ - /* - * Configures USART Clock Mode - * Configures TXPO and RXPO - * Configures Data Order - * Configures Standby Mode - * Configures Sampling rate - * Configures IBON - */ - - SERCOM3_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; - - /* Configure Baud Rate */ - SERCOM3_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM3_USART_INT_BAUD_VALUE); - - /* - * Configures RXEN - * Configures TXEN - * Configures CHSIZE - * Configures Parity - * Configures Stop bits - */ - SERCOM3_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - /* Enable the UART after the configurations */ - SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Initialize instance object */ - sercom3USARTObj.rxBuffer = NULL; - sercom3USARTObj.rxSize = 0; - sercom3USARTObj.rxProcessedSize = 0; - sercom3USARTObj.rxBusyStatus = false; - sercom3USARTObj.rxCallback = NULL; - sercom3USARTObj.txBuffer = NULL; - sercom3USARTObj.txSize = 0; - sercom3USARTObj.txProcessedSize = 0; - sercom3USARTObj.txBusyStatus = false; - sercom3USARTObj.txCallback = NULL; - sercom3USARTObj.errorStatus = USART_ERROR_NONE; -} - - - - - -uint32_t SERCOM3_USART_FrequencyGet( void ) -{ - return 48000000UL; -} - -bool SERCOM3_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) -{ - bool setupStatus = false; - uint32_t baudValue = 0U; - uint32_t sampleRate = 0U; - uint32_t sampleCount = 0U; - - bool transferProgress = sercom3USARTObj.txBusyStatus; - transferProgress = sercom3USARTObj.rxBusyStatus || transferProgress; - if(transferProgress) - { - /* Transaction is in progress, so return without updating settings */ - return setupStatus; - } - - if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) - { - if(clkFrequency == 0U) - { - clkFrequency = SERCOM3_USART_FrequencyGet(); - } - - if(clkFrequency >= (16U * serialSetup->baudRate)) - { - sampleRate = 0U; - sampleCount = 16U; - } - else if(clkFrequency >= (8U * serialSetup->baudRate)) - { - sampleRate = 2U; - sampleCount = 8U; - } - else if(clkFrequency >= (3U * serialSetup->baudRate)) - { - sampleRate = 4U; - sampleCount = 3U; - } - else - { - /* Do nothing */ - } - baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); - /* Disable the USART before configurations */ - SERCOM3_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Configure Baud Rate */ - SERCOM3_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); - - /* Configure Parity Options */ - if(serialSetup->parity == USART_PARITY_NONE) - { - SERCOM3_REGS->USART_INT.SERCOM_CTRLA = (SERCOM3_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); - SERCOM3_REGS->USART_INT.SERCOM_CTRLB = (SERCOM3_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); - } - else - { - SERCOM3_REGS->USART_INT.SERCOM_CTRLA = (SERCOM3_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); - SERCOM3_REGS->USART_INT.SERCOM_CTRLB = (SERCOM3_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; - } - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Enable the USART after the configurations */ - SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - setupStatus = true; - } - - return setupStatus; -} - -USART_ERROR SERCOM3_USART_ErrorGet( void ) -{ - USART_ERROR errorStatus = sercom3USARTObj.errorStatus; - - sercom3USARTObj.errorStatus = USART_ERROR_NONE; - - return errorStatus; -} - -void SERCOM3_USART_Enable( void ) -{ - if((SERCOM3_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) - { - SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - } -} - -void SERCOM3_USART_Disable( void ) -{ - if((SERCOM3_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) - { - SERCOM3_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - } -} - - -void SERCOM3_USART_TransmitterEnable( void ) -{ - SERCOM3_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -void SERCOM3_USART_TransmitterDisable( void ) -{ - SERCOM3_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -bool SERCOM3_USART_Write( void *buffer, const size_t size ) -{ - bool writeStatus = false; - uint32_t processedSize = 0U; - - if(buffer != NULL) - { - if(sercom3USARTObj.txBusyStatus == false) - { - sercom3USARTObj.txBuffer = buffer; - sercom3USARTObj.txSize = size; - sercom3USARTObj.txBusyStatus = true; - - size_t txSize = sercom3USARTObj.txSize; - - /* Initiate the transfer by sending first byte */ - while (((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) && - (processedSize < txSize)) - { - if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) - { - /* 8-bit mode */ - SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)(buffer))[processedSize]; - } - else - { - /* 9-bit mode */ - SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)(buffer))[processedSize]; - } - processedSize += 1U; - } - sercom3USARTObj.txProcessedSize = processedSize; - SERCOM3_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk; - - writeStatus = true; - } - } - - return writeStatus; -} - - -bool SERCOM3_USART_WriteIsBusy( void ) -{ - return sercom3USARTObj.txBusyStatus; -} - -size_t SERCOM3_USART_WriteCountGet( void ) -{ - return sercom3USARTObj.txProcessedSize; -} - -void SERCOM3_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) -{ - sercom3USARTObj.txCallback = callback; - - sercom3USARTObj.txContext = context; -} - - -bool SERCOM3_USART_TransmitComplete( void ) -{ - bool transmitComplete = false; - - if ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) - { - transmitComplete = true; - } - - return transmitComplete; -} - -void SERCOM3_USART_ReceiverEnable( void ) -{ - SERCOM3_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -void SERCOM3_USART_ReceiverDisable( void ) -{ - SERCOM3_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; - - /* Wait for sync */ - while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -bool SERCOM3_USART_Read( void *buffer, const size_t size ) -{ - bool readStatus = false; - - if(buffer != NULL) - { - if(sercom3USARTObj.rxBusyStatus == false) - { - /* Clear error flags and flush out error data that may have been received when no active request was pending */ - SERCOM3_USART_ErrorClear(); - - sercom3USARTObj.rxBuffer = buffer; - sercom3USARTObj.rxSize = size; - sercom3USARTObj.rxProcessedSize = 0U; - sercom3USARTObj.rxBusyStatus = true; - sercom3USARTObj.errorStatus = USART_ERROR_NONE; - - readStatus = true; - - /* Enable receive and error interrupt */ - SERCOM3_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)(SERCOM_USART_INT_INTENSET_ERROR_Msk | SERCOM_USART_INT_INTENSET_RXC_Msk); - } - } - - return readStatus; -} - -bool SERCOM3_USART_ReadIsBusy( void ) -{ - return sercom3USARTObj.rxBusyStatus; -} - -size_t SERCOM3_USART_ReadCountGet( void ) -{ - return sercom3USARTObj.rxProcessedSize; -} - -bool SERCOM3_USART_ReadAbort(void) -{ - if (sercom3USARTObj.rxBusyStatus == true) - { - /* Disable receive and error interrupt */ - SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); - - sercom3USARTObj.rxBusyStatus = false; - - /* If required application should read the num bytes processed prior to calling the read abort API */ - sercom3USARTObj.rxSize = 0U; - sercom3USARTObj.rxProcessedSize = 0U; - } - - return true; -} - -void SERCOM3_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) -{ - sercom3USARTObj.rxCallback = callback; - - sercom3USARTObj.rxContext = context; -} - - -static void __attribute__((used)) SERCOM3_USART_ISR_ERR_Handler( void ) -{ - USART_ERROR errorStatus; - - errorStatus = (USART_ERROR) (SERCOM3_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); - - if(errorStatus != USART_ERROR_NONE) - { - /* Save the error to be reported later */ - sercom3USARTObj.errorStatus = errorStatus; - - /* Clear the error flags and flush out the error bytes */ - SERCOM3_USART_ErrorClear(); - - /* Disable error and receive interrupt to abort on-going transfer */ - SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); - - /* Clear the RX busy flag */ - sercom3USARTObj.rxBusyStatus = false; - - if(sercom3USARTObj.rxCallback != NULL) - { - uintptr_t rxContext = sercom3USARTObj.rxContext; - - sercom3USARTObj.rxCallback(rxContext); - } - } -} - -static void __attribute__((used)) SERCOM3_USART_ISR_RX_Handler( void ) -{ - uint16_t temp; - - - if(sercom3USARTObj.rxBusyStatus == true) - { - size_t rxSize = sercom3USARTObj.rxSize; - - if(sercom3USARTObj.rxProcessedSize < rxSize) - { - uintptr_t rxContext = sercom3USARTObj.rxContext; - - temp = (uint16_t)SERCOM3_REGS->USART_INT.SERCOM_DATA; - size_t rxProcessedSize = sercom3USARTObj.rxProcessedSize; - - if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) - { - /* 8-bit mode */ - ((uint8_t*)sercom3USARTObj.rxBuffer)[rxProcessedSize] = (uint8_t) (temp); - } - else - { - /* 9-bit mode */ - ((uint16_t*)sercom3USARTObj.rxBuffer)[rxProcessedSize] = temp; - } - - /* Increment processed size */ - rxProcessedSize++; - sercom3USARTObj.rxProcessedSize = rxProcessedSize; - - if(rxProcessedSize == sercom3USARTObj.rxSize) - { - sercom3USARTObj.rxBusyStatus = false; - sercom3USARTObj.rxSize = 0U; - SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_RXC_Msk | SERCOM_USART_INT_INTENCLR_ERROR_Msk); - - if(sercom3USARTObj.rxCallback != NULL) - { - sercom3USARTObj.rxCallback(rxContext); - } - } - - } - } -} - -static void __attribute__((used)) SERCOM3_USART_ISR_TX_Handler( void ) -{ - bool dataRegisterEmpty; - bool dataAvailable; - if(sercom3USARTObj.txBusyStatus == true) - { - size_t txProcessedSize = sercom3USARTObj.txProcessedSize; - - dataAvailable = (txProcessedSize < sercom3USARTObj.txSize); - dataRegisterEmpty = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); - - while(dataRegisterEmpty && dataAvailable) - { - if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) - { - /* 8-bit mode */ - SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)sercom3USARTObj.txBuffer)[txProcessedSize]; - } - else - { - /* 9-bit mode */ - SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)sercom3USARTObj.txBuffer)[txProcessedSize]; - } - /* Increment processed size */ - txProcessedSize++; - - dataAvailable = (txProcessedSize < sercom3USARTObj.txSize); - dataRegisterEmpty = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); - } - - sercom3USARTObj.txProcessedSize = txProcessedSize; - - if(txProcessedSize >= sercom3USARTObj.txSize) - { - sercom3USARTObj.txBusyStatus = false; - sercom3USARTObj.txSize = 0U; - SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)SERCOM_USART_INT_INTENCLR_DRE_Msk; - - if(sercom3USARTObj.txCallback != NULL) - { - uintptr_t txContext = sercom3USARTObj.txContext; - sercom3USARTObj.txCallback(txContext); - } - } - } -} - -void __attribute__((used)) SERCOM3_USART_InterruptHandler( void ) -{ - bool testCondition; - if(SERCOM3_REGS->USART_INT.SERCOM_INTENSET != 0U) - { - /* Checks for error flag */ - testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_ERROR_Msk) == SERCOM_USART_INT_INTFLAG_ERROR_Msk); - testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_ERROR_Msk) == SERCOM_USART_INT_INTENSET_ERROR_Msk) && testCondition; - if(testCondition) - { - SERCOM3_USART_ISR_ERR_Handler(); - } - - testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); - testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_DRE_Msk) == SERCOM_USART_INT_INTENSET_DRE_Msk) && testCondition; - /* Checks for data register empty flag */ - if(testCondition) - { - SERCOM3_USART_ISR_TX_Handler(); - } - - testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk); - testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_RXC_Msk) == SERCOM_USART_INT_INTENSET_RXC_Msk) && testCondition; - /* Checks for receive complete empty flag */ - if(testCondition) - { - SERCOM3_USART_ISR_RX_Handler(); - } - } -} - - - - diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h deleted file mode 100644 index 22cbca64..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h +++ /dev/null @@ -1,121 +0,0 @@ -/******************************************************************************* - SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom3_usart.h - - Summary - USART peripheral library interface. - - Description - This file defines the interface to the USART peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef PLIB_SERCOM3_USART_H // Guards against multiple inclusion -#define PLIB_SERCOM3_USART_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include "plib_sercom_usart_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -void SERCOM3_USART_Initialize( void ); - -bool SERCOM3_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); - -void SERCOM3_USART_Enable( void ); - -void SERCOM3_USART_Disable( void ); - -void SERCOM3_USART_TransmitterEnable( void ); - -void SERCOM3_USART_TransmitterDisable( void ); - -bool SERCOM3_USART_Write( void *buffer, const size_t size ); - -bool SERCOM3_USART_TransmitComplete( void ); - - -bool SERCOM3_USART_WriteIsBusy( void ); - -size_t SERCOM3_USART_WriteCountGet( void ); - -void SERCOM3_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); - - -void SERCOM3_USART_ReceiverEnable( void ); - -void SERCOM3_USART_ReceiverDisable( void ); - -bool SERCOM3_USART_Read( void *buffer, const size_t size ); - -bool SERCOM3_USART_ReadIsBusy( void ); - -size_t SERCOM3_USART_ReadCountGet( void ); - -bool SERCOM3_USART_ReadAbort(void); - -void SERCOM3_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); - -USART_ERROR SERCOM3_USART_ErrorGet( void ); - -uint32_t SERCOM3_USART_FrequencyGet( void ); - - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif //PLIB_SERCOM3_USART_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c deleted file mode 100644 index 89ba9800..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.c +++ /dev/null @@ -1,462 +0,0 @@ -/******************************************************************************* - SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom4_usart.c - - Summary - USART peripheral library interface. - - Description - This file defines the interface to the USART peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** -#include "interrupts.h" -#include "plib_sercom4_usart.h" - -/* - * ATSAMC21E18A exposes SERCOM3 register base for the PA22/PA23 UART route. - * Keep SERCOM4 USART API names stable for existing application code. - */ -#ifndef SERCOM4_REGS -#define SERCOM4_REGS SERCOM3_REGS -#endif -// ***************************************************************************** -// ***************************************************************************** -// Section: Global Data -// ***************************************************************************** -// ***************************************************************************** -/* SERCOM4 USART baud value for 115200 Hz baud rate */ -#define SERCOM4_USART_INT_BAUD_VALUE (63019UL) - - - -// ***************************************************************************** -// ***************************************************************************** -// Section: SERCOM4 USART Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -static void SERCOM4_USART_ErrorClear( void ) -{ - uint8_t u8dummyData = 0U; - USART_ERROR errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); - - if(errorStatus != USART_ERROR_NONE) - { - /* Clear error flag */ - SERCOM4_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; - /* Clear all errors */ - SERCOM4_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); - - /* Flush existing error bytes from the RX FIFO */ - while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) - { - u8dummyData = (uint8_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; - } - } - - /* Ignore the warning */ - (void)u8dummyData; -} - -void SERCOM4_USART_Initialize( void ) -{ - /* - * Configures USART Clock Mode - * Configures TXPO and RXPO - * Configures Data Order - * Configures Standby Mode - * Configures Sampling rate - * Configures IBON - */ - - SERCOM4_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x3UL) | SERCOM_USART_INT_CTRLA_TXPO(0x1UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; - - /* Configure Baud Rate */ - SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM4_USART_INT_BAUD_VALUE); - - /* - * Configures RXEN - * Configures TXEN - * Configures CHSIZE - * Configures Parity - * Configures Stop bits - */ - SERCOM4_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - - /* Enable the UART after the configurations */ - SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - - - - - -uint32_t SERCOM4_USART_FrequencyGet( void ) -{ - return 48000000UL; -} - -bool SERCOM4_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) -{ - bool setupStatus = false; - uint32_t baudValue = 0U; - uint32_t sampleRate = 0U; - uint32_t sampleCount = 0U; - - if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) - { - if(clkFrequency == 0U) - { - clkFrequency = SERCOM4_USART_FrequencyGet(); - } - - if(clkFrequency >= (16U * serialSetup->baudRate)) - { - sampleRate = 0U; - sampleCount = 16U; - } - else if(clkFrequency >= (8U * serialSetup->baudRate)) - { - sampleRate = 2U; - sampleCount = 8U; - } - else if(clkFrequency >= (3U * serialSetup->baudRate)) - { - sampleRate = 4U; - sampleCount = 3U; - } - else - { - /* Do nothing */ - } - baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); - /* Disable the USART before configurations */ - SERCOM4_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Configure Baud Rate */ - SERCOM4_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); - - /* Configure Parity Options */ - if(serialSetup->parity == USART_PARITY_NONE) - { - SERCOM4_REGS->USART_INT.SERCOM_CTRLA = (SERCOM4_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); - SERCOM4_REGS->USART_INT.SERCOM_CTRLB = (SERCOM4_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); - } - else - { - SERCOM4_REGS->USART_INT.SERCOM_CTRLA = (SERCOM4_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); - SERCOM4_REGS->USART_INT.SERCOM_CTRLB = (SERCOM4_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; - } - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - /* Enable the USART after the configurations */ - SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - - setupStatus = true; - } - - return setupStatus; -} - -USART_ERROR SERCOM4_USART_ErrorGet( void ) -{ - USART_ERROR errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); - - if(errorStatus != USART_ERROR_NONE) - { - SERCOM4_USART_ErrorClear(); - } - - return errorStatus; -} - -void SERCOM4_USART_Enable( void ) -{ - if((SERCOM4_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) - { - SERCOM4_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - } -} - -void SERCOM4_USART_Disable( void ) -{ - if((SERCOM4_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) - { - SERCOM4_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } - } -} - - -void SERCOM4_USART_TransmitterEnable( void ) -{ - SERCOM4_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -void SERCOM4_USART_TransmitterDisable( void ) -{ - SERCOM4_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -bool SERCOM4_USART_Write( void *buffer, const size_t size ) -{ - bool writeStatus = false; - uint8_t *pu8Data = (uint8_t*)buffer; - uint16_t *pu16Data = (uint16_t*)buffer; - uint32_t u32Index = 0U; - - if(buffer != NULL) - { - /* Blocks while buffer is being transferred */ - while(u32Index < size) - { - /* Check if USART is ready for new data */ - while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk) == 0U) - { - /* Do nothing */ - } - - /* Write data to USART module */ - if (((SERCOM4_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) - { - /* 8-bit mode */ - SERCOM4_REGS->USART_INT.SERCOM_DATA = pu8Data[u32Index]; - } - else - { - /* 9-bit mode */ - SERCOM4_REGS->USART_INT.SERCOM_DATA = pu16Data[u32Index]; - } - - /* Increment index */ - u32Index++; - } - writeStatus = true; - } - - return writeStatus; -} - - -bool SERCOM4_USART_TransmitterIsReady( void ) -{ - bool transmitterStatus = false; - - if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) - { - transmitterStatus = true; - } - - return transmitterStatus; -} - -void SERCOM4_USART_WriteByte( int data ) -{ - /* Check if USART is ready for new data */ - while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == 0U) - { - /* Do nothing */ - } - - SERCOM4_REGS->USART_INT.SERCOM_DATA = (uint16_t)data; -} - -bool SERCOM4_USART_TransmitComplete( void ) -{ - bool transmitComplete = false; - - if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) - { - transmitComplete = true; - } - - return transmitComplete; -} - -void SERCOM4_USART_ReceiverEnable( void ) -{ - SERCOM4_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -void SERCOM4_USART_ReceiverDisable( void ) -{ - SERCOM4_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; - - /* Wait for sync */ - while((SERCOM4_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) - { - /* Do nothing */ - } -} - -bool SERCOM4_USART_Read( void *buffer, const size_t size ) -{ - bool readStatus = false; - uint8_t* pu8Data = (uint8_t*)buffer; - uint16_t *pu16Data = (uint16_t*)buffer; - uint32_t u32Index = 0U; - USART_ERROR errorStatus = USART_ERROR_NONE; - - if(buffer != NULL) - { - - /* Clear error flags and flush out error data that may have been received when no active request was pending */ - SERCOM4_USART_ErrorClear(); - - while(u32Index < size) - { - /* Check if USART has new data */ - while((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == 0U) - { - /* Do nothing */ - } - - errorStatus = (USART_ERROR) (SERCOM4_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); - - if(errorStatus != USART_ERROR_NONE) - { - break; - } - - if (((SERCOM4_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) - { - /* 8-bit mode */ - pu8Data[u32Index] = (uint8_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; - } - else - { - /* 9-bit mode */ - pu16Data[u32Index] = (uint16_t)SERCOM4_REGS->USART_INT.SERCOM_DATA; - } - - /* Increment index */ - u32Index++; - } - - if(size == u32Index) - { - readStatus = true; - } - } - - return readStatus; -} - -bool SERCOM4_USART_ReceiverIsReady( void ) -{ - bool receiverStatus = false; - - if ((SERCOM4_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk) - { - receiverStatus = true; - } - - return receiverStatus; -} - -int SERCOM4_USART_ReadByte( void ) -{ - return (int)SERCOM4_REGS->USART_INT.SERCOM_DATA; -} - - - - - diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h deleted file mode 100644 index bc21fb11..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom4_usart.h +++ /dev/null @@ -1,115 +0,0 @@ -/******************************************************************************* - SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom4_usart.h - - Summary - USART peripheral library interface. - - Description - This file defines the interface to the USART peripheral library. This - library provides access to and control of the associated peripheral - instance. - - Remarks: - None. -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef PLIB_SERCOM4_USART_H // Guards against multiple inclusion -#define PLIB_SERCOM4_USART_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include "plib_sercom_usart_common.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section: Interface Routines -// ***************************************************************************** -// ***************************************************************************** - -void SERCOM4_USART_Initialize( void ); - -bool SERCOM4_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); - -void SERCOM4_USART_Enable( void ); - -void SERCOM4_USART_Disable( void ); - -void SERCOM4_USART_TransmitterEnable( void ); - -void SERCOM4_USART_TransmitterDisable( void ); - -bool SERCOM4_USART_Write( void *buffer, const size_t size ); - -bool SERCOM4_USART_TransmitComplete( void ); - - -bool SERCOM4_USART_TransmitterIsReady( void ); - -void SERCOM4_USART_WriteByte( int data ); - - -void SERCOM4_USART_ReceiverEnable( void ); - -void SERCOM4_USART_ReceiverDisable( void ); - -bool SERCOM4_USART_Read( void *buffer, const size_t size ); - -bool SERCOM4_USART_ReceiverIsReady( void ); - -int SERCOM4_USART_ReadByte( void ); - -USART_ERROR SERCOM4_USART_ErrorGet( void ); - -uint32_t SERCOM4_USART_FrequencyGet( void ); - - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif //PLIB_SERCOM4_USART_H diff --git a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h b/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h deleted file mode 100644 index ab6321c6..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h +++ /dev/null @@ -1,405 +0,0 @@ -/******************************************************************************* - SERCOM Universal Synchronous/Asynchronous Receiver/Transmitter PLIB - - Company - Microchip Technology Inc. - - File Name - plib_sercom_usart_common.h - - Summary - Data Type definition of the USART Peripheral Interface Plib. - - Description - This file defines the Data Types for the USART Plib. - - Remarks: - None. -*******************************************************************************/ - -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#ifndef PLIB_SERCOM_USART_COMMON_H // Guards against multiple inclusion -#define PLIB_SERCOM_USART_COMMON_H - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include -#include -#include -#include "device.h" - -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - extern "C" { - -#endif -// DOM-IGNORE-END - -// ***************************************************************************** -// ***************************************************************************** -// Section:Preprocessor macros -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* USART Error convenience macros */ -// ***************************************************************************** -// ***************************************************************************** - /* Error status when no error has occurred */ -#define USART_ERROR_NONE 0U - - /* Error status when parity error has occurred */ -#define USART_ERROR_PARITY SERCOM_USART_INT_STATUS_PERR_Msk - - /* Error status when framing error has occurred */ -#define USART_ERROR_FRAMING SERCOM_USART_INT_STATUS_FERR_Msk - - /* Error status when overrun error has occurred */ -#define USART_ERROR_OVERRUN SERCOM_USART_INT_STATUS_BUFOVF_Msk - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Data Types -// ***************************************************************************** -// ***************************************************************************** -// ***************************************************************************** - -// ***************************************************************************** -/* USART Errors - - Summary: - Defines the data type for the USART peripheral errors. - - Description: - This may be used to check the type of error occurred with the USART - peripheral during error status. - - Remarks: - None. -*/ - -typedef uint16_t USART_ERROR; - -// ***************************************************************************** -/* USART DATA - - Summary: - Defines the data type for the USART peripheral data. - - Description: - This may be used to check the type of data with the USART - peripheral during serial setup. - - Remarks: - None. -*/ - -typedef enum -{ - USART_DATA_5_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT, - USART_DATA_6_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT, - USART_DATA_7_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT, - USART_DATA_8_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT, - USART_DATA_9_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT, - - - /* Force the compiler to reserve 32-bit memory for each enum */ - USART_DATA_INVALID = 0xFFFFFFFFU - -} USART_DATA; - -// ***************************************************************************** -/* USART PARITY - - Summary: - Defines the data type for the USART peripheral parity. - - Description: - This may be used to check the type of parity with the USART - peripheral during serial setup. - - Remarks: - None. -*/ - -typedef enum -{ - USART_PARITY_EVEN = SERCOM_USART_INT_CTRLB_PMODE_EVEN, - - USART_PARITY_ODD = SERCOM_USART_INT_CTRLB_PMODE_ODD, - - /* This enum is defined to set frame format only - * This value won't be written to register - */ - USART_PARITY_NONE = 0x2, - - /* Force the compiler to reserve 32-bit memory for each enum */ - USART_PARITY_INVALID = 0xFFFFFFFFU - -} USART_PARITY; - -// ***************************************************************************** -/* USART STOP - - Summary: - Defines the data type for the USART peripheral stop bits. - - Description: - This may be used to check the type of stop bits with the USART - peripheral during serial setup. - - Remarks: - None. -*/ - -typedef enum -{ - USART_STOP_0_BIT = SERCOM_USART_INT_CTRLB_SBMODE_1_BIT, - USART_STOP_1_BIT = SERCOM_USART_INT_CTRLB_SBMODE_2_BIT, - - - /* Force the compiler to reserve 32-bit memory for each enum */ - USART_STOP_INVALID = 0xFFFFFFFFU - -} USART_STOP; - -// ***************************************************************************** -/* USART LIN Command - - Summary: - Defines the data type for the USART peripheral LIN Command. - - Description: - This may be used to set the USART LIN Master mode command. - - Remarks: - None. -*/ - -typedef enum -{ - USART_LIN_MASTER_CMD_NONE = SERCOM_USART_INT_CTRLB_LINCMD_NONE, - - USART_LIN_MASTER_CMD_SOFTWARE_CONTROLLED = SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD, - - USART_LIN_MASTER_CMD_AUTO_TRANSMIT = SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD - -} USART_LIN_MASTER_CMD; - -// ***************************************************************************** -/* USART Serial Configuration - - Summary: - Defines the data type for the USART serial configurations. - - Description: - This may be used to set the serial configurations for USART. - - Remarks: - None. -*/ - -typedef struct -{ - uint32_t baudRate; - - USART_PARITY parity; - - USART_DATA dataWidth; - - USART_STOP stopBits; - -} USART_SERIAL_SETUP; - -// ***************************************************************************** -/* Callback Function Pointer - - Summary: - Defines the data type and function signature for the USART peripheral - callback function. - - Description: - This data type defines the function signature for the USART peripheral - callback function. The USART peripheral will call back the client's - function with this signature when the USART buffer event has occurred. - - Remarks: - None. -*/ - -typedef void (*SERCOM_USART_CALLBACK)( uintptr_t context ); - -// ***************************************************************************** -/* SERCOM USART Object - - Summary: - Defines the data type for the data structures used for - peripheral operations. - - Description: - This may be for used for peripheral operations. - - Remarks: - None. -*/ - -typedef struct -{ - void * txBuffer; - - size_t txSize; - - size_t txProcessedSize; - - SERCOM_USART_CALLBACK txCallback; - - uintptr_t txContext; - - bool txBusyStatus; - - void * rxBuffer; - - size_t rxSize; - - size_t rxProcessedSize; - - SERCOM_USART_CALLBACK rxCallback; - - uintptr_t rxContext; - - bool rxBusyStatus; - - USART_ERROR errorStatus; - -} SERCOM_USART_OBJECT; - - -typedef enum -{ - /* Threshold number of bytes are available in the receive ring buffer */ - SERCOM_USART_EVENT_READ_THRESHOLD_REACHED = 0, - - /* Receive ring buffer is full. Application must read the data out to avoid missing data on the next RX interrupt. */ - SERCOM_USART_EVENT_READ_BUFFER_FULL, - - /* USART error. Application must call the SERCOMx_USART_ErrorGet API to get the type of error and clear the error. */ - SERCOM_USART_EVENT_READ_ERROR, - - /* Threshold number of free space is available in the transmit ring buffer */ - SERCOM_USART_EVENT_WRITE_THRESHOLD_REACHED, - - /* Recevie break signal is detected */ - SERCOM_USART_EVENT_BREAK_SIGNAL_DETECTED, -}SERCOM_USART_EVENT; - -// ***************************************************************************** -/* Callback Function Pointer - - Summary: - Defines the data type and function signature for the USART peripheral - callback function. - - Description: - This data type defines the function signature for the USART peripheral - callback function. The USART peripheral will call back the client's - function with this signature when the USART buffer event has occurred. - - Remarks: - None. -*/ - -typedef void (*SERCOM_USART_RING_BUFFER_CALLBACK)(SERCOM_USART_EVENT event, uintptr_t context ); - -// ***************************************************************************** -/* SERCOM USART Ring Buffer Object - - Summary: - Defines the data type for the data structures used for - peripheral operations. - - Description: - This may be for used for peripheral operations. - - Remarks: - None. -*/ - -typedef struct -{ - SERCOM_USART_RING_BUFFER_CALLBACK wrCallback; - - uintptr_t wrContext; - - uint32_t wrInIndex; - - uint32_t wrOutIndex; - - uint32_t wrBufferSize; - - bool isWrNotificationEnabled; - - uint32_t wrThreshold; - - bool isWrNotifyPersistently; - - SERCOM_USART_RING_BUFFER_CALLBACK rdCallback; - - uintptr_t rdContext; - - uint32_t rdInIndex; - - uint32_t rdOutIndex; - - uint32_t rdBufferSize; - - bool isRdNotificationEnabled; - - uint32_t rdThreshold; - - bool isRdNotifyPersistently; - - USART_ERROR errorStatus; - -} SERCOM_USART_RING_BUFFER_OBJECT; - -// ***************************************************************************** -// DOM-IGNORE-BEGIN -#ifdef __cplusplus // Provide C++ Compatibility - - } - -#endif -// DOM-IGNORE-END - -#endif //PLIB_SERCOM_USART_COMMON_H diff --git a/bms/bms/bms_config_e18a/src/config/default/startup_xc32.c b/bms/bms/bms_config_e18a/src/config/default/startup_xc32.c deleted file mode 100644 index d9430dd5..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/startup_xc32.c +++ /dev/null @@ -1,145 +0,0 @@ -// DOM-IGNORE-BEGIN -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -// DOM-IGNORE-END - -#include -#include -#include -#include "device.h" -#include "interrupts.h" - -/* - * The MPLAB X Simulator does not yet support simulation of programming the - * GPNVM bits yet. We can remove this once it supports the FRDY bit. - */ - /* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 21.1 deviated 1 time. Deviation record ID - H3_MISRAC_2012_R_21_1_DR_1 */ -#ifdef __MPLAB_DEBUGGER_SIMULATOR -#define __XC32_SKIP_STARTUP_GPNVM_WAIT -#endif -/* MISRAC 2012 deviation block end */ - -/* - * This startup code relies on features that are specific to the MPLAB XC32 - * toolchain. Do not use it with other toolchains. - */ -#ifndef __XC32 -#warning This startup code is intended for use with the MPLAB XC32 Compiler only. -#endif - -/* MISRAC 2012 deviation block start */ -/* MISRA C-2012 Rule 21.2 deviated 5 times. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ -/* MISRA C-2012 Rule 8.6 deviated 6 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ - -/* array initialization function */ -extern void __attribute__((long_call)) __libc_init_array(void); - -/* Optional application-provided functions */ -extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_reset(void); -extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_bootstrap(void); - -/* Reserved for use by the MPLAB XC32 Compiler */ -extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_reset(void); -extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_bootstrap(void); - -/* Linker defined variables */ -extern uint32_t __svectors; -#if defined (__REINIT_STACK_POINTER) -extern uint32_t _stack; -#endif - -/* MISRAC 2012 deviation block end */ - - -extern int main(void); - - - -/* Brief default application function used as a weak reference */ -extern void Dummy_App_Func(void); -void __attribute__((optimize("-O1"),long_call))Dummy_App_Func(void) -{ - /* Do nothing */ - return; -} - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void __attribute__((optimize("-O1"), section(".text.Reset_Handler"), long_call, noreturn)) Reset_Handler(void) -{ -#ifdef SCB_VTOR_TBLOFF_Msk - uint32_t *pSrc; -#endif - -#if defined (__REINIT_STACK_POINTER) - /* Initialize SP from linker-defined _stack symbol. */ - __set_MSP((uint32_t)&_stack); - -#ifdef SCB_VTOR_TBLOFF_Msk - /* Buy stack for locals */ - __asm__ volatile ("sub sp, sp, #8" : : : "sp"); -#endif - __asm__ volatile ("add r7, sp, #0" : : : "r7"); -#endif - - /* Call the optional application-provided _on_reset() function. */ - _on_reset(); - - /* Reserved for use by MPLAB XC32. */ - __xc32_on_reset(); - - /* Initialize data after TCM is enabled. - * Data initialization from the XC32 .dinit template */ - __pic32c_data_initialization(); - - -# ifdef SCB_VTOR_TBLOFF_Msk - /* Set the vector-table base address in FLASH */ - pSrc = (uint32_t *) & __svectors; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); -# endif /* SCB_VTOR_TBLOFF_Msk */ - - /* Initialize the C library */ - __libc_init_array(); - - /* Call the optional application-provided _on_bootstrap() function. */ - _on_bootstrap(); - - /* Reserved for use by MPLAB XC32. */ - __xc32_on_bootstrap(); - - /* Branch to application's main function */ - (void)main(); - -#if (defined(__DEBUG) || defined(__DEBUG_D)) && defined(__XC32) - __builtin_software_breakpoint(); -#endif - - while (true) - { - /* Infinite loop */ - } -} diff --git a/bms/bms/bms_config_e18a/src/config/default/stdio/xc32_monitor.c b/bms/bms/bms_config_e18a/src/config/default/stdio/xc32_monitor.c deleted file mode 100644 index 8d9df630..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/stdio/xc32_monitor.c +++ /dev/null @@ -1,54 +0,0 @@ -/******************************************************************************* - Debug Console Source file - - Company: - Microchip Technology Inc. - - File Name: - xc32_monitor.c - - Summary: - debug console Source File - - Description: - None - -*******************************************************************************/ - -/******************************************************************************* -* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ -#include - -extern int read(int handle, void *buffer, unsigned int len); -extern int write(int handle, void * buffer, size_t count); - - -int read(int handle, void *buffer, unsigned int len) -{ - return -1; -} - -int write(int handle, void * buffer, size_t count) -{ - return -1; -} \ No newline at end of file diff --git a/bms/bms/bms_config_e18a/src/config/default/toolchain_specifics.h b/bms/bms/bms_config_e18a/src/config/default/toolchain_specifics.h deleted file mode 100644 index 96407a4e..00000000 --- a/bms/bms/bms_config_e18a/src/config/default/toolchain_specifics.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************************************************************************* -* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. -* -* Subject to your compliance with these terms, you may use Microchip software -* and any derivatives exclusively with Microchip products. It is your -* responsibility to comply with third party license terms applicable to your -* use of third party software (including open source software) that may -* accompany Microchip software. -* -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER -* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED -* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A -* PARTICULAR PURPOSE. -* -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE -* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN -* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, -* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -*******************************************************************************/ - -#ifndef TOOLCHAIN_SPECIFICS_H -#define TOOLCHAIN_SPECIFICS_H - -#ifdef __cplusplus // Provide C++ Compatibility -extern "C" { -#endif - -#pragma GCC diagnostic push -#ifndef __cplusplus - #pragma GCC diagnostic ignored "-Wnested-externs" -#endif -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wattributes" -#pragma GCC diagnostic ignored "-Wundef" -#include "cmsis_compiler.h" -#pragma GCC diagnostic pop - -#include - -#define NO_INIT __attribute__((section(".no_init"))) -#define SECTION(a) __attribute__((__section__(a))) - -#define CACHE_LINE_SIZE (4u) -#define CACHE_ALIGN - -#define CACHE_ALIGNED_SIZE_GET(size) ((size) + ((((size) % (CACHE_LINE_SIZE))!= 0U)? ((CACHE_LINE_SIZE) - ((size) % (CACHE_LINE_SIZE))) : (0U))) - -#ifndef FORMAT_ATTRIBUTE - #define FORMAT_ATTRIBUTE(archetype, string_index, first_to_check) __attribute__ ((format (archetype, string_index, first_to_check))) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif // end of header - diff --git a/bms/bms/bms_config_e18a/src/ic_bms/BQ769x2Header.h b/bms/bms/bms_config_e18a/src/ic_bms/BQ769x2Header.h deleted file mode 100644 index fe82dbf3..00000000 --- a/bms/bms/bms_config_e18a/src/ic_bms/BQ769x2Header.h +++ /dev/null @@ -1,409 +0,0 @@ -//BQ769x2 General Program Header File - -//Data Memory registers Name in TRM -#define Cell1Gain 0x9180 //Calibration:Voltage:Cell 1 Gain -#define Cell2Gain 0x9182 //Calibration:Voltage:Cell 2 Gain -#define Cell3Gain 0x9184 //Calibration:Voltage:Cell 3 Gain -#define Cell4Gain 0x9186 //Calibration:Voltage:Cell 4 Gain -#define Cell5Gain 0x9188 //Calibration:Voltage:Cell 5 Gain -#define Cell6Gain 0x918A //Calibration:Voltage:Cell 6 Gain -#define Cell7Gain 0x918C //Calibration:Voltage:Cell 7 Gain -#define Cell8Gain 0x918E //Calibration:Voltage:Cell 8 Gain -#define Cell9Gain 0x9190 //Calibration:Voltage:Cell 9 Gain -#define Cell10Gain 0x9192 //Calibration:Voltage:Cell 10 Gain -#define Cell11Gain 0x9194 //Calibration:Voltage:Cell 11 Gain -#define Cell12Gain 0x9196 //Calibration:Voltage:Cell 12 Gain -#define Cell13Gain 0x9198 //Calibration:Voltage:Cell 13 Gain -#define Cell14Gain 0x919A //Calibration:Voltage:Cell 14 Gain -#define Cell15Gain 0x919C //Calibration:Voltage:Cell 15 Gain -#define Cell16Gain 0x919E //Calibration:Voltage:Cell 16 Gain -#define PackGain 0x91A0 //Calibration:Voltage:Pack Gain -#define TOSGain 0x91A2 //Calibration:Voltage:TOS Gain -#define LDGain 0x91A4 //Calibration:Voltage:LD Gain -#define ADCGain 0x91A6 //Calibration:Voltage:ADC Gain -#define CCGain 0x91A8 //Calibration:Current:CC Gain -#define CapacityGain 0x91AC //Calibration:Current:Capacity Gain -#define VcellOffset 0x91B0 //Calibration:Vcell Offset:Vcell Offset -#define VdivOffset 0x91B2 //Calibration:V Divider Offset:Vdiv Offset -#define CoulombCounterOffsetSamples 0x91C6 //Calibration:Current Offset:Coulomb Counter Offset Samples -#define BoardOffset 0x91C8 //Calibration:Current Offset:Board Offset -#define InternalTempOffset 0x91CA //Calibration:Temperature:Internal Temp Offset -#define CFETOFFTempOffset 0x91CB //Calibration:Temperature:CFETOFF Temp Offset -#define DFETOFFTempOffset 0x91CC //Calibration:Temperature:DFETOFF Temp Offset -#define ALERTTempOffset 0x91CD //Calibration:Temperature:ALERT Temp Offset -#define TS1TempOffset 0x91CE //Calibration:Temperature:TS1 Temp Offset -#define TS2TempOffset 0x91CF //Calibration:Temperature:TS2 Temp Offset -#define TS3TempOffset 0x91D0 //Calibration:Temperature:TS3 Temp Offset -#define HDQTempOffset 0x91D1 //Calibration:Temperature:HDQ Temp Offset -#define DCHGTempOffset 0x91D2 //Calibration:Temperature:DCHG Temp Offset -#define DDSGTempOffset 0x91D3 //Calibration:Temperature:DDSG Temp Offset -#define IntGain 0x91E2 //Calibration:Internal Temp Model:Int Gain -#define Intbaseoffset 0x91E4 //Calibration:Internal Temp Model:Int base offset -#define IntMaximumAD 0x91E6 //Calibration:Internal Temp Model:Int Maximum AD -#define IntMaximumTemp 0x91E8 //Calibration:Internal Temp Model:Int Maximum Temp -#define T18kCoeffa1 0x91EA //Calibration:18K Temperature Model:Coeff a1 -#define T18kCoeffa2 0x91EC //Calibration:18K Temperature Model:Coeff a2 -#define T18kCoeffa3 0x91EE //Calibration:18K Temperature Model:Coeff a3 -#define T18kCoeffa4 0x91F0 //Calibration:18K Temperature Model:Coeff a4 -#define T18kCoeffa5 0x91F2 //Calibration:18K Temperature Model:Coeff a5 -#define T18kCoeffb1 0x91F4 //Calibration:18K Temperature Model:Coeff b1 -#define T18kCoeffb2 0x91F6 //Calibration:18K Temperature Model:Coeff b2 -#define T18kCoeffb3 0x91F8 //Calibration:18K Temperature Model:Coeff b3 -#define T18kCoeffb4 0x91FA //Calibration:18K Temperature Model:Coeff b4 -#define T18kAdc0 0x91FE //Calibration:18K Temperature Model:Adc0 -#define T180kCoeffa1 0x9200 //Calibration:180K Temperature Model:Coeff a1 -#define T180kCoeffa2 0x9202 //Calibration:180K Temperature Model:Coeff a2 -#define T180kCoeffa3 0x9204 //Calibration:180K Temperature Model:Coeff a3 -#define T180kCoeffa4 0x9206 //Calibration:180K Temperature Model:Coeff a4 -#define T180kCoeffa5 0x9208 //Calibration:180K Temperature Model:Coeff a5 -#define T180kCoeffb1 0x920A //Calibration:180K Temperature Model:Coeff b1 -#define T180kCoeffb2 0x920C //Calibration:180K Temperature Model:Coeff b2 -#define T180kCoeffb3 0x920E //Calibration:180K Temperature Model:Coeff b3 -#define T180kCoeffb4 0x9210 //Calibration:180K Temperature Model:Coeff b4 -#define T180kAdc0 0x9214 //Calibration:180K Temperature Model:Adc0 -#define CustomCoeffa1 0x9216 //Calibration:Custom Temperature Model:Coeff a1 -#define CustomCoeffa2 0x9218 //Calibration:Custom Temperature Model:Coeff a2 -#define CustomCoeffa3 0x921A //Calibration:Custom Temperature Model:Coeff a3 -#define CustomCoeffa4 0x921C //Calibration:Custom Temperature Model:Coeff a4 -#define CustomCoeffa5 0x921E //Calibration:Custom Temperature Model:Coeff a5 -#define CustomCoeffb1 0x9220 //Calibration:Custom Temperature Model:Coeff b1 -#define CustomCoeffb2 0x9222 //Calibration:Custom Temperature Model:Coeff b2 -#define CustomCoeffb3 0x9224 //Calibration:Custom Temperature Model:Coeff b3 -#define CustomCoeffb4 0x9226 //Calibration:Custom Temperature Model:Coeff b4 -#define CustomRc0 0x9228 //Calibration:Custom Temperature Model:Rc0 -#define CustomAdc0 0x922A //Calibration:Custom Temperature Model:Adc0 -#define CoulombCounterDeadband 0x922D //Calibration:Current Deadband:Coulomb Counter Deadband -#define CUVThresholdOverride 0x91D4 //Calibration:CUV:CUV Threshold Override -#define COVThresholdOverride 0x91D6 //Calibration:COV:COV Threshold Override -#define MinBlowFuseVoltage 0x9231 //Settings:Fuse:Min Blow Fuse Voltage -#define FuseBlowTimeout 0x9233 //Settings:Fuse:Fuse Blow Timeout -#define PowerConfig 0x9234 //Settings:Configuration:Power Config -#define REG12Config 0x9236 //Settings:Configuration:REG12 Config -#define REG0Config 0x9237 //Settings:Configuration:REG0 Config -#define HWDRegulatorOptions 0x9238 //Settings:Configuration:HWD Regulator Options -#define CommType 0x9239 //Settings:Configuration:Comm Type -#define I2CAddress 0x923A //Settings:Configuration:I2C Address -#define SPIConfiguration 0x923C //Settings:Configuration:SPI Configuration -#define CommIdleTime 0x923D //Settings:Configuration:Comm Idle Time -#define CFETOFFPinConfig 0x92FA //Settings:Configuration:CFETOFF Pin Config -#define DFETOFFPinConfig 0x92FB //Settings:Configuration:DFETOFF Pin Config -#define ALERTPinConfig 0x92FC //Settings:Configuration:ALERT Pin Config -#define TS1Config 0x92FD //Settings:Configuration:TS1 Config -#define TS2Config 0x92FE //Settings:Configuration:TS2 Config -#define TS3Config 0x92FF //Settings:Configuration:TS3 Config -#define HDQPinConfig 0x9300 //Settings:Configuration:HDQ Pin Config -#define DCHGPinConfig 0x9301 //Settings:Configuration:DCHG Pin Config -#define DDSGPinConfig 0x9302 //Settings:Configuration:DDSG Pin Config -#define DAConfiguration 0x9303 //Settings:Configuration:DA Configuration -#define VCellMode 0x9304 //Settings:Configuration:Vcell Mode -#define CC3Samples 0x9307 //Settings:Configuration:CC3 Samples -#define ProtectionConfiguration 0x925F //Settings:Protection:Protection Configuration -#define EnabledProtectionsA 0x9261 //Settings:Protection:Enabled Protections A -#define EnabledProtectionsB 0x9262 //Settings:Protection:Enabled Protections B -#define EnabledProtectionsC 0x9263 //Settings:Protection:Enabled Protections C -#define CHGFETProtectionsA 0x9265 //Settings:Protection:CHG FET Protections A -#define CHGFETProtectionsB 0x9266 //Settings:Protection:CHG FET Protections B -#define CHGFETProtectionsC 0x9267 //Settings:Protection:CHG FET Protections C -#define DSGFETProtectionsA 0x9269 //Settings:Protection:DSG FET Protections A -#define DSGFETProtectionsB 0x926A //Settings:Protection:DSG FET Protections B -#define DSGFETProtectionsC 0x926B //Settings:Protection:DSG FET Protections C -#define BodyDiodeThreshold 0x9273 //Settings:Protection:Body Diode Threshold -#define DefaultAlarmMask 0x926D //Settings:Alarm:Default Alarm Mask -#define SFAlertMaskA 0x926F //Settings:Alarm:SF Alert Mask A -#define SFAlertMaskB 0x9270 //Settings:Alarm:SF Alert Mask B -#define SFAlertMaskC 0x9271 //Settings:Alarm:SF Alert Mask C -#define PFAlertMaskA 0x92C4 //Settings:Alarm:PF Alert Mask A -#define PFAlertMaskB 0x92C5 //Settings:Alarm:PF Alert Mask B -#define PFAlertMaskC 0x92C6 //Settings:Alarm:PF Alert Mask C -#define PFAlertMaskD 0x92C7 //Settings:Alarm:PF Alert Mask D -#define EnabledPFA 0x92C0 //Settings:Permanent Failure:Enabled PF A -#define EnabledPFB 0x92C1 //Settings:Permanent Failure:Enabled PF B -#define EnabledPFC 0x92C2 //Settings:Permanent Failure:Enabled PF C -#define EnabledPFD 0x92C3 //Settings:Permanent Failure:Enabled PF D -#define FETOptions 0x9308 //Settings:FET:FET Options -#define ChgPumpControl 0x9309 //Settings:FET:Chg Pump Control -#define PrechargeStartVoltage 0x930A //Settings:FET:Precharge Start Voltage -#define PrechargeStopVoltage 0x930C //Settings:FET:Precharge Stop Voltage -#define PredischargeTimeout 0x930E //Settings:FET:Predischarge Timeout -#define PredischargeStopDelta 0x930F //Settings:FET:Predischarge Stop Delta -#define DsgCurrentThreshold 0x9310 //Settings:Current Thresholds:Dsg Current Threshold -#define ChgCurrentThreshold 0x9312 //Settings:Current Thresholds:Chg Current Threshold -#define CheckTime 0x9314 //Settings:Cell Open-Wire:Check Time -#define Cell1Interconnect 0x9315 //Settings:Interconnect Resistances:Cell 1 Interconnect -#define Cell2Interconnect 0x9317 //Settings:Interconnect Resistances:Cell 2 Interconnect -#define Cell3Interconnect 0x9319 //Settings:Interconnect Resistances:Cell 3 Interconnect -#define Cell4Interconnect 0x931B //Settings:Interconnect Resistances:Cell 4 Interconnect -#define Cell5Interconnect 0x931D //Settings:Interconnect Resistances:Cell 5 Interconnect -#define Cell6Interconnect 0x931F //Settings:Interconnect Resistances:Cell 6 Interconnect -#define Cell7Interconnect 0x9321 //Settings:Interconnect Resistances:Cell 7 Interconnect -#define Cell8Interconnect 0x9323 //Settings:Interconnect Resistances:Cell 8 Interconnect -#define Cell9Interconnect 0x9325 //Settings:Interconnect Resistances:Cell 9 Interconnect -#define Cell10Interconnect 0x9327 //Settings:Interconnect Resistances:Cell 10 Interconnect -#define Cell11Interconnect 0x9329 //Settings:Interconnect Resistances:Cell 11 Interconnect -#define Cell12Interconnect 0x932B //Settings:Interconnect Resistances:Cell 12 Interconnect -#define Cell13Interconnect 0x932D //Settings:Interconnect Resistances:Cell 13 Interconnect -#define Cell14Interconnect 0x932F //Settings:Interconnect Resistances:Cell 14 Interconnect -#define Cell15Interconnect 0x9331 //Settings:Interconnect Resistances:Cell 15 Interconnect -#define Cell16Interconnect 0x9333 //Settings:Interconnect Resistances:Cell 16 Interconnect -#define MfgStatusInit 0x9343 //Settings:Manufacturing:Mfg Status Init -#define BalancingConfiguration 0x9335 //Settings:Cell Balancing Config:Balancing Configuration -#define MinCellTemp 0x9336 //Settings:Cell Balancing Config:Min Cell Temp -#define MaxCellTemp 0x9337 //Settings:Cell Balancing Config:Max Cell Temp -#define MaxInternalTemp 0x9338 //Settings:Cell Balancing Config:Max Internal Temp -#define CellBalanceInterval 0x9339 //Settings:Cell Balancing Config:Cell Balance Interval -#define CellBalanceMaxCells 0x933A //Settings:Cell Balancing Config:Cell Balance Max Cells -#define CellBalanceMinCellVCharge 0x933B //Settings:Cell Balancing Config:Cell Balance Min Cell V (Charge) -#define CellBalanceMinDeltaCharge 0x933D //Settings:Cell Balancing Config:Cell Balance Min Delta (Charge) -#define CellBalanceStopDeltaCharge 0x933E //Settings:Cell Balancing Config:Cell Balance Stop Delta (Charge) -#define CellBalanceMinCellVRelax 0x933F //Settings:Cell Balancing Config:Cell Balance Min Cell V (Relax) -#define CellBalanceMinDeltaRelax 0x9341 //Settings:Cell Balancing Config:Cell Balance Min Delta (Relax) -#define CellBalanceStopDeltaRelax 0x9342 //Settings:Cell Balancing Config:Cell Balance Stop Delta (Relax) -#define ShutdownCellVoltage 0x923F //Power:Shutdown:Shutdown Cell Voltage -#define ShutdownStackVoltage 0x9241 //Power:Shutdown:Shutdown Stack Voltage -#define LowVShutdownDelay 0x9243 //Power:Shutdown:Low V Shutdown Delay -#define ShutdownTemperature 0x9244 //Power:Shutdown:Shutdown Temperature -#define ShutdownTemperatureDelay 0x9245 //Power:Shutdown:Shutdown Temperature Delay -#define FETOffDelay 0x9252 //Power:Shutdown:FET Off Delay -#define ShutdownCommandDelay 0x9253 //Power:Shutdown:Shutdown Command Delay -#define AutoShutdownTime 0x9254 //Power:Shutdown:Auto Shutdown Time -#define RAMFailShutdownTime 0x9255 //Power:Shutdown:RAM Fail Shutdown Time -#define SleepCurrent 0x9248 //Power:Sleep:Sleep Current -#define VoltageTime 0x924A //Power:Sleep:Voltage Time -#define WakeComparatorCurrent 0x924B //Power:Sleep:Wake Comparator Current -#define SleepHysteresisTime 0x924D //Power:Sleep:Sleep Hysteresis Time -#define SleepChargerVoltageThreshold 0x924E //Power:Sleep:Sleep Charger Voltage Threshold -#define SleepChargerPACKTOSDelta 0x9250 //Power:Sleep:Sleep Charger PACK-TOS Delta -#define ConfigRAMSignature 0x91E0 //System Data:Integrity:Config RAM Signature -#define CUVThreshold 0x9275 //Protections:CUV:Threshold -#define CUVDelay 0x9276 //Protections:CUV:Delay -#define CUVRecoveryHysteresis 0x927B //Protections:CUV:Recovery Hysteresis -#define COVThreshold 0x9278 //Protections:COV:Threshold -#define COVDelay 0x9279 //Protections:COV:Delay -#define COVRecoveryHysteresis 0x927C //Protections:COV:Recovery Hysteresis -#define COVLLatchLimit 0x927D //Protections:COVL:Latch Limit -#define COVLCounterDecDelay 0x927E //Protections:COVL:Counter Dec Delay -#define COVLRecoveryTime 0x927F //Protections:COVL:Recovery Time -#define OCCThreshold 0x9280 //Protections:OCC:Threshold -#define OCCDelay 0x9281 //Protections:OCC:Delay -#define OCCRecoveryThreshold 0x9288 //Protections:OCC:Recovery Threshold -#define OCCPACKTOSDelta 0x92B0 //Protections:OCC:PACK-TOS Delta -#define OCD1Threshold 0x9282 //Protections:OCD1:Threshold -#define OCD1Delay 0x9283 //Protections:OCD1:Delay -#define OCD2Threshold 0x9284 //Protections:OCD2:Threshold -#define OCD2Delay 0x9285 //Protections:OCD2:Delay -#define SCDThreshold 0x9286 //Protections:SCD:Threshold -#define SCDDelay 0x9287 //Protections:SCD:Delay -#define SCDRecoveryTime 0x9294 //Protections:SCD:Recovery Time -#define OCD3Threshold 0x928A //Protections:OCD3:Threshold -#define OCD3Delay 0x928C //Protections:OCD3:Delay -#define OCDRecoveryThreshold 0x928D //Protections:OCD:Recovery Threshold -#define OCDLLatchLimit 0x928F //Protections:OCDL:Latch Limit -#define OCDLCounterDecDelay 0x9290 //Protections:OCDL:Counter Dec Delay -#define OCDLRecoveryTime 0x9291 //Protections:OCDL:Recovery Time -#define OCDLRecoveryThreshold 0x9292 //Protections:OCDL:Recovery Threshold -#define SCDLLatchLimit 0x9295 //Protections:SCDL:Latch Limit -#define SCDLCounterDecDelay 0x9296 //Protections:SCDL:Counter Dec Delay -#define SCDLRecoveryTime 0x9297 //Protections:SCDL:Recovery Time -#define SCDLRecoveryThreshold 0x9298 //Protections:SCDL:Recovery Threshold -#define OTCThreshold 0x929A //Protections:OTC:Threshold -#define OTCDelay 0x920B //Protections:OTC:Delay -#define OTCRecovery 0x929C //Protections:OTC:Recovery -#define OTDThreshold 0x929D //Protections:OTD:Threshold -#define OTDDelay 0x929E //Protections:OTD:Delay -#define OTDRecovery 0x929F //Protections:OTD:Recovery -#define OTFThreshold 0x92A0 //Protections:OTF:Threshold -#define OTFDelay 0x92A1 //Protections:OTF:Delay -#define OTFRecovery 0x92A2 //Protections:OTF:Recovery -#define OTINTThreshold 0x92A3 //Protections:OTINT:Threshold -#define OTINTDelay 0x92A4 //Protections:OTINT:Delay -#define OTINTRecovery 0x92A5 //Protections:OTINT:Recovery -#define UTCThreshold 0x92A6 //Protections:UTC:Threshold -#define UTCDelay 0x92A7 //Protections:UTC:Delay -#define UTCRecovery 0x92A8 //Protections:UTC:Recovery -#define UTDThreshold 0x92A9 //Protections:UTD:Threshold -#define UTDDelay 0x92AA //Protections:UTD:Delay -#define UTDRecovery 0x92AB //Protections:UTD:Recovery -#define UTINTThreshold 0x92AC //Protections:UTINT:Threshold -#define UTINTDelay 0x92AD //Protections:UTINT:Delay -#define UTINTRecovery 0x92AE //Protections:UTINT:Recovery -#define ProtectionsRecoveryTime 0x92AF //Protections:Recovery:Time -#define HWDDelay 0x92B2 //Protections:HWD:Delay -#define LoadDetectActiveTime 0x92B4 //Protections:Load Detect:Active Time -#define LoadDetectRetryDelay 0x92B5 //Protections:Load Detect:Retry Delay -#define LoadDetectTimeout 0x92B6 //Protections:Load Detect:Timeout -#define PTOChargeThreshold 0x92BA //Protections:PTO:Charge Threshold -#define PTODelay 0x92BC //Protections:PTO:Delay -#define PTOReset 0x92BE //Protections:PTO:Reset -#define CUDEPThreshold 0x92C8 //Permanent Fail:CUDEP:Threshold -#define CUDEPDelay 0x92CA //Permanent Fail:CUDEP:Delay -#define SUVThreshold 0x92CB //Permanent Fail:SUV:Threshold -#define SUVDelay 0x92CD //Permanent Fail:SUV:Delay -#define SOVThreshold 0x92CE //Permanent Fail:SOV:Threshold -#define SOVDelay 0x92D0 //Permanent Fail:SOV:Delay -#define TOSSThreshold 0x92D1 //Permanent Fail:TOS:Threshold -#define TOSSDelay 0x92D3 //Permanent Fail:TOS:Delay -#define SOCCThreshold 0x92D4 //Permanent Fail:SOCC:Threshold -#define SOCCDelay 0x92D6 //Permanent Fail:SOCC:Delay -#define SOCDThreshold 0x92D7 //Permanent Fail:SOCD:Threshold -#define SOCDDelay 0x92D9 //Permanent Fail:SOCD:Delay -#define SOTThreshold 0x92DA //Permanent Fail:SOT:Threshold -#define SOTDelay 0x92DB //Permanent Fail:SOT:Delay -#define SOTFThreshold 0x92DC //Permanent Fail:SOTF:Threshold -#define SOTFDelay 0x92DD //Permanent Fail:SOTF:Delay -#define VIMRCheckVoltage 0x92DE //Permanent Fail:VIMR:Check Voltage -#define VIMRMaxRelaxCurrent 0x92E0 //Permanent Fail:VIMR:Max Relax Current -#define VIMRThreshold 0x92E2 //Permanent Fail:VIMR:Threshold -#define VIMRDelay 0x92E4 //Permanent Fail:VIMR:Delay -#define VIMRRelaxMinDuration 0x92E5 //Permanent Fail:VIMR:Relax Min Duration -#define VIMACheckVoltage 0x92E7 //Permanent Fail:VIMA:Check Voltage -#define VIMAMinActiveCurrent 0x92E9 //Permanent Fail:VIMA:Min Active Current -#define VIMAThreshold 0x92EB //Permanent Fail:VIMA:Threshold -#define VIMADelay 0x92ED //Permanent Fail:VIMA:Delay -#define CFETFOFFThreshold 0x92EE //Permanent Fail:CFETF:OFF Threshold -#define CFETFOFFDelay 0x92F0 //Permanent Fail:CFETF:OFF Delay -#define DFETFOFFThreshold 0x92F1 //Permanent Fail:DFETF:OFF Threshold -#define DFETFOFFDelay 0x92F3 //Permanent Fail:DFETF:OFF Delay -#define VSSFFailThreshold 0x92F4 //Permanent Fail:VSSF:Fail Threshold -#define VSSFDelay 0x92F6 //Permanent Fail:VSSF:Delay -#define PF2LVLDelay 0x92F7 //Permanent Fail:2LVL:Delay -#define LFOFDelay 0x92F8 //Permanent Fail:LFOF:Delay -#define HWMXDelay 0x92F9 //Permanent Fail:HWMX:Delay -#define SecuritySettings 0x9256 //Security:Settings:Security Settings -#define UnsealKeyStep1 0x9257 //Security:Keys:Unseal Key Step 1 -#define UnsealKeyStep2 0x9259 //Security:Keys:Unseal Key Step 2 -#define FullAccessKeyStep1 0x925B //Security:Keys:Full Access Key Step 1 -#define FullAccessKeyStep2 0x925D //Security:Keys:Full Access Key Step 2 - -//Direct Commands -#define ControlStatus 0x00 -#define SafetyAlertA 0x02 -#define SafetyStatusA 0x03 -#define SafetyAlertB 0x04 -#define SafetyStatusB 0x05 -#define SafetyAlertC 0x06 -#define SafetyStatusC 0x07 -#define PFAlertA 0x0A -#define PFStatusA 0x0B -#define PFAlertB 0x0C -#define PFStatusB 0x0D -#define PFAlertC 0x0E -#define PFStatusC 0x0F -#define PFAlertD 0x10 -#define PFStatusD 0x11 -#define BatteryStatus 0x12 -#define Cell1Voltage 0x14 -#define Cell2Voltage 0x16 -#define Cell3Voltage 0x18 -#define Cell4Voltage 0x1A -#define Cell5Voltage 0x1C -#define Cell6Voltage 0x1E -#define Cell7Voltage 0x20 -#define Cell8Voltage 0x22 -#define Cell9Voltage 0x24 -#define Cell10Voltage 0x26 -#define Cell11Voltage 0x28 -#define Cell12Voltage 0x2A -#define Cell13Voltage 0x2C -#define Cell14Voltage 0x2E -#define Cell15Voltage 0x30 -#define Cell16Voltage 0x32 -#define StackVoltage 0x34 -#define PACKPinVoltage 0x36 -#define LDPinVoltage 0x38 -#define CC2Current 0x3A -#define AlarmStatus 0x62 -#define AlarmRawStatus 0x64 -#define AlarmEnable 0x66 -#define IntTemperature 0x68 -#define CFETOFFTemperature 0x6A -#define DFETOFFTemperature 0x6C -#define ALERTTemperature 0x6E -#define TS1Temperature 0x70 -#define TS2Temperature 0x72 -#define TS3Temperature 0x74 -#define HDQTemperature 0x76 -#define DCHGTemperature 0x78 -#define DDSGTemperature 0x7A -#define FETStatus 0x7F - -//Subcommands -#define DEVICE_NUMBER 0x0001 -#define FW_VERSION 0x0002 -#define HW_VERSION 0x0003 -#define IROM_SIG 0x0004 -#define STATIC_CFG_SIG 0x0005 -#define PREV_MACWRITE 0x0007 -#define DROM_SIG 0x0009 -#define SECURITY_KEYS 0x0035 -#define SAVED_PF_STATUS 0x0053 -#define MANUFACTURINGSTATUS 0x0057 -#define MANU_DATA 0x0070 -#define DASTATUS1 0x0071 -#define DASTATUS2 0x0072 -#define DASTATUS3 0x0073 -#define DASTATUS4 0x0074 -#define DASTATUS5 0x0075 -#define DASTATUS6 0x0076 -#define DASTATUS7 0x0077 -#define CUV_SNAPSHOT 0x0080 -#define COV_SNAPSHOT 0X0081 -#define CB_ACTIVE_CELLS 0x0083 -#define CB_SET_LVL 0x0084 -#define CBSTATUS1 0x0085 -#define CBSTATUS2 0x0086 -#define CBSTATUS3 0x0087 -#define FET_CONTROL 0x0097 -#define REG12_CONTROL 0x0098 -#define OTP_WR_CHECK 0x00A0 -#define OTP_WRITE 0x00A1 -#define READ_CAL1 0xF081 -#define CAL_CUV 0xF090 -#define CAL_COV 0xF091 - -// Command Only Subcommands -#define EXIT_DEEPSLEEP 0x000E -#define DEEPSLEEP 0x000F -#define SHUTDOWN 0x0010 -#define BQ769x2_RESET 0x0012 //"RESET" in documentation -#define PDSGTEST 0x001C -#define FUSE_TOGGLE 0x001D -#define PCHGTEST 0x001E -#define CHGTEST 0x001F -#define DSGTEST 0x0020 -#define FET_ENABLE 0x0022 -#define PF_ENABLE 0x0024 -#define PF_RESET 0x0029 -#define SEAL 0x0030 -#define RESET_PASSQ 0x0082 -#define PTO_RECOVER 0x008A -#define SET_CFGUPDATE 0x0090 -#define EXIT_CFGUPDATE 0x0092 -#define DSG_PDSG_OFF 0x0093 -#define CHG_PCHG_OFF 0x0094 -#define ALL_FETS_OFF 0x0095 -#define ALL_FETS_ON 0x0096 -#define SLEEP_ENABLE 0x0099 -#define SLEEP_DISABLE 0x009A -#define OCDL_RECOVER 0x009B -#define SCDL_RECOVER 0x009C -#define LOAD_DETECT_RESTART 0x009D -#define LOAD_DETECT_ON 0x009E -#define LOAD_DETECT_OFF 0x009F -#define CFETOFF_LO 0x2800 -#define DFETOFF_LO 0x2801 -#define ALERT_LO 0x2802 -#define HDQ_LO 0x2806 -#define DCHG_LO 0x2807 -#define DDSG_LO 0x2808 -#define CFETOFF_HI 0x2810 -#define DFETOFF_HI 0x2811 -#define ALERT_HI 0x2812 -#define HDQ_HI 0x2816 -#define DCHG_HI 0x2817 -#define DDSG_HI 0x2818 -#define PF_FORCE_A 0x2857 -#define PF_FORCE_B 0x29A3 -#define SWAP_COMM_MODE 0x29BC -#define SWAP_TO_I2C 0x29E7 -#define SWAP_TO_SPI 0x7C35 -#define SWAP_TO_HDQ 0x7C40 diff --git a/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.c b/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.c deleted file mode 100644 index 05e886a8..00000000 --- a/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.c +++ /dev/null @@ -1,460 +0,0 @@ -#include -#include -#include -#include -#include "peripheral/sercom/spi_master/plib_sercom_spi_master_common.h" -#include "peripheral/sercom/spi_master/plib_sercom0_spi_master.h" -#include "definitions.h" -#include "bms_spi.h" - - - - -static inline void bq_cs_low(void) { PORT_REGS->GROUP[bq_cs_group].PORT_OUTCLR = bq_cs_mask; } -static inline void bq_cs_high(void) { PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; } - -static inline void _delay(uint32_t cycles){ - - for (volatile uint32_t i=0; iGROUP[bq_cs_group].PORT_DIRSET = bq_cs_mask; - PORT_REGS->GROUP[bq_cs_group].PORT_OUTSET = bq_cs_mask; // Set HIGH (inactive) - - // --- IC configuration sequence --- - bq_command_only(ENTER_CONFIG_UPDATE); - bms_set_protection_threshold(); - bq_command_only(EXIT_CONFIG_UPDATE); - - // Status check - uint8_t status = 0; - if (bq_direct_read(0x12, &status, 1)) - printf("BQ76942 communication OK\n"); - else - printf("BQ76942 communication failed\n"); -} - - -bool Spi_TransferBytes(uint8_t *tx, uint8_t *rx, uint8_t length) -{ - if (SERCOM0_SPI_IsBusy()) - return false; - - bq_cs_low(); - bool ok = SERCOM0_SPI_WriteRead(tx, length, rx, length); - if (ok) - { - ok = bq_spi_wait_idle(); - } - bq_cs_high(); - - return ok; -} - -static uint8_t bq_crc8_calc(const uint8_t *data, uint8_t len) -{ - uint8_t crc = 0x00; // init - - for (uint8_t i = 0; i < len; i++) { - - crc ^= data[i]; // XOR in next byte - for (uint8_t b = 0; b < 8; b++) { - if (crc & 0x80) // test MSB - crc = (uint8_t)((crc << 1) ^ 0x07); - else - crc <<= 1; - } - } - return crc; -} - - -bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length) -{ - - - if (SERCOM0_SPI_IsBusy()) - return false; - if (length == 0) - return true; - - // Pack back-to-back 24-bit frames: [cmd, data_byte, crc] * length - uint8_t tx_bytes[3 * length]; - - for (uint8_t i=0;i> 8) & 0xFF; // MSB - ok = bq_direct_write(command, buf, 2); - } - else if (type == 'R') // Read - { - ok = bq_direct_read(command, buf, 2); - if (ok) - *data = (uint16_t)(buf[0] | (buf[1] << 8)); // Little endian - } - - - return ok; -} - - -bool bq_command_only(uint16_t subcmd){ - - - // Send 0x3E/0x3F in one SPI frame - uint8_t two[2] = { - (uint8_t)(subcmd & 0xFF), - (uint8_t)((subcmd >> 8) & 0xFF) - }; - if (!write_reg(0x3E, two, 2)) - return false; - - return true; -} - -/* - example of BQ_commandOnly usage: - - Reset the BQ76942 - BQ_CommandOnly(RESET); -*/ - - -bool bq_read_sub_command(uint16_t subcmd, uint8_t *data, uint8_t length) -{ - if (length > 32) - length = 32; - - // Write subcommand (0x3E LSB, 0x3F MSB) in one frame - uint8_t sub[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) }; - if (!write_reg(0x3E, sub, 2)) - return false; - - // Poll for echo of 0x3E/0x3F (in as few frames as possible) - uint8_t echo[2] = {0xFF, 0xFF}; - uint32_t tries = 0; - do { - if (!read_reg(0x3E, echo, 2)) - return false; - if (++tries > BQ_SUBCMD_MAX_POLLS) - return false; - } while ((echo[0] == 0xFF && echo[1] == 0xFF) || echo[0] != sub[0] || echo[1] != sub[1]); - - // Read full buffer 0x40..0x61 (34 bytes) in one frame - uint8_t buf[34]; - if (!read_reg(0x40, buf, sizeof(buf))) - return false; - - uint8_t len_total = buf[0x61 - 0x40]; - if (len_total < 4) // must include 0x3E,0x3F,0x60,0x61 => 4 minimum - return false; - - uint8_t buf_len = (uint8_t)(len_total - 4); - if (buf_len > 32) - buf_len = 32; - - // Copy out payload (0x40.. as the buffer start) - uint8_t to_copy = (length < buf_len) ? length : buf_len; - memcpy(data, buf, to_copy); - - // Verify checksum - uint8_t sum = (uint8_t)(sub[0] + sub[1]); - for (uint8_t i = 0; i < buf_len; i++) - sum = (uint8_t)(sum + buf[i]); - - uint8_t ck_calc = (uint8_t)(0xFF - (sum & 0xFF)); - uint8_t ck_read = buf[0x60 - 0x40]; - - return (ck_read == ck_calc); -} - -bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length) -{ - if (length > 32) - return false; - - // Subcommand in one frame - uint8_t sub[2] = { (uint8_t)(subcmd & 0xFF), (uint8_t)((subcmd >> 8) & 0xFF) }; - if (!write_reg(0x3E, sub, 2)) - return false; - - // Write payload 0x40.. in one frame - if (length > 0 && !write_reg(0x40, data, length)) - return false; - - // Write checksum+length (0x60, 0x61) in one frame - uint8_t sum = (uint8_t)(sub[0] + sub[1]); - for (uint8_t i = 0; i < length; i++) - sum = (uint8_t)(sum + data[i]); - - //verify checksum - uint8_t tail[2]; - tail[0] = (uint8_t)(0xFF - (sum & 0xFF)); - tail[1] = (uint8_t)(4 + length); - if (!write_reg(0x60, tail, 2)) - return false; - - return true; -} - - - -void bms_set_protection_threshold(void) -{ - - bq_command_only(ENTER_CONFIG_UPDATE); - - - uint8_t cov_val = (uint8_t)(COV_THRESHOLD_MV / 50.6f + 0.5f); - if (cov_val < 20) cov_val = 20; - if (cov_val > 110) cov_val = 110; - bq_write_subcommand(COV_THRESHOLD_ADDR, &cov_val, 1); - - uint16_t cov_delay_ticks = (uint16_t)(COV_DELAY_MS / 3.3f + 0.5f); - uint8_t cov_delay_bytes[2] = { - (uint8_t)(cov_delay_ticks & 0xFF), - (uint8_t)((cov_delay_ticks >> 8) & 0xFF) - }; - bq_write_subcommand(COV_DELAY_ADDR, cov_delay_bytes, 2); - - - uint8_t cuv_val = (uint8_t)(CUV_THRESHOLD_MV / 50.6f + 0.5f); - if (cuv_val < 20) cuv_val = 20; - if (cuv_val > 110) cuv_val = 110; - bq_write_subcommand(CUV_THRESHOLD_ADDR, &cuv_val, 1); - - uint16_t cuv_delay_ticks = (uint16_t)(CUV_DELAY_MS / 3.3f + 0.5f); - uint8_t cuv_delay_bytes[2] = { - (uint8_t)(cuv_delay_ticks & 0xFF), - (uint8_t)((cuv_delay_ticks >> 8) & 0xFF) - }; - bq_write_subcommand(CUV_DELAY_ADDR, cuv_delay_bytes, 2); - - - bq_command_only(EXIT_CONFIG_UPDATE); -} - - -void bms_battery_status(void){ - - uint8_t fetReg=0; - - if(!bq_direct_read(FET_STATUS, &fetReg, 1)){ - printf("Failed to read FET status\n"); - return; - } - - bool chg_on = (fetReg & (1 << 0)); // CHG_FET bit - bool pchg_on = (fetReg & (1 << 1)); // PCHG_FET bit - bool dsg_on = (fetReg & (1 << 2)); // DSG_FET bit - - - if (pchg_on) - printf("Battery in precharge mode\n"); //maybe not printf - else if (chg_on && !dsg_on) - printf("Battery is charging\n"); - else if (dsg_on && !chg_on) - printf("Battery is discharging\n"); - else if (!chg_on && !dsg_on) - printf("Battery is idle\n"); - else - printf("Both CHG_FET and DSG_FET ACTIVE (transition)\n"); - - - -} - - -bool read_cells_1to6(uint16_t cell_mV[6]) -{ - const uint8_t addr[6] = { - CELL_1_VOLTAGE, CELL_2_VOLTAGE, CELL_3_VOLTAGE, - CELL_4_VOLTAGE, CELL_5_VOLTAGE, CELL_6_VOLTAGE - }; - uint16_t raw = 0; - uint8_t i; - bool ok = true; - - if (cell_mV == NULL) - return false; - - for (i = 0; i < 6; i++) - { - if (bq_direct_command(addr[i], &raw, R)) - { - cell_mV[i] = raw; // mV - } - else - { - cell_mV[i] = 0; - ok = false; - } - } - return ok; -} - - - -bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC) -{ - uint16_t raw; - - if (temp_dC == 0) - return false; - - if (!bq_direct_command(ts_cmd, &raw, 'R')) - return false; - - *temp_dC = (int16_t)raw - 2731; // raw is signed 0.1 K -> 0.1 C - - return true; - } - -bool bms_read_current(int16_t *current_mA) -{ - uint16_t raw; - - if (current_mA == 0) - return false; - if (!bq_direct_command(CC2_CURRENT, &raw, 'R')) - return false; - - *current_mA = (int16_t)raw; - return true; - - -} - -void bothoff_init(void) -{ - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[PIN_BOTHOFF] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); // GPIO mode - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRSET = BOTHOFF_PIN_MASK; // Set as output - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Safe default: HIGH (bothoff OFF) -} - -void bothoff_high(void) -{ - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTSET = BOTHOFF_PIN_MASK; // Set HIGH to turn bothoff OFF -} -void bothoff_low(void) -{ - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_OUTCLR = BOTHOFF_PIN_MASK; // Set LOW to turn bothoff ON -} - -void can_wakeup_pin(void){ - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] &= (uint8_t)(~PORT_PINCFG_PMUXEN_Msk); - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_DIRCLR = (1u << 16U); // Set as input - PORT_REGS->GROUP[GPIO_GROUP_A].PORT_PINCFG[16U] |= PORT_PINCFG_INEN_Msk; // Enable INPUT -} diff --git a/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.h b/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.h deleted file mode 100644 index 66c0f907..00000000 --- a/bms/bms/bms_config_e18a/src/ic_bms/bms_spi.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef BMS_SPI_H -#define BMS_SPI_H - -#include -#include - - - -//direct commands - -#define BATTERY_STATUS 0x12 -#define STACK_VOLTAGE 0x34 - -#define CELL_1_VOLTAGE 0x14 -#define CELL_2_VOLTAGE 0x16 -#define CELL_3_VOLTAGE 0x18 -#define CELL_4_VOLTAGE 0x1A -#define CELL_5_VOLTAGE 0x1C -#define CELL_6_VOLTAGE 0x1E -#define CC2_CURRENT 0x3A - - -/* -#define Cell7Voltage 0x20 -#define Cell8Voltage 0x22 -#define Cell9Voltage 0x24 -#define Cell10Voltage 0x26 -#define Cell11Voltage 0x28 -#define Cell12Voltage 0x2A -#define Cell13Voltage 0x2C -#define Cell14Voltage 0x2E -#define Cell15Voltage 0x30 -#define Cell16Voltage 0x32 - -*/ // 16 cell voltage readings avaliable - -#define bq_cs_group (0U) -#define bq_cs_mask (1UL << 7) // PA07: CS (GPIO) - -#define R 0 // Read; Used in directcommands and Subcommands functions -#define W 1 // Write; Used in directcommands and Subcommands functions -#define BQ_SUBCMD_MAX_POLLS 2000u - - -#define SWAP_COMM_MODE 0x29BC -#define SWAP_TO_SPI 0x7C35 -#define SWAP_TO_I2C 0x29E7 //maybe needed - -#define THERMISOR_TEMP 0x6A -#define INTERNAL_TEMP 0x68 -#define TS1_TEMP 0x70 -#define TS2_TEMP 0x72 -#define TS3_TEMP 0x74 - -//command only (R) - -#define RESET 0x0012 -#define SHUTDOWN 0x0010 - -// Thresholds and Delays values (TBC) - -#define COV_THRESHOLD_MV 4250 -#define COV_DELAY_MS 200 -#define CUV_THRESHOLD_MV 3000 -#define CUV_DELAY_MS 300 - -// Threshold Addresses -#define COV_THRESHOLD_ADDR 0x9278 -#define COV_DELAY_ADDR 0x9279 -#define CUV_THRESHOLD_ADDR 0x9275 -#define CUV_DELAY_ADDR 0x9276 - -//Config Mode -#define ENTER_CONFIG_UPDATE 0x0090 -#define EXIT_CONFIG_UPDATE 0x0092 - -#define FET_STATUS 0x7F - -// BOTHOFF PINS - -#define GPIO_GROUP_A 0u -#define PIN_BOTHOFF 6u -#define BOTHOFF_PIN_MASK (1u << PIN_BOTHOFF) - -/* Minimal driver: only SPI+CS bring-up */ - -void bq76942_init(void); -bool write_reg(uint8_t regAddr, const uint8_t *data, uint8_t length); -bool read_reg(uint8_t regAddr, uint8_t *data, uint8_t length); -bool bq_direct_command(uint8_t command, uint16_t *data, char type); -bool bq_command_only(uint16_t subcmd); -bool bq_direct_read(uint8_t command, uint8_t *data, uint8_t count); -bool bq_direct_write(uint8_t command, const uint8_t *data, uint8_t count); -bool bq_read_subcommand(uint16_t subcmd, uint8_t *data, uint8_t length); -bool bq_write_subcommand(uint16_t subcmd, const uint8_t *data, uint8_t length); -void bms_set_protection_threshold(void); -void bms_battery_status(void); -bool read_cells_1to6(uint16_t cell_mV[6]); -void bms_sample_temps(void); -bool bms_read_ts_temp(uint8_t ts_cmd, int16_t *temp_dC); -bool bms_current_read(int16_t *current_userA); -void bothoff_init(void); -void bothoff_high(void); -void bothoff_low(void); - - - - - - - -#endif /* bq76942_H */ diff --git a/bms/bms/bms_config_e18a/src/ic_bms/spi_test.c b/bms/bms/bms_config_e18a/src/ic_bms/spi_test.c deleted file mode 100644 index 8056caac..00000000 --- a/bms/bms/bms_config_e18a/src/ic_bms/spi_test.c +++ /dev/null @@ -1,175 +0,0 @@ -#include -#include -#include -#include "definitions.h" -#include "spi_test.h" - -#define SPI_TEST_CS_GROUP (0U) -#define SPI_TEST_CS_MASK (1UL << 7) // PA07 -#define SPI_TEST_WAIT_TIMEOUT (2000000UL) - -// Drives the same CS GPIO used by the production BMS SPI path. -static inline void spi_test_cs_low(void) -{ - PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTCLR = SPI_TEST_CS_MASK; -} - -static inline void spi_test_cs_high(void) -{ - PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_OUTSET = SPI_TEST_CS_MASK; -} - -// Prevents tests from hanging forever if SPI stays busy. -static bool spi_test_wait_idle(void) -{ - uint32_t timeout = SPI_TEST_WAIT_TIMEOUT; - - while (SERCOM0_SPI_IsBusy()) - { - if (timeout-- == 0U) - { - return false; - } - } - - return true; -} - -// UART helper so we can inspect exact bytes sent/received on the live target. -static void spi_test_print_bytes(const char *label, const uint8_t *buf, size_t len) -{ - printf("%s:", label); - for (size_t i = 0; i < len; i++) - { - printf(" %02X", buf[i]); - } - printf("\n"); -} - -// Same CRC-8 polynomial (0x07) used in bms_spi.c framing. -static uint8_t spi_test_crc8_calc(const uint8_t *data, uint8_t len) -{ - uint8_t crc = 0x00U; - - for (uint8_t i = 0; i < len; i++) - { - crc ^= data[i]; - for (uint8_t b = 0; b < 8U; b++) - { - crc = (crc & 0x80U) ? (uint8_t)((crc << 1U) ^ 0x07U) : (uint8_t)(crc << 1U); - } - } - return crc; -} - -// Tests write_reg frame construction and one real SPI write transfer. -// With loopback only, this validates transport/framing (not real BQ register writes). -static bool spi_test_write_reg_exact(uint8_t reg_addr, const uint8_t *data, uint8_t length) -{ - uint8_t tx_bytes[3U * 32U]; - - if ((length == 0U) || (length > 32U) || SERCOM0_SPI_IsBusy()) - { - return false; - } - - for (uint8_t i = 0U; i < length; i++) - { - uint8_t cmd = (uint8_t)(0x80U | (uint8_t)((reg_addr + i) & 0x7FU)); - uint8_t pair[2] = {cmd, data[i]}; - tx_bytes[3U * i + 0U] = cmd; - tx_bytes[3U * i + 1U] = data[i]; - tx_bytes[3U * i + 2U] = spi_test_crc8_calc(pair, 2U); - } - - spi_test_print_bytes("write_reg tx", tx_bytes, (size_t)(3U * length)); - - spi_test_cs_low(); - bool ok = SERCOM0_SPI_Write(tx_bytes, (size_t)(3U * length)); - if (ok) - { - ok = spi_test_wait_idle(); - } - spi_test_cs_high(); - return ok; -} - -// Tests read_reg frame construction, SPI full-duplex transfer, and CRC parsing. -// In loopback mode, rx mirrors tx; this still validates parser/CRC path end-to-end. -static bool spi_test_read_reg_exact(uint8_t reg_addr, uint8_t *data, uint8_t length) -{ - uint8_t tx[3U * 33U]; - uint8_t rx[3U * 33U]; - uint8_t frames; - - if ((length == 0U) || (length > 32U) || SERCOM0_SPI_IsBusy()) - { - return false; - } - - frames = (uint8_t)(length + 1U); - - { - uint8_t pair0[2] = {(uint8_t)(reg_addr & 0x7FU), 0x00U}; - tx[0] = pair0[0]; - tx[1] = pair0[1]; - tx[2] = spi_test_crc8_calc(pair0, 2U); - } - - for (uint8_t i = 1U; i < frames; i++) - { - uint8_t cmd = (i < (uint8_t)(frames - 1U)) ? (uint8_t)((reg_addr + i) & 0x7FU) : (uint8_t)0x00U; - uint8_t pair[2] = {cmd, 0x00U}; - tx[3U * i + 0U] = pair[0]; - tx[3U * i + 1U] = pair[1]; - tx[3U * i + 2U] = spi_test_crc8_calc(pair, 2U); - } - - spi_test_print_bytes("read_reg tx", tx, (size_t)(3U * frames)); - - spi_test_cs_low(); - bool ok = SERCOM0_SPI_WriteRead(tx, (size_t)(3U * frames), rx, (size_t)(3U * frames)); - if (ok) - { - ok = spi_test_wait_idle(); - } - spi_test_cs_high(); - if (!ok) - { - return false; - } - - spi_test_print_bytes("read_reg rx", rx, (size_t)(3U * frames)); - - for (uint8_t j = 1U; j <= length; j++) - { - uint8_t *chunk = &rx[3U * j]; - if (spi_test_crc8_calc(chunk, 2U) != chunk[2]) - { - return false; - } - data[j - 1U] = chunk[1]; - } - return true; -} - -void spi_driver_self_test_run(void) -{ - uint8_t wr_data[3] = {0x12U, 0x34U, 0x56U}; - uint8_t rd_data[3] = {0U}; - bool ok_write; - bool ok_read; - - PORT_REGS->GROUP[SPI_TEST_CS_GROUP].PORT_DIRSET = SPI_TEST_CS_MASK; - spi_test_cs_high(); - - printf("=== SPI read/write reg transport test (PA08->PA09 loopback) ===\n"); - - ok_write = spi_test_write_reg_exact(0x10U, wr_data, sizeof(wr_data)); - ok_read = spi_test_read_reg_exact(0x10U, rd_data, sizeof(rd_data)); - - printf("write_reg_exact(0x10, len=3): %s\n", ok_write ? "OK" : "FAIL"); - printf("read_reg_exact(0x10, len=3): %s\n", ok_read ? "OK" : "FAIL"); - spi_test_print_bytes("read_reg data", rd_data, sizeof(rd_data)); - printf("Note: this confirms MCU SPI framing/path only; real BQ register behavior needs the BQ IC connected.\n"); -} diff --git a/bms/bms/bms_config_e18a/src/ic_bms/spi_test.h b/bms/bms/bms_config_e18a/src/ic_bms/spi_test.h deleted file mode 100644 index 4710c0e2..00000000 --- a/bms/bms/bms_config_e18a/src/ic_bms/spi_test.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef SPI_TEST_H -#define SPI_TEST_H - -void spi_driver_self_test_run(void); - -#endif /* SPI_TEST_H */ diff --git a/bms/bms/bms_config_e18a/src/main.c b/bms/bms/bms_config_e18a/src/main.c deleted file mode 100644 index 44629f9c..00000000 --- a/bms/bms/bms_config_e18a/src/main.c +++ /dev/null @@ -1,98 +0,0 @@ -/******************************************************************************* - Main Source File - - Company: - Microchip Technology Inc. - - File Name: - main.c - - Summary: - This file contains the "main" function for a project. - - Description: - This file contains the "main" function for a project. The - "main" function calls the "SYS_Initialize" function to initialize the state - machines of all modules in the system - *******************************************************************************/ - -// ***************************************************************************** -// ***************************************************************************** -// Section: Included Files -// ***************************************************************************** -// ***************************************************************************** - -#include // Defines NULL -#include // Defines true -#include // Defines EXIT_FAILURE -#include "definitions.h" // SYS function prototypes -#include "ic_bms/bms_spi.h" -#include "ic_bms/spi_test.h" -#include "app/can_facade.h" -#include "app/can_telemetry.h" -#include "app/pwr_mode.h" -#include "app/state_machine.h" -#include "peripheral/port/plib_port.h" -#include -#include - - -// ***************************************************************************** -// ***************************************************************************** -// Section: Main Entry Point -// ***************************************************************************** -// ***************************************************************************** -static void CAN_Wake_EIC_Callback(uintptr_t context) // called when a CAN wake-up interrupt occurs on EIC pin 11 -{ - (void)context; - sm_on_can_wake(); -} - - -static void TelemetryRtcCb(RTC_TIMER32_INT_MASK intCause, uintptr_t context) // called every 100ms by the RTC timer interrupt -{ - (void)intCause; - (void)context; - sm_on_rtc_tick(); - CAN_telemetry_tickISR(); -} - - - -int main ( void ) -{ - /* Initialize all modules */ - SYS_Initialize ( NULL ); - pwr_mode_init(); - CAN_Init(); - CAN_telemetry_init(); - RTC_Timer32CallbackRegister(TelemetryRtcCb, 0); - RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK_CMP0); - RTC_Timer32Start(); - EIC_CallbackRegister(EIC_PIN_11, CAN_Wake_EIC_Callback, 0); - EIC_InterruptEnable(EIC_PIN_11); - - //spi_driver_self_test_run(); - bq76942_init(); - bothoff_init(); - sm_init(); - //bms_battery_status(); - - while ( true ) - { - /* Maintain state machines of all polled MPLAB Harmony modules. */ - SYS_Tasks ( ); - state_machine(); - } - - - /* Execution should not come here during normal operation */ - - return ( EXIT_FAILURE ); -} - - -/******************************************************************************* - End of File -*/ - diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ac.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ac.h deleted file mode 100644 index 96212c05..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ac.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Component description for AC - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_AC_COMPONENT_H_ -#define _SAMC21_AC_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR AC */ -/* ************************************************************************** */ - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#define AC_CTRLA_RESETVALUE _UINT8_(0x00) /* (AC_CTRLA) Control A Reset Value */ - -#define AC_CTRLA_SWRST_Pos _UINT8_(0) /* (AC_CTRLA) Software Reset Position */ -#define AC_CTRLA_SWRST_Msk (_UINT8_(0x1) << AC_CTRLA_SWRST_Pos) /* (AC_CTRLA) Software Reset Mask */ -#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & (_UINT8_(value) << AC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the AC_CTRLA register */ -#define AC_CTRLA_ENABLE_Pos _UINT8_(1) /* (AC_CTRLA) Enable Position */ -#define AC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << AC_CTRLA_ENABLE_Pos) /* (AC_CTRLA) Enable Mask */ -#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & (_UINT8_(value) << AC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_CTRLA register */ -#define AC_CTRLA_Msk _UINT8_(0x03) /* (AC_CTRLA) Register Mask */ - - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#define AC_CTRLB_RESETVALUE _UINT8_(0x00) /* (AC_CTRLB) Control B Reset Value */ - -#define AC_CTRLB_START0_Pos _UINT8_(0) /* (AC_CTRLB) Comparator 0 Start Comparison Position */ -#define AC_CTRLB_START0_Msk (_UINT8_(0x1) << AC_CTRLB_START0_Pos) /* (AC_CTRLB) Comparator 0 Start Comparison Mask */ -#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & (_UINT8_(value) << AC_CTRLB_START0_Pos)) /* Assignment of value for START0 in the AC_CTRLB register */ -#define AC_CTRLB_START1_Pos _UINT8_(1) /* (AC_CTRLB) Comparator 1 Start Comparison Position */ -#define AC_CTRLB_START1_Msk (_UINT8_(0x1) << AC_CTRLB_START1_Pos) /* (AC_CTRLB) Comparator 1 Start Comparison Mask */ -#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & (_UINT8_(value) << AC_CTRLB_START1_Pos)) /* Assignment of value for START1 in the AC_CTRLB register */ -#define AC_CTRLB_START2_Pos _UINT8_(2) /* (AC_CTRLB) Comparator 2 Start Comparison Position */ -#define AC_CTRLB_START2_Msk (_UINT8_(0x1) << AC_CTRLB_START2_Pos) /* (AC_CTRLB) Comparator 2 Start Comparison Mask */ -#define AC_CTRLB_START2(value) (AC_CTRLB_START2_Msk & (_UINT8_(value) << AC_CTRLB_START2_Pos)) /* Assignment of value for START2 in the AC_CTRLB register */ -#define AC_CTRLB_START3_Pos _UINT8_(3) /* (AC_CTRLB) Comparator 3 Start Comparison Position */ -#define AC_CTRLB_START3_Msk (_UINT8_(0x1) << AC_CTRLB_START3_Pos) /* (AC_CTRLB) Comparator 3 Start Comparison Mask */ -#define AC_CTRLB_START3(value) (AC_CTRLB_START3_Msk & (_UINT8_(value) << AC_CTRLB_START3_Pos)) /* Assignment of value for START3 in the AC_CTRLB register */ -#define AC_CTRLB_Msk _UINT8_(0x0F) /* (AC_CTRLB) Register Mask */ - -#define AC_CTRLB_START_Pos _UINT8_(0) /* (AC_CTRLB Position) Comparator 3 Start Comparison */ -#define AC_CTRLB_START_Msk (_UINT8_(0xF) << AC_CTRLB_START_Pos) /* (AC_CTRLB Mask) START */ -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & (_UINT8_(value) << AC_CTRLB_START_Pos)) - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#define AC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (AC_EVCTRL) Event Control Reset Value */ - -#define AC_EVCTRL_COMPEO0_Pos _UINT16_(0) /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */ -#define AC_EVCTRL_COMPEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO0_Pos) /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ -#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assignment of value for COMPEO0 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEO1_Pos _UINT16_(1) /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */ -#define AC_EVCTRL_COMPEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO1_Pos) /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ -#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assignment of value for COMPEO1 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEO2_Pos _UINT16_(2) /* (AC_EVCTRL) Comparator 2 Event Output Enable Position */ -#define AC_EVCTRL_COMPEO2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO2_Pos) /* (AC_EVCTRL) Comparator 2 Event Output Enable Mask */ -#define AC_EVCTRL_COMPEO2(value) (AC_EVCTRL_COMPEO2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO2_Pos)) /* Assignment of value for COMPEO2 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEO3_Pos _UINT16_(3) /* (AC_EVCTRL) Comparator 3 Event Output Enable Position */ -#define AC_EVCTRL_COMPEO3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO3_Pos) /* (AC_EVCTRL) Comparator 3 Event Output Enable Mask */ -#define AC_EVCTRL_COMPEO3(value) (AC_EVCTRL_COMPEO3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO3_Pos)) /* Assignment of value for COMPEO3 in the AC_EVCTRL register */ -#define AC_EVCTRL_WINEO0_Pos _UINT16_(4) /* (AC_EVCTRL) Window 0 Event Output Enable Position */ -#define AC_EVCTRL_WINEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO0_Pos) /* (AC_EVCTRL) Window 0 Event Output Enable Mask */ -#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assignment of value for WINEO0 in the AC_EVCTRL register */ -#define AC_EVCTRL_WINEO1_Pos _UINT16_(5) /* (AC_EVCTRL) Window 1 Event Output Enable Position */ -#define AC_EVCTRL_WINEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO1_Pos) /* (AC_EVCTRL) Window 1 Event Output Enable Mask */ -#define AC_EVCTRL_WINEO1(value) (AC_EVCTRL_WINEO1_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO1_Pos)) /* Assignment of value for WINEO1 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEI0_Pos _UINT16_(8) /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */ -#define AC_EVCTRL_COMPEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI0_Pos) /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ -#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assignment of value for COMPEI0 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEI1_Pos _UINT16_(9) /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */ -#define AC_EVCTRL_COMPEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI1_Pos) /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ -#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assignment of value for COMPEI1 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEI2_Pos _UINT16_(10) /* (AC_EVCTRL) Comparator 2 Event Input Enable Position */ -#define AC_EVCTRL_COMPEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI2_Pos) /* (AC_EVCTRL) Comparator 2 Event Input Enable Mask */ -#define AC_EVCTRL_COMPEI2(value) (AC_EVCTRL_COMPEI2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI2_Pos)) /* Assignment of value for COMPEI2 in the AC_EVCTRL register */ -#define AC_EVCTRL_COMPEI3_Pos _UINT16_(11) /* (AC_EVCTRL) Comparator 3 Event Input Enable Position */ -#define AC_EVCTRL_COMPEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI3_Pos) /* (AC_EVCTRL) Comparator 3 Event Input Enable Mask */ -#define AC_EVCTRL_COMPEI3(value) (AC_EVCTRL_COMPEI3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI3_Pos)) /* Assignment of value for COMPEI3 in the AC_EVCTRL register */ -#define AC_EVCTRL_INVEI0_Pos _UINT16_(12) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ -#define AC_EVCTRL_INVEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI0_Pos) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ -#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assignment of value for INVEI0 in the AC_EVCTRL register */ -#define AC_EVCTRL_INVEI1_Pos _UINT16_(13) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ -#define AC_EVCTRL_INVEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI1_Pos) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ -#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assignment of value for INVEI1 in the AC_EVCTRL register */ -#define AC_EVCTRL_INVEI2_Pos _UINT16_(14) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Position */ -#define AC_EVCTRL_INVEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI2_Pos) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Mask */ -#define AC_EVCTRL_INVEI2(value) (AC_EVCTRL_INVEI2_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI2_Pos)) /* Assignment of value for INVEI2 in the AC_EVCTRL register */ -#define AC_EVCTRL_INVEI3_Pos _UINT16_(15) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Position */ -#define AC_EVCTRL_INVEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI3_Pos) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Mask */ -#define AC_EVCTRL_INVEI3(value) (AC_EVCTRL_INVEI3_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI3_Pos)) /* Assignment of value for INVEI3 in the AC_EVCTRL register */ -#define AC_EVCTRL_Msk _UINT16_(0xFF3F) /* (AC_EVCTRL) Register Mask */ - -#define AC_EVCTRL_COMPEO_Pos _UINT16_(0) /* (AC_EVCTRL Position) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEO_Pos) /* (AC_EVCTRL Mask) COMPEO */ -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO_Pos _UINT16_(4) /* (AC_EVCTRL Position) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_UINT16_(0x3) << AC_EVCTRL_WINEO_Pos) /* (AC_EVCTRL Mask) WINEO */ -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI_Pos _UINT16_(8) /* (AC_EVCTRL Position) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEI_Pos) /* (AC_EVCTRL Mask) COMPEI */ -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI_Pos _UINT16_(12) /* (AC_EVCTRL Position) Comparator 3 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_UINT16_(0xF) << AC_EVCTRL_INVEI_Pos) /* (AC_EVCTRL Mask) INVEI */ -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI_Pos)) - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#define AC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AC_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define AC_INTENCLR_COMP0_Pos _UINT8_(0) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ -#define AC_INTENCLR_COMP0_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP0_Pos) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ -#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & (_UINT8_(value) << AC_INTENCLR_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTENCLR register */ -#define AC_INTENCLR_COMP1_Pos _UINT8_(1) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ -#define AC_INTENCLR_COMP1_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP1_Pos) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ -#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & (_UINT8_(value) << AC_INTENCLR_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTENCLR register */ -#define AC_INTENCLR_COMP2_Pos _UINT8_(2) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Position */ -#define AC_INTENCLR_COMP2_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP2_Pos) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Mask */ -#define AC_INTENCLR_COMP2(value) (AC_INTENCLR_COMP2_Msk & (_UINT8_(value) << AC_INTENCLR_COMP2_Pos)) /* Assignment of value for COMP2 in the AC_INTENCLR register */ -#define AC_INTENCLR_COMP3_Pos _UINT8_(3) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Position */ -#define AC_INTENCLR_COMP3_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP3_Pos) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Mask */ -#define AC_INTENCLR_COMP3(value) (AC_INTENCLR_COMP3_Msk & (_UINT8_(value) << AC_INTENCLR_COMP3_Pos)) /* Assignment of value for COMP3 in the AC_INTENCLR register */ -#define AC_INTENCLR_WIN0_Pos _UINT8_(4) /* (AC_INTENCLR) Window 0 Interrupt Enable Position */ -#define AC_INTENCLR_WIN0_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN0_Pos) /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */ -#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & (_UINT8_(value) << AC_INTENCLR_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTENCLR register */ -#define AC_INTENCLR_WIN1_Pos _UINT8_(5) /* (AC_INTENCLR) Window 1 Interrupt Enable Position */ -#define AC_INTENCLR_WIN1_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN1_Pos) /* (AC_INTENCLR) Window 1 Interrupt Enable Mask */ -#define AC_INTENCLR_WIN1(value) (AC_INTENCLR_WIN1_Msk & (_UINT8_(value) << AC_INTENCLR_WIN1_Pos)) /* Assignment of value for WIN1 in the AC_INTENCLR register */ -#define AC_INTENCLR_Msk _UINT8_(0x3F) /* (AC_INTENCLR) Register Mask */ - -#define AC_INTENCLR_COMP_Pos _UINT8_(0) /* (AC_INTENCLR Position) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_UINT8_(0xF) << AC_INTENCLR_COMP_Pos) /* (AC_INTENCLR Mask) COMP */ -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & (_UINT8_(value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN_Pos _UINT8_(4) /* (AC_INTENCLR Position) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_UINT8_(0x3) << AC_INTENCLR_WIN_Pos) /* (AC_INTENCLR Mask) WIN */ -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & (_UINT8_(value) << AC_INTENCLR_WIN_Pos)) - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#define AC_INTENSET_RESETVALUE _UINT8_(0x00) /* (AC_INTENSET) Interrupt Enable Set Reset Value */ - -#define AC_INTENSET_COMP0_Pos _UINT8_(0) /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */ -#define AC_INTENSET_COMP0_Msk (_UINT8_(0x1) << AC_INTENSET_COMP0_Pos) /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ -#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & (_UINT8_(value) << AC_INTENSET_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTENSET register */ -#define AC_INTENSET_COMP1_Pos _UINT8_(1) /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */ -#define AC_INTENSET_COMP1_Msk (_UINT8_(0x1) << AC_INTENSET_COMP1_Pos) /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ -#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & (_UINT8_(value) << AC_INTENSET_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTENSET register */ -#define AC_INTENSET_COMP2_Pos _UINT8_(2) /* (AC_INTENSET) Comparator 2 Interrupt Enable Position */ -#define AC_INTENSET_COMP2_Msk (_UINT8_(0x1) << AC_INTENSET_COMP2_Pos) /* (AC_INTENSET) Comparator 2 Interrupt Enable Mask */ -#define AC_INTENSET_COMP2(value) (AC_INTENSET_COMP2_Msk & (_UINT8_(value) << AC_INTENSET_COMP2_Pos)) /* Assignment of value for COMP2 in the AC_INTENSET register */ -#define AC_INTENSET_COMP3_Pos _UINT8_(3) /* (AC_INTENSET) Comparator 3 Interrupt Enable Position */ -#define AC_INTENSET_COMP3_Msk (_UINT8_(0x1) << AC_INTENSET_COMP3_Pos) /* (AC_INTENSET) Comparator 3 Interrupt Enable Mask */ -#define AC_INTENSET_COMP3(value) (AC_INTENSET_COMP3_Msk & (_UINT8_(value) << AC_INTENSET_COMP3_Pos)) /* Assignment of value for COMP3 in the AC_INTENSET register */ -#define AC_INTENSET_WIN0_Pos _UINT8_(4) /* (AC_INTENSET) Window 0 Interrupt Enable Position */ -#define AC_INTENSET_WIN0_Msk (_UINT8_(0x1) << AC_INTENSET_WIN0_Pos) /* (AC_INTENSET) Window 0 Interrupt Enable Mask */ -#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & (_UINT8_(value) << AC_INTENSET_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTENSET register */ -#define AC_INTENSET_WIN1_Pos _UINT8_(5) /* (AC_INTENSET) Window 1 Interrupt Enable Position */ -#define AC_INTENSET_WIN1_Msk (_UINT8_(0x1) << AC_INTENSET_WIN1_Pos) /* (AC_INTENSET) Window 1 Interrupt Enable Mask */ -#define AC_INTENSET_WIN1(value) (AC_INTENSET_WIN1_Msk & (_UINT8_(value) << AC_INTENSET_WIN1_Pos)) /* Assignment of value for WIN1 in the AC_INTENSET register */ -#define AC_INTENSET_Msk _UINT8_(0x3F) /* (AC_INTENSET) Register Mask */ - -#define AC_INTENSET_COMP_Pos _UINT8_(0) /* (AC_INTENSET Position) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_UINT8_(0xF) << AC_INTENSET_COMP_Pos) /* (AC_INTENSET Mask) COMP */ -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & (_UINT8_(value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN_Pos _UINT8_(4) /* (AC_INTENSET Position) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_UINT8_(0x3) << AC_INTENSET_WIN_Pos) /* (AC_INTENSET Mask) WIN */ -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & (_UINT8_(value) << AC_INTENSET_WIN_Pos)) - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#define AC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ - -#define AC_INTFLAG_COMP0_Pos _UINT8_(0) /* (AC_INTFLAG) Comparator 0 Position */ -#define AC_INTFLAG_COMP0_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP0_Pos) /* (AC_INTFLAG) Comparator 0 Mask */ -#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & (_UINT8_(value) << AC_INTFLAG_COMP0_Pos)) /* Assignment of value for COMP0 in the AC_INTFLAG register */ -#define AC_INTFLAG_COMP1_Pos _UINT8_(1) /* (AC_INTFLAG) Comparator 1 Position */ -#define AC_INTFLAG_COMP1_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP1_Pos) /* (AC_INTFLAG) Comparator 1 Mask */ -#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & (_UINT8_(value) << AC_INTFLAG_COMP1_Pos)) /* Assignment of value for COMP1 in the AC_INTFLAG register */ -#define AC_INTFLAG_COMP2_Pos _UINT8_(2) /* (AC_INTFLAG) Comparator 2 Position */ -#define AC_INTFLAG_COMP2_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP2_Pos) /* (AC_INTFLAG) Comparator 2 Mask */ -#define AC_INTFLAG_COMP2(value) (AC_INTFLAG_COMP2_Msk & (_UINT8_(value) << AC_INTFLAG_COMP2_Pos)) /* Assignment of value for COMP2 in the AC_INTFLAG register */ -#define AC_INTFLAG_COMP3_Pos _UINT8_(3) /* (AC_INTFLAG) Comparator 3 Position */ -#define AC_INTFLAG_COMP3_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP3_Pos) /* (AC_INTFLAG) Comparator 3 Mask */ -#define AC_INTFLAG_COMP3(value) (AC_INTFLAG_COMP3_Msk & (_UINT8_(value) << AC_INTFLAG_COMP3_Pos)) /* Assignment of value for COMP3 in the AC_INTFLAG register */ -#define AC_INTFLAG_WIN0_Pos _UINT8_(4) /* (AC_INTFLAG) Window 0 Position */ -#define AC_INTFLAG_WIN0_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN0_Pos) /* (AC_INTFLAG) Window 0 Mask */ -#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & (_UINT8_(value) << AC_INTFLAG_WIN0_Pos)) /* Assignment of value for WIN0 in the AC_INTFLAG register */ -#define AC_INTFLAG_WIN1_Pos _UINT8_(5) /* (AC_INTFLAG) Window 1 Position */ -#define AC_INTFLAG_WIN1_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN1_Pos) /* (AC_INTFLAG) Window 1 Mask */ -#define AC_INTFLAG_WIN1(value) (AC_INTFLAG_WIN1_Msk & (_UINT8_(value) << AC_INTFLAG_WIN1_Pos)) /* Assignment of value for WIN1 in the AC_INTFLAG register */ -#define AC_INTFLAG_Msk _UINT8_(0x3F) /* (AC_INTFLAG) Register Mask */ - -#define AC_INTFLAG_COMP_Pos _UINT8_(0) /* (AC_INTFLAG Position) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_UINT8_(0xF) << AC_INTFLAG_COMP_Pos) /* (AC_INTFLAG Mask) COMP */ -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & (_UINT8_(value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN_Pos _UINT8_(4) /* (AC_INTFLAG Position) Window x */ -#define AC_INTFLAG_WIN_Msk (_UINT8_(0x3) << AC_INTFLAG_WIN_Pos) /* (AC_INTFLAG Mask) WIN */ -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & (_UINT8_(value) << AC_INTFLAG_WIN_Pos)) - -/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ -#define AC_STATUSA_RESETVALUE _UINT8_(0x00) /* (AC_STATUSA) Status A Reset Value */ - -#define AC_STATUSA_STATE0_Pos _UINT8_(0) /* (AC_STATUSA) Comparator 0 Current State Position */ -#define AC_STATUSA_STATE0_Msk (_UINT8_(0x1) << AC_STATUSA_STATE0_Pos) /* (AC_STATUSA) Comparator 0 Current State Mask */ -#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & (_UINT8_(value) << AC_STATUSA_STATE0_Pos)) /* Assignment of value for STATE0 in the AC_STATUSA register */ -#define AC_STATUSA_STATE1_Pos _UINT8_(1) /* (AC_STATUSA) Comparator 1 Current State Position */ -#define AC_STATUSA_STATE1_Msk (_UINT8_(0x1) << AC_STATUSA_STATE1_Pos) /* (AC_STATUSA) Comparator 1 Current State Mask */ -#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & (_UINT8_(value) << AC_STATUSA_STATE1_Pos)) /* Assignment of value for STATE1 in the AC_STATUSA register */ -#define AC_STATUSA_STATE2_Pos _UINT8_(2) /* (AC_STATUSA) Comparator 2 Current State Position */ -#define AC_STATUSA_STATE2_Msk (_UINT8_(0x1) << AC_STATUSA_STATE2_Pos) /* (AC_STATUSA) Comparator 2 Current State Mask */ -#define AC_STATUSA_STATE2(value) (AC_STATUSA_STATE2_Msk & (_UINT8_(value) << AC_STATUSA_STATE2_Pos)) /* Assignment of value for STATE2 in the AC_STATUSA register */ -#define AC_STATUSA_STATE3_Pos _UINT8_(3) /* (AC_STATUSA) Comparator 3 Current State Position */ -#define AC_STATUSA_STATE3_Msk (_UINT8_(0x1) << AC_STATUSA_STATE3_Pos) /* (AC_STATUSA) Comparator 3 Current State Mask */ -#define AC_STATUSA_STATE3(value) (AC_STATUSA_STATE3_Msk & (_UINT8_(value) << AC_STATUSA_STATE3_Pos)) /* Assignment of value for STATE3 in the AC_STATUSA register */ -#define AC_STATUSA_WSTATE0_Pos _UINT8_(4) /* (AC_STATUSA) Window 0 Current State Position */ -#define AC_STATUSA_WSTATE0_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Window 0 Current State Mask */ -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assignment of value for WSTATE0 in the AC_STATUSA register */ -#define AC_STATUSA_WSTATE0_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */ -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */ -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */ -#define AC_STATUSA_WSTATE1_Pos _UINT8_(6) /* (AC_STATUSA) Window 1 Current State Position */ -#define AC_STATUSA_WSTATE1_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Window 1 Current State Mask */ -#define AC_STATUSA_WSTATE1(value) (AC_STATUSA_WSTATE1_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE1_Pos)) /* Assignment of value for WSTATE1 in the AC_STATUSA register */ -#define AC_STATUSA_WSTATE1_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE1_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE1_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE1_ABOVE (AC_STATUSA_WSTATE1_ABOVE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is above window Position */ -#define AC_STATUSA_WSTATE1_INSIDE (AC_STATUSA_WSTATE1_INSIDE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is inside window Position */ -#define AC_STATUSA_WSTATE1_BELOW (AC_STATUSA_WSTATE1_BELOW_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is below window Position */ -#define AC_STATUSA_Msk _UINT8_(0xFF) /* (AC_STATUSA) Register Mask */ - -#define AC_STATUSA_STATE_Pos _UINT8_(0) /* (AC_STATUSA Position) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_UINT8_(0xF) << AC_STATUSA_STATE_Pos) /* (AC_STATUSA Mask) STATE */ -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & (_UINT8_(value) << AC_STATUSA_STATE_Pos)) - -/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ -#define AC_STATUSB_RESETVALUE _UINT8_(0x00) /* (AC_STATUSB) Status B Reset Value */ - -#define AC_STATUSB_READY0_Pos _UINT8_(0) /* (AC_STATUSB) Comparator 0 Ready Position */ -#define AC_STATUSB_READY0_Msk (_UINT8_(0x1) << AC_STATUSB_READY0_Pos) /* (AC_STATUSB) Comparator 0 Ready Mask */ -#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & (_UINT8_(value) << AC_STATUSB_READY0_Pos)) /* Assignment of value for READY0 in the AC_STATUSB register */ -#define AC_STATUSB_READY1_Pos _UINT8_(1) /* (AC_STATUSB) Comparator 1 Ready Position */ -#define AC_STATUSB_READY1_Msk (_UINT8_(0x1) << AC_STATUSB_READY1_Pos) /* (AC_STATUSB) Comparator 1 Ready Mask */ -#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & (_UINT8_(value) << AC_STATUSB_READY1_Pos)) /* Assignment of value for READY1 in the AC_STATUSB register */ -#define AC_STATUSB_READY2_Pos _UINT8_(2) /* (AC_STATUSB) Comparator 2 Ready Position */ -#define AC_STATUSB_READY2_Msk (_UINT8_(0x1) << AC_STATUSB_READY2_Pos) /* (AC_STATUSB) Comparator 2 Ready Mask */ -#define AC_STATUSB_READY2(value) (AC_STATUSB_READY2_Msk & (_UINT8_(value) << AC_STATUSB_READY2_Pos)) /* Assignment of value for READY2 in the AC_STATUSB register */ -#define AC_STATUSB_READY3_Pos _UINT8_(3) /* (AC_STATUSB) Comparator 3 Ready Position */ -#define AC_STATUSB_READY3_Msk (_UINT8_(0x1) << AC_STATUSB_READY3_Pos) /* (AC_STATUSB) Comparator 3 Ready Mask */ -#define AC_STATUSB_READY3(value) (AC_STATUSB_READY3_Msk & (_UINT8_(value) << AC_STATUSB_READY3_Pos)) /* Assignment of value for READY3 in the AC_STATUSB register */ -#define AC_STATUSB_Msk _UINT8_(0x0F) /* (AC_STATUSB) Register Mask */ - -#define AC_STATUSB_READY_Pos _UINT8_(0) /* (AC_STATUSB Position) Comparator 3 Ready */ -#define AC_STATUSB_READY_Msk (_UINT8_(0xF) << AC_STATUSB_READY_Pos) /* (AC_STATUSB Mask) READY */ -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & (_UINT8_(value) << AC_STATUSB_READY_Pos)) - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#define AC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AC_DBGCTRL) Debug Control Reset Value */ - -#define AC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AC_DBGCTRL) Debug Run Position */ -#define AC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /* (AC_DBGCTRL) Debug Run Mask */ -#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the AC_DBGCTRL register */ -#define AC_DBGCTRL_Msk _UINT8_(0x01) /* (AC_DBGCTRL) Register Mask */ - - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#define AC_WINCTRL_RESETVALUE _UINT8_(0x00) /* (AC_WINCTRL) Window Control Reset Value */ - -#define AC_WINCTRL_WEN0_Pos _UINT8_(0) /* (AC_WINCTRL) Window 0 Mode Enable Position */ -#define AC_WINCTRL_WEN0_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN0_Pos) /* (AC_WINCTRL) Window 0 Mode Enable Mask */ -#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & (_UINT8_(value) << AC_WINCTRL_WEN0_Pos)) /* Assignment of value for WEN0 in the AC_WINCTRL register */ -#define AC_WINCTRL_WINTSEL0_Pos _UINT8_(1) /* (AC_WINCTRL) Window 0 Interrupt Selection Position */ -#define AC_WINCTRL_WINTSEL0_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Window 0 Interrupt Selection Mask */ -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL0_Pos)) /* Assignment of value for WINTSEL0 in the AC_WINCTRL register */ -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ -#define AC_WINCTRL_WEN1_Pos _UINT8_(4) /* (AC_WINCTRL) Window 1 Mode Enable Position */ -#define AC_WINCTRL_WEN1_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN1_Pos) /* (AC_WINCTRL) Window 1 Mode Enable Mask */ -#define AC_WINCTRL_WEN1(value) (AC_WINCTRL_WEN1_Msk & (_UINT8_(value) << AC_WINCTRL_WEN1_Pos)) /* Assignment of value for WEN1 in the AC_WINCTRL register */ -#define AC_WINCTRL_WINTSEL1_Pos _UINT8_(5) /* (AC_WINCTRL) Window 1 Interrupt Selection Position */ -#define AC_WINCTRL_WINTSEL1_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Window 1 Interrupt Selection Mask */ -#define AC_WINCTRL_WINTSEL1(value) (AC_WINCTRL_WINTSEL1_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL1_Pos)) /* Assignment of value for WINTSEL1 in the AC_WINCTRL register */ -#define AC_WINCTRL_WINTSEL1_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL1_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL1_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL1_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL1_ABOVE (AC_WINCTRL_WINTSEL1_ABOVE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ -#define AC_WINCTRL_WINTSEL1_INSIDE (AC_WINCTRL_WINTSEL1_INSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ -#define AC_WINCTRL_WINTSEL1_BELOW (AC_WINCTRL_WINTSEL1_BELOW_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ -#define AC_WINCTRL_WINTSEL1_OUTSIDE (AC_WINCTRL_WINTSEL1_OUTSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ -#define AC_WINCTRL_Msk _UINT8_(0x77) /* (AC_WINCTRL) Register Mask */ - - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#define AC_SCALER_RESETVALUE _UINT8_(0x00) /* (AC_SCALER) Scaler n Reset Value */ - -#define AC_SCALER_VALUE_Pos _UINT8_(0) /* (AC_SCALER) Scaler Value Position */ -#define AC_SCALER_VALUE_Msk (_UINT8_(0x3F) << AC_SCALER_VALUE_Pos) /* (AC_SCALER) Scaler Value Mask */ -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & (_UINT8_(value) << AC_SCALER_VALUE_Pos)) /* Assignment of value for VALUE in the AC_SCALER register */ -#define AC_SCALER_Msk _UINT8_(0x3F) /* (AC_SCALER) Register Mask */ - - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#define AC_COMPCTRL_RESETVALUE _UINT32_(0x00) /* (AC_COMPCTRL) Comparator Control n Reset Value */ - -#define AC_COMPCTRL_ENABLE_Pos _UINT32_(1) /* (AC_COMPCTRL) Enable Position */ -#define AC_COMPCTRL_ENABLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos) /* (AC_COMPCTRL) Enable Mask */ -#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_COMPCTRL register */ -#define AC_COMPCTRL_SINGLE_Pos _UINT32_(2) /* (AC_COMPCTRL) Single-Shot Mode Position */ -#define AC_COMPCTRL_SINGLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos) /* (AC_COMPCTRL) Single-Shot Mode Mask */ -#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assignment of value for SINGLE in the AC_COMPCTRL register */ -#define AC_COMPCTRL_INTSEL_Pos _UINT32_(3) /* (AC_COMPCTRL) Interrupt Selection Position */ -#define AC_COMPCTRL_INTSEL_Msk (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt Selection Mask */ -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assignment of value for INTSEL in the AC_COMPCTRL register */ -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _UINT32_(0x0) /* (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _UINT32_(0x1) /* (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _UINT32_(0x2) /* (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _UINT32_(0x3) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */ -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */ -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */ -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ -#define AC_COMPCTRL_RUNSTDBY_Pos _UINT32_(6) /* (AC_COMPCTRL) Run in Standby Position */ -#define AC_COMPCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /* (AC_COMPCTRL) Run in Standby Mask */ -#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the AC_COMPCTRL register */ -#define AC_COMPCTRL_MUXNEG_Pos _UINT32_(8) /* (AC_COMPCTRL) Negative Input Mux Selection Position */ -#define AC_COMPCTRL_MUXNEG_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Negative Input Mux Selection Mask */ -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assignment of value for MUXNEG in the AC_COMPCTRL register */ -#define AC_COMPCTRL_MUXNEG_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _UINT32_(0x4) /* (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _UINT32_(0x5) /* (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _UINT32_(0x6) /* (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _UINT32_(0x7) /* (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */ -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) VDD scaler Position */ -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal bandgap voltage Position */ -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) DAC output Position */ -#define AC_COMPCTRL_MUXPOS_Pos _UINT32_(12) /* (AC_COMPCTRL) Positive Input Mux Selection Position */ -#define AC_COMPCTRL_MUXPOS_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Positive Input Mux Selection Mask */ -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assignment of value for MUXPOS in the AC_COMPCTRL register */ -#define AC_COMPCTRL_MUXPOS_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _UINT32_(0x4) /* (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) VDD Scaler Position */ -#define AC_COMPCTRL_SWAP_Pos _UINT32_(15) /* (AC_COMPCTRL) Swap Inputs and Invert Position */ -#define AC_COMPCTRL_SWAP_Msk (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos) /* (AC_COMPCTRL) Swap Inputs and Invert Mask */ -#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assignment of value for SWAP in the AC_COMPCTRL register */ -#define AC_COMPCTRL_SPEED_Pos _UINT32_(16) /* (AC_COMPCTRL) Speed Selection Position */ -#define AC_COMPCTRL_SPEED_Msk (_UINT32_(0x3) << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Speed Selection Mask */ -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assignment of value for SPEED in the AC_COMPCTRL register */ -#define AC_COMPCTRL_SPEED_LOW_Val _UINT32_(0x0) /* (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val _UINT32_(0x3) /* (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Low speed Position */ -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed Position */ -#define AC_COMPCTRL_HYSTEN_Pos _UINT32_(19) /* (AC_COMPCTRL) Hysteresis Enable Position */ -#define AC_COMPCTRL_HYSTEN_Msk (_UINT32_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /* (AC_COMPCTRL) Hysteresis Enable Mask */ -#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & (_UINT32_(value) << AC_COMPCTRL_HYSTEN_Pos)) /* Assignment of value for HYSTEN in the AC_COMPCTRL register */ -#define AC_COMPCTRL_FLEN_Pos _UINT32_(24) /* (AC_COMPCTRL) Filter Length Position */ -#define AC_COMPCTRL_FLEN_Msk (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) Filter Length Mask */ -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assignment of value for FLEN in the AC_COMPCTRL register */ -#define AC_COMPCTRL_FLEN_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _UINT32_(0x1) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _UINT32_(0x2) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) No filtering Position */ -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ -#define AC_COMPCTRL_OUT_Pos _UINT32_(28) /* (AC_COMPCTRL) Output Position */ -#define AC_COMPCTRL_OUT_Msk (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) Output Mask */ -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assignment of value for OUT in the AC_COMPCTRL register */ -#define AC_COMPCTRL_OUT_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _UINT32_(0x1) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _UINT32_(0x2) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ -#define AC_COMPCTRL_Msk _UINT32_(0x370BF75E) /* (AC_COMPCTRL) Register Mask */ - - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ -#define AC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (AC_SYNCBUSY) Synchronization Busy Reset Value */ - -#define AC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ -#define AC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ -#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (AC_SYNCBUSY) Enable Synchronization Busy Position */ -#define AC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */ -#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_WINCTRL_Pos _UINT32_(2) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ -#define AC_SYNCBUSY_WINCTRL_Msk (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ -#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) /* Assignment of value for WINCTRL in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_COMPCTRL0_Pos _UINT32_(3) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ -#define AC_SYNCBUSY_COMPCTRL0_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ -#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assignment of value for COMPCTRL0 in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_COMPCTRL1_Pos _UINT32_(4) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ -#define AC_SYNCBUSY_COMPCTRL1_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ -#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assignment of value for COMPCTRL1 in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_COMPCTRL2_Pos _UINT32_(5) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Position */ -#define AC_SYNCBUSY_COMPCTRL2_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL2_Pos) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Mask */ -#define AC_SYNCBUSY_COMPCTRL2(value) (AC_SYNCBUSY_COMPCTRL2_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL2_Pos)) /* Assignment of value for COMPCTRL2 in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_COMPCTRL3_Pos _UINT32_(6) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Position */ -#define AC_SYNCBUSY_COMPCTRL3_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL3_Pos) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Mask */ -#define AC_SYNCBUSY_COMPCTRL3(value) (AC_SYNCBUSY_COMPCTRL3_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL3_Pos)) /* Assignment of value for COMPCTRL3 in the AC_SYNCBUSY register */ -#define AC_SYNCBUSY_Msk _UINT32_(0x0000007F) /* (AC_SYNCBUSY) Register Mask */ - -#define AC_SYNCBUSY_COMPCTRL_Pos _UINT32_(3) /* (AC_SYNCBUSY Position) COMPCTRL 3 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_UINT32_(0xF) << AC_SYNCBUSY_COMPCTRL_Pos) /* (AC_SYNCBUSY Mask) COMPCTRL */ -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) - -/* AC register offsets definitions */ -#define AC_CTRLA_REG_OFST _UINT32_(0x00) /* (AC_CTRLA) Control A Offset */ -#define AC_CTRLB_REG_OFST _UINT32_(0x01) /* (AC_CTRLB) Control B Offset */ -#define AC_EVCTRL_REG_OFST _UINT32_(0x02) /* (AC_EVCTRL) Event Control Offset */ -#define AC_INTENCLR_REG_OFST _UINT32_(0x04) /* (AC_INTENCLR) Interrupt Enable Clear Offset */ -#define AC_INTENSET_REG_OFST _UINT32_(0x05) /* (AC_INTENSET) Interrupt Enable Set Offset */ -#define AC_INTFLAG_REG_OFST _UINT32_(0x06) /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ -#define AC_STATUSA_REG_OFST _UINT32_(0x07) /* (AC_STATUSA) Status A Offset */ -#define AC_STATUSB_REG_OFST _UINT32_(0x08) /* (AC_STATUSB) Status B Offset */ -#define AC_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AC_DBGCTRL) Debug Control Offset */ -#define AC_WINCTRL_REG_OFST _UINT32_(0x0A) /* (AC_WINCTRL) Window Control Offset */ -#define AC_SCALER_REG_OFST _UINT32_(0x0C) /* (AC_SCALER) Scaler n Offset */ -#define AC_SCALER0_REG_OFST _UINT32_(0x0C) /* (AC_SCALER0) Scaler n Offset */ -#define AC_SCALER1_REG_OFST _UINT32_(0x0D) /* (AC_SCALER1) Scaler n Offset */ -#define AC_SCALER2_REG_OFST _UINT32_(0x0E) /* (AC_SCALER2) Scaler n Offset */ -#define AC_SCALER3_REG_OFST _UINT32_(0x0F) /* (AC_SCALER3) Scaler n Offset */ -#define AC_COMPCTRL_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL) Comparator Control n Offset */ -#define AC_COMPCTRL0_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL0) Comparator Control n Offset */ -#define AC_COMPCTRL1_REG_OFST _UINT32_(0x14) /* (AC_COMPCTRL1) Comparator Control n Offset */ -#define AC_COMPCTRL2_REG_OFST _UINT32_(0x18) /* (AC_COMPCTRL2) Comparator Control n Offset */ -#define AC_COMPCTRL3_REG_OFST _UINT32_(0x1C) /* (AC_COMPCTRL3) Comparator Control n Offset */ -#define AC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (AC_SYNCBUSY) Synchronization Busy Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* AC register API structure */ -typedef struct -{ /* Analog Comparators */ - __IO uint8_t AC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ - __O uint8_t AC_CTRLB; /* Offset: 0x01 ( /W 8) Control B */ - __IO uint16_t AC_EVCTRL; /* Offset: 0x02 (R/W 16) Event Control */ - __IO uint8_t AC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO uint8_t AC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO uint8_t AC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I uint8_t AC_STATUSA; /* Offset: 0x07 (R/ 8) Status A */ - __I uint8_t AC_STATUSB; /* Offset: 0x08 (R/ 8) Status B */ - __IO uint8_t AC_DBGCTRL; /* Offset: 0x09 (R/W 8) Debug Control */ - __IO uint8_t AC_WINCTRL; /* Offset: 0x0A (R/W 8) Window Control */ - __I uint8_t Reserved1[0x01]; - __IO uint8_t AC_SCALER[4]; /* Offset: 0x0C (R/W 8) Scaler n */ - __IO uint32_t AC_COMPCTRL[4]; /* Offset: 0x10 (R/W 32) Comparator Control n */ - __I uint32_t AC_SYNCBUSY; /* Offset: 0x20 (R/ 32) Synchronization Busy */ -} ac_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAMC21_AC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/adc.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/adc.h deleted file mode 100644 index 7430110c..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/adc.h +++ /dev/null @@ -1,524 +0,0 @@ -/* - * Component description for ADC - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_ADC_COMPONENT_H_ -#define _SAMC21_ADC_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR ADC */ -/* ************************************************************************** */ - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#define ADC_CTRLA_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLA) Control A Reset Value */ - -#define ADC_CTRLA_SWRST_Pos _UINT8_(0) /* (ADC_CTRLA) Software Reset Position */ -#define ADC_CTRLA_SWRST_Msk (_UINT8_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ -#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT8_(value) << ADC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_CTRLA register */ -#define ADC_CTRLA_ENABLE_Pos _UINT8_(1) /* (ADC_CTRLA) Enable Position */ -#define ADC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ -#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT8_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_CTRLA register */ -#define ADC_CTRLA_SLAVEEN_Pos _UINT8_(5) /* (ADC_CTRLA) Slave Enable Position */ -#define ADC_CTRLA_SLAVEEN_Msk (_UINT8_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ -#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT8_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assignment of value for SLAVEEN in the ADC_CTRLA register */ -#define ADC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (ADC_CTRLA) Run During Standby Position */ -#define ADC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run During Standby Mask */ -#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the ADC_CTRLA register */ -#define ADC_CTRLA_ONDEMAND_Pos _UINT8_(7) /* (ADC_CTRLA) On Demand Control Position */ -#define ADC_CTRLA_ONDEMAND_Msk (_UINT8_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ -#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT8_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assignment of value for ONDEMAND in the ADC_CTRLA register */ -#define ADC_CTRLA_Msk _UINT8_(0xE3) /* (ADC_CTRLA) Register Mask */ - - -/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ -#define ADC_CTRLB_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLB) Control B Reset Value */ - -#define ADC_CTRLB_PRESCALER_Pos _UINT8_(0) /* (ADC_CTRLB) Prescaler Configuration Position */ -#define ADC_CTRLB_PRESCALER_Msk (_UINT8_(0x7) << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Prescaler Configuration Mask */ -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & (_UINT8_(value) << ADC_CTRLB_PRESCALER_Pos)) /* Assignment of value for PRESCALER in the ADC_CTRLB register */ -#define ADC_CTRLB_PRESCALER_DIV2_Val _UINT8_(0x0) /* (ADC_CTRLB) Peripheral clock / 2 */ -#define ADC_CTRLB_PRESCALER_DIV4_Val _UINT8_(0x1) /* (ADC_CTRLB) Peripheral clock / 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val _UINT8_(0x2) /* (ADC_CTRLB) Peripheral clock / 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val _UINT8_(0x3) /* (ADC_CTRLB) Peripheral clock / 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val _UINT8_(0x4) /* (ADC_CTRLB) Peripheral clock / 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val _UINT8_(0x5) /* (ADC_CTRLB) Peripheral clock / 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val _UINT8_(0x6) /* (ADC_CTRLB) Peripheral clock / 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val _UINT8_(0x7) /* (ADC_CTRLB) Peripheral clock / 256 */ -#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 2 Position */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 4 Position */ -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 8 Position */ -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 16 Position */ -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 32 Position */ -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 64 Position */ -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 128 Position */ -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 256 Position */ -#define ADC_CTRLB_Msk _UINT8_(0x07) /* (ADC_CTRLB) Register Mask */ - - -/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ -#define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ - -#define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ -#define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assignment of value for REFSEL in the ADC_REFCTRL register */ -#define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x1) /* (ADC_REFCTRL) 1/1.6 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x3) /* (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_DAC_Val _UINT8_(0x4) /* (ADC_REFCTRL) DAC */ -#define ADC_REFCTRL_REFSEL_INTVCC2_Val _UINT8_(0x5) /* (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/1.6 VDDANA Position */ -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 VDDANA Position */ -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference Position */ -#define ADC_REFCTRL_REFSEL_DAC (ADC_REFCTRL_REFSEL_DAC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) DAC Position */ -#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) VDDANA Position */ -#define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ -#define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ -#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assignment of value for REFCOMP in the ADC_REFCTRL register */ -#define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ - - -/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ -#define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ - -#define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ -#define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ -#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assignment of value for FLUSHEI in the ADC_EVCTRL register */ -#define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ -#define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ -#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the ADC_EVCTRL register */ -#define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ -#define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ -#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assignment of value for FLUSHINV in the ADC_EVCTRL register */ -#define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Event Invert Enable Position */ -#define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Event Invert Enable Mask */ -#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assignment of value for STARTINV in the ADC_EVCTRL register */ -#define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ -#define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ -#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assignment of value for RESRDYEO in the ADC_EVCTRL register */ -#define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ -#define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ -#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assignment of value for WINMONEO in the ADC_EVCTRL register */ -#define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ - - -/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ -#define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ -#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTENCLR register */ -#define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ -#define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ -#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTENCLR register */ -#define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ -#define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ -#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTENCLR register */ -#define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ - - -/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ - -#define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ -#define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ -#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTENSET register */ -#define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ -#define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ -#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTENSET register */ -#define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ -#define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ -#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTENSET register */ -#define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ - - -/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ - -#define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ -#define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ -#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assignment of value for RESRDY in the ADC_INTFLAG register */ -#define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ -#define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ -#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assignment of value for OVERRUN in the ADC_INTFLAG register */ -#define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ -#define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ -#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assignment of value for WINMON in the ADC_INTFLAG register */ -#define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ - - -/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) ( R/ 8) Sequence Status -------- */ -#define ADC_SEQSTATUS_RESETVALUE _UINT8_(0x00) /* (ADC_SEQSTATUS) Sequence Status Reset Value */ - -#define ADC_SEQSTATUS_SEQSTATE_Pos _UINT8_(0) /* (ADC_SEQSTATUS) Sequence State Position */ -#define ADC_SEQSTATUS_SEQSTATE_Msk (_UINT8_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) /* (ADC_SEQSTATUS) Sequence State Mask */ -#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQSTATE_Pos)) /* Assignment of value for SEQSTATE in the ADC_SEQSTATUS register */ -#define ADC_SEQSTATUS_SEQBUSY_Pos _UINT8_(7) /* (ADC_SEQSTATUS) Sequence Busy Position */ -#define ADC_SEQSTATUS_SEQBUSY_Msk (_UINT8_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) /* (ADC_SEQSTATUS) Sequence Busy Mask */ -#define ADC_SEQSTATUS_SEQBUSY(value) (ADC_SEQSTATUS_SEQBUSY_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQBUSY_Pos)) /* Assignment of value for SEQBUSY in the ADC_SEQSTATUS register */ -#define ADC_SEQSTATUS_Msk _UINT8_(0x9F) /* (ADC_SEQSTATUS) Register Mask */ - - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ -#define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ - -#define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assignment of value for MUXPOS in the ADC_INPUTCTRL register */ -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _UINT16_(0x1C) /* (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC Output Position */ -#define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assignment of value for MUXNEG in the ADC_INPUTCTRL register */ -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ -#define ADC_INPUTCTRL_Msk _UINT16_(0x1F1F) /* (ADC_INPUTCTRL) Register Mask */ - - -/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ -#define ADC_CTRLC_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLC) Control C Reset Value */ - -#define ADC_CTRLC_DIFFMODE_Pos _UINT16_(0) /* (ADC_CTRLC) Differential Mode Position */ -#define ADC_CTRLC_DIFFMODE_Msk (_UINT16_(0x1) << ADC_CTRLC_DIFFMODE_Pos) /* (ADC_CTRLC) Differential Mode Mask */ -#define ADC_CTRLC_DIFFMODE(value) (ADC_CTRLC_DIFFMODE_Msk & (_UINT16_(value) << ADC_CTRLC_DIFFMODE_Pos)) /* Assignment of value for DIFFMODE in the ADC_CTRLC register */ -#define ADC_CTRLC_LEFTADJ_Pos _UINT16_(1) /* (ADC_CTRLC) Left-Adjusted Result Position */ -#define ADC_CTRLC_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLC_LEFTADJ_Pos) /* (ADC_CTRLC) Left-Adjusted Result Mask */ -#define ADC_CTRLC_LEFTADJ(value) (ADC_CTRLC_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLC_LEFTADJ_Pos)) /* Assignment of value for LEFTADJ in the ADC_CTRLC register */ -#define ADC_CTRLC_FREERUN_Pos _UINT16_(2) /* (ADC_CTRLC) Free Running Mode Position */ -#define ADC_CTRLC_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLC_FREERUN_Pos) /* (ADC_CTRLC) Free Running Mode Mask */ -#define ADC_CTRLC_FREERUN(value) (ADC_CTRLC_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLC_FREERUN_Pos)) /* Assignment of value for FREERUN in the ADC_CTRLC register */ -#define ADC_CTRLC_CORREN_Pos _UINT16_(3) /* (ADC_CTRLC) Digital Correction Logic Enable Position */ -#define ADC_CTRLC_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLC_CORREN_Pos) /* (ADC_CTRLC) Digital Correction Logic Enable Mask */ -#define ADC_CTRLC_CORREN(value) (ADC_CTRLC_CORREN_Msk & (_UINT16_(value) << ADC_CTRLC_CORREN_Pos)) /* Assignment of value for CORREN in the ADC_CTRLC register */ -#define ADC_CTRLC_RESSEL_Pos _UINT16_(4) /* (ADC_CTRLC) Conversion Result Resolution Position */ -#define ADC_CTRLC_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) Conversion Result Resolution Mask */ -#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLC_RESSEL_Pos)) /* Assignment of value for RESSEL in the ADC_CTRLC register */ -#define ADC_CTRLC_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLC) 12-bit */ -#define ADC_CTRLC_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLC) 16-bit averaging mode */ -#define ADC_CTRLC_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLC) 10-bit */ -#define ADC_CTRLC_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLC) 8-bit */ -#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 12-bit Position */ -#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 16-bit averaging mode Position */ -#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 10-bit Position */ -#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 8-bit Position */ -#define ADC_CTRLC_R2R_Pos _UINT16_(7) /* (ADC_CTRLC) Rail-to-Rail mode enable Position */ -#define ADC_CTRLC_R2R_Msk (_UINT16_(0x1) << ADC_CTRLC_R2R_Pos) /* (ADC_CTRLC) Rail-to-Rail mode enable Mask */ -#define ADC_CTRLC_R2R(value) (ADC_CTRLC_R2R_Msk & (_UINT16_(value) << ADC_CTRLC_R2R_Pos)) /* Assignment of value for R2R in the ADC_CTRLC register */ -#define ADC_CTRLC_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLC) Window Monitor Mode Position */ -#define ADC_CTRLC_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) Window Monitor Mode Mask */ -#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLC_WINMODE_Pos)) /* Assignment of value for WINMODE in the ADC_CTRLC register */ -#define ADC_CTRLC_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLC) No window mode (default) */ -#define ADC_CTRLC_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLC) RESULT > WINLT */ -#define ADC_CTRLC_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLC) RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLC) WINLT < RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) No window mode (default) Position */ -#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT > WINLT Position */ -#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT < WINUT Position */ -#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) WINLT < RESULT < WINUT Position */ -#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) Position */ -#define ADC_CTRLC_DUALSEL_Pos _UINT16_(12) /* (ADC_CTRLC) Dual Mode Trigger Selection Position */ -#define ADC_CTRLC_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Dual Mode Trigger Selection Mask */ -#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLC_DUALSEL_Pos)) /* Assignment of value for DUALSEL in the ADC_CTRLC register */ -#define ADC_CTRLC_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs Position */ -#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 Position */ -#define ADC_CTRLC_Msk _UINT16_(0x37BF) /* (ADC_CTRLC) Register Mask */ - - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ -#define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assignment of value for SAMPLENUM in the ADC_AVGCTRL register */ -#define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ -#define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ -#define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assignment of value for ADJRES in the ADC_AVGCTRL register */ -#define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ - - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ -#define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assignment of value for SAMPLEN in the ADC_SAMPCTRL register */ -#define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ -#define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ -#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assignment of value for OFFCOMP in the ADC_SAMPCTRL register */ -#define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ - - -/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ -#define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ - -#define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ -#define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_WINLT register */ -#define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ - - -/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ -#define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ - -#define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ -#define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_WINUT register */ -#define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ - - -/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ -#define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ - -#define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ -#define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_GAINCORR register */ -#define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ - - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ -#define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_OFFSETCORR register */ -#define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ - - -/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ -#define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ - -#define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Flush Position */ -#define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Flush Mask */ -#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assignment of value for FLUSH in the ADC_SWTRIG register */ -#define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ -#define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ -#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assignment of value for START in the ADC_SWTRIG register */ -#define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ - - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ -#define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ - -#define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ -#define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ -#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the ADC_DBGCTRL register */ -#define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ - - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) ( R/ 16) Synchronization Busy -------- */ -#define ADC_SYNCBUSY_RESETVALUE _UINT16_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ - -#define ADC_SYNCBUSY_SWRST_Pos _UINT16_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ -#define ADC_SYNCBUSY_SWRST_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ -#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_ENABLE_Pos _UINT16_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ -#define ADC_SYNCBUSY_ENABLE_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ -#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT16_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT16_(2) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Position */ -#define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Mask */ -#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assignment of value for INPUTCTRL in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_CTRLC_Pos _UINT16_(3) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Position */ -#define ADC_SYNCBUSY_CTRLC_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Mask */ -#define ADC_SYNCBUSY_CTRLC(value) (ADC_SYNCBUSY_CTRLC_Msk & (_UINT16_(value) << ADC_SYNCBUSY_CTRLC_Pos)) /* Assignment of value for CTRLC in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_AVGCTRL_Pos _UINT16_(4) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Position */ -#define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Mask */ -#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assignment of value for AVGCTRL in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT16_(5) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Position */ -#define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Mask */ -#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assignment of value for SAMPCTRL in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_WINLT_Pos _UINT16_(6) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Position */ -#define ADC_SYNCBUSY_WINLT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Mask */ -#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assignment of value for WINLT in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_WINUT_Pos _UINT16_(7) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Position */ -#define ADC_SYNCBUSY_WINUT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Mask */ -#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assignment of value for WINUT in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_GAINCORR_Pos _UINT16_(8) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Position */ -#define ADC_SYNCBUSY_GAINCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Mask */ -#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assignment of value for GAINCORR in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT16_(9) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Position */ -#define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Mask */ -#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assignment of value for OFFSETCORR in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_SWTRIG_Pos _UINT16_(10) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Position */ -#define ADC_SYNCBUSY_SWTRIG_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Mask */ -#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assignment of value for SWTRIG in the ADC_SYNCBUSY register */ -#define ADC_SYNCBUSY_Msk _UINT16_(0x07FF) /* (ADC_SYNCBUSY) Register Mask */ - - -/* -------- ADC_RESULT : (ADC Offset: 0x24) ( R/ 16) Result -------- */ -#define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Reset Value */ - -#define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Value Position */ -#define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Value Mask */ -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assignment of value for RESULT in the ADC_RESULT register */ -#define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ - - -/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ -#define ADC_SEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_SEQCTRL) Sequence Control Reset Value */ - -#define ADC_SEQCTRL_SEQEN_Pos _UINT32_(0) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Position */ -#define ADC_SEQCTRL_SEQEN_Msk (_UINT32_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Mask */ -#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & (_UINT32_(value) << ADC_SEQCTRL_SEQEN_Pos)) /* Assignment of value for SEQEN in the ADC_SEQCTRL register */ -#define ADC_SEQCTRL_Msk _UINT32_(0xFFFFFFFF) /* (ADC_SEQCTRL) Register Mask */ - - -/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ -#define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ - -#define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ -#define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assignment of value for BIASCOMP in the ADC_CALIB register */ -#define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ -#define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assignment of value for BIASREFBUF in the ADC_CALIB register */ -#define ADC_CALIB_Msk _UINT16_(0x0707) /* (ADC_CALIB) Register Mask */ - - -/* ADC register offsets definitions */ -#define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ -#define ADC_CTRLB_REG_OFST _UINT32_(0x01) /* (ADC_CTRLB) Control B Offset */ -#define ADC_REFCTRL_REG_OFST _UINT32_(0x02) /* (ADC_REFCTRL) Reference Control Offset */ -#define ADC_EVCTRL_REG_OFST _UINT32_(0x03) /* (ADC_EVCTRL) Event Control Offset */ -#define ADC_INTENCLR_REG_OFST _UINT32_(0x04) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ -#define ADC_INTENSET_REG_OFST _UINT32_(0x05) /* (ADC_INTENSET) Interrupt Enable Set Offset */ -#define ADC_INTFLAG_REG_OFST _UINT32_(0x06) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ -#define ADC_SEQSTATUS_REG_OFST _UINT32_(0x07) /* (ADC_SEQSTATUS) Sequence Status Offset */ -#define ADC_INPUTCTRL_REG_OFST _UINT32_(0x08) /* (ADC_INPUTCTRL) Input Control Offset */ -#define ADC_CTRLC_REG_OFST _UINT32_(0x0A) /* (ADC_CTRLC) Control C Offset */ -#define ADC_AVGCTRL_REG_OFST _UINT32_(0x0C) /* (ADC_AVGCTRL) Average Control Offset */ -#define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0D) /* (ADC_SAMPCTRL) Sample Time Control Offset */ -#define ADC_WINLT_REG_OFST _UINT32_(0x0E) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ -#define ADC_WINUT_REG_OFST _UINT32_(0x10) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ -#define ADC_GAINCORR_REG_OFST _UINT32_(0x12) /* (ADC_GAINCORR) Gain Correction Offset */ -#define ADC_OFFSETCORR_REG_OFST _UINT32_(0x14) /* (ADC_OFFSETCORR) Offset Correction Offset */ -#define ADC_SWTRIG_REG_OFST _UINT32_(0x18) /* (ADC_SWTRIG) Software Trigger Offset */ -#define ADC_DBGCTRL_REG_OFST _UINT32_(0x1C) /* (ADC_DBGCTRL) Debug Control Offset */ -#define ADC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ -#define ADC_RESULT_REG_OFST _UINT32_(0x24) /* (ADC_RESULT) Result Offset */ -#define ADC_SEQCTRL_REG_OFST _UINT32_(0x28) /* (ADC_SEQCTRL) Sequence Control Offset */ -#define ADC_CALIB_REG_OFST _UINT32_(0x2C) /* (ADC_CALIB) Calibration Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* ADC register API structure */ -typedef struct -{ /* Analog Digital Converter */ - __IO uint8_t ADC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ - __IO uint8_t ADC_CTRLB; /* Offset: 0x01 (R/W 8) Control B */ - __IO uint8_t ADC_REFCTRL; /* Offset: 0x02 (R/W 8) Reference Control */ - __IO uint8_t ADC_EVCTRL; /* Offset: 0x03 (R/W 8) Event Control */ - __IO uint8_t ADC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO uint8_t ADC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO uint8_t ADC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I uint8_t ADC_SEQSTATUS; /* Offset: 0x07 (R/ 8) Sequence Status */ - __IO uint16_t ADC_INPUTCTRL; /* Offset: 0x08 (R/W 16) Input Control */ - __IO uint16_t ADC_CTRLC; /* Offset: 0x0A (R/W 16) Control C */ - __IO uint8_t ADC_AVGCTRL; /* Offset: 0x0C (R/W 8) Average Control */ - __IO uint8_t ADC_SAMPCTRL; /* Offset: 0x0D (R/W 8) Sample Time Control */ - __IO uint16_t ADC_WINLT; /* Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ - __IO uint16_t ADC_WINUT; /* Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ - __IO uint16_t ADC_GAINCORR; /* Offset: 0x12 (R/W 16) Gain Correction */ - __IO uint16_t ADC_OFFSETCORR; /* Offset: 0x14 (R/W 16) Offset Correction */ - __I uint8_t Reserved1[0x02]; - __IO uint8_t ADC_SWTRIG; /* Offset: 0x18 (R/W 8) Software Trigger */ - __I uint8_t Reserved2[0x03]; - __IO uint8_t ADC_DBGCTRL; /* Offset: 0x1C (R/W 8) Debug Control */ - __I uint8_t Reserved3[0x03]; - __I uint16_t ADC_SYNCBUSY; /* Offset: 0x20 (R/ 16) Synchronization Busy */ - __I uint8_t Reserved4[0x02]; - __I uint16_t ADC_RESULT; /* Offset: 0x24 (R/ 16) Result */ - __I uint8_t Reserved5[0x02]; - __IO uint32_t ADC_SEQCTRL; /* Offset: 0x28 (R/W 32) Sequence Control */ - __IO uint16_t ADC_CALIB; /* Offset: 0x2C (R/W 16) Calibration */ -} adc_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAMC21_ADC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/can.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/can.h deleted file mode 100644 index f84adbc0..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/can.h +++ /dev/null @@ -1,2528 +0,0 @@ -/* - * Component description for CAN - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_CAN_COMPONENT_H_ -#define _SAMC21_CAN_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR CAN */ -/* ************************************************************************** */ - -/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ -#define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ -#define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ -#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXBE_0 register */ -#define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ -#define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ -#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXBE_0 register */ -#define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ -#define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ -#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXBE_0 register */ -#define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ -#define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ -#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXBE_0 register */ -#define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ - - -/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ -#define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ -#define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ -#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXBE_1 register */ -#define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ -#define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ -#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXBE_1 register */ -#define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ -#define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ -#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXBE_1 register */ -#define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ -#define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ -#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXBE_1 register */ -#define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ -#define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ -#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXBE_1 register */ -#define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ -#define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ -#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXBE_1 register */ -#define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ - - -/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ -#define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ -#define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ -#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXBE_DATA register */ -#define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ -#define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ -#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXBE_DATA register */ -#define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ -#define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ -#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXBE_DATA register */ -#define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ -#define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ -#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXBE_DATA register */ -#define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ - - -/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ -#define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ -#define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ -#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXF0E_0 register */ -#define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ -#define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ -#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXF0E_0 register */ -#define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ -#define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ -#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXF0E_0 register */ -#define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ -#define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ -#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXF0E_0 register */ -#define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ - - -/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ -#define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ -#define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ -#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXF0E_1 register */ -#define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ -#define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ -#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXF0E_1 register */ -#define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ -#define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ -#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXF0E_1 register */ -#define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ -#define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ -#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXF0E_1 register */ -#define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ -#define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ -#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXF0E_1 register */ -#define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ -#define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ -#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXF0E_1 register */ -#define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ - - -/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ -#define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ -#define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ -#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXF0E_DATA register */ -#define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ -#define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ -#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXF0E_DATA register */ -#define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ -#define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ -#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXF0E_DATA register */ -#define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ -#define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ -#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXF0E_DATA register */ -#define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ - - -/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ -#define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ -#define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ -#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXF1E_0 register */ -#define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ -#define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ -#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXF1E_0 register */ -#define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ -#define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ -#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXF1E_0 register */ -#define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ -#define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ -#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXF1E_0 register */ -#define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ - - -/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ -#define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ -#define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ -#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXF1E_1 register */ -#define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ -#define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ -#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXF1E_1 register */ -#define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ -#define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ -#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXF1E_1 register */ -#define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ -#define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ -#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXF1E_1 register */ -#define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ -#define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ -#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXF1E_1 register */ -#define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ -#define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ -#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXF1E_1 register */ -#define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ - - -/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ -#define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ -#define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ -#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXF1E_DATA register */ -#define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ -#define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ -#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXF1E_DATA register */ -#define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ -#define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ -#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXF1E_DATA register */ -#define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ -#define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ -#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXF1E_DATA register */ -#define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ - - -/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ -#define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ -#define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ -#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assignment of value for ID in the CAN_TXBE_0 register */ -#define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ -#define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ -#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_TXBE_0 register */ -#define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ -#define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ -#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_TXBE_0 register */ -#define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ -#define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ -#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_TXBE_0 register */ -#define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ - - -/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ -#define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ -#define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ -#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_TXBE_1 register */ -#define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ -#define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ -#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_TXBE_1 register */ -#define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ -#define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ -#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_TXBE_1 register */ -#define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ -#define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ -#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assignment of value for EFC in the CAN_TXBE_1 register */ -#define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ -#define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ -#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assignment of value for MM in the CAN_TXBE_1 register */ -#define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ - - -/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ -#define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ -#define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ -#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_TXBE_DATA register */ -#define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ -#define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ -#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_TXBE_DATA register */ -#define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ -#define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ -#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_TXBE_DATA register */ -#define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ -#define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ -#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_TXBE_DATA register */ -#define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ - - -/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ -#define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ -#define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ -#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assignment of value for ID in the CAN_TXEFE_0 register */ -#define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ -#define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ -#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_TXEFE_0 register */ -#define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ -#define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ -#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_TXEFE_0 register */ -#define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ -#define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ -#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_TXEFE_0 register */ -#define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ - - -/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ -#define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ -#define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ -#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assignment of value for TXTS in the CAN_TXEFE_1 register */ -#define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ -#define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ -#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_TXEFE_1 register */ -#define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ -#define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ -#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_TXEFE_1 register */ -#define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ -#define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ -#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_TXEFE_1 register */ -#define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ -#define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ -#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assignment of value for ET in the CAN_TXEFE_1 register */ -#define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ -#define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ -#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ -#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ -#define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ -#define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ -#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assignment of value for MM in the CAN_TXEFE_1 register */ -#define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ - - -/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ -#define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ -#define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ -#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assignment of value for SFID2 in the CAN_SIDFE_0 register */ -#define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ -#define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ -#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assignment of value for SFID1 in the CAN_SIDFE_0 register */ -#define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ -#define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ -#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assignment of value for SFEC in the CAN_SIDFE_0 register */ -#define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ -#define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ -#define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ -#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ -#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ -#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ -#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ -#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ -#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ -#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ -#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ -#define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ -#define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ -#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assignment of value for SFT in the CAN_SIDFE_0 register */ -#define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ -#define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ -#define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ -#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ -#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ -#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ -#define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ - - -/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ -#define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ -#define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ -#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assignment of value for EFID1 in the CAN_XIDFE_0 register */ -#define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ -#define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ -#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assignment of value for EFEC in the CAN_XIDFE_0 register */ -#define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ -#define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ -#define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ -#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ -#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ -#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ -#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ -#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ -#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ -#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ -#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ -#define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ - - -/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ -#define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ -#define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ -#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assignment of value for EFID2 in the CAN_XIDFE_1 register */ -#define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ -#define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ -#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assignment of value for EFT in the CAN_XIDFE_1 register */ -#define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ -#define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ -#define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ -#define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ -#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ -#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ -#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ -#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ -#define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ - - -/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ -#define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ - -#define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ -#define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ -#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assignment of value for SUBSTEP in the CAN_CREL register */ -#define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ -#define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ -#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assignment of value for STEP in the CAN_CREL register */ -#define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ -#define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ -#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assignment of value for REL in the CAN_CREL register */ -#define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ - - -/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ -#define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ - -#define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ -#define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ -#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assignment of value for ETV in the CAN_ENDN register */ -#define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ - - -/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ -#define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ - -#define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ -#define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ -#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assignment of value for QOS in the CAN_MRCFG register */ -#define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ -#define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ -#define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ -#define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ -#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ -#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ -#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ -#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ -#define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ - - -/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ -#define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ - -#define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ -#define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ -#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assignment of value for DSJW in the CAN_DBTP register */ -#define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ -#define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ -#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assignment of value for DTSEG2 in the CAN_DBTP register */ -#define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ -#define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ -#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assignment of value for DTSEG1 in the CAN_DBTP register */ -#define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ -#define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ -#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assignment of value for DBRP in the CAN_DBTP register */ -#define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ -#define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ -#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assignment of value for TDC in the CAN_DBTP register */ -#define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ - - -/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ -#define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ - -#define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ -#define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ -#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assignment of value for LBCK in the CAN_TEST register */ -#define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ -#define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ -#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assignment of value for TX in the CAN_TEST register */ -#define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ -#define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ -#define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ -#define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ -#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ -#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ -#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ -#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ -#define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ -#define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ -#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assignment of value for RX in the CAN_TEST register */ -#define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ - - -/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ -#define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ - -#define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ -#define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ -#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assignment of value for WDC in the CAN_RWD register */ -#define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ -#define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ -#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assignment of value for WDV in the CAN_RWD register */ -#define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ - - -/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ -#define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ - -#define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ -#define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ -#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assignment of value for INIT in the CAN_CCCR register */ -#define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ -#define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ -#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assignment of value for CCE in the CAN_CCCR register */ -#define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ -#define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ -#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assignment of value for ASM in the CAN_CCCR register */ -#define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ -#define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ -#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assignment of value for CSA in the CAN_CCCR register */ -#define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ -#define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ -#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assignment of value for CSR in the CAN_CCCR register */ -#define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ -#define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ -#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assignment of value for MON in the CAN_CCCR register */ -#define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ -#define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ -#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assignment of value for DAR in the CAN_CCCR register */ -#define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ -#define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ -#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assignment of value for TEST in the CAN_CCCR register */ -#define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ -#define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ -#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assignment of value for FDOE in the CAN_CCCR register */ -#define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ -#define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ -#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assignment of value for BRSE in the CAN_CCCR register */ -#define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ -#define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ -#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assignment of value for PXHD in the CAN_CCCR register */ -#define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ -#define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ -#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assignment of value for EFBI in the CAN_CCCR register */ -#define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ -#define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ -#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assignment of value for TXP in the CAN_CCCR register */ -#define CAN_CCCR_NISO_Pos _UINT32_(15) /* (CAN_CCCR) Non ISO Operation Position */ -#define CAN_CCCR_NISO_Msk (_UINT32_(0x1) << CAN_CCCR_NISO_Pos) /* (CAN_CCCR) Non ISO Operation Mask */ -#define CAN_CCCR_NISO(value) (CAN_CCCR_NISO_Msk & (_UINT32_(value) << CAN_CCCR_NISO_Pos)) /* Assignment of value for NISO in the CAN_CCCR register */ -#define CAN_CCCR_Msk _UINT32_(0x0000F3FF) /* (CAN_CCCR) Register Mask */ - - -/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ -#define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ - -#define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ -#define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ -#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assignment of value for NTSEG2 in the CAN_NBTP register */ -#define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ -#define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ -#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assignment of value for NTSEG1 in the CAN_NBTP register */ -#define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ -#define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ -#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assignment of value for NBRP in the CAN_NBTP register */ -#define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ -#define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ -#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assignment of value for NSJW in the CAN_NBTP register */ -#define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ - - -/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ -#define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ - -#define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ -#define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ -#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assignment of value for TSS in the CAN_TSCC register */ -#define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ -#define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ -#define CAN_TSCC_TSS_EXT_Val _UINT32_(0x2) /* (CAN_TSCC) External timestamp counter value used */ -#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ -#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ -#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) External timestamp counter value used Position */ -#define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ -#define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ -#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assignment of value for TCP in the CAN_TSCC register */ -#define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ - - -/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ -#define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ - -#define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ -#define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ -#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assignment of value for TSC in the CAN_TSCV register */ -#define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ - - -/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ -#define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ - -#define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ -#define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ -#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assignment of value for ETOC in the CAN_TOCC register */ -#define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ -#define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ -#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assignment of value for TOS in the CAN_TOCC register */ -#define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ -#define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ -#define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ -#define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ -#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ -#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ -#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ -#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ -#define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ -#define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ -#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assignment of value for TOP in the CAN_TOCC register */ -#define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ - - -/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ -#define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ - -#define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ -#define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ -#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assignment of value for TOC in the CAN_TOCV register */ -#define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ - - -/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ -#define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ - -#define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ -#define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ -#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assignment of value for TEC in the CAN_ECR register */ -#define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ -#define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ -#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assignment of value for REC in the CAN_ECR register */ -#define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ -#define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ -#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assignment of value for RP in the CAN_ECR register */ -#define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ -#define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ -#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assignment of value for CEL in the CAN_ECR register */ -#define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ - - -/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ -#define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ - -#define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ -#define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ -#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assignment of value for LEC in the CAN_PSR register */ -#define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ -#define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ -#define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ -#define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ -#define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ -#define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ -#define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ -#define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ -#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ -#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ -#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ -#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ -#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ -#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ -#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ -#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ -#define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ -#define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ -#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assignment of value for ACT in the CAN_PSR register */ -#define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ -#define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ -#define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ -#define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ -#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ -#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ -#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ -#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ -#define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ -#define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ -#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assignment of value for EP in the CAN_PSR register */ -#define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ -#define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ -#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assignment of value for EW in the CAN_PSR register */ -#define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ -#define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ -#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assignment of value for BO in the CAN_PSR register */ -#define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ -#define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ -#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assignment of value for DLEC in the CAN_PSR register */ -#define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ -#define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ -#define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ -#define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ -#define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ -#define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ -#define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ -#define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ -#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ -#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ -#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ -#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ -#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ -#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ -#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ -#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ -#define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ -#define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ -#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assignment of value for RESI in the CAN_PSR register */ -#define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ -#define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ -#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assignment of value for RBRS in the CAN_PSR register */ -#define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ -#define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ -#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assignment of value for RFDF in the CAN_PSR register */ -#define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ -#define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ -#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assignment of value for PXE in the CAN_PSR register */ -#define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ -#define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ -#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assignment of value for TDCV in the CAN_PSR register */ -#define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ - - -/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ -#define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ - -#define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ -#define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ -#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assignment of value for TDCF in the CAN_TDCR register */ -#define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ -#define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ -#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assignment of value for TDCO in the CAN_TDCR register */ -#define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ - - -/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ -#define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ - -#define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ -#define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ -#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assignment of value for RF0N in the CAN_IR register */ -#define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ -#define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ -#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assignment of value for RF0W in the CAN_IR register */ -#define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ -#define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ -#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assignment of value for RF0F in the CAN_IR register */ -#define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ -#define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ -#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_IR register */ -#define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ -#define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ -#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assignment of value for RF1N in the CAN_IR register */ -#define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ -#define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ -#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assignment of value for RF1W in the CAN_IR register */ -#define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ -#define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ -#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assignment of value for RF1F in the CAN_IR register */ -#define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ -#define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ -#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_IR register */ -#define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ -#define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ -#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assignment of value for HPM in the CAN_IR register */ -#define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ -#define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ -#define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assignment of value for TC in the CAN_IR register */ -#define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ -#define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ -#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assignment of value for TCF in the CAN_IR register */ -#define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ -#define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ -#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assignment of value for TFE in the CAN_IR register */ -#define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ -#define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ -#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assignment of value for TEFN in the CAN_IR register */ -#define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ -#define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ -#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assignment of value for TEFW in the CAN_IR register */ -#define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ -#define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ -#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assignment of value for TEFF in the CAN_IR register */ -#define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ -#define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ -#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_IR register */ -#define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ -#define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ -#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assignment of value for TSW in the CAN_IR register */ -#define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ -#define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ -#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assignment of value for MRAF in the CAN_IR register */ -#define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ -#define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ -#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assignment of value for TOO in the CAN_IR register */ -#define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ -#define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ -#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assignment of value for DRX in the CAN_IR register */ -#define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ -#define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ -#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assignment of value for BEC in the CAN_IR register */ -#define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ -#define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ -#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assignment of value for BEU in the CAN_IR register */ -#define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ -#define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ -#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assignment of value for ELO in the CAN_IR register */ -#define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ -#define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ -#define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assignment of value for EP in the CAN_IR register */ -#define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ -#define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ -#define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assignment of value for EW in the CAN_IR register */ -#define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ -#define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ -#define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assignment of value for BO in the CAN_IR register */ -#define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ -#define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ -#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assignment of value for WDI in the CAN_IR register */ -#define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ -#define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ -#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assignment of value for PEA in the CAN_IR register */ -#define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ -#define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ -#define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assignment of value for PED in the CAN_IR register */ -#define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ -#define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ -#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assignment of value for ARA in the CAN_IR register */ -#define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ - - -/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ -#define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ - -#define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ -#define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ -#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assignment of value for RF0NE in the CAN_IE register */ -#define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ -#define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ -#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assignment of value for RF0WE in the CAN_IE register */ -#define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ -#define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ -#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assignment of value for RF0FE in the CAN_IE register */ -#define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ -#define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ -#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assignment of value for RF0LE in the CAN_IE register */ -#define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ -#define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ -#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assignment of value for RF1NE in the CAN_IE register */ -#define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ -#define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ -#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assignment of value for RF1WE in the CAN_IE register */ -#define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ -#define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ -#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assignment of value for RF1FE in the CAN_IE register */ -#define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ -#define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ -#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assignment of value for RF1LE in the CAN_IE register */ -#define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ -#define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ -#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assignment of value for HPME in the CAN_IE register */ -#define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ -#define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ -#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assignment of value for TCE in the CAN_IE register */ -#define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ -#define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ -#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assignment of value for TCFE in the CAN_IE register */ -#define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ -#define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ -#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assignment of value for TFEE in the CAN_IE register */ -#define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ -#define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ -#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assignment of value for TEFNE in the CAN_IE register */ -#define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ -#define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ -#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assignment of value for TEFWE in the CAN_IE register */ -#define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ -#define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ -#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assignment of value for TEFFE in the CAN_IE register */ -#define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ -#define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ -#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assignment of value for TEFLE in the CAN_IE register */ -#define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ -#define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ -#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assignment of value for TSWE in the CAN_IE register */ -#define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ -#define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ -#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assignment of value for MRAFE in the CAN_IE register */ -#define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ -#define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ -#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assignment of value for TOOE in the CAN_IE register */ -#define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ -#define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ -#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assignment of value for DRXE in the CAN_IE register */ -#define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ -#define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ -#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assignment of value for BECE in the CAN_IE register */ -#define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ -#define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ -#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assignment of value for BEUE in the CAN_IE register */ -#define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ -#define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ -#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assignment of value for ELOE in the CAN_IE register */ -#define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ -#define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ -#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assignment of value for EPE in the CAN_IE register */ -#define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ -#define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ -#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assignment of value for EWE in the CAN_IE register */ -#define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ -#define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ -#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assignment of value for BOE in the CAN_IE register */ -#define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ -#define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ -#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assignment of value for WDIE in the CAN_IE register */ -#define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ -#define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ -#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assignment of value for PEAE in the CAN_IE register */ -#define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ -#define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ -#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assignment of value for PEDE in the CAN_IE register */ -#define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ -#define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ -#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assignment of value for ARAE in the CAN_IE register */ -#define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ - - -/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ -#define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ - -#define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ -#define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ -#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assignment of value for RF0NL in the CAN_ILS register */ -#define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ -#define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ -#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assignment of value for RF0WL in the CAN_ILS register */ -#define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ -#define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ -#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assignment of value for RF0FL in the CAN_ILS register */ -#define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ -#define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ -#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assignment of value for RF0LL in the CAN_ILS register */ -#define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ -#define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ -#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assignment of value for RF1NL in the CAN_ILS register */ -#define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ -#define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ -#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assignment of value for RF1WL in the CAN_ILS register */ -#define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ -#define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ -#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assignment of value for RF1FL in the CAN_ILS register */ -#define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ -#define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ -#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assignment of value for RF1LL in the CAN_ILS register */ -#define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ -#define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ -#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assignment of value for HPML in the CAN_ILS register */ -#define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ -#define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ -#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assignment of value for TCL in the CAN_ILS register */ -#define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ -#define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ -#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assignment of value for TCFL in the CAN_ILS register */ -#define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ -#define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ -#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assignment of value for TFEL in the CAN_ILS register */ -#define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ -#define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ -#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assignment of value for TEFNL in the CAN_ILS register */ -#define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ -#define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ -#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assignment of value for TEFWL in the CAN_ILS register */ -#define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ -#define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ -#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assignment of value for TEFFL in the CAN_ILS register */ -#define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ -#define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ -#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assignment of value for TEFLL in the CAN_ILS register */ -#define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ -#define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ -#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assignment of value for TSWL in the CAN_ILS register */ -#define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ -#define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ -#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assignment of value for MRAFL in the CAN_ILS register */ -#define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ -#define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ -#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assignment of value for TOOL in the CAN_ILS register */ -#define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ -#define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ -#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assignment of value for DRXL in the CAN_ILS register */ -#define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ -#define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ -#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assignment of value for BECL in the CAN_ILS register */ -#define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ -#define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ -#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assignment of value for BEUL in the CAN_ILS register */ -#define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ -#define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ -#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assignment of value for ELOL in the CAN_ILS register */ -#define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ -#define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ -#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assignment of value for EPL in the CAN_ILS register */ -#define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ -#define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ -#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assignment of value for EWL in the CAN_ILS register */ -#define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ -#define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ -#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assignment of value for BOL in the CAN_ILS register */ -#define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ -#define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ -#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assignment of value for WDIL in the CAN_ILS register */ -#define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ -#define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ -#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assignment of value for PEAL in the CAN_ILS register */ -#define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ -#define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ -#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assignment of value for PEDL in the CAN_ILS register */ -#define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ -#define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ -#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assignment of value for ARAL in the CAN_ILS register */ -#define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ - - -/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ -#define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ - -#define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ -#define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ -#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assignment of value for EINT0 in the CAN_ILE register */ -#define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ -#define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ -#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assignment of value for EINT1 in the CAN_ILE register */ -#define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ - -#define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ -#define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ -#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) - -/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ -#define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ - -#define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ -#define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ -#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assignment of value for RRFE in the CAN_GFC register */ -#define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ -#define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ -#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assignment of value for RRFS in the CAN_GFC register */ -#define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ -#define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ -#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assignment of value for ANFE in the CAN_GFC register */ -#define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ -#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ -#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ -#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ -#define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ -#define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ -#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assignment of value for ANFS in the CAN_GFC register */ -#define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ -#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ -#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ -#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ -#define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ - - -/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ -#define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ - -#define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ -#define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ -#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assignment of value for FLSSA in the CAN_SIDFC register */ -#define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ -#define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ -#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assignment of value for LSS in the CAN_SIDFC register */ -#define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ - - -/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ -#define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ - -#define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ -#define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ -#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assignment of value for FLESA in the CAN_XIDFC register */ -#define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ -#define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ -#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assignment of value for LSE in the CAN_XIDFC register */ -#define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ - - -/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ -#define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ - -#define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ -#define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ -#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assignment of value for EIDM in the CAN_XIDAM register */ -#define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ - - -/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ -#define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ - -#define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ -#define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ -#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assignment of value for BIDX in the CAN_HPMS register */ -#define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ -#define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ -#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assignment of value for MSI in the CAN_HPMS register */ -#define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ -#define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ -#define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ -#define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ -#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ -#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ -#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ -#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ -#define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ -#define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ -#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_HPMS register */ -#define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ -#define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ -#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assignment of value for FLST in the CAN_HPMS register */ -#define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ - - -/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ -#define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ - -#define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ -#define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ -#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assignment of value for ND0 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ -#define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ -#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assignment of value for ND1 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ -#define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ -#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assignment of value for ND2 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ -#define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ -#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assignment of value for ND3 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ -#define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ -#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assignment of value for ND4 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ -#define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ -#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assignment of value for ND5 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ -#define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ -#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assignment of value for ND6 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ -#define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ -#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assignment of value for ND7 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ -#define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ -#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assignment of value for ND8 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ -#define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ -#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assignment of value for ND9 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ -#define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ -#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assignment of value for ND10 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ -#define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ -#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assignment of value for ND11 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ -#define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ -#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assignment of value for ND12 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ -#define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ -#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assignment of value for ND13 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ -#define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ -#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assignment of value for ND14 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ -#define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ -#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assignment of value for ND15 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ -#define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ -#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assignment of value for ND16 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ -#define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ -#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assignment of value for ND17 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ -#define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ -#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assignment of value for ND18 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ -#define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ -#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assignment of value for ND19 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ -#define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ -#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assignment of value for ND20 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ -#define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ -#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assignment of value for ND21 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ -#define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ -#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assignment of value for ND22 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ -#define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ -#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assignment of value for ND23 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ -#define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ -#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assignment of value for ND24 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ -#define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ -#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assignment of value for ND25 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ -#define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ -#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assignment of value for ND26 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ -#define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ -#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assignment of value for ND27 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ -#define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ -#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assignment of value for ND28 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ -#define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ -#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assignment of value for ND29 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ -#define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ -#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assignment of value for ND30 in the CAN_NDAT1 register */ -#define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ -#define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ -#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assignment of value for ND31 in the CAN_NDAT1 register */ -#define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ - -#define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ -#define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ -#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) - -/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ -#define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ - -#define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ -#define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ -#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assignment of value for ND32 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ -#define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ -#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assignment of value for ND33 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ -#define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ -#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assignment of value for ND34 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ -#define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ -#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assignment of value for ND35 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ -#define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ -#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assignment of value for ND36 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ -#define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ -#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assignment of value for ND37 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ -#define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ -#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assignment of value for ND38 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ -#define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ -#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assignment of value for ND39 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ -#define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ -#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assignment of value for ND40 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ -#define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ -#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assignment of value for ND41 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ -#define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ -#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assignment of value for ND42 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ -#define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ -#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assignment of value for ND43 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ -#define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ -#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assignment of value for ND44 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ -#define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ -#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assignment of value for ND45 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ -#define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ -#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assignment of value for ND46 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ -#define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ -#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assignment of value for ND47 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ -#define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ -#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assignment of value for ND48 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ -#define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ -#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assignment of value for ND49 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ -#define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ -#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assignment of value for ND50 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ -#define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ -#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assignment of value for ND51 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ -#define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ -#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assignment of value for ND52 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ -#define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ -#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assignment of value for ND53 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ -#define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ -#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assignment of value for ND54 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ -#define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ -#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assignment of value for ND55 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ -#define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ -#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assignment of value for ND56 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ -#define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ -#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assignment of value for ND57 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ -#define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ -#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assignment of value for ND58 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ -#define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ -#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assignment of value for ND59 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ -#define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ -#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assignment of value for ND60 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ -#define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ -#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assignment of value for ND61 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ -#define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ -#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assignment of value for ND62 in the CAN_NDAT2 register */ -#define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ -#define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ -#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assignment of value for ND63 in the CAN_NDAT2 register */ -#define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ - -#define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ -#define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ -#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) - -/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ -#define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ - -#define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ -#define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ -#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assignment of value for F0SA in the CAN_RXF0C register */ -#define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ -#define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ -#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assignment of value for F0S in the CAN_RXF0C register */ -#define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ -#define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ -#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assignment of value for F0WM in the CAN_RXF0C register */ -#define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ -#define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ -#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assignment of value for F0OM in the CAN_RXF0C register */ -#define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ - - -/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ -#define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ - -#define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ -#define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ -#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assignment of value for F0FL in the CAN_RXF0S register */ -#define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ -#define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ -#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assignment of value for F0GI in the CAN_RXF0S register */ -#define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ -#define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ -#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assignment of value for F0PI in the CAN_RXF0S register */ -#define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ -#define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ -#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assignment of value for F0F in the CAN_RXF0S register */ -#define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ -#define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ -#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_RXF0S register */ -#define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ - - -/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ -#define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ - -#define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ -#define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ -#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assignment of value for F0AI in the CAN_RXF0A register */ -#define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ - - -/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ -#define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ - -#define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ -#define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ -#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assignment of value for RBSA in the CAN_RXBC register */ -#define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ - - -/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ -#define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ - -#define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ -#define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ -#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assignment of value for F1SA in the CAN_RXF1C register */ -#define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ -#define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ -#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assignment of value for F1S in the CAN_RXF1C register */ -#define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ -#define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ -#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assignment of value for F1WM in the CAN_RXF1C register */ -#define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ -#define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ -#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assignment of value for F1OM in the CAN_RXF1C register */ -#define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ - - -/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ -#define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ - -#define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ -#define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ -#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assignment of value for F1FL in the CAN_RXF1S register */ -#define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ -#define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ -#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assignment of value for F1GI in the CAN_RXF1S register */ -#define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ -#define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ -#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assignment of value for F1PI in the CAN_RXF1S register */ -#define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ -#define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ -#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assignment of value for F1F in the CAN_RXF1S register */ -#define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ -#define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ -#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_RXF1S register */ -#define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ -#define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ -#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assignment of value for DMS in the CAN_RXF1S register */ -#define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ -#define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ -#define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ -#define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ -#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ -#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ -#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ -#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ -#define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ - - -/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ -#define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ - -#define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ -#define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ -#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assignment of value for F1AI in the CAN_RXF1A register */ -#define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ - - -/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ -#define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ - -#define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ -#define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ -#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assignment of value for F0DS in the CAN_RXESC register */ -#define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ -#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ -#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ -#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ -#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ -#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ -#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ -#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ -#define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ -#define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ -#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assignment of value for F1DS in the CAN_RXESC register */ -#define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ -#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ -#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ -#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ -#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ -#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ -#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ -#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ -#define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ -#define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ -#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assignment of value for RBDS in the CAN_RXESC register */ -#define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ -#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ -#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ -#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ -#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ -#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ -#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ -#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ -#define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ - - -/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ -#define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ - -#define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ -#define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ -#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assignment of value for TBSA in the CAN_TXBC register */ -#define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ -#define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ -#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assignment of value for NDTB in the CAN_TXBC register */ -#define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ -#define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ -#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assignment of value for TFQS in the CAN_TXBC register */ -#define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ -#define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ -#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assignment of value for TFQM in the CAN_TXBC register */ -#define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ - - -/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ -#define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ - -#define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ -#define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ -#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assignment of value for TFFL in the CAN_TXFQS register */ -#define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ -#define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ -#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assignment of value for TFGI in the CAN_TXFQS register */ -#define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ -#define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ -#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assignment of value for TFQPI in the CAN_TXFQS register */ -#define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ -#define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ -#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assignment of value for TFQF in the CAN_TXFQS register */ -#define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ - - -/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ -#define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ - -#define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ -#define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ -#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assignment of value for TBDS in the CAN_TXESC register */ -#define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ -#define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ -#define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ -#define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ -#define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ -#define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ -#define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ -#define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ -#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ -#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ -#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ -#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ -#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ -#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ -#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ -#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ -#define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ - - -/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ -#define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ - -#define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ -#define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ -#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assignment of value for TRP0 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ -#define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ -#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assignment of value for TRP1 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ -#define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ -#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assignment of value for TRP2 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ -#define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ -#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assignment of value for TRP3 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ -#define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ -#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assignment of value for TRP4 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ -#define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ -#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assignment of value for TRP5 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ -#define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ -#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assignment of value for TRP6 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ -#define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ -#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assignment of value for TRP7 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ -#define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ -#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assignment of value for TRP8 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ -#define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ -#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assignment of value for TRP9 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ -#define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ -#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assignment of value for TRP10 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ -#define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ -#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assignment of value for TRP11 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ -#define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ -#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assignment of value for TRP12 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ -#define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ -#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assignment of value for TRP13 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ -#define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ -#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assignment of value for TRP14 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ -#define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ -#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assignment of value for TRP15 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ -#define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ -#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assignment of value for TRP16 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ -#define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ -#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assignment of value for TRP17 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ -#define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ -#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assignment of value for TRP18 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ -#define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ -#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assignment of value for TRP19 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ -#define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ -#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assignment of value for TRP20 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ -#define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ -#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assignment of value for TRP21 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ -#define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ -#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assignment of value for TRP22 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ -#define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ -#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assignment of value for TRP23 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ -#define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ -#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assignment of value for TRP24 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ -#define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ -#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assignment of value for TRP25 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ -#define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ -#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assignment of value for TRP26 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ -#define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ -#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assignment of value for TRP27 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ -#define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ -#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assignment of value for TRP28 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ -#define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ -#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assignment of value for TRP29 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ -#define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ -#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assignment of value for TRP30 in the CAN_TXBRP register */ -#define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ -#define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ -#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assignment of value for TRP31 in the CAN_TXBRP register */ -#define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ - -#define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ -#define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ -#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) - -/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ -#define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ - -#define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ -#define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ -#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assignment of value for AR0 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ -#define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ -#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assignment of value for AR1 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ -#define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ -#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assignment of value for AR2 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ -#define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ -#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assignment of value for AR3 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ -#define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ -#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assignment of value for AR4 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ -#define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ -#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assignment of value for AR5 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ -#define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ -#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assignment of value for AR6 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ -#define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ -#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assignment of value for AR7 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ -#define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ -#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assignment of value for AR8 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ -#define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ -#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assignment of value for AR9 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ -#define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ -#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assignment of value for AR10 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ -#define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ -#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assignment of value for AR11 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ -#define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ -#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assignment of value for AR12 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ -#define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ -#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assignment of value for AR13 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ -#define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ -#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assignment of value for AR14 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ -#define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ -#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assignment of value for AR15 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ -#define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ -#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assignment of value for AR16 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ -#define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ -#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assignment of value for AR17 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ -#define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ -#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assignment of value for AR18 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ -#define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ -#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assignment of value for AR19 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ -#define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ -#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assignment of value for AR20 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ -#define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ -#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assignment of value for AR21 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ -#define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ -#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assignment of value for AR22 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ -#define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ -#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assignment of value for AR23 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ -#define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ -#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assignment of value for AR24 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ -#define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ -#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assignment of value for AR25 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ -#define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ -#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assignment of value for AR26 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ -#define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ -#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assignment of value for AR27 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ -#define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ -#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assignment of value for AR28 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ -#define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ -#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assignment of value for AR29 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ -#define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ -#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assignment of value for AR30 in the CAN_TXBAR register */ -#define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ -#define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ -#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assignment of value for AR31 in the CAN_TXBAR register */ -#define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ - -#define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ -#define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ -#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) - -/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ -#define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ - -#define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ -#define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ -#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assignment of value for CR0 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ -#define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ -#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assignment of value for CR1 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ -#define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ -#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assignment of value for CR2 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ -#define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ -#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assignment of value for CR3 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ -#define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ -#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assignment of value for CR4 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ -#define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ -#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assignment of value for CR5 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ -#define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ -#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assignment of value for CR6 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ -#define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ -#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assignment of value for CR7 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ -#define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ -#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assignment of value for CR8 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ -#define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ -#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assignment of value for CR9 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ -#define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ -#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assignment of value for CR10 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ -#define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ -#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assignment of value for CR11 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ -#define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ -#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assignment of value for CR12 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ -#define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ -#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assignment of value for CR13 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ -#define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ -#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assignment of value for CR14 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ -#define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ -#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assignment of value for CR15 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ -#define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ -#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assignment of value for CR16 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ -#define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ -#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assignment of value for CR17 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ -#define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ -#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assignment of value for CR18 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ -#define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ -#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assignment of value for CR19 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ -#define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ -#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assignment of value for CR20 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ -#define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ -#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assignment of value for CR21 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ -#define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ -#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assignment of value for CR22 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ -#define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ -#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assignment of value for CR23 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ -#define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ -#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assignment of value for CR24 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ -#define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ -#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assignment of value for CR25 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ -#define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ -#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assignment of value for CR26 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ -#define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ -#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assignment of value for CR27 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ -#define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ -#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assignment of value for CR28 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ -#define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ -#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assignment of value for CR29 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ -#define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ -#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assignment of value for CR30 in the CAN_TXBCR register */ -#define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ -#define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ -#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assignment of value for CR31 in the CAN_TXBCR register */ -#define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ - -#define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ -#define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ -#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) - -/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ -#define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ - -#define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ -#define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ -#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assignment of value for TO0 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ -#define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ -#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assignment of value for TO1 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ -#define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ -#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assignment of value for TO2 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ -#define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ -#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assignment of value for TO3 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ -#define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ -#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assignment of value for TO4 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ -#define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ -#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assignment of value for TO5 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ -#define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ -#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assignment of value for TO6 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ -#define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ -#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assignment of value for TO7 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ -#define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ -#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assignment of value for TO8 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ -#define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ -#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assignment of value for TO9 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ -#define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ -#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assignment of value for TO10 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ -#define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ -#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assignment of value for TO11 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ -#define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ -#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assignment of value for TO12 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ -#define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ -#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assignment of value for TO13 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ -#define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ -#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assignment of value for TO14 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ -#define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ -#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assignment of value for TO15 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ -#define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ -#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assignment of value for TO16 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ -#define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ -#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assignment of value for TO17 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ -#define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ -#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assignment of value for TO18 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ -#define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ -#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assignment of value for TO19 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ -#define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ -#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assignment of value for TO20 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ -#define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ -#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assignment of value for TO21 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ -#define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ -#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assignment of value for TO22 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ -#define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ -#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assignment of value for TO23 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ -#define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ -#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assignment of value for TO24 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ -#define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ -#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assignment of value for TO25 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ -#define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ -#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assignment of value for TO26 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ -#define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ -#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assignment of value for TO27 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ -#define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ -#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assignment of value for TO28 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ -#define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ -#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assignment of value for TO29 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ -#define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ -#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assignment of value for TO30 in the CAN_TXBTO register */ -#define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ -#define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ -#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assignment of value for TO31 in the CAN_TXBTO register */ -#define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ - -#define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ -#define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ -#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) - -/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ -#define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ - -#define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ -#define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ -#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assignment of value for CF0 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ -#define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ -#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assignment of value for CF1 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ -#define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ -#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assignment of value for CF2 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ -#define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ -#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assignment of value for CF3 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ -#define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ -#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assignment of value for CF4 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ -#define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ -#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assignment of value for CF5 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ -#define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ -#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assignment of value for CF6 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ -#define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ -#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assignment of value for CF7 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ -#define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ -#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assignment of value for CF8 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ -#define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ -#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assignment of value for CF9 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ -#define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ -#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assignment of value for CF10 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ -#define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ -#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assignment of value for CF11 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ -#define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ -#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assignment of value for CF12 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ -#define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ -#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assignment of value for CF13 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ -#define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ -#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assignment of value for CF14 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ -#define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ -#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assignment of value for CF15 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ -#define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ -#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assignment of value for CF16 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ -#define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ -#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assignment of value for CF17 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ -#define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ -#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assignment of value for CF18 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ -#define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ -#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assignment of value for CF19 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ -#define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ -#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assignment of value for CF20 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ -#define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ -#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assignment of value for CF21 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ -#define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ -#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assignment of value for CF22 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ -#define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ -#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assignment of value for CF23 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ -#define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ -#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assignment of value for CF24 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ -#define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ -#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assignment of value for CF25 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ -#define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ -#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assignment of value for CF26 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ -#define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ -#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assignment of value for CF27 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ -#define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ -#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assignment of value for CF28 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ -#define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ -#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assignment of value for CF29 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ -#define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ -#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assignment of value for CF30 in the CAN_TXBCF register */ -#define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ -#define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ -#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assignment of value for CF31 in the CAN_TXBCF register */ -#define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ - -#define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ -#define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ -#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) - -/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ -#define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ - -#define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ -#define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ -#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assignment of value for TIE0 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ -#define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ -#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assignment of value for TIE1 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ -#define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ -#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assignment of value for TIE2 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ -#define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ -#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assignment of value for TIE3 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ -#define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ -#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assignment of value for TIE4 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ -#define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ -#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assignment of value for TIE5 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ -#define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ -#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assignment of value for TIE6 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ -#define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ -#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assignment of value for TIE7 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ -#define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ -#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assignment of value for TIE8 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ -#define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ -#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assignment of value for TIE9 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ -#define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ -#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assignment of value for TIE10 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ -#define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ -#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assignment of value for TIE11 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ -#define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ -#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assignment of value for TIE12 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ -#define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ -#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assignment of value for TIE13 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ -#define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ -#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assignment of value for TIE14 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ -#define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ -#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assignment of value for TIE15 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ -#define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ -#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assignment of value for TIE16 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ -#define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ -#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assignment of value for TIE17 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ -#define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ -#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assignment of value for TIE18 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ -#define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ -#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assignment of value for TIE19 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ -#define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ -#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assignment of value for TIE20 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ -#define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ -#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assignment of value for TIE21 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ -#define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ -#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assignment of value for TIE22 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ -#define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ -#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assignment of value for TIE23 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ -#define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ -#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assignment of value for TIE24 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ -#define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ -#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assignment of value for TIE25 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ -#define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ -#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assignment of value for TIE26 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ -#define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ -#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assignment of value for TIE27 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ -#define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ -#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assignment of value for TIE28 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ -#define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ -#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assignment of value for TIE29 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ -#define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ -#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assignment of value for TIE30 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ -#define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ -#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assignment of value for TIE31 in the CAN_TXBTIE register */ -#define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ - -#define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ -#define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ -#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) - -/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ -#define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ - -#define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ -#define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ -#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assignment of value for CFIE0 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ -#define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ -#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assignment of value for CFIE1 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ -#define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ -#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assignment of value for CFIE2 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ -#define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ -#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assignment of value for CFIE3 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ -#define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ -#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assignment of value for CFIE4 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ -#define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ -#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assignment of value for CFIE5 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ -#define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ -#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assignment of value for CFIE6 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ -#define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ -#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assignment of value for CFIE7 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ -#define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ -#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assignment of value for CFIE8 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ -#define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ -#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assignment of value for CFIE9 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ -#define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ -#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assignment of value for CFIE10 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ -#define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ -#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assignment of value for CFIE11 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ -#define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ -#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assignment of value for CFIE12 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ -#define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ -#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assignment of value for CFIE13 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ -#define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ -#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assignment of value for CFIE14 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ -#define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ -#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assignment of value for CFIE15 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ -#define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ -#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assignment of value for CFIE16 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ -#define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ -#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assignment of value for CFIE17 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ -#define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ -#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assignment of value for CFIE18 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ -#define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ -#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assignment of value for CFIE19 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ -#define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ -#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assignment of value for CFIE20 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ -#define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ -#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assignment of value for CFIE21 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ -#define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ -#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assignment of value for CFIE22 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ -#define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ -#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assignment of value for CFIE23 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ -#define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ -#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assignment of value for CFIE24 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ -#define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ -#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assignment of value for CFIE25 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ -#define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ -#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assignment of value for CFIE26 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ -#define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ -#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assignment of value for CFIE27 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ -#define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ -#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assignment of value for CFIE28 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ -#define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ -#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assignment of value for CFIE29 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ -#define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ -#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assignment of value for CFIE30 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ -#define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ -#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assignment of value for CFIE31 in the CAN_TXBCIE register */ -#define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ - -#define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ -#define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ -#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) - -/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ -#define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ - -#define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ -#define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ -#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assignment of value for EFSA in the CAN_TXEFC register */ -#define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ -#define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ -#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assignment of value for EFS in the CAN_TXEFC register */ -#define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ -#define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ -#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assignment of value for EFWM in the CAN_TXEFC register */ -#define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ - - -/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ -#define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ - -#define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ -#define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ -#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assignment of value for EFFL in the CAN_TXEFS register */ -#define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ -#define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ -#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assignment of value for EFGI in the CAN_TXEFS register */ -#define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ -#define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ -#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assignment of value for EFPI in the CAN_TXEFS register */ -#define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ -#define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ -#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assignment of value for EFF in the CAN_TXEFS register */ -#define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ -#define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ -#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_TXEFS register */ -#define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ - - -/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ -#define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ - -#define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ -#define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ -#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assignment of value for EFAI in the CAN_TXEFA register */ -#define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ - - -/* CAN register offsets definitions */ -#define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ -#define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ -#define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ -#define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ -#define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ -#define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ -#define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ -#define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ -#define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ -#define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ -#define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ -#define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ -#define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ -#define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ -#define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ -#define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ -#define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ -#define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ -#define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ -#define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ -#define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ -#define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ -#define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ -#define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ -#define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ -#define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ -#define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ -#define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ -#define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ -#define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ -#define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ -#define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ -#define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ -#define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ -#define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ -#define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ -#define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ -#define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ -#define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ -#define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ -#define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ -#define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ -#define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ -#define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ -#define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ -#define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ -#define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ -#define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ -#define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ -#define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ -#define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ -#define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ -#define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ -#define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ -#define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ -#define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ -#define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ -#define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ -#define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ -#define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ -#define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ -#define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ -#define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ -#define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* CAN_RXBE register API structure */ -typedef struct -{ /* Rx Buffer Element */ - __IO uint32_t CAN_RXBE_0; /* Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ - __IO uint32_t CAN_RXBE_1; /* Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ - __IO uint32_t CAN_RXBE_DATA; /* Offset: 0x08 (R/W 32) Rx Buffer Element Data */ -} can_rxbe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN_RXF0E register API structure */ -typedef struct -{ /* Rx FIFO 0 Element */ - __IO uint32_t CAN_RXF0E_0; /* Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ - __IO uint32_t CAN_RXF0E_1; /* Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ - __IO uint32_t CAN_RXF0E_DATA; /* Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ -} can_rxf0e_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN_RXF1E register API structure */ -typedef struct -{ /* Rx FIFO 1 Element */ - __IO uint32_t CAN_RXF1E_0; /* Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ - __IO uint32_t CAN_RXF1E_1; /* Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ - __IO uint32_t CAN_RXF1E_DATA; /* Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ -} can_rxf1e_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN_TXBE register API structure */ -typedef struct -{ /* Tx Buffer Element */ - __IO uint32_t CAN_TXBE_0; /* Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ - __IO uint32_t CAN_TXBE_1; /* Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ - __IO uint32_t CAN_TXBE_DATA; /* Offset: 0x08 (R/W 32) Tx Buffer Element Data */ -} can_txbe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN_TXEFE register API structure */ -typedef struct -{ /* Tx Event FIFO Element */ - __IO uint32_t CAN_TXEFE_0; /* Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ - __IO uint32_t CAN_TXEFE_1; /* Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ -} can_txefe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN_SIDFE register API structure */ -typedef struct -{ /* Standard Message ID Filter Element */ - __IO uint32_t CAN_SIDFE_0; /* Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ -} can_sidfe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN_XIDFE register API structure */ -typedef struct -{ /* Extended Message ID Filter Element */ - __IO uint32_t CAN_XIDFE_0; /* Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ - __IO uint32_t CAN_XIDFE_1; /* Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ -} can_xidfe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/* CAN register API structure */ -typedef struct -{ /* Control Area Network */ - __I uint32_t CAN_CREL; /* Offset: 0x00 (R/ 32) Core Release */ - __I uint32_t CAN_ENDN; /* Offset: 0x04 (R/ 32) Endian */ - __IO uint32_t CAN_MRCFG; /* Offset: 0x08 (R/W 32) Message RAM Configuration */ - __IO uint32_t CAN_DBTP; /* Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ - __IO uint32_t CAN_TEST; /* Offset: 0x10 (R/W 32) Test */ - __IO uint32_t CAN_RWD; /* Offset: 0x14 (R/W 32) RAM Watchdog */ - __IO uint32_t CAN_CCCR; /* Offset: 0x18 (R/W 32) CC Control */ - __IO uint32_t CAN_NBTP; /* Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ - __IO uint32_t CAN_TSCC; /* Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ - __I uint32_t CAN_TSCV; /* Offset: 0x24 (R/ 32) Timestamp Counter Value */ - __IO uint32_t CAN_TOCC; /* Offset: 0x28 (R/W 32) Timeout Counter Configuration */ - __IO uint32_t CAN_TOCV; /* Offset: 0x2C (R/W 32) Timeout Counter Value */ - __I uint8_t Reserved1[0x10]; - __I uint32_t CAN_ECR; /* Offset: 0x40 (R/ 32) Error Counter */ - __I uint32_t CAN_PSR; /* Offset: 0x44 (R/ 32) Protocol Status */ - __IO uint32_t CAN_TDCR; /* Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ - __I uint8_t Reserved2[0x04]; - __IO uint32_t CAN_IR; /* Offset: 0x50 (R/W 32) Interrupt */ - __IO uint32_t CAN_IE; /* Offset: 0x54 (R/W 32) Interrupt Enable */ - __IO uint32_t CAN_ILS; /* Offset: 0x58 (R/W 32) Interrupt Line Select */ - __IO uint32_t CAN_ILE; /* Offset: 0x5C (R/W 32) Interrupt Line Enable */ - __I uint8_t Reserved3[0x20]; - __IO uint32_t CAN_GFC; /* Offset: 0x80 (R/W 32) Global Filter Configuration */ - __IO uint32_t CAN_SIDFC; /* Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ - __IO uint32_t CAN_XIDFC; /* Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ - __I uint8_t Reserved4[0x04]; - __IO uint32_t CAN_XIDAM; /* Offset: 0x90 (R/W 32) Extended ID AND Mask */ - __I uint32_t CAN_HPMS; /* Offset: 0x94 (R/ 32) High Priority Message Status */ - __IO uint32_t CAN_NDAT1; /* Offset: 0x98 (R/W 32) New Data 1 */ - __IO uint32_t CAN_NDAT2; /* Offset: 0x9C (R/W 32) New Data 2 */ - __IO uint32_t CAN_RXF0C; /* Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ - __I uint32_t CAN_RXF0S; /* Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ - __IO uint32_t CAN_RXF0A; /* Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ - __IO uint32_t CAN_RXBC; /* Offset: 0xAC (R/W 32) Rx Buffer Configuration */ - __IO uint32_t CAN_RXF1C; /* Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ - __I uint32_t CAN_RXF1S; /* Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ - __IO uint32_t CAN_RXF1A; /* Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ - __IO uint32_t CAN_RXESC; /* Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ - __IO uint32_t CAN_TXBC; /* Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ - __I uint32_t CAN_TXFQS; /* Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ - __IO uint32_t CAN_TXESC; /* Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ - __I uint32_t CAN_TXBRP; /* Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ - __IO uint32_t CAN_TXBAR; /* Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ - __IO uint32_t CAN_TXBCR; /* Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ - __I uint32_t CAN_TXBTO; /* Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ - __I uint32_t CAN_TXBCF; /* Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ - __IO uint32_t CAN_TXBTIE; /* Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ - __IO uint32_t CAN_TXBCIE; /* Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ - __I uint8_t Reserved5[0x08]; - __IO uint32_t CAN_TXEFC; /* Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ - __I uint32_t CAN_TXEFS; /* Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ - __IO uint32_t CAN_TXEFA; /* Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ -} can_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAMC21_CAN_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ccl.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ccl.h deleted file mode 100644 index 19211ee3..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/ccl.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Component description for CCL - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_CCL_COMPONENT_H_ -#define _SAMC21_CCL_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR CCL */ -/* ************************************************************************** */ - -/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ -#define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ - -#define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ -#define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ -#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assignment of value for SWRST in the CCL_CTRL register */ -#define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ -#define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ -#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ -#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ -#define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ -#define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ -#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the CCL_CTRL register */ -#define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ -#define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ -#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ -#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ -#define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ -#define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ -#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the CCL_CTRL register */ -#define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ -#define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ -#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ -#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ -#define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ - - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ -#define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ - -#define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ -#define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assignment of value for SEQSEL in the CCL_SEQCTRL register */ -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ -#define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ - - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ -#define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ - -#define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ -#define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ -#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assignment of value for ENABLE in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ -#define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ -#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ -#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ -#define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ -#define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assignment of value for FILTSEL in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ -#define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ -#define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ -#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assignment of value for EDGESEL in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ -#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ -#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ -#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ -#define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ -#define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assignment of value for INSEL0 in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ -#define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ -#define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assignment of value for INSEL1 in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ -#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ -#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ -#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ -#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ -#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ -#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ -#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ -#define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ -#define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assignment of value for INSEL2 in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ -#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ -#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ -#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ -#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ -#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ -#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ -#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ -#define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ -#define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ -#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assignment of value for INVEI in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ -#define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ -#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ -#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ -#define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ -#define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ -#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assignment of value for LUTEI in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ -#define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ -#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ -#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ -#define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ -#define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ -#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assignment of value for LUTEO in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ -#define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ -#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ -#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ -#define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ -#define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assignment of value for TRUTH in the CCL_LUTCTRL register */ -#define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ - - -/* CCL register offsets definitions */ -#define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ -#define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ -#define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ -#define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ -#define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ -#define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ -#define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ -#define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ -#define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* CCL register API structure */ -typedef struct -{ /* Configurable Custom Logic */ - __IO uint8_t CCL_CTRL; /* Offset: 0x00 (R/W 8) Control */ - __I uint8_t Reserved1[0x03]; - __IO uint8_t CCL_SEQCTRL[2]; /* Offset: 0x04 (R/W 8) SEQ Control x */ - __I uint8_t Reserved2[0x02]; - __IO uint32_t CCL_LUTCTRL[4]; /* Offset: 0x08 (R/W 32) LUT Control x */ -} ccl_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAMC21_CCL_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dac.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dac.h deleted file mode 100644 index f55c9482..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dac.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Component description for DAC - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_DAC_COMPONENT_H_ -#define _SAMC21_DAC_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR DAC */ -/* ************************************************************************** */ - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ - -#define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ -#define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ -#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assignment of value for SWRST in the DAC_CTRLA register */ -#define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable Position */ -#define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable Mask */ -#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_CTRLA register */ -#define DAC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (DAC_CTRLA) Run in Standby Position */ -#define DAC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) /* (DAC_CTRLA) Run in Standby Mask */ -#define DAC_CTRLA_RUNSTDBY(value) (DAC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << DAC_CTRLA_RUNSTDBY_Pos)) /* Assignment of value for RUNSTDBY in the DAC_CTRLA register */ -#define DAC_CTRLA_Msk _UINT8_(0x43) /* (DAC_CTRLA) Register Mask */ - - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#define DAC_CTRLB_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLB) Control B Reset Value */ - -#define DAC_CTRLB_EOEN_Pos _UINT8_(0) /* (DAC_CTRLB) External Output Enable Position */ -#define DAC_CTRLB_EOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_EOEN_Pos) /* (DAC_CTRLB) External Output Enable Mask */ -#define DAC_CTRLB_EOEN(value) (DAC_CTRLB_EOEN_Msk & (_UINT8_(value) << DAC_CTRLB_EOEN_Pos)) /* Assignment of value for EOEN in the DAC_CTRLB register */ -#define DAC_CTRLB_IOEN_Pos _UINT8_(1) /* (DAC_CTRLB) Internal Output Enable Position */ -#define DAC_CTRLB_IOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_IOEN_Pos) /* (DAC_CTRLB) Internal Output Enable Mask */ -#define DAC_CTRLB_IOEN(value) (DAC_CTRLB_IOEN_Msk & (_UINT8_(value) << DAC_CTRLB_IOEN_Pos)) /* Assignment of value for IOEN in the DAC_CTRLB register */ -#define DAC_CTRLB_LEFTADJ_Pos _UINT8_(2) /* (DAC_CTRLB) Left Adjusted Data Position */ -#define DAC_CTRLB_LEFTADJ_Msk (_UINT8_(0x1) << DAC_CTRLB_LEFTADJ_Pos) /* (DAC_CTRLB) Left Adjusted Data Mask */ -#define DAC_CTRLB_LEFTADJ(value) (DAC_CTRLB_LEFTADJ_Msk & (_UINT8_(value) << DAC_CTRLB_LEFTADJ_Pos)) /* Assignment of value for LEFTADJ in the DAC_CTRLB register */ -#define DAC_CTRLB_VPD_Pos _UINT8_(3) /* (DAC_CTRLB) Voltage Pump Disable Position */ -#define DAC_CTRLB_VPD_Msk (_UINT8_(0x1) << DAC_CTRLB_VPD_Pos) /* (DAC_CTRLB) Voltage Pump Disable Mask */ -#define DAC_CTRLB_VPD(value) (DAC_CTRLB_VPD_Msk & (_UINT8_(value) << DAC_CTRLB_VPD_Pos)) /* Assignment of value for VPD in the DAC_CTRLB register */ -#define DAC_CTRLB_DITHER_Pos _UINT8_(5) /* (DAC_CTRLB) Dither Enable Position */ -#define DAC_CTRLB_DITHER_Msk (_UINT8_(0x1) << DAC_CTRLB_DITHER_Pos) /* (DAC_CTRLB) Dither Enable Mask */ -#define DAC_CTRLB_DITHER(value) (DAC_CTRLB_DITHER_Msk & (_UINT8_(value) << DAC_CTRLB_DITHER_Pos)) /* Assignment of value for DITHER in the DAC_CTRLB register */ -#define DAC_CTRLB_REFSEL_Pos _UINT8_(6) /* (DAC_CTRLB) Reference Selection Position */ -#define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection Mask */ -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assignment of value for REFSEL in the DAC_CTRLB register */ -#define DAC_CTRLB_REFSEL_INT1V_Val _UINT8_(0x0) /* (DAC_CTRLB) Internal 1.0V reference */ -#define DAC_CTRLB_REFSEL_AVCC_Val _UINT8_(0x1) /* (DAC_CTRLB) AVCC */ -#define DAC_CTRLB_REFSEL_VREFP_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference */ -#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal 1.0V reference Position */ -#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) AVCC Position */ -#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference Position */ -#define DAC_CTRLB_Msk _UINT8_(0xEF) /* (DAC_CTRLB) Register Mask */ - - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ - -#define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input Position */ -#define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL) Start Conversion Event Input Mask */ -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) /* Assignment of value for STARTEI in the DAC_EVCTRL register */ -#define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(1) /* (DAC_EVCTRL) Data Buffer Empty Event Output Position */ -#define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output Mask */ -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) /* Assignment of value for EMPTYEO in the DAC_EVCTRL register */ -#define DAC_EVCTRL_INVEI_Pos _UINT8_(2) /* (DAC_EVCTRL) Invert Event Input Position */ -#define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL) Invert Event Input Mask */ -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) /* Assignment of value for INVEI in the DAC_EVCTRL register */ -#define DAC_EVCTRL_Msk _UINT8_(0x07) /* (DAC_EVCTRL) Register Mask */ - - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun Interrupt Enable Position */ -#define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR) Underrun Interrupt Enable Mask */ -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) /* Assignment of value for UNDERRUN in the DAC_INTENCLR register */ -#define DAC_INTENCLR_EMPTY_Pos _UINT8_(1) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Position */ -#define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Mask */ -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) /* Assignment of value for EMPTY in the DAC_INTENCLR register */ -#define DAC_INTENCLR_Msk _UINT8_(0x03) /* (DAC_INTENCLR) Register Mask */ - - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ - -#define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun Interrupt Enable Position */ -#define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET) Underrun Interrupt Enable Mask */ -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) /* Assignment of value for UNDERRUN in the DAC_INTENSET register */ -#define DAC_INTENSET_EMPTY_Pos _UINT8_(1) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Position */ -#define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Mask */ -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) /* Assignment of value for EMPTY in the DAC_INTENSET register */ -#define DAC_INTENSET_Msk _UINT8_(0x03) /* (DAC_INTENSET) Register Mask */ - - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ - -#define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG) Underrun Position */ -#define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG) Underrun Mask */ -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) /* Assignment of value for UNDERRUN in the DAC_INTFLAG register */ -#define DAC_INTFLAG_EMPTY_Pos _UINT8_(1) /* (DAC_INTFLAG) Data Buffer Empty Position */ -#define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG) Data Buffer Empty Mask */ -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) /* Assignment of value for EMPTY in the DAC_INTFLAG register */ -#define DAC_INTFLAG_Msk _UINT8_(0x03) /* (DAC_INTFLAG) Register Mask */ - - -/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ -#define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ - -#define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS) Ready Position */ -#define DAC_STATUS_READY_Msk (_UINT8_(0x1) << DAC_STATUS_READY_Pos) /* (DAC_STATUS) Ready Mask */ -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) /* Assignment of value for READY in the DAC_STATUS register */ -#define DAC_STATUS_Msk _UINT8_(0x01) /* (DAC_STATUS) Register Mask */ - - -/* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */ -#define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) Data Reset Value */ - -#define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) Data value to be converted Position */ -#define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) Data value to be converted Mask */ -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assignment of value for DATA in the DAC_DATA register */ -#define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ - - -/* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */ -#define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) Data Buffer Reset Value */ - -#define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) Data Buffer Position */ -#define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) Data Buffer Mask */ -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assignment of value for DATABUF in the DAC_DATABUF register */ -#define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ - - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) ( R/ 32) Synchronization Busy -------- */ -#define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ - -#define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ -#define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ -#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assignment of value for SWRST in the DAC_SYNCBUSY register */ -#define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) Enable Position */ -#define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) Enable Mask */ -#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assignment of value for ENABLE in the DAC_SYNCBUSY register */ -#define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data Position */ -#define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY) Data Mask */ -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) /* Assignment of value for DATA in the DAC_SYNCBUSY register */ -#define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data Buffer Position */ -#define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY) Data Buffer Mask */ -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) /* Assignment of value for DATABUF in the DAC_SYNCBUSY register */ -#define DAC_SYNCBUSY_Msk _UINT32_(0x0000000F) /* (DAC_SYNCBUSY) Register Mask */ - - -/* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */ -#define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ - -#define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ -#define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ -#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assignment of value for DBGRUN in the DAC_DBGCTRL register */ -#define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ - - -/* DAC register offsets definitions */ -#define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ -#define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ -#define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ -#define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ -#define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ -#define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ -#define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ -#define DAC_DATA_REG_OFST _UINT32_(0x08) /* (DAC_DATA) Data Offset */ -#define DAC_DATABUF_REG_OFST _UINT32_(0x0C) /* (DAC_DATABUF) Data Buffer Offset */ -#define DAC_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ -#define DAC_DBGCTRL_REG_OFST _UINT32_(0x14) /* (DAC_DBGCTRL) Debug Control Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* DAC register API structure */ -typedef struct -{ /* Digital Analog Converter */ - __IO uint8_t DAC_CTRLA; /* Offset: 0x00 (R/W 8) Control A */ - __IO uint8_t DAC_CTRLB; /* Offset: 0x01 (R/W 8) Control B */ - __IO uint8_t DAC_EVCTRL; /* Offset: 0x02 (R/W 8) Event Control */ - __I uint8_t Reserved1[0x01]; - __IO uint8_t DAC_INTENCLR; /* Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO uint8_t DAC_INTENSET; /* Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO uint8_t DAC_INTFLAG; /* Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I uint8_t DAC_STATUS; /* Offset: 0x07 (R/ 8) Status */ - __O uint16_t DAC_DATA; /* Offset: 0x08 ( /W 16) Data */ - __I uint8_t Reserved2[0x02]; - __O uint16_t DAC_DATABUF; /* Offset: 0x0C ( /W 16) Data Buffer */ - __I uint8_t Reserved3[0x02]; - __I uint32_t DAC_SYNCBUSY; /* Offset: 0x10 (R/ 32) Synchronization Busy */ - __IO uint8_t DAC_DBGCTRL; /* Offset: 0x14 (R/W 8) Debug Control */ -} dac_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAMC21_DAC_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/divas.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/divas.h deleted file mode 100644 index 82413246..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/divas.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Component description for DIVAS - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_DIVAS_COMPONENT_H_ -#define _SAMC21_DIVAS_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR DIVAS */ -/* ************************************************************************** */ - -/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */ -#define DIVAS_CTRLA_RESETVALUE _UINT8_(0x00) /* (DIVAS_CTRLA) Control Reset Value */ - -#define DIVAS_CTRLA_SIGNED_Pos _UINT8_(0) /* (DIVAS_CTRLA) Signed Position */ -#define DIVAS_CTRLA_SIGNED_Msk (_UINT8_(0x1) << DIVAS_CTRLA_SIGNED_Pos) /* (DIVAS_CTRLA) Signed Mask */ -#define DIVAS_CTRLA_SIGNED(value) (DIVAS_CTRLA_SIGNED_Msk & (_UINT8_(value) << DIVAS_CTRLA_SIGNED_Pos)) /* Assignment of value for SIGNED in the DIVAS_CTRLA register */ -#define DIVAS_CTRLA_DLZ_Pos _UINT8_(1) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Position */ -#define DIVAS_CTRLA_DLZ_Msk (_UINT8_(0x1) << DIVAS_CTRLA_DLZ_Pos) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Mask */ -#define DIVAS_CTRLA_DLZ(value) (DIVAS_CTRLA_DLZ_Msk & (_UINT8_(value) << DIVAS_CTRLA_DLZ_Pos)) /* Assignment of value for DLZ in the DIVAS_CTRLA register */ -#define DIVAS_CTRLA_Msk _UINT8_(0x03) /* (DIVAS_CTRLA) Register Mask */ - - -/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */ -#define DIVAS_STATUS_RESETVALUE _UINT8_(0x00) /* (DIVAS_STATUS) Status Reset Value */ - -#define DIVAS_STATUS_BUSY_Pos _UINT8_(0) /* (DIVAS_STATUS) DIVAS Accelerator Busy Position */ -#define DIVAS_STATUS_BUSY_Msk (_UINT8_(0x1) << DIVAS_STATUS_BUSY_Pos) /* (DIVAS_STATUS) DIVAS Accelerator Busy Mask */ -#define DIVAS_STATUS_BUSY(value) (DIVAS_STATUS_BUSY_Msk & (_UINT8_(value) << DIVAS_STATUS_BUSY_Pos)) /* Assignment of value for BUSY in the DIVAS_STATUS register */ -#define DIVAS_STATUS_DBZ_Pos _UINT8_(1) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Position */ -#define DIVAS_STATUS_DBZ_Msk (_UINT8_(0x1) << DIVAS_STATUS_DBZ_Pos) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Mask */ -#define DIVAS_STATUS_DBZ(value) (DIVAS_STATUS_DBZ_Msk & (_UINT8_(value) << DIVAS_STATUS_DBZ_Pos)) /* Assignment of value for DBZ in the DIVAS_STATUS register */ -#define DIVAS_STATUS_Msk _UINT8_(0x03) /* (DIVAS_STATUS) Register Mask */ - - -/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */ -#define DIVAS_DIVIDEND_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVIDEND) Dividend Reset Value */ - -#define DIVAS_DIVIDEND_DIVIDEND_Pos _UINT32_(0) /* (DIVAS_DIVIDEND) DIVIDEND Position */ -#define DIVAS_DIVIDEND_DIVIDEND_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos) /* (DIVAS_DIVIDEND) DIVIDEND Mask */ -#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & (_UINT32_(value) << DIVAS_DIVIDEND_DIVIDEND_Pos)) /* Assignment of value for DIVIDEND in the DIVAS_DIVIDEND register */ -#define DIVAS_DIVIDEND_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVIDEND) Register Mask */ - - -/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */ -#define DIVAS_DIVISOR_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVISOR) Divisor Reset Value */ - -#define DIVAS_DIVISOR_DIVISOR_Pos _UINT32_(0) /* (DIVAS_DIVISOR) DIVISOR Position */ -#define DIVAS_DIVISOR_DIVISOR_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos) /* (DIVAS_DIVISOR) DIVISOR Mask */ -#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & (_UINT32_(value) << DIVAS_DIVISOR_DIVISOR_Pos)) /* Assignment of value for DIVISOR in the DIVAS_DIVISOR register */ -#define DIVAS_DIVISOR_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVISOR) Register Mask */ - - -/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) ( R/ 32) Result -------- */ -#define DIVAS_RESULT_RESETVALUE _UINT32_(0x00) /* (DIVAS_RESULT) Result Reset Value */ - -#define DIVAS_RESULT_RESULT_Pos _UINT32_(0) /* (DIVAS_RESULT) RESULT Position */ -#define DIVAS_RESULT_RESULT_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos) /* (DIVAS_RESULT) RESULT Mask */ -#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & (_UINT32_(value) << DIVAS_RESULT_RESULT_Pos)) /* Assignment of value for RESULT in the DIVAS_RESULT register */ -#define DIVAS_RESULT_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_RESULT) Register Mask */ - - -/* -------- DIVAS_REM : (DIVAS Offset: 0x14) ( R/ 32) Remainder -------- */ -#define DIVAS_REM_RESETVALUE _UINT32_(0x00) /* (DIVAS_REM) Remainder Reset Value */ - -#define DIVAS_REM_REM_Pos _UINT32_(0) /* (DIVAS_REM) REM Position */ -#define DIVAS_REM_REM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_REM_REM_Pos) /* (DIVAS_REM) REM Mask */ -#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & (_UINT32_(value) << DIVAS_REM_REM_Pos)) /* Assignment of value for REM in the DIVAS_REM register */ -#define DIVAS_REM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_REM) Register Mask */ - - -/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */ -#define DIVAS_SQRNUM_RESETVALUE _UINT32_(0x00) /* (DIVAS_SQRNUM) Square Root Input Reset Value */ - -#define DIVAS_SQRNUM_SQRNUM_Pos _UINT32_(0) /* (DIVAS_SQRNUM) Square Root Input Position */ -#define DIVAS_SQRNUM_SQRNUM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos) /* (DIVAS_SQRNUM) Square Root Input Mask */ -#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & (_UINT32_(value) << DIVAS_SQRNUM_SQRNUM_Pos)) /* Assignment of value for SQRNUM in the DIVAS_SQRNUM register */ -#define DIVAS_SQRNUM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_SQRNUM) Register Mask */ - - -/* DIVAS register offsets definitions */ -#define DIVAS_CTRLA_REG_OFST _UINT32_(0x00) /* (DIVAS_CTRLA) Control Offset */ -#define DIVAS_STATUS_REG_OFST _UINT32_(0x04) /* (DIVAS_STATUS) Status Offset */ -#define DIVAS_DIVIDEND_REG_OFST _UINT32_(0x08) /* (DIVAS_DIVIDEND) Dividend Offset */ -#define DIVAS_DIVISOR_REG_OFST _UINT32_(0x0C) /* (DIVAS_DIVISOR) Divisor Offset */ -#define DIVAS_RESULT_REG_OFST _UINT32_(0x10) /* (DIVAS_RESULT) Result Offset */ -#define DIVAS_REM_REG_OFST _UINT32_(0x14) /* (DIVAS_REM) Remainder Offset */ -#define DIVAS_SQRNUM_REG_OFST _UINT32_(0x18) /* (DIVAS_SQRNUM) Square Root Input Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* DIVAS register API structure */ -typedef struct -{ /* Divide and Square Root Accelerator */ - __IO uint8_t DIVAS_CTRLA; /* Offset: 0x00 (R/W 8) Control */ - __I uint8_t Reserved1[0x03]; - __IO uint8_t DIVAS_STATUS; /* Offset: 0x04 (R/W 8) Status */ - __I uint8_t Reserved2[0x03]; - __IO uint32_t DIVAS_DIVIDEND; /* Offset: 0x08 (R/W 32) Dividend */ - __IO uint32_t DIVAS_DIVISOR; /* Offset: 0x0C (R/W 32) Divisor */ - __I uint32_t DIVAS_RESULT; /* Offset: 0x10 (R/ 32) Result */ - __I uint32_t DIVAS_REM; /* Offset: 0x14 (R/ 32) Remainder */ - __IO uint32_t DIVAS_SQRNUM; /* Offset: 0x18 (R/W 32) Square Root Input */ -} divas_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAMC21_DIVAS_COMPONENT_H_ */ diff --git a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dmac.h b/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dmac.h deleted file mode 100644 index 0a4a8640..00000000 --- a/bms/bms/bms_config_e18a/src/packs/ATSAMC21E18A_DFP/component/dmac.h +++ /dev/null @@ -1,883 +0,0 @@ -/* - * Component description for DMAC - * - * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* file generated from device description file (ATDF) version 2025-06-24T07:32:57Z */ -#ifndef _SAMC21_DMAC_COMPONENT_H_ -#define _SAMC21_DMAC_COMPONENT_H_ - -#include "core_cm0plus.h" - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR DMAC */ -/* ************************************************************************** */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#define DMAC_BTCTRL_RESETVALUE _UINT16_(0x00) /* (DMAC_BTCTRL) Block Transfer Control Reset Value */ - -#define DMAC_BTCTRL_VALID_Pos _UINT16_(0) /* (DMAC_BTCTRL) Descriptor Valid Position */ -#define DMAC_BTCTRL_VALID_Msk (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos) /* (DMAC_BTCTRL) Descriptor Valid Mask */ -#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assignment of value for VALID in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_EVOSEL_Pos _UINT16_(1) /* (DMAC_BTCTRL) Event Output Selection Position */ -#define DMAC_BTCTRL_EVOSEL_Msk (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event Output Selection Mask */ -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assignment of value for EVOSEL in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */ -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when block transfer complete Position */ -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when beat transfer complete Position */ -#define DMAC_BTCTRL_BLOCKACT_Pos _UINT16_(3) /* (DMAC_BTCTRL) Block Action Position */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Block Action Mask */ -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assignment of value for BLOCKACT in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _UINT16_(0x2) /* (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */ -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ -#define DMAC_BTCTRL_BEATSIZE_Pos _UINT16_(8) /* (DMAC_BTCTRL) Beat Size Position */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) Beat Size Mask */ -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assignment of value for BEATSIZE in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _UINT16_(0x1) /* (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _UINT16_(0x2) /* (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */ -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */ -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */ -#define DMAC_BTCTRL_SRCINC_Pos _UINT16_(10) /* (DMAC_BTCTRL) Source Address Increment Enable Position */ -#define DMAC_BTCTRL_SRCINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /* (DMAC_BTCTRL) Source Address Increment Enable Mask */ -#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assignment of value for SRCINC in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_DSTINC_Pos _UINT16_(11) /* (DMAC_BTCTRL) Destination Address Increment Enable Position */ -#define DMAC_BTCTRL_DSTINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */ -#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assignment of value for DSTINC in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_STEPSEL_Pos _UINT16_(12) /* (DMAC_BTCTRL) Step Selection Position */ -#define DMAC_BTCTRL_STEPSEL_Msk (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step Selection Mask */ -#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assignment of value for STEPSEL in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_STEPSEL_DST_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */ -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */ -#define DMAC_BTCTRL_STEPSIZE_Pos _UINT16_(13) /* (DMAC_BTCTRL) Address Increment Step Size Position */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Address Increment Step Size Mask */ -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assignment of value for STEPSIZE in the DMAC_BTCTRL register */ -#define DMAC_BTCTRL_STEPSIZE_X1_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Next ADDR = ADDR + (1< -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !defined(SKIP_INTEGER_LITERALS) -# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) -# error "Integer constant value macros already defined elsewhere" -# endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with sizes of integer constants for C/C++ */ -# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ -# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ -# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ - -#else /* Assembler */ - -# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ -# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ -# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* Interrupt Number Definition */ -typedef enum IRQn -{ -/****** CORTEX-M0PLUS Processor Exceptions Numbers ******************************/ - Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /* -2 Pendable request for system service */ - SysTick_IRQn = -1, /* -1 System Tick Timer */ - -/* ***************** SAMC21E18A specific Interrupt Numbers ****************** */ - MCLK_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (MCLK) */ - OSC32KCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSC32KCTRL) */ - OSCCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSCCTRL) */ - PAC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (PAC) */ - SUPC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (SUPC) */ - WDT_IRQn = 1, /* 1 Watchdog Timer (WDT) */ - RTC_IRQn = 2, /* 2 Real-Time Counter (RTC) */ - EIC_IRQn = 3, /* 3 External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /* 4 Frequency Meter (FREQM) */ - TSENS_IRQn = 5, /* 5 Temperature Sensor (TSENS) */ - NVMCTRL_IRQn = 6, /* 6 Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /* 7 Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /* 8 Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /* 9 Serial Communication Interface (SERCOM0) */ - SERCOM1_IRQn = 10, /* 10 Serial Communication Interface (SERCOM1) */ - SERCOM2_IRQn = 11, /* 11 Serial Communication Interface (SERCOM2) */ - SERCOM3_IRQn = 12, /* 12 Serial Communication Interface (SERCOM3) */ - CAN0_IRQn = 15, /* 15 Control Area Network (CAN0) */ - TCC0_IRQn = 17, /* 17 Timer Counter Control (TCC0) */ - TCC1_IRQn = 18, /* 18 Timer Counter Control (TCC1) */ - TCC2_IRQn = 19, /* 19 Timer Counter Control (TCC2) */ - TC0_IRQn = 20, /* 20 Basic Timer Counter (TC0) */ - TC1_IRQn = 21, /* 21 Basic Timer Counter (TC1) */ - TC2_IRQn = 22, /* 22 Basic Timer Counter (TC2) */ - TC3_IRQn = 23, /* 23 Basic Timer Counter (TC3) */ - TC4_IRQn = 24, /* 24 Basic Timer Counter (TC4) */ - ADC0_IRQn = 25, /* 25 Analog Digital Converter (ADC0) */ - ADC1_IRQn = 26, /* 26 Analog Digital Converter (ADC1) */ - AC_IRQn = 27, /* 27 Analog Comparators (AC) */ - DAC_IRQn = 28, /* 28 Digital Analog Converter (DAC) */ - SDADC_IRQn = 29, /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ - PTC_IRQn = 30, /* 30 Peripheral Touch Controller (PTC) */ - - PERIPH_MAX_IRQn = 30 /* Max peripheral ID */ -} IRQn_Type; -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - /* CORTEX-M0PLUS handlers */ - void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ - void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ - void* pvReservedC12; - void* pvReservedC11; - void* pvReservedC10; - void* pvReservedC9; - void* pvReservedC8; - void* pvReservedC7; - void* pvReservedC6; - void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ - void* pvReservedC4; - void* pvReservedC3; - void* pfnPendSV_Handler; /* -2 Pendable request for system service */ - void* pfnSysTick_Handler; /* -1 System Tick Timer */ - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt (MCLK OSCCTRL OSC32KCTRL PAC SUPC) */ - void* pfnWDT_Handler; /* 1 Watchdog Timer (WDT) */ - void* pfnRTC_Handler; /* 2 Real-Time Counter (RTC) */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller (EIC) */ - void* pfnFREQM_Handler; /* 4 Frequency Meter (FREQM) */ - void* pfnTSENS_Handler; /* 5 Temperature Sensor (TSENS) */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller (DMAC) */ - void* pfnEVSYS_Handler; /* 8 Event System Interface (EVSYS) */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface (SERCOM3) */ - void* pvReserved13; - void* pvReserved14; - void* pfnCAN0_Handler; /* 15 Control Area Network (CAN0) */ - void* pvReserved16; - void* pfnTCC0_Handler; /* 17 Timer Counter Control (TCC0) */ - void* pfnTCC1_Handler; /* 18 Timer Counter Control (TCC1) */ - void* pfnTCC2_Handler; /* 19 Timer Counter Control (TCC2) */ - void* pfnTC0_Handler; /* 20 Basic Timer Counter (TC0) */ - void* pfnTC1_Handler; /* 21 Basic Timer Counter (TC1) */ - void* pfnTC2_Handler; /* 22 Basic Timer Counter (TC2) */ - void* pfnTC3_Handler; /* 23 Basic Timer Counter (TC3) */ - void* pfnTC4_Handler; /* 24 Basic Timer Counter (TC4) */ - void* pfnADC0_Handler; /* 25 Analog Digital Converter (ADC0) */ - void* pfnADC1_Handler; /* 26 Analog Digital Converter (ADC1) */ - void* pfnAC_Handler; /* 27 Analog Comparators (AC) */ - void* pfnDAC_Handler; /* 28 Digital Analog Converter (DAC) */ - void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ - void* pfnPTC_Handler; /* 30 Peripheral Touch Controller (PTC) */ -} DeviceVectors; - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS -/* CORTEX-M0PLUS exception handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ - -#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -/* Peripherals interrupt handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void TSENS_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void CAN0_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC0_Handler ( void ); -void ADC1_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void SDADC_Handler ( void ); -void PTC_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* Configuration of the CORTEX-M0PLUS Processor and Core Peripherals */ -#define __CM0PLUS_REV 0x0001 /* Cortex-M0+ Core Revision */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __ARCH_ARM 1 -#define __ARCH_ARM_CORTEX_M 1 - -/* CMSIS includes */ -#include "core_cm0plus.h" -#if defined USE_CMSIS_INIT -#include "system_samc21e18a.h" -#endif /* USE_CMSIS_INIT */ - -/* ************************************************************************** */ -/* SOFTWARE PERIPHERAL API DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#include "component/ac.h" -#include "component/adc.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/divas.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/fuses.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/osc32kctrl.h" -#include "component/oscctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/ptc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdadc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/tsens.h" -#include "component/wdt.h" - -/* ************************************************************************** */ -/* INSTANCE DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/can0.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/divas.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/fuses.h" -#include "instance/gclk.h" -#include "instance/hmatrixhs.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/oscctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdadc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tsens.h" -#include "instance/wdt.h" - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#define ID_PAC ( 0) /* Peripheral Access Controller (PAC) */ -#define ID_PM ( 1) /* Power Manager (PM) */ -#define ID_MCLK ( 2) /* Main Clock (MCLK) */ -#define ID_RSTC ( 3) /* Reset Controller (RSTC) */ -#define ID_OSCCTRL ( 4) /* Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL ( 5) /* 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC ( 6) /* Supply Controller (SUPC) */ -#define ID_GCLK ( 7) /* Generic Clock Generator (GCLK) */ -#define ID_WDT ( 8) /* Watchdog Timer (WDT) */ -#define ID_RTC ( 9) /* Real-Time Counter (RTC) */ -#define ID_EIC ( 10) /* External Interrupt Controller (EIC) */ -#define ID_FREQM ( 11) /* Frequency Meter (FREQM) */ -#define ID_TSENS ( 12) /* Temperature Sensor (TSENS) */ -#define ID_PORT ( 32) /* Port Module (PORT) */ -#define ID_DSU ( 33) /* Device Service Unit (DSU) */ -#define ID_NVMCTRL ( 34) /* Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_DMAC ( 35) /* Direct Memory Access Controller (DMAC) */ -#define ID_MTB ( 36) /* Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_HMATRIXHS ( 37) /* HSB Matrix (HMATRIXHS) */ -#define ID_EVSYS ( 64) /* Event System Interface (EVSYS) */ -#define ID_SERCOM0 ( 65) /* Serial Communication Interface (SERCOM0) */ -#define ID_SERCOM1 ( 66) /* Serial Communication Interface (SERCOM1) */ -#define ID_SERCOM2 ( 67) /* Serial Communication Interface (SERCOM2) */ -#define ID_SERCOM3 ( 68) /* Serial Communication Interface (SERCOM3) */ -#define ID_CAN0 ( 71) /* Control Area Network (CAN0) */ -#define ID_TCC0 ( 73) /* Timer Counter Control (TCC0) */ -#define ID_TCC1 ( 74) /* Timer Counter Control (TCC1) */ -#define ID_TCC2 ( 75) /* Timer Counter Control (TCC2) */ -#define ID_TC0 ( 76) /* Basic Timer Counter (TC0) */ -#define ID_TC1 ( 77) /* Basic Timer Counter (TC1) */ -#define ID_TC2 ( 78) /* Basic Timer Counter (TC2) */ -#define ID_TC3 ( 79) /* Basic Timer Counter (TC3) */ -#define ID_TC4 ( 80) /* Basic Timer Counter (TC4) */ -#define ID_ADC0 ( 81) /* Analog Digital Converter (ADC0) */ -#define ID_ADC1 ( 82) /* Analog Digital Converter (ADC1) */ -#define ID_SDADC ( 83) /* Sigma-Delta Analog Digital Converter (SDADC) */ -#define ID_AC ( 84) /* Analog Comparators (AC) */ -#define ID_DAC ( 85) /* Digital Analog Converter (DAC) */ -#define ID_PTC ( 86) /* Peripheral Touch Controller (PTC) */ -#define ID_CCL ( 87) /* Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_MAX ( 87) /* Number of peripheral IDs */ - -/* ************************************************************************** */ -/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#define AC_REGS ((ac_registers_t*)0x42005000) /* AC Registers Address */ -#define ADC0_REGS ((adc_registers_t*)0x42004400) /* ADC0 Registers Address */ -#define ADC1_REGS ((adc_registers_t*)0x42004800) /* ADC1 Registers Address */ -#define CAN0_REGS ((can_registers_t*)0x42001c00) /* CAN0 Registers Address */ -#define CCL_REGS ((ccl_registers_t*)0x42005c00) /* CCL Registers Address */ -#define DAC_REGS ((dac_registers_t*)0x42005400) /* DAC Registers Address */ -#define DIVAS_REGS ((divas_registers_t*)0x48000000) /* DIVAS Registers Address */ -#define DMAC_REGS ((dmac_registers_t*)0x41006000) /* DMAC Registers Address */ -#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ -#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ -#define EVSYS_REGS ((evsys_registers_t*)0x42000000) /* EVSYS Registers Address */ -#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ -#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ -#define HMATRIXHS_REGS ((hmatrixb_registers_t*)0x4100a000) /* HMATRIXHS Registers Address */ -#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ -#define MTB_REGS ((mtb_registers_t*)0x41008000) /* MTB Registers Address */ -#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ -#define OTP5_FUSES_REGS ((fuses_otp5_fuses_registers_t*)0x00806020) /* FUSES Registers Address */ -#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00806030) /* FUSES Registers Address */ -#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ -#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ -#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ -#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ -#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ -#define PORT_REGS ((port_registers_t*)0x41000000) /* PORT Registers Address */ -#define PORT_IOBUS_REGS ((port_registers_t*)0x60000000) /* PORT Registers Address */ -#define PTC_REGS ((ptc_registers_t*)0x42005800) /* PTC Registers Address */ -#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ -#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ -#define SDADC_REGS ((sdadc_registers_t*)0x42004c00) /* SDADC Registers Address */ -#define SERCOM0_REGS ((sercom_registers_t*)0x42000400) /* SERCOM0 Registers Address */ -#define SERCOM1_REGS ((sercom_registers_t*)0x42000800) /* SERCOM1 Registers Address */ -#define SERCOM2_REGS ((sercom_registers_t*)0x42000c00) /* SERCOM2 Registers Address */ -#define SERCOM3_REGS ((sercom_registers_t*)0x42001000) /* SERCOM3 Registers Address */ -#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ -#define TC0_REGS ((tc_registers_t*)0x42003000) /* TC0 Registers Address */ -#define TC1_REGS ((tc_registers_t*)0x42003400) /* TC1 Registers Address */ -#define TC2_REGS ((tc_registers_t*)0x42003800) /* TC2 Registers Address */ -#define TC3_REGS ((tc_registers_t*)0x42003c00) /* TC3 Registers Address */ -#define TC4_REGS ((tc_registers_t*)0x42004000) /* TC4 Registers Address */ -#define TCC0_REGS ((tcc_registers_t*)0x42002400) /* TCC0 Registers Address */ -#define TCC1_REGS ((tcc_registers_t*)0x42002800) /* TCC1 Registers Address */ -#define TCC2_REGS ((tcc_registers_t*)0x42002c00) /* TCC2 Registers Address */ -#define TSENS_REGS ((tsens_registers_t*)0x40003000) /* TSENS Registers Address */ -#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ -#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#define AC_BASE_ADDRESS _UINT32_(0x42005000) /* AC Base Address */ -#define ADC0_BASE_ADDRESS _UINT32_(0x42004400) /* ADC0 Base Address */ -#define ADC1_BASE_ADDRESS _UINT32_(0x42004800) /* ADC1 Base Address */ -#define CAN0_BASE_ADDRESS _UINT32_(0x42001c00) /* CAN0 Base Address */ -#define CCL_BASE_ADDRESS _UINT32_(0x42005c00) /* CCL Base Address */ -#define DAC_BASE_ADDRESS _UINT32_(0x42005400) /* DAC Base Address */ -#define DIVAS_BASE_ADDRESS _UINT32_(0x48000000) /* DIVAS Base Address */ -#define DMAC_BASE_ADDRESS _UINT32_(0x41006000) /* DMAC Base Address */ -#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ -#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ -#define EVSYS_BASE_ADDRESS _UINT32_(0x42000000) /* EVSYS Base Address */ -#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ -#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ -#define HMATRIXHS_BASE_ADDRESS _UINT32_(0x4100a000) /* HMATRIXHS Base Address */ -#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ -#define MTB_BASE_ADDRESS _UINT32_(0x41008000) /* MTB Base Address */ -#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ -#define OTP5_FUSES_BASE_ADDRESS _UINT32_(0x00806020) /* FUSES Base Address */ -#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00806030) /* FUSES Base Address */ -#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ -#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ -#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ -#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ -#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ -#define PORT_BASE_ADDRESS _UINT32_(0x41000000) /* PORT Base Address */ -#define PORT_IOBUS_BASE_ADDRESS _UINT32_(0x60000000) /* PORT Base Address */ -#define PTC_BASE_ADDRESS _UINT32_(0x42005800) /* PTC Base Address */ -#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ -#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ -#define SDADC_BASE_ADDRESS _UINT32_(0x42004c00) /* SDADC Base Address */ -#define SERCOM0_BASE_ADDRESS _UINT32_(0x42000400) /* SERCOM0 Base Address */ -#define SERCOM1_BASE_ADDRESS _UINT32_(0x42000800) /* SERCOM1 Base Address */ -#define SERCOM2_BASE_ADDRESS _UINT32_(0x42000c00) /* SERCOM2 Base Address */ -#define SERCOM3_BASE_ADDRESS _UINT32_(0x42001000) /* SERCOM3 Base Address */ -#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ -#define TC0_BASE_ADDRESS _UINT32_(0x42003000) /* TC0 Base Address */ -#define TC1_BASE_ADDRESS _UINT32_(0x42003400) /* TC1 Base Address */ -#define TC2_BASE_ADDRESS _UINT32_(0x42003800) /* TC2 Base Address */ -#define TC3_BASE_ADDRESS _UINT32_(0x42003c00) /* TC3 Base Address */ -#define TC4_BASE_ADDRESS _UINT32_(0x42004000) /* TC4 Base Address */ -#define TCC0_BASE_ADDRESS _UINT32_(0x42002400) /* TCC0 Base Address */ -#define TCC1_BASE_ADDRESS _UINT32_(0x42002800) /* TCC1 Base Address */ -#define TCC2_BASE_ADDRESS _UINT32_(0x42002c00) /* TCC2 Base Address */ -#define TSENS_BASE_ADDRESS _UINT32_(0x40003000) /* TSENS Base Address */ -#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#include "pio/samc21e18a.h" - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ -#define FLASH_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: flash */ -#define FLASH_PAGE_SIZE _UINT32_( 64) -#define FLASH_NB_OF_PAGES _UINT32_( 4096) - -#define OTP5_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ -#define USER_PAGE_SIZE _UINT32_(0x00000100) /* 0kB Memory segment type: user_page */ -#define USER_PAGE_PAGE_SIZE _UINT32_( 64) -#define USER_PAGE_NB_OF_PAGES _UINT32_( 4) - -#define RWW_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: flash */ -#define RWW_PAGE_SIZE _UINT32_( 64) -#define RWW_NB_OF_PAGES _UINT32_( 128) - -#define HSRAM_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ -#define HPB0_SIZE _UINT32_(0x00004000) /* 16kB Memory segment type: io */ -#define HPB1_SIZE _UINT32_(0x00010000) /* 64kB Memory segment type: io */ -#define HPB2_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: io */ -#define DIVAS_SIZE _UINT32_(0x00000020) /* 0kB Memory segment type: io */ -#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ -#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ -#define PERIPHERALS_SIZE _UINT32_(0x20000000) /* 524288kB Memory segment type: io */ - -#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ -#define OTP5_ADDR _UINT32_(0x00806020) /* OTP5 base address (type: fuses)*/ -#define TEMP_LOG_ADDR _UINT32_(0x00806030) /* TEMP_LOG base address (type: fuses)*/ -#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ -#define RWW_ADDR _UINT32_(0x00400000) /* RWW base address (type: flash)*/ -#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ -#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ -#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ -#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ -#define DIVAS_ADDR _UINT32_(0x48000000) /* DIVAS base address (type: io)*/ -#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ -#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ -#define PERIPHERALS_ADDR _UINT32_(0x40000000) /* PERIPHERALS base address (type: io)*/ - -/* ************************************************************************** */ -/* DEVICE SIGNATURES FOR SAMC21E18A */ -/* ************************************************************************** */ -#define CHIP_DSU_DID _UINT32_(0X1101050A) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAMC21E18A */ -/* ************************************************************************** */ - -/* ************************************************************************** */ -/* Event Generator IDs for SAMC21E18A */ -/* ************************************************************************** */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL 1 /* ID for OSCCTRL event generator XOSC_FAIL */ -#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ -#define EVENT_ID_GEN_RTC_CMP_0 3 /* ID for RTC event generator CMP_0 */ -#define EVENT_ID_GEN_RTC_CMP_1 4 /* ID for RTC event generator CMP_1 */ -#define EVENT_ID_GEN_RTC_OVF 5 /* ID for RTC event generator OVF */ -#define EVENT_ID_GEN_RTC_PER_0 6 /* ID for RTC event generator PER_0 */ -#define EVENT_ID_GEN_RTC_PER_1 7 /* ID for RTC event generator PER_1 */ -#define EVENT_ID_GEN_RTC_PER_2 8 /* ID for RTC event generator PER_2 */ -#define EVENT_ID_GEN_RTC_PER_3 9 /* ID for RTC event generator PER_3 */ -#define EVENT_ID_GEN_RTC_PER_4 10 /* ID for RTC event generator PER_4 */ -#define EVENT_ID_GEN_RTC_PER_5 11 /* ID for RTC event generator PER_5 */ -#define EVENT_ID_GEN_RTC_PER_6 12 /* ID for RTC event generator PER_6 */ -#define EVENT_ID_GEN_RTC_PER_7 13 /* ID for RTC event generator PER_7 */ -#define EVENT_ID_GEN_EIC_EXTINT_0 14 /* ID for EIC event generator EXTINT_0 */ -#define EVENT_ID_GEN_EIC_EXTINT_1 15 /* ID for EIC event generator EXTINT_1 */ -#define EVENT_ID_GEN_EIC_EXTINT_2 16 /* ID for EIC event generator EXTINT_2 */ -#define EVENT_ID_GEN_EIC_EXTINT_3 17 /* ID for EIC event generator EXTINT_3 */ -#define EVENT_ID_GEN_EIC_EXTINT_4 18 /* ID for EIC event generator EXTINT_4 */ -#define EVENT_ID_GEN_EIC_EXTINT_5 19 /* ID for EIC event generator EXTINT_5 */ -#define EVENT_ID_GEN_EIC_EXTINT_6 20 /* ID for EIC event generator EXTINT_6 */ -#define EVENT_ID_GEN_EIC_EXTINT_7 21 /* ID for EIC event generator EXTINT_7 */ -#define EVENT_ID_GEN_EIC_EXTINT_8 22 /* ID for EIC event generator EXTINT_8 */ -#define EVENT_ID_GEN_EIC_EXTINT_9 23 /* ID for EIC event generator EXTINT_9 */ -#define EVENT_ID_GEN_EIC_EXTINT_10 24 /* ID for EIC event generator EXTINT_10 */ -#define EVENT_ID_GEN_EIC_EXTINT_11 25 /* ID for EIC event generator EXTINT_11 */ -#define EVENT_ID_GEN_EIC_EXTINT_12 26 /* ID for EIC event generator EXTINT_12 */ -#define EVENT_ID_GEN_EIC_EXTINT_13 27 /* ID for EIC event generator EXTINT_13 */ -#define EVENT_ID_GEN_EIC_EXTINT_14 28 /* ID for EIC event generator EXTINT_14 */ -#define EVENT_ID_GEN_EIC_EXTINT_15 29 /* ID for EIC event generator EXTINT_15 */ -#define EVENT_ID_GEN_TSENS_WINMON 30 /* ID for TSENS event generator WINMON */ -#define EVENT_ID_GEN_DMAC_CH_0 31 /* ID for DMAC event generator CH_0 */ -#define EVENT_ID_GEN_DMAC_CH_1 32 /* ID for DMAC event generator CH_1 */ -#define EVENT_ID_GEN_DMAC_CH_2 33 /* ID for DMAC event generator CH_2 */ -#define EVENT_ID_GEN_DMAC_CH_3 34 /* ID for DMAC event generator CH_3 */ -#define EVENT_ID_GEN_TCC0_OVF 35 /* ID for TCC0 event generator OVF */ -#define EVENT_ID_GEN_TCC0_TRG 36 /* ID for TCC0 event generator TRG */ -#define EVENT_ID_GEN_TCC0_CNT 37 /* ID for TCC0 event generator CNT */ -#define EVENT_ID_GEN_TCC0_MC_0 38 /* ID for TCC0 event generator MC_0 */ -#define EVENT_ID_GEN_TCC0_MC_1 39 /* ID for TCC0 event generator MC_1 */ -#define EVENT_ID_GEN_TCC0_MC_2 40 /* ID for TCC0 event generator MC_2 */ -#define EVENT_ID_GEN_TCC0_MC_3 41 /* ID for TCC0 event generator MC_3 */ -#define EVENT_ID_GEN_TCC1_OVF 42 /* ID for TCC1 event generator OVF */ -#define EVENT_ID_GEN_TCC1_TRG 43 /* ID for TCC1 event generator TRG */ -#define EVENT_ID_GEN_TCC1_CNT 44 /* ID for TCC1 event generator CNT */ -#define EVENT_ID_GEN_TCC1_MC_0 45 /* ID for TCC1 event generator MC_0 */ -#define EVENT_ID_GEN_TCC1_MC_1 46 /* ID for TCC1 event generator MC_1 */ -#define EVENT_ID_GEN_TCC2_OVF 47 /* ID for TCC2 event generator OVF */ -#define EVENT_ID_GEN_TCC2_TRG 48 /* ID for TCC2 event generator TRG */ -#define EVENT_ID_GEN_TCC2_CNT 49 /* ID for TCC2 event generator CNT */ -#define EVENT_ID_GEN_TCC2_MC_0 50 /* ID for TCC2 event generator MC_0 */ -#define EVENT_ID_GEN_TCC2_MC_1 51 /* ID for TCC2 event generator MC_1 */ -#define EVENT_ID_GEN_TC0_OVF 52 /* ID for TC0 event generator OVF */ -#define EVENT_ID_GEN_TC0_MC_0 53 /* ID for TC0 event generator MC_0 */ -#define EVENT_ID_GEN_TC0_MC_1 54 /* ID for TC0 event generator MC_1 */ -#define EVENT_ID_GEN_TC1_OVF 55 /* ID for TC1 event generator OVF */ -#define EVENT_ID_GEN_TC1_MC_0 56 /* ID for TC1 event generator MC_0 */ -#define EVENT_ID_GEN_TC1_MC_1 57 /* ID for TC1 event generator MC_1 */ -#define EVENT_ID_GEN_TC2_OVF 58 /* ID for TC2 event generator OVF */ -#define EVENT_ID_GEN_TC2_MC_0 59 /* ID for TC2 event generator MC_0 */ -#define EVENT_ID_GEN_TC2_MC_1 60 /* ID for TC2 event generator MC_1 */ -#define EVENT_ID_GEN_TC3_OVF 61 /* ID for TC3 event generator OVF */ -#define EVENT_ID_GEN_TC3_MC_0 62 /* ID for TC3 event generator MC_0 */ -#define EVENT_ID_GEN_TC3_MC_1 63 /* ID for TC3 event generator MC_1 */ -#define EVENT_ID_GEN_TC4_OVF 64 /* ID for TC4 event generator OVF */ -#define EVENT_ID_GEN_TC4_MC_0 65 /* ID for TC4 event generator MC_0 */ -#define EVENT_ID_GEN_TC4_MC_1 66 /* ID for TC4 event generator MC_1 */ -#define EVENT_ID_GEN_ADC0_RESRDY 67 /* ID for ADC0 event generator RESRDY */ -#define EVENT_ID_GEN_ADC0_WINMON 68 /* ID for ADC0 event generator WINMON */ -#define EVENT_ID_GEN_ADC1_RESRDY 69 /* ID for ADC1 event generator RESRDY */ -#define EVENT_ID_GEN_ADC1_WINMON 70 /* ID for ADC1 event generator WINMON */ -#define EVENT_ID_GEN_SDADC_RESRDY 71 /* ID for SDADC event generator RESRDY */ -#define EVENT_ID_GEN_SDADC_WINMON 72 /* ID for SDADC event generator WINMON */ -#define EVENT_ID_GEN_AC_COMP_0 73 /* ID for AC event generator COMP_0 */ -#define EVENT_ID_GEN_AC_COMP_1 74 /* ID for AC event generator COMP_1 */ -#define EVENT_ID_GEN_AC_COMP_2 75 /* ID for AC event generator COMP_2 */ -#define EVENT_ID_GEN_AC_COMP_3 76 /* ID for AC event generator COMP_3 */ -#define EVENT_ID_GEN_AC_WIN_0 77 /* ID for AC event generator WIN_0 */ -#define EVENT_ID_GEN_AC_WIN_1 78 /* ID for AC event generator WIN_1 */ -#define EVENT_ID_GEN_DAC_EMPTY 79 /* ID for DAC event generator EMPTY */ -#define EVENT_ID_GEN_PTC_EOC 80 /* ID for PTC event generator EOC */ -#define EVENT_ID_GEN_PTC_WIN_COMP 81 /* ID for PTC event generator WIN_COMP */ -#define EVENT_ID_GEN_CCL_LUTOUT_0 82 /* ID for CCL event generator LUTOUT_0 */ -#define EVENT_ID_GEN_CCL_LUTOUT_1 83 /* ID for CCL event generator LUTOUT_1 */ -#define EVENT_ID_GEN_CCL_LUTOUT_2 84 /* ID for CCL event generator LUTOUT_2 */ -#define EVENT_ID_GEN_CCL_LUTOUT_3 85 /* ID for CCL event generator LUTOUT_3 */ -#define EVENT_ID_GEN_PAC_ACCERR 86 /* ID for PAC event generator ACCERR */ - -/* ************************************************************************** */ -/* Event User IDs for SAMC21E18A */ -/* ************************************************************************** */ -#define EVENT_ID_USER_TSENS_START 0 /* ID for TSENS event user START */ -#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ -#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ -#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ -#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ -#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ -#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ -#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ -#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ -#define EVENT_ID_USER_TCC0_EV_0 9 /* ID for TCC0 event user EV_0 */ -#define EVENT_ID_USER_TCC0_EV_1 10 /* ID for TCC0 event user EV_1 */ -#define EVENT_ID_USER_TCC0_MC_0 11 /* ID for TCC0 event user MC_0 */ -#define EVENT_ID_USER_TCC0_MC_1 12 /* ID for TCC0 event user MC_1 */ -#define EVENT_ID_USER_TCC0_MC_2 13 /* ID for TCC0 event user MC_2 */ -#define EVENT_ID_USER_TCC0_MC_3 14 /* ID for TCC0 event user MC_3 */ -#define EVENT_ID_USER_TCC1_EV_0 15 /* ID for TCC1 event user EV_0 */ -#define EVENT_ID_USER_TCC1_EV_1 16 /* ID for TCC1 event user EV_1 */ -#define EVENT_ID_USER_TCC1_MC_0 17 /* ID for TCC1 event user MC_0 */ -#define EVENT_ID_USER_TCC1_MC_1 18 /* ID for TCC1 event user MC_1 */ -#define EVENT_ID_USER_TCC2_EV_0 19 /* ID for TCC2 event user EV_0 */ -#define EVENT_ID_USER_TCC2_EV_1 20 /* ID for TCC2 event user EV_1 */ -#define EVENT_ID_USER_TCC2_MC_0 21 /* ID for TCC2 event user MC_0 */ -#define EVENT_ID_USER_TCC2_MC_1 22 /* ID for TCC2 event user MC_1 */ -#define EVENT_ID_USER_TC0_EVU 23 /* ID for TC0 event user EVU */ -#define EVENT_ID_USER_TC1_EVU 24 /* ID for TC1 event user EVU */ -#define EVENT_ID_USER_TC2_EVU 25 /* ID for TC2 event user EVU */ -#define EVENT_ID_USER_TC3_EVU 26 /* ID for TC3 event user EVU */ -#define EVENT_ID_USER_TC4_EVU 27 /* ID for TC4 event user EVU */ -#define EVENT_ID_USER_ADC0_START 28 /* ID for ADC0 event user START */ -#define EVENT_ID_USER_ADC0_SYNC 29 /* ID for ADC0 event user SYNC */ -#define EVENT_ID_USER_ADC1_START 30 /* ID for ADC1 event user START */ -#define EVENT_ID_USER_ADC1_SYNC 31 /* ID for ADC1 event user SYNC */ -#define EVENT_ID_USER_SDADC_START 32 /* ID for SDADC event user START */ -#define EVENT_ID_USER_SDADC_FLUSH 33 /* ID for SDADC event user FLUSH */ -#define EVENT_ID_USER_AC_SOC_0 34 /* ID for AC event user SOC_0 */ -#define EVENT_ID_USER_AC_SOC_1 35 /* ID for AC event user SOC_1 */ -#define EVENT_ID_USER_AC_SOC_2 36 /* ID for AC event user SOC_2 */ -#define EVENT_ID_USER_AC_SOC_3 37 /* ID for AC event user SOC_3 */ -#define EVENT_ID_USER_DAC_START 38 /* ID for DAC event user START */ -#define EVENT_ID_USER_CCL_LUTIN_0 40 /* ID for CCL event user LUTIN_0 */ -#define EVENT_ID_USER_CCL_LUTIN_1 41 /* ID for CCL event user LUTIN_1 */ -#define EVENT_ID_USER_CCL_LUTIN_2 42 /* ID for CCL event user LUTIN_2 */ -#define EVENT_ID_USER_CCL_LUTIN_3 43 /* ID for CCL event user LUTIN_3 */ -#define EVENT_ID_USER_MTB_START 45 /* ID for MTB event user START */ -#define EVENT_ID_USER_MTB_STOP 46 /* ID for MTB event user STOP */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SAMC21E18A_H_ */ - diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h deleted file mode 100644 index 9f4c4d77..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h +++ /dev/null @@ -1,411 +0,0 @@ -/****************************************************************************** - * @file cachel1_armv7.h - * @brief CMSIS Level 1 Cache API for Armv7-M and later - * @version V1.0.1 - * @date 19. April 2021 - ******************************************************************************/ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_CACHEL1_ARMV7_H -#define ARM_CACHEL1_ARMV7_H - -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#ifndef __SCB_DCACHE_LINE_SIZE -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -#ifndef __SCB_ICACHE_LINE_SIZE -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ - -#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h deleted file mode 100644 index a2ad65fb..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.3.2 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - /* __ARM_ARCH_8_1M_MAIN__ not applicable */ - -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; - __ISB(); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h deleted file mode 100644 index 74bc4a2d..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h +++ /dev/null @@ -1,1503 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.4.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h deleted file mode 100644 index 6edd5096..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang_ltm.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.5.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h deleted file mode 100644 index 21a2c711..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h deleted file mode 100644 index 045aaf19..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h +++ /dev/null @@ -1,2211 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h deleted file mode 100644 index 407b94ba..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h +++ /dev/null @@ -1,1002 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.3.0 - * @date 14. April 2021 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2021 IAR Systems -// Copyright (c) 2017-2021 Arm Limited. All rights reserved. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h deleted file mode 100644 index 6addcbb7..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.5 - * @date 02. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h deleted file mode 100644 index ed961aa4..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h +++ /dev/null @@ -1,1087 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.9 - * @date 21. August 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ -#endif - /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ -#endif -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h b/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h deleted file mode 100644 index 3b268177..00000000 --- a/bms/bms/bms_config_e18a/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h +++ /dev/null @@ -1,275 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.2 - * @date 25. May 2020 - ******************************************************************************/ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/bms/bms/bms_config_e18a/src/safety/current.c b/bms/bms/bms_config_e18a/src/safety/current.c deleted file mode 100644 index 813c31d1..00000000 --- a/bms/bms/bms_config_e18a/src/safety/current.c +++ /dev/null @@ -1,77 +0,0 @@ -#include "current.h" -#include "definitions.h" -#include "peripheral/adc/plib_adc0.h" -#include -#include - - -static int current_flags = 0; - -uint16_t adc_read_channel(uint8_t channel) -{ - // 1. Select ADC input (MUXPOS) - ADC0_REGS->ADC_INPUTCTRL = ADC_INPUTCTRL_MUXPOS(channel); - while (ADC0_REGS->ADC_SYNCBUSY & ADC_SYNCBUSY_INPUTCTRL_Msk); - - // 2. Start conversion - ADC0_REGS->ADC_SWTRIG |= ADC_SWTRIG_START_Msk; - - // 3. Wait for conversion to complete - while ((ADC0_REGS->ADC_INTFLAG & ADC_INTFLAG_RESRDY_Msk) == 0); - - // 4. Read result - uint16_t result = ADC0_REGS->ADC_RESULT; - - // 5. Clear the RESRDY flag (write 1 to clear) - ADC0_REGS->ADC_INTFLAG = ADC_INTFLAG_RESRDY_Msk; - - return result; -} - - - -//static float read_current_amps(void){} - - -void current_init(){ - - ADC0_Initialize(); - ADC0_Enable(); - ADC0_ChannelSelect(ADC_POSINPUT_AIN0, ADC_NEGINPUT_GND); - ADC0_ConversionStart(); - - - -} - - - -void current_check(){ - - if (ADC0_REGS->ADC_RESULT > CURRENT_THRESHOLD_A){ - - - - current_flags++;} - - -} - - - - -void check_raise_flags(void){ - //check if current sense flags are raised - //if raised, take action - if (current_flags>5){ - //raise system fault - - } -} - - - - -//raise flags logic if current is out of range -//fault handling logic -//current limiting logic diff --git a/bms/bms/bms_config_e18a/src/safety/current.h b/bms/bms/bms_config_e18a/src/safety/current.h deleted file mode 100644 index 1942156b..00000000 --- a/bms/bms/bms_config_e18a/src/safety/current.h +++ /dev/null @@ -1,16 +0,0 @@ - -#include "definitions.h" -#include "peripheral/adc/plib_adc0.h" -#include - - -#define CURRENT_THRESHOLD_A 25 -#define SENSOR_SENSITIVITY_V_A 0.04 -#define SENSOR_OFFSET_V 1.65 - - - -void current_init(void); -void current_check(void); -void current_raise_flags(void); - diff --git a/bms/bms/bms_config_e18a/src/safety/killswitch.c b/bms/bms/bms_config_e18a/src/safety/killswitch.c deleted file mode 100644 index e69de29b..00000000 diff --git a/bms/bms/bms_config_e18a/src/safety/killswitch.h b/bms/bms/bms_config_e18a/src/safety/killswitch.h deleted file mode 100644 index e69de29b..00000000 diff --git a/bms/bms/bms_config_e18a/src/safety/temperature.c b/bms/bms/bms_config_e18a/src/safety/temperature.c deleted file mode 100644 index e69de29b..00000000 diff --git a/bms/bms/bms_config_e18a/src/safety/temperature.h b/bms/bms/bms_config_e18a/src/safety/temperature.h deleted file mode 100644 index e69de29b..00000000 diff --git a/bms/bms/bms_config_e18a/src/safety/voltage.c b/bms/bms/bms_config_e18a/src/safety/voltage.c deleted file mode 100644 index e69de29b..00000000 diff --git a/bms/bms/bms_config_e18a/src/safety/voltage.h b/bms/bms/bms_config_e18a/src/safety/voltage.h deleted file mode 100644 index e69de29b..00000000 diff --git a/bms/bms/cmake/bms_config_e18a/default/CMakeLists.txt b/bms/bms/cmake/bms_config_e18a/default/CMakeLists.txt deleted file mode 100644 index 81cf0477..00000000 --- a/bms/bms/cmake/bms_config_e18a/default/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ - -# This CMakeLists.txt is generated. -# Do not modify directly. -# If you want to customize cmake behavior create a user.cmake in this -# directory and add it to your version control system. - -# format v1.00 -# { - -cmake_minimum_required(VERSION 3.24.0) -set(CMAKE_SYSTEM_NAME "Generic") - -project(bms_config_e18a_default_project LANGUAGES C CXX ASM) - -include("${CMAKE_CURRENT_LIST_DIR}/.generated/main.cmake") - -if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/user.cmake) - include(user.cmake) -endif() - - -# } - diff --git a/bms/bms/cmake/bms_config_e18a/default/CMakePresets.json b/bms/bms/cmake/bms_config_e18a/default/CMakePresets.json deleted file mode 100644 index a7f55b22..00000000 --- a/bms/bms/cmake/bms_config_e18a/default/CMakePresets.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "version": 6, - "configurePresets": [ - { - "name": "bms_config_e18a_default_conf", - "binaryDir": "${fileDir}/../../../_build/bms_config_e18a/default", - "generator": "Ninja", - "toolchainFile": "${fileDir}/.generated/toolchain.cmake", - "cacheVariables": { - "CMAKE_USER_MAKE_RULES_OVERRIDE": { - "type": "FILEPATH", - "value": "${fileDir}/.generated/overrides.cmake" - }, - "CMAKE_EXPORT_COMPILE_COMMANDS": { - "type": "BOOL", - "value": "ON" - } - } - } - ] -} \ No newline at end of file From f1987b0f35a3fdadbf2a9d07d2b3ae0941a066d3 Mon Sep 17 00:00:00 2001 From: alihsar1kaya Date: Thu, 12 Mar 2026 12:19:02 +0100 Subject: [PATCH 30/30] feat: added e18a config --- bms_e18a/README.md | 13 + .../My_MCC_Config_default/components/can0.yml | 20 + .../components/cmsis.yml | 24 + .../My_MCC_Config_default/components/core.yml | 829 ++++++ .../My_MCC_Config_default/components/dfp.yml | 20 + .../My_MCC_Config_default/components/eic.yml | 20 + .../components/evsys.yml | 20 + .../components/nvmctrl.yml | 20 + .../My_MCC_Config_default/components/rtc.yml | 20 + .../components/sercom0.yml | 108 + .../components/sercom1.yml | 108 + .../components/sercom2.yml | 108 + .../components/sercom3.yml | 108 + .../mcc/My_MCC_Config_default/mcc-config.mc4 | 280 ++ .../mcc/mcc-manifest-autosave.yml | 22 + .../mcc/mcc-manifest-generated-success.yml | 22 + bms_e18a/bms_e18a_config/mcc/mcc.vscode | 10 + .../src/config/default/ATSAMC21E18A.ld | 241 ++ .../src/config/default/definitions.h | 150 + .../src/config/default/device.h | 65 + .../src/config/default/device_cache.h | 94 + .../src/config/default/device_vectors.h | 118 + .../src/config/default/exceptions.c | 89 + .../default/harmony-manifest-success.yml | 22 + .../src/config/default/initialization.c | 170 ++ .../src/config/default/interrupts.c | 160 ++ .../src/config/default/interrupts.h | 70 + .../src/config/default/libc_syscalls.c | 61 + .../config/default/peripheral/can/plib_can0.c | 705 +++++ .../config/default/peripheral/can/plib_can0.h | 124 + .../default/peripheral/can/plib_can_common.h | 668 +++++ .../default/peripheral/clock/plib_clock.c | 155 + .../default/peripheral/clock/plib_clock.h | 143 + .../config/default/peripheral/eic/plib_eic.c | 114 + .../config/default/peripheral/eic/plib_eic.h | 183 ++ .../default/peripheral/evsys/plib_evsys.c | 52 + .../default/peripheral/evsys/plib_evsys.h | 68 + .../default/peripheral/nvic/plib_nvic.c | 127 + .../default/peripheral/nvic/plib_nvic.h | 72 + .../default/peripheral/nvmctrl/plib_nvmctrl.c | 260 ++ .../default/peripheral/nvmctrl/plib_nvmctrl.h | 137 + .../default/peripheral/port/plib_port.c | 334 +++ .../default/peripheral/port/plib_port.h | 961 +++++++ .../config/default/peripheral/rtc/plib_rtc.h | 116 + .../default/peripheral/rtc/plib_rtc_timer.c | 196 ++ .../sercom/usart/plib_sercom0_usart.c | 615 ++++ .../sercom/usart/plib_sercom0_usart.h | 121 + .../sercom/usart/plib_sercom1_usart.c | 615 ++++ .../sercom/usart/plib_sercom1_usart.h | 121 + .../sercom/usart/plib_sercom2_usart.c | 615 ++++ .../sercom/usart/plib_sercom2_usart.h | 121 + .../sercom/usart/plib_sercom3_usart.c | 615 ++++ .../sercom/usart/plib_sercom3_usart.h | 121 + .../sercom/usart/plib_sercom_usart_common.h | 405 +++ .../src/config/default/startup_xc32.c | 145 + .../src/config/default/stdio/xc32_monitor.c | 54 + .../src/config/default/toolchain_specifics.h | 61 + bms_e18a/bms_e18a_config/src/main.c | 57 + .../src/packs/ATSAMC21E18A_DFP/component/ac.h | 490 ++++ .../packs/ATSAMC21E18A_DFP/component/adc.h | 523 ++++ .../packs/ATSAMC21E18A_DFP/component/can.h | 2527 +++++++++++++++++ .../packs/ATSAMC21E18A_DFP/component/ccl.h | 217 ++ .../packs/ATSAMC21E18A_DFP/component/dac.h | 216 ++ .../packs/ATSAMC21E18A_DFP/component/divas.h | 126 + .../packs/ATSAMC21E18A_DFP/component/dmac.h | 882 ++++++ .../packs/ATSAMC21E18A_DFP/component/dsu.h | 424 +++ .../packs/ATSAMC21E18A_DFP/component/eic.h | 333 +++ .../packs/ATSAMC21E18A_DFP/component/evsys.h | 552 ++++ .../packs/ATSAMC21E18A_DFP/component/freqm.h | 150 + .../packs/ATSAMC21E18A_DFP/component/fuses.h | 277 ++ .../packs/ATSAMC21E18A_DFP/component/gclk.h | 395 +++ .../ATSAMC21E18A_DFP/component/hmatrixb.h | 348 +++ .../packs/ATSAMC21E18A_DFP/component/mclk.h | 309 ++ .../packs/ATSAMC21E18A_DFP/component/mtb.h | 235 ++ .../ATSAMC21E18A_DFP/component/nvmctrl.h | 273 ++ .../ATSAMC21E18A_DFP/component/osc32kctrl.h | 269 ++ .../ATSAMC21E18A_DFP/component/oscctrl.h | 527 ++++ .../packs/ATSAMC21E18A_DFP/component/pac.h | 470 +++ .../src/packs/ATSAMC21E18A_DFP/component/pm.h | 80 + .../packs/ATSAMC21E18A_DFP/component/port.h | 338 +++ .../packs/ATSAMC21E18A_DFP/component/ptc.h | 39 + .../packs/ATSAMC21E18A_DFP/component/rstc.h | 65 + .../packs/ATSAMC21E18A_DFP/component/rtc.h | 1050 +++++++ .../packs/ATSAMC21E18A_DFP/component/sdadc.h | 429 +++ .../packs/ATSAMC21E18A_DFP/component/sercom.h | 1957 +++++++++++++ .../packs/ATSAMC21E18A_DFP/component/supc.h | 328 +++ .../src/packs/ATSAMC21E18A_DFP/component/tc.h | 589 ++++ .../packs/ATSAMC21E18A_DFP/component/tcc.h | 1344 +++++++++ .../packs/ATSAMC21E18A_DFP/component/tsens.h | 279 ++ .../packs/ATSAMC21E18A_DFP/component/wdt.h | 223 ++ .../src/packs/ATSAMC21E18A_DFP/instance/ac.h | 36 + .../packs/ATSAMC21E18A_DFP/instance/adc0.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/adc1.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/can0.h | 35 + .../packs/ATSAMC21E18A_DFP/instance/can1.h | 35 + .../src/packs/ATSAMC21E18A_DFP/instance/ccl.h | 35 + .../src/packs/ATSAMC21E18A_DFP/instance/dac.h | 33 + .../packs/ATSAMC21E18A_DFP/instance/divas.h | 27 + .../packs/ATSAMC21E18A_DFP/instance/dmac.h | 42 + .../src/packs/ATSAMC21E18A_DFP/instance/dsu.h | 31 + .../src/packs/ATSAMC21E18A_DFP/instance/eic.h | 35 + .../packs/ATSAMC21E18A_DFP/instance/evsys.h | 51 + .../packs/ATSAMC21E18A_DFP/instance/freqm.h | 33 + .../packs/ATSAMC21E18A_DFP/instance/fuses.h | 27 + .../packs/ATSAMC21E18A_DFP/instance/gclk.h | 47 + .../ATSAMC21E18A_DFP/instance/hmatrixhs.h | 44 + .../packs/ATSAMC21E18A_DFP/instance/mclk.h | 35 + .../src/packs/ATSAMC21E18A_DFP/instance/mtb.h | 31 + .../packs/ATSAMC21E18A_DFP/instance/nvmctrl.h | 54 + .../ATSAMC21E18A_DFP/instance/osc32kctrl.h | 32 + .../packs/ATSAMC21E18A_DFP/instance/oscctrl.h | 36 + .../src/packs/ATSAMC21E18A_DFP/instance/pac.h | 33 + .../src/packs/ATSAMC21E18A_DFP/instance/pm.h | 33 + .../packs/ATSAMC21E18A_DFP/instance/port.h | 37 + .../src/packs/ATSAMC21E18A_DFP/instance/ptc.h | 39 + .../packs/ATSAMC21E18A_DFP/instance/rstc.h | 32 + .../src/packs/ATSAMC21E18A_DFP/instance/rtc.h | 36 + .../packs/ATSAMC21E18A_DFP/instance/sdadc.h | 34 + .../packs/ATSAMC21E18A_DFP/instance/sercom0.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/sercom1.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/sercom2.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/sercom3.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/sercom4.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/sercom5.h | 37 + .../packs/ATSAMC21E18A_DFP/instance/supc.h | 34 + .../src/packs/ATSAMC21E18A_DFP/instance/tc0.h | 39 + .../src/packs/ATSAMC21E18A_DFP/instance/tc1.h | 39 + .../src/packs/ATSAMC21E18A_DFP/instance/tc2.h | 39 + .../src/packs/ATSAMC21E18A_DFP/instance/tc3.h | 39 + .../src/packs/ATSAMC21E18A_DFP/instance/tc4.h | 39 + .../packs/ATSAMC21E18A_DFP/instance/tcc0.h | 47 + .../packs/ATSAMC21E18A_DFP/instance/tcc1.h | 45 + .../packs/ATSAMC21E18A_DFP/instance/tcc2.h | 45 + .../packs/ATSAMC21E18A_DFP/instance/tsens.h | 33 + .../src/packs/ATSAMC21E18A_DFP/instance/wdt.h | 31 + .../packs/ATSAMC21E18A_DFP/pio/samc21e18a.h | 1097 +++++++ .../src/packs/ATSAMC21E18A_DFP/samc21e18a.h | 665 +++++ .../CMSIS/CMSIS/Core/Include/cachel1_armv7.h | 411 +++ .../CMSIS/CMSIS/Core/Include/cmsis_armcc.h | 888 ++++++ .../CMSIS/CMSIS/Core/Include/cmsis_armclang.h | 1503 ++++++++++ .../CMSIS/Core/Include/cmsis_armclang_ltm.h | 1928 +++++++++++++ .../CMSIS/CMSIS/Core/Include/cmsis_compiler.h | 283 ++ .../CMSIS/CMSIS/Core/Include/cmsis_gcc.h | 2211 ++++++++++++++ .../CMSIS/CMSIS/Core/Include/cmsis_iccarm.h | 1002 +++++++ .../CMSIS/CMSIS/Core/Include/cmsis_version.h | 39 + .../CMSIS/CMSIS/Core/Include/core_cm0plus.h | 1087 +++++++ .../CMSIS/CMSIS/Core/Include/mpu_armv7.h | 275 ++ .../cmake/bms_e18a/default/CMakeLists.txt | 23 + .../cmake/bms_e18a/default/CMakePresets.json | 21 + 149 files changed, 40439 insertions(+) create mode 100644 bms_e18a/README.md create mode 100644 bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/can0.yml create mode 100644 bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/cmsis.yml create mode 100644 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bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h create mode 100644 bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h create mode 100644 bms_e18a/cmake/bms_e18a/default/CMakeLists.txt create mode 100644 bms_e18a/cmake/bms_e18a/default/CMakePresets.json diff --git a/bms_e18a/README.md b/bms_e18a/README.md new file mode 100644 index 00000000..dae3133c --- /dev/null +++ b/bms_e18a/README.md @@ -0,0 +1,13 @@ + +# bms_e18a + +## Structure + +| Path | Purpose | +|-----------------------------|-------------------------------------------------------------------------------------------------------------------------------------| +| _build | The [CMake build tree](https://cmake.org/cmake/help/latest/manual/cmake.1.html#introduction-to-cmake-buildsystems), can be deleted. | +| cmake | Generated [CMake](https://cmake.org/) files. May be deleted if user.cmake has not been added | +| .vscode | See [VSCode](https://code.visualstudio.com/docs/getstarted/settings) | +| .vscode/settings.json | Workspace specific settings | +| .vscode/bms_e18a.mplab.json | The MPLAB project file, should not be deleted | +| out | Final build artifacts | diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/can0.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/can0.yml new file mode 100644 index 00000000..631e7165 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/can0.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: can0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: can0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/cmsis.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/cmsis.yml new file mode 100644 index 00000000..f9f85905 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/cmsis.yml @@ -0,0 +1,24 @@ +configVersion: 1.0.0 +componentName: cmsis +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: cmsis + type: module + version: '' +- dependencyPackage: '' + name: CMSIS_5 + type: package + version: 5.9.1-dev +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/core.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/core.yml new file mode 100644 index 00000000..3c95f350 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/core.yml @@ -0,0 +1,829 @@ +configVersion: 1.0.0 +componentName: core +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: core + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: + CAN0_CLOCK_ENABLE: + attributes: + id: CAN0_CLOCK_ENABLE + children: + - children: + - attributes: + id: can0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + CAN0_CLOCK_FREQUENCY: + attributes: + id: CAN0_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + EIC_CLOCK_ENABLE: + attributes: + id: EIC_CLOCK_ENABLE + children: + - children: + - attributes: + id: eic + value: 'true' + type: Dynamic + type: Values + type: Boolean + EIC_CLOCK_FREQUENCY: + attributes: + id: EIC_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_19_CHEN: + attributes: + id: GCLK_ID_19_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_19_FREQ: + attributes: + id: GCLK_ID_19_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_20_CHEN: + attributes: + id: GCLK_ID_20_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_20_FREQ: + attributes: + id: GCLK_ID_20_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_21_CHEN: + attributes: + id: GCLK_ID_21_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_21_FREQ: + attributes: + id: GCLK_ID_21_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_22_CHEN: + attributes: + id: GCLK_ID_22_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_22_FREQ: + attributes: + id: GCLK_ID_22_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_26_CHEN: + attributes: + id: GCLK_ID_26_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_26_FREQ: + attributes: + id: GCLK_ID_26_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + GCLK_ID_2_CHEN: + attributes: + id: GCLK_ID_2_CHEN + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + GCLK_ID_2_FREQ: + attributes: + id: GCLK_ID_2_FREQ + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + MCLK_AHB_INITIAL_VALUE: + attributes: + id: MCLK_AHB_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1dff' + type: Dynamic + type: Values + type: String + MCLK_APBA_INITIAL_VALUE: + attributes: + id: MCLK_APBA_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0xfff' + type: Dynamic + type: Values + type: String + MCLK_APBC_INITIAL_VALUE: + attributes: + id: MCLK_APBC_INITIAL_VALUE + children: + - children: + - attributes: + id: core + value: '0x1e' + type: Dynamic + type: Values + type: String + NVIC_10_0_ENABLE: + attributes: + id: NVIC_10_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_10_0_HANDLER: + attributes: + id: NVIC_10_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM1_USART_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_10_0_HANDLER_LOCK: + attributes: + id: NVIC_10_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_11_0_ENABLE: + attributes: + id: NVIC_11_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_11_0_HANDLER: + attributes: + id: NVIC_11_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM2_USART_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_11_0_HANDLER_LOCK: + attributes: + id: NVIC_11_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_ENABLE: + attributes: + id: NVIC_12_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_12_0_HANDLER: + attributes: + id: NVIC_12_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM3_USART_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_12_0_HANDLER_LOCK: + attributes: + id: NVIC_12_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_ENABLE: + attributes: + id: NVIC_2_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_2_0_HANDLER: + attributes: + id: NVIC_2_0_HANDLER + children: + - children: + - attributes: + id: core + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_2_0_HANDLER_LOCK: + attributes: + id: NVIC_2_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_ENABLE: + attributes: + id: NVIC_9_0_ENABLE + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + NVIC_9_0_HANDLER: + attributes: + id: NVIC_9_0_HANDLER + children: + - children: + - attributes: + id: core + value: SERCOM0_USART_InterruptHandler + type: Dynamic + type: Values + type: String + NVIC_9_0_HANDLER_LOCK: + attributes: + id: NVIC_9_0_HANDLER_LOCK + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PIN_3_DIR: + attributes: + id: PIN_3_DIR + children: + - children: + - attributes: + value: Out + type: User + type: Values + type: String + PIN_3_FUNCTION_NAME: + attributes: + id: PIN_3_FUNCTION_NAME + children: + - children: + - attributes: + value: GPIO_PA02 + type: User + type: Values + type: String + PIN_3_FUNCTION_TYPE: + attributes: + id: PIN_3_FUNCTION_TYPE + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PIN_3_INEN: + attributes: + id: PIN_3_INEN + children: + - children: + - attributes: + value: 'True' + type: User + type: Values + type: String + PIN_3_MODE: + attributes: + id: PIN_3_MODE + children: + - children: + - attributes: + value: '' + type: User + type: Values + type: String + PIN_3_PERIPHERAL_FUNCTION: + attributes: + id: PIN_3_PERIPHERAL_FUNCTION + children: + - children: + - attributes: + value: GPIO + type: User + type: Values + type: String + PORT_GROUP_0_DIR: + attributes: + id: PORT_GROUP_0_DIR + children: + - children: + - attributes: + id: core + value: '0x4' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PAD_2: + attributes: + id: PORT_GROUP_0_PAD_2 + children: + - children: + - attributes: + id: core + value: PA02 + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PINCFG2: + attributes: + id: PORT_GROUP_0_PINCFG2 + children: + - children: + - attributes: + id: core + value: '0x2' + type: Dynamic + type: Values + type: String + PORT_GROUP_0_PIN_2_USED: + attributes: + id: PORT_GROUP_0_PIN_2_USED + children: + - children: + - attributes: + id: core + value: 'true' + type: Dynamic + type: Values + type: Boolean + PORT_GROUP_0_PMUX1: + attributes: + id: PORT_GROUP_0_PMUX1 + children: + - children: + - attributes: + id: core + value: '0x0' + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_ENABLE: + attributes: + id: RTC_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_ENABLE_UPDATE: + attributes: + id: RTC_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + RTC_INTERRUPT_HANDLER: + attributes: + id: RTC_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: rtc + value: RTC_InterruptHandler + type: Dynamic + type: Values + type: String + RTC_INTERRUPT_HANDLER_LOCK: + attributes: + id: RTC_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: rtc + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM0_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM0_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + SERCOM0_INTERRUPT_ENABLE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM0_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM0_INTERRUPT_HANDLER: + attributes: + id: SERCOM0_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom0 + value: SERCOM0_USART_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM0_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM0_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM1_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM1_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + SERCOM1_INTERRUPT_ENABLE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM1_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM1_INTERRUPT_HANDLER: + attributes: + id: SERCOM1_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom1 + value: SERCOM1_USART_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM1_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM1_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM2_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM2_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom2 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM2_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM2_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + SERCOM2_INTERRUPT_ENABLE: + attributes: + id: SERCOM2_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom2 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM2_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM2_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM2_INTERRUPT_HANDLER: + attributes: + id: SERCOM2_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom2 + value: SERCOM2_USART_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM2_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM2_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom2 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_ENABLE: + attributes: + id: SERCOM3_CORE_CLOCK_ENABLE + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_CORE_CLOCK_FREQUENCY: + attributes: + id: SERCOM3_CORE_CLOCK_FREQUENCY + children: + - children: + - attributes: + id: core + value: '48000000' + type: Dynamic + type: Values + type: Integer + SERCOM3_INTERRUPT_ENABLE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + SERCOM3_INTERRUPT_ENABLE_UPDATE: + attributes: + id: SERCOM3_INTERRUPT_ENABLE_UPDATE + children: + - children: + - attributes: + id: core + value: 'false' + type: Dynamic + type: Values + type: Boolean + SERCOM3_INTERRUPT_HANDLER: + attributes: + id: SERCOM3_INTERRUPT_HANDLER + children: + - children: + - attributes: + id: sercom3 + value: SERCOM3_USART_InterruptHandler + type: Dynamic + type: Values + type: String + SERCOM3_INTERRUPT_HANDLER_LOCK: + attributes: + id: SERCOM3_INTERRUPT_HANDLER_LOCK + children: + - children: + - attributes: + id: sercom3 + value: 'true' + type: Dynamic + type: Values + type: Boolean + userData: + children: + - attributes: + canvasHeight: '0' + canvasWidth: '0' + type: GraphSettings + - children: + - attributes: + id: profile0 + name: Main + type: Profile + type: PowerProfiles + type: UserData diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/dfp.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/dfp.yml new file mode 100644 index 00000000..60876f2b --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/dfp.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: dfp +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: dfp + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/eic.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/eic.yml new file mode 100644 index 00000000..6c4e037d --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/eic.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: eic +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: eic + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/evsys.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/evsys.yml new file mode 100644 index 00000000..f3dd4b75 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/evsys.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: evsys +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: evsys + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/nvmctrl.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/nvmctrl.yml new file mode 100644 index 00000000..e2d9019c --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/nvmctrl.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: nvmctrl +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: nvmctrl + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/rtc.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/rtc.yml new file mode 100644 index 00000000..7b420269 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/rtc.yml @@ -0,0 +1,20 @@ +configVersion: 1.0.0 +componentName: rtc +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: rtc + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: {} + symbols: {} + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom0.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom0.yml new file mode 100644 index 00000000..46baed4b --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom0.yml @@ -0,0 +1,108 @@ +configVersion: 1.0.0 +componentName: sercom0 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom0 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom0 + x: '527' + y: '259' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom0 + value: '232' + type: Dynamic + type: Values + type: Hex + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '23' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom0 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom0 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom0 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom0 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom0 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom1.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom1.yml new file mode 100644 index 00000000..ff36a266 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom1.yml @@ -0,0 +1,108 @@ +configVersion: 1.0.0 +componentName: sercom1 +coreVersion: 5.8.4 +device: ATSAMC21E18A +library: [] +dependency: +- dependencyPackage: class com.microchip.mcc.harmony.HarmonyModule + name: sercom1 + type: module + version: '' +- dependencyPackage: '' + name: csp + type: package + version: v3.23.0 +customDataClassName: com.microchip.utils_mh3.utils.persistence.CustomModuleData +data: + attachments: {} + elementPosition: + attributes: + id: __ROOTVIEW + children: + - children: + - attributes: + id: sercom1 + x: '210' + y: '256' + type: ElementPosition + type: ElementPositions + type: ComponentGraph + symbols: + I2CM_BAUD: + attributes: + id: I2CM_BAUD + children: + - children: + - attributes: + id: sercom1 + value: '232' + type: Dynamic + type: Values + type: Hex + SPI_BAUD_REG_VALUE: + attributes: + id: SPI_BAUD_REG_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '23' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom1 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom1 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom1 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom1 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom1 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff --git a/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom2.yml b/bms_e18a/bms_e18a_config/mcc/My_MCC_Config_default/components/sercom2.yml new file mode 100644 index 00000000..f4bbcf3d --- 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value: '23' + type: Dynamic + type: Values + type: Integer + USART_BAUD_VALUE: + attributes: + id: USART_BAUD_VALUE + children: + - children: + - attributes: + id: sercom2 + value: '63019' + type: Dynamic + type: Values + type: Integer + USART_LIN_MASTER_SUPPORTED: + attributes: + id: USART_LIN_MASTER_SUPPORTED + children: + - children: + - attributes: + id: sercom2 + value: 'true' + type: Dynamic + type: Values + type: Boolean + USART_SAMPLE_COUNT: + attributes: + id: USART_SAMPLE_COUNT + children: + - children: + - attributes: + id: sercom2 + value: '16' + type: Dynamic + type: Values + type: Integer + USART_SAMPLE_RATE: + attributes: + id: USART_SAMPLE_RATE + children: + - children: + - attributes: + id: sercom2 + value: '0' + type: Dynamic + type: Values + type: Integer + USART_USE_FRACTIONAL_BAUD: + attributes: + id: USART_USE_FRACTIONAL_BAUD + children: + - children: + - attributes: + id: sercom2 + value: 'false' + type: Dynamic + type: Values + type: Boolean + userData: {} diff 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Please do not edit this file. + +manifest_file_version: 1.0.0 +project: My_MCC_Config_default +creation_date: 2026-03-12T12:15:17.253+01:00[Europe/Oslo] +operating_system: Linux +mcc_mode: VSCodePlugin +mcc_mode_version: Unknown +device_name: ATSAMC21E18A +compiler: N/A +mcc_version: 5.6.4 +mcc_core_version: 5.8.4 +content_manager_version: 6.0.4 +is_mcc_offline: false +is_using_prerelease_versions: false +mcc_content_registries: https://registry.npmjs.org/ +device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, + version: Bundled} +packs: {name: SAMC21_DFP, version: 3.8.119} +modules: +- {name: csp, type: HARMONY, version: v3.23.0} +- {name: CMSIS_5, type: HARMONY, version: 5.9.1-dev} diff --git a/bms_e18a/bms_e18a_config/mcc/mcc-manifest-generated-success.yml b/bms_e18a/bms_e18a_config/mcc/mcc-manifest-generated-success.yml new file mode 100644 index 00000000..7a5fa2d8 --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/mcc-manifest-generated-success.yml @@ -0,0 +1,22 @@ +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. + +manifest_file_version: 1.0.0 +project: My_MCC_Config_default +creation_date: 2026-03-12T12:14:59.210+01:00[Europe/Oslo] +operating_system: Linux +mcc_mode: VSCodePlugin +mcc_mode_version: Unknown +device_name: ATSAMC21E18A +compiler: N/A +mcc_version: 5.6.4 +mcc_core_version: 5.8.4 +content_manager_version: 6.0.4 +is_mcc_offline: false +is_using_prerelease_versions: false +mcc_content_registries: https://registry.npmjs.org/ +device_library: {library_class: com.microchip.mcc.harmony.Harmony3Library, name: Bundled, + version: Bundled} +packs: {name: SAMC21_DFP, version: 3.8.119} +modules: +- {name: csp, type: HARMONY, version: v3.23.0} +- {name: CMSIS_5, type: HARMONY, version: 5.9.1-dev} diff --git a/bms_e18a/bms_e18a_config/mcc/mcc.vscode b/bms_e18a/bms_e18a_config/mcc/mcc.vscode new file mode 100644 index 00000000..ce6efbfb --- /dev/null +++ b/bms_e18a/bms_e18a_config/mcc/mcc.vscode @@ -0,0 +1,10 @@ +# This file has been autogenerated by MCC. Please do not edit this file. + +configName: My_MCC_Config +fileVersion: 1.0.0 +device: ATSAMC21E18A +associatedIDEProjects: + MPLAB: + - name: bms_e18a + path: ../../.vscode + config: default diff --git a/bms_e18a/bms_e18a_config/src/config/default/ATSAMC21E18A.ld b/bms_e18a/bms_e18a_config/src/config/default/ATSAMC21E18A.ld new file mode 100644 index 00000000..6e2de873 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/ATSAMC21E18A.ld @@ -0,0 +1,241 @@ +/*-------------------------------------------------------------------------- + * MPLAB XC32 Compiler - ATSAMC21E18A linker script + * + * Copyright (c) 2022, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* + * Define the __XC32_RESET_HANDLER_NAME macro on the command line when you + * want to use a different name for the Reset Handler function. + */ +#ifndef __XC32_RESET_HANDLER_NAME +#define __XC32_RESET_HANDLER_NAME Reset_Handler +#endif /* __XC32_RESET_HANDLER_NAME */ + +/* Set the entry point in the ELF file. Once the entry point is in the ELF + * file, you can then use the --write-sla option to xc32-bin2hex to place + * the address into the hex file using the SLA field (RECTYPE 5). This hex + * record may be useful for a bootloader that needs to determine the entry + * point to the application. + */ +ENTRY(__XC32_RESET_HANDLER_NAME) + +/************************************************************************* + * Memory-Region Macro Definitions + * The XC32 linker preprocesses linker scripts. You may define these + * macros in the MPLAB X project properties or on the command line when + * calling the linker via the xc32-gcc shell. + *************************************************************************/ + +#ifndef ROM_ORIGIN +# define ROM_ORIGIN 0x0 +#endif +#ifndef ROM_LENGTH +# define ROM_LENGTH 0x40000 +#elif (ROM_LENGTH > 0x40000) +# error ROM_LENGTH is greater than the max size of 0x40000 +#endif +#ifndef RAM_ORIGIN +# define RAM_ORIGIN 0x20000000 +#endif +#ifndef RAM_LENGTH +# define RAM_LENGTH 0x8000 +#elif (RAM_LENGTH > 0x8000) +# error RAM_LENGTH is greater than the max size of 0x8000 +#endif + + +/************************************************************************* + * Memory-Region Definitions + * The MEMORY command describes the location and size of blocks of memory + * on the target device. The command below uses the macros defined above. + *************************************************************************/ +MEMORY +{ + rom (LRX) : ORIGIN = ROM_ORIGIN, LENGTH = ROM_LENGTH + ram (WX!R) : ORIGIN = RAM_ORIGIN, LENGTH = RAM_LENGTH + config_00804000 : ORIGIN = 0x00804000, LENGTH = 0x4 + config_00804004 : ORIGIN = 0x00804004, LENGTH = 0x4 + +} +/************************************************************************* + * Output region definitions. + * CODE_REGION defines the output region for .text/.rodata. + * DATA_REGION defines the output region for .data/.bss + * VECTOR_REGION defines the output region for .vectors. + * + * CODE_REGION defaults to 'rom', if rom is present (non-zero length), + * and 'ram' otherwise. + * DATA_REGION defaults to 'ram', which must be present. + * VECTOR_REGION defaults to CODE_REGION, unless 'boot_rom' is present. + */ +#ifndef CODE_REGION +# if ROM_LENGTH > 0 +# define CODE_REGION rom +# else +# define CODE_REGION ram +# endif +#endif +#ifndef DATA_REGION +# define DATA_REGION ram +#endif +#ifndef VECTOR_REGION +# define VECTOR_REGION CODE_REGION +#endif + +__rom_end = ORIGIN(rom) + LENGTH(rom); +__ram_end = ORIGIN(ram) + LENGTH(ram); + +/************************************************************************* + * Section Definitions - Map input sections to output sections + *************************************************************************/ +SECTIONS +{ + .config_00804000 : { + KEEP(*(.config_00804000)) + } > config_00804000 + .config_00804004 : { + KEEP(*(.config_00804004)) + } > config_00804004 + + /* + * The linker moves the .vectors section into itcm when itcm is + * enabled via the -mitcm option, but only when this .vectors output + * section exists in the linker script. + */ + .vectors : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.* .vectors_default .vectors_default.*)) + KEEP(*(.isr_vector)) + KEEP(*(.reset*)) + KEEP(*(.after_vectors)) + } > VECTOR_REGION + /* + * Code Sections - Note that standard input sections such as + * *(.text), *(.text.*), *(.rodata), & *(.rodata.*) + * are not mapped here. The best-fit allocator locates them, + * so that input sections may flow around absolute sections + * as needed. + */ + .text : + { + . = ALIGN(4); + *(.glue_7t) *(.glue_7) + *(.gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > CODE_REGION + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > CODE_REGION + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + + /* + * Align here to ensure that the .bss section occupies space up to + * _end. Align after .bss to ensure correct alignment even if the + * .bss section disappears because there are no input sections. + * + * Note that input sections named .bss* are no longer mapped here. + * The best-fit allocator locates them, so that they may flow + * around absolute sections as needed. + */ + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = . ; + _szero = .; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = . ; + _ezero = .; + } > DATA_REGION + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; + +} + diff --git a/bms_e18a/bms_e18a_config/src/config/default/definitions.h b/bms_e18a/bms_e18a_config/src/config/default/definitions.h new file mode 100644 index 00000000..874e7627 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/definitions.h @@ -0,0 +1,150 @@ +/******************************************************************************* + System Definitions + + File Name: + definitions.h + + Summary: + project system definitions. + + Description: + This file contains the system-wide prototypes and definitions for a project. + + *******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +//DOM-IGNORE-END + +#ifndef DEFINITIONS_H +#define DEFINITIONS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include +#include +#include +#include "peripheral/sercom/usart/plib_sercom3_usart.h" +#include "peripheral/sercom/usart/plib_sercom2_usart.h" +#include "peripheral/nvmctrl/plib_nvmctrl.h" +#include "peripheral/sercom/usart/plib_sercom1_usart.h" +#include "peripheral/sercom/usart/plib_sercom0_usart.h" +#include "peripheral/evsys/plib_evsys.h" +#include "peripheral/port/plib_port.h" +#include "peripheral/clock/plib_clock.h" +#include "peripheral/nvic/plib_nvic.h" +#include "peripheral/can/plib_can0.h" +#include "peripheral/eic/plib_eic.h" +#include "peripheral/rtc/plib_rtc.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +/* Device Information */ +#define DEVICE_NAME "ATSAMC21E18A" +#define DEVICE_ARCH "CORTEX-M0PLUS" +#define DEVICE_FAMILY "SAMC" +#define DEVICE_SERIES "SAMC21" + +/* CPU clock frequency */ +#define CPU_CLOCK_FREQUENCY 48000000U + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Functions +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* System Initialization Function + + Function: + void SYS_Initialize( void *data ) + + Summary: + Function that initializes all modules in the system. + + Description: + This function initializes all modules in the system, including any drivers, + services, middleware, and applications. + + Precondition: + None. + + Parameters: + data - Pointer to the data structure containing any data + necessary to initialize the module. This pointer may + be null if no data is required and default initialization + is to be used. + + Returns: + None. + + Example: + + SYS_Initialize ( NULL ); + + while ( true ) + { + SYS_Tasks ( ); + } + + + Remarks: + This function will only be called once, after system reset. +*/ + +void SYS_Initialize( void *data ); + +/* Nullify SYS_Tasks() if only PLIBs are used. */ +#define SYS_Tasks() + +// ***************************************************************************** +// ***************************************************************************** +// Section: extern declarations +// ***************************************************************************** +// ***************************************************************************** + + + + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif /* DEFINITIONS_H */ +/******************************************************************************* + End of File +*/ + diff --git a/bms_e18a/bms_e18a_config/src/config/default/device.h b/bms_e18a/bms_e18a_config/src/config/default/device.h new file mode 100644 index 00000000..669c7985 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/device.h @@ -0,0 +1,65 @@ +/******************************************************************************* + Device Header File + + Company: + Microchip Technology Inc. + + File Name: + device.h + + Summary: + This file includes the selected device from within the project. + The device will provide access to respective device packs. + + Description: + None + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_H +#define DEVICE_H + +#pragma GCC diagnostic push +#ifndef __cplusplus +#pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#ifndef DONT_USE_PREDEFINED_CORE_HANDLERS + #define DONT_USE_PREDEFINED_CORE_HANDLERS +#endif //DONT_USE_PREDEFINED_CORE_HANDLERS +#ifndef DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#endif //DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +#include "samc21e18a.h" +#pragma GCC diagnostic pop +#include "device_cache.h" +#include "toolchain_specifics.h" + +#endif //DEVICE_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/device_cache.h b/bms_e18a/bms_e18a_config/src/config/default/device_cache.h new file mode 100644 index 00000000..802e5dc5 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/device_cache.h @@ -0,0 +1,94 @@ +/******************************************************************************* + Cortex-M L1 Cache Header + + File Name: + device_cache.h + + Summary: + Preprocessor definitions to provide L1 Cache control. + + Description: + An MPLAB PLIB or Project can include this header to perform cache cleans, + invalidates etc. For the DCache and ICache. + + Remarks: + This header should not define any prototypes or data definitions, or + include any files that do. The file only provides macro definitions for + build-time. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_CACHE_H +#define DEVICE_CACHE_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section Includes other configuration headers necessary to completely + define this configuration. +*/ + +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: L1 Cache Configuration +// ***************************************************************************** +// ***************************************************************************** + + +#define ICACHE_ENABLE() +#define ICACHE_DISABLE() +#define ICACHE_INVALIDATE() + +#define DCACHE_ENABLE() +#define DCACHE_DISABLE() +#define DCACHE_INVALIDATE() +#define DCACHE_CLEAN() +#define DCACHE_CLEAN_INVALIDATE() +#define DCACHE_CLEAN_BY_ADDR(addr,sz) +#define DCACHE_INVALIDATE_BY_ADDR(addr,sz) +#define DCACHE_CLEAN_INVALIDATE_BY_ADDR(addr,sz) + +//DOM-IGNORE-BEGIN +#ifdef __cplusplus +} +#endif +//DOM-IGNORE-END + +#endif // #ifndef DEVICE_CACHE_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/device_vectors.h b/bms_e18a/bms_e18a_config/src/config/default/device_vectors.h new file mode 100644 index 00000000..a584fcdf --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/device_vectors.h @@ -0,0 +1,118 @@ +/******************************************************************************* + Cortex-M device vectors file + + Company: + Microchip Technology Inc. + + File Name: + device_vectors.h + + Summary: + Harmony3 device handler structure for cortex-M devices + + Description: + This file contains Harmony3 device handler structure for cortex-M devices + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef DEVICE_VECTORS_H +#define DEVICE_VECTORS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +/* Function pointer type for vector handlers */ +typedef void (*pfn_handler_t)(void); + +/* Structure defining device vector types */ +typedef struct H3DeviceVectorsTag +{ + /* Stack pointer */ + uint32_t* pvStack; + + /* CORTEX-M0PLUS handlers */ + pfn_handler_t pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + pfn_handler_t pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + pfn_handler_t pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + pfn_handler_t pfnReservedC12; + pfn_handler_t pfnReservedC11; + pfn_handler_t pfnReservedC10; + pfn_handler_t pfnReservedC9; + pfn_handler_t pfnReservedC8; + pfn_handler_t pfnReservedC7; + pfn_handler_t pfnReservedC6; + pfn_handler_t pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + pfn_handler_t pfnReservedC4; + pfn_handler_t pfnReservedC3; + pfn_handler_t pfnPendSV_Handler; /* -2 Pendable request for system service */ + pfn_handler_t pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + pfn_handler_t pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt */ + pfn_handler_t pfnWDT_Handler; /* 1 Watchdog Timer */ + pfn_handler_t pfnRTC_Handler; /* 2 Real Time Counter */ + pfn_handler_t pfnEIC_Handler; /* 3 External Interrupt Controller */ + pfn_handler_t pfnFREQM_Handler; /* 4 Frequency Meter */ + pfn_handler_t pfnTSENS_Handler; /* 5 Temperature Sensor */ + pfn_handler_t pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + pfn_handler_t pfnDMAC_Handler; /* 7 Direct Memory Controller */ + pfn_handler_t pfnEVSYS_Handler; /* 8 Event Systems */ + pfn_handler_t pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + pfn_handler_t pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + pfn_handler_t pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + pfn_handler_t pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + pfn_handler_t pfnReserved13; + pfn_handler_t pfnReserved14; + pfn_handler_t pfnCAN0_Handler; /* 15 Control Area Network 0 */ + pfn_handler_t pfnReserved16; + pfn_handler_t pfnTCC0_Handler; /* 17 Timer/Counter for Control Applications 0 */ + pfn_handler_t pfnTCC1_Handler; /* 18 Timer/Counter for Control Applications 1 */ + pfn_handler_t pfnTCC2_Handler; /* 19 Timer/Counter for Control Applications 2 */ + pfn_handler_t pfnTC0_Handler; /* 20 Timer/Counter 0 */ + pfn_handler_t pfnTC1_Handler; /* 21 Timer/Counter 1 */ + pfn_handler_t pfnTC2_Handler; /* 22 Timer/Counter 2 */ + pfn_handler_t pfnTC3_Handler; /* 23 Timer/Counter 3 */ + pfn_handler_t pfnTC4_Handler; /* 24 Timer/Counter 4 */ + pfn_handler_t pfnADC0_Handler; /* 25 Analog-to-Digital Converter 0 */ + pfn_handler_t pfnADC1_Handler; /* 26 Analog-to-Digital Converter 1 */ + pfn_handler_t pfnAC_Handler; /* 27 Analog Comparators */ + pfn_handler_t pfnDAC_Handler; /* 28 Digital-to-Analog Converter */ + pfn_handler_t pfnSDADC_Handler; /* 29 Sigma-Delat Analog-to-Digital Converter */ + pfn_handler_t pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +}H3DeviceVectors; + +#endif //DEVICE_VECTORS_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/exceptions.c b/bms_e18a/bms_e18a_config/src/config/default/exceptions.c new file mode 100644 index 00000000..664dd4ad --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/exceptions.c @@ -0,0 +1,89 @@ +/******************************************************************************* + System Exceptions File + + File Name: + exceptions.c + + Summary: + This file contains a function which overrides the default _weak_ exception + handlers provided by the interrupt.c file. + + Description: + This file redefines the default _weak_ exception handler with a more debug + friendly one. If an unexpected exception occurs the code will stop in a + while(1) loop. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "definitions.h" + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Exception Handling Routine +// ***************************************************************************** +// ***************************************************************************** +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 might be violated here if the users provide a strong + implementations to these weak handler functions. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 +*/ + + +/* Brief default interrupt handlers for core IRQs.*/ +void __attribute__((noreturn, weak)) NonMaskableInt_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + +void __attribute__((noreturn, weak)) HardFault_Handler(void) +{ +#if defined(__DEBUG) || defined(__DEBUG_D) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + while (true) + { + } +} + + +/* MISRAC 2012 deviation block end for rule 8.6 */ + +/******************************************************************************* + End of File + */ diff --git a/bms_e18a/bms_e18a_config/src/config/default/harmony-manifest-success.yml b/bms_e18a/bms_e18a_config/src/config/default/harmony-manifest-success.yml new file mode 100644 index 00000000..f33c2974 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/harmony-manifest-success.yml @@ -0,0 +1,22 @@ + +# This file has been autogenerated by MPLAB Code Configurator. Please do not edit this file. +# Project "My_MCC_Config_default" has been created by using mentioned Harmony 3 packages + + +project: My_MCC_Config_default +creation_date: 2026-03-12T12:14:59.216+01:00[Europe/Oslo] # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime +operating_system: Linux +mcc_mode: VSCodePlugin # [IDE|Standalone|Headless] +mcc_version: v5.6.4 +mcc_core_version: v5.8.4 +mplabx_version: NA # if MPLAB X plugin only +harmony_version: v5.6.4 +compiler: NA + +modules: + - {name: "csp", version: "v3.23.0"} + - {name: "CMSIS_5", version: "5.9.1-dev"} + +packs: + - {name: "SAMC21_DFP", version: "3.8.119"} + diff --git a/bms_e18a/bms_e18a_config/src/config/default/initialization.c b/bms_e18a/bms_e18a_config/src/config/default/initialization.c new file mode 100644 index 00000000..14a1df3f --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/initialization.c @@ -0,0 +1,170 @@ +/******************************************************************************* + System Initialization File + + File Name: + initialization.c + + Summary: + This file contains source code necessary to initialize the system. + + Description: + This file contains source code necessary to initialize the system. It + implements the "SYS_Initialize" function, defines the configuration bits, + and allocates any necessary global system resources, + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "definitions.h" +#include "device.h" + + +// **************************************************************************** +// **************************************************************************** +// Section: Configuration Bits +// **************************************************************************** +// **************************************************************************** +#pragma config NVMCTRL_BOOTPROT = SIZE_0BYTES +#pragma config NVMCTRL_EEPROM_SIZE = SIZE_0BYTES +#pragma config BODVDDUSERLEVEL = 0x8U // Enter Hexadecimal value +#pragma config BODVDD_DIS = DISABLED +#pragma config BODVDD_ACTION = NONE + +#pragma config BODVDD_HYST = DISABLED +#pragma config NVMCTRL_REGION_LOCKS = 0xffffU // Enter Hexadecimal value + +#pragma config WDT_ENABLE = DISABLED +#pragma config WDT_ALWAYSON = DISABLED +#pragma config WDT_PER = CYC8 + +#pragma config WDT_WINDOW = CYC8 +#pragma config WDT_EWOFFSET = CYC8 +#pragma config WDT_WEN = DISABLED + + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Driver Initialization Data +// ***************************************************************************** +// ***************************************************************************** +/* Following MISRA-C rules are deviated in the below code block */ +/* MISRA C-2012 Rule 7.2 - Deviation record ID - H3_MISRAC_2012_R_7_2_DR_1 */ +/* MISRA C-2012 Rule 11.1 - Deviation record ID - H3_MISRAC_2012_R_11_1_DR_1 */ +/* MISRA C-2012 Rule 11.3 - Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1 */ +/* MISRA C-2012 Rule 11.8 - Deviation record ID - H3_MISRAC_2012_R_11_8_DR_1 */ + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Data +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +// ***************************************************************************** +// Section: Library/Stack Initialization Data +// ***************************************************************************** +// ***************************************************************************** + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Initialization +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Local initialization functions +// ***************************************************************************** +// ***************************************************************************** + +/* MISRAC 2012 deviation block end */ + +/******************************************************************************* + Function: + void SYS_Initialize ( void *data ) + + Summary: + Initializes the board, services, drivers, application and other modules. + + Remarks: + */ + +void SYS_Initialize ( void* data ) +{ + + /* MISRAC 2012 deviation block start */ + /* MISRA C-2012 Rule 2.2 deviated in this file. Deviation record ID - H3_MISRAC_2012_R_2_2_DR_1 */ + + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_RWS(3UL); + + + PORT_Initialize(); + + CLOCK_Initialize(); + + + + + SERCOM3_USART_Initialize(); + + SERCOM2_USART_Initialize(); + + NVMCTRL_Initialize( ); + + SERCOM1_USART_Initialize(); + + SERCOM0_USART_Initialize(); + + EVSYS_Initialize(); + + CAN0_Initialize(); + + EIC_Initialize(); + + RTC_Initialize(); + + + NVIC_Initialize(); + + + /* MISRAC 2012 deviation block end */ +} + +/******************************************************************************* + End of File +*/ diff --git a/bms_e18a/bms_e18a_config/src/config/default/interrupts.c b/bms_e18a/bms_e18a_config/src/config/default/interrupts.c new file mode 100644 index 00000000..be934386 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/interrupts.c @@ -0,0 +1,160 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.c + + Summary: + Interrupt vectors mapping + + Description: + This file maps all the interrupt vectors to their corresponding + implementations. If a particular module interrupt is used, then its ISR + definition can be found in corresponding PLIB source file. If a module + interrupt is not used, then its ISR implementation is mapped to dummy + handler. + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "device_vectors.h" +#include "interrupts.h" +#include "definitions.h" + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: System Interrupt Vector Functions +// ***************************************************************************** +// ***************************************************************************** + +/* MISRA C-2012 Rule 8.6 deviated below. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +extern uint32_t _stack; +extern const H3DeviceVectors exception_table; + +extern void Dummy_Handler(void); + +/* Brief default interrupt handler for unused IRQs.*/ +void __attribute__((optimize("-O1"), long_call, noreturn, used))Dummy_Handler(void) +{ + while (true) + { + } +} + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 8.6 deviated 26 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ +/* Device vectors list dummy definition*/ +extern void SVCall_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void PendSV_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SysTick_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SYSTEM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void WDT_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void EIC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void FREQM_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TSENS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void NVMCTRL_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void DMAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void EVSYS_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void CAN0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TCC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC2_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC3_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void TC4_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void ADC0_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void ADC1_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void AC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void DAC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void SDADC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); +extern void PTC_Handler ( void ) __attribute__((weak, alias("Dummy_Handler"),noreturn)); + + +/* MISRAC 2012 deviation block end */ + +/* Multiple handlers for vector */ + + + +__attribute__ ((section(".vectors"), used)) +const H3DeviceVectors exception_table= +{ + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = &_stack, + + .pfnReset_Handler = Reset_Handler, + .pfnNonMaskableInt_Handler = NonMaskableInt_Handler, + .pfnHardFault_Handler = HardFault_Handler, + .pfnSVCall_Handler = SVCall_Handler, + .pfnPendSV_Handler = PendSV_Handler, + .pfnSysTick_Handler = SysTick_Handler, + .pfnSYSTEM_Handler = SYSTEM_Handler, + .pfnWDT_Handler = WDT_Handler, + .pfnRTC_Handler = RTC_InterruptHandler, + .pfnEIC_Handler = EIC_Handler, + .pfnFREQM_Handler = FREQM_Handler, + .pfnTSENS_Handler = TSENS_Handler, + .pfnNVMCTRL_Handler = NVMCTRL_Handler, + .pfnDMAC_Handler = DMAC_Handler, + .pfnEVSYS_Handler = EVSYS_Handler, + .pfnSERCOM0_Handler = SERCOM0_USART_InterruptHandler, + .pfnSERCOM1_Handler = SERCOM1_USART_InterruptHandler, + .pfnSERCOM2_Handler = SERCOM2_USART_InterruptHandler, + .pfnSERCOM3_Handler = SERCOM3_USART_InterruptHandler, + .pfnCAN0_Handler = CAN0_Handler, + .pfnTCC0_Handler = TCC0_Handler, + .pfnTCC1_Handler = TCC1_Handler, + .pfnTCC2_Handler = TCC2_Handler, + .pfnTC0_Handler = TC0_Handler, + .pfnTC1_Handler = TC1_Handler, + .pfnTC2_Handler = TC2_Handler, + .pfnTC3_Handler = TC3_Handler, + .pfnTC4_Handler = TC4_Handler, + .pfnADC0_Handler = ADC0_Handler, + .pfnADC1_Handler = ADC1_Handler, + .pfnAC_Handler = AC_Handler, + .pfnDAC_Handler = DAC_Handler, + .pfnSDADC_Handler = SDADC_Handler, + .pfnPTC_Handler = PTC_Handler, + + +}; + +/******************************************************************************* + End of File +*/ diff --git a/bms_e18a/bms_e18a_config/src/config/default/interrupts.h b/bms_e18a/bms_e18a_config/src/config/default/interrupts.h new file mode 100644 index 00000000..36226044 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/interrupts.h @@ -0,0 +1,70 @@ +/******************************************************************************* + System Interrupts File + + Company: + Microchip Technology Inc. + + File Name: + interrupt.h + + Summary: + Interrupt vectors mapping + + Description: + This file contains declarations of device vectors used by Harmony 3 + *******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + *******************************************************************************/ +// DOM-IGNORE-END + +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Handler Routines +// ***************************************************************************** +// ***************************************************************************** +void Reset_Handler (void); +void NonMaskableInt_Handler (void); +void HardFault_Handler (void); +void RTC_InterruptHandler (void); +void SERCOM0_USART_InterruptHandler (void); +void SERCOM1_USART_InterruptHandler (void); +void SERCOM2_USART_InterruptHandler (void); +void SERCOM3_USART_InterruptHandler (void); + + + +#endif // INTERRUPTS_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/libc_syscalls.c b/bms_e18a/bms_e18a_config/src/config/default/libc_syscalls.c new file mode 100644 index 00000000..ae819a61 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/libc_syscalls.c @@ -0,0 +1,61 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include +#include "device.h" /* for ARM CMSIS __BKPT() */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated twice. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* Harmony specific + * We implement only the syscalls we want over the stubs provided by libpic32c + */ +extern void _exit(int status); + +void _exit(int status) +{ + /* Software breakpoint */ +#ifdef __DEBUG + __BKPT(0); +#endif + + /* halt CPU */ + while (true) + { + } +} + +#ifdef __cplusplus +} +#endif + +/* MISRAC 2012 deviation block end */ diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can0.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can0.c new file mode 100644 index 00000000..56a2d466 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can0.c @@ -0,0 +1,705 @@ +/******************************************************************************* + Controller Area Network (CAN) Peripheral Library Source File + + Company: + Microchip Technology Inc. + + File Name: + plib_can0.c + + Summary: + CAN peripheral library interface. + + Description: + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Header Includes +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include "interrupts.h" +#include "plib_can0.h" + +// ***************************************************************************** +// ***************************************************************************** +// Global Data +// ***************************************************************************** +// ***************************************************************************** +#define CAN_STD_ID_Msk 0x7FFU + +static CAN_OBJ can0Obj; + +// ***************************************************************************** +// ***************************************************************************** +// CAN0 PLib Interface Routines +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void CAN0_Initialize(void) + + Summary: + Initializes given instance of the CAN peripheral. + + Precondition: + None. + + Parameters: + None. + + Returns: + None +*/ +void CAN0_Initialize(void) +{ + /* Start CAN initialization */ + CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + /* Set Nominal Bit timing and Prescaler Register */ + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(23UL) | CAN_NBTP_NTSEG1(70UL) | CAN_NBTP_NBRP(0UL) | CAN_NBTP_NSJW(23UL); + + + /* Global Filter Configuration Register */ + CAN0_REGS->CAN_GFC = CAN_GFC_ANFS_REJECT | CAN_GFC_ANFE_REJECT; + + /* Set the operation mode */ + + + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + (void) memset(&can0Obj.msgRAMConfig, 0x00, sizeof(CAN_MSG_RAM_CONFIG)); +} + + +// ***************************************************************************** +/* Function: + bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) + + Summary: + Transmit multiple messages into CAN bus from Tx FIFO. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfMessage - Total number of message. + txBuffer - Pointer to Tx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer) +{ + uint8_t *txFifo = NULL; + uint8_t *txBuf = (uint8_t *)txBuffer; + uint32_t bufferNumber = 0U; + uint8_t tfqpi = 0U; + uint8_t count = 0U; + bool transmitFifo_event = false; + + if (!(((numberOfMessage < 1U) || (numberOfMessage > 1U)) || (txBuffer == NULL))) + { + + tfqpi = (uint8_t)((CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos); + + for (count = 0U; count < numberOfMessage; count++) + { + txFifo = (uint8_t *)((uint8_t*)can0Obj.msgRAMConfig.txBuffersAddress + ((uint32_t)tfqpi * CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE)); + + (void) memcpy(txFifo, txBuf, CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE); + + txBuf += CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE; + bufferNumber |= (1UL << tfqpi); + tfqpi++; + if (tfqpi == 1U) + { + tfqpi = 0U; + } + } + + __DSB(); + + /* Set Transmission request */ + CAN0_REGS->CAN_TXBAR = bufferNumber; + + transmitFifo_event = true; + } + return transmitFifo_event; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN0_TxFifoFreeLevelGet(void) + + Summary: + Returns Tx FIFO Free Level. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Tx FIFO Free Level. +*/ +uint8_t CAN0_TxFifoFreeLevelGet(void) +{ + return (uint8_t)(CAN0_REGS->CAN_TXFQS & CAN_TXFQS_TFFL_Msk); +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) + + Summary: + Check if Transmission request is pending for the specific Tx buffer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + true - Transmission request is pending. + false - Transmission request is not pending. +*/ +bool CAN0_TxBufferIsBusy(uint8_t bufferNumber) +{ + return ((CAN0_REGS->CAN_TXBRP & (1UL << bufferNumber)) != 0U); +} + +// ***************************************************************************** +/* Function: + bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) + + Summary: + Read Tx Event FIFO for the transmitted messages. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + numberOfTxEvent - Total number of Tx Event + txEventFifo - Pointer to Tx Event FIFO + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo) +{ + uint8_t txefgi = 0U; + uint8_t count = 0U; + uint8_t *txEvent = NULL; + uint8_t *txEvtFifo = (uint8_t *)txEventFifo; + bool txFifo_event = false; + + if (txEventFifo != NULL) + { + /* Read data from the Rx FIFO0 */ + txefgi = (uint8_t)((CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos); + for (count = 0U; count < numberOfTxEvent; count++) + { + txEvent = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.txEventFIFOAddress + ((uint32_t)txefgi * sizeof(CAN_TX_EVENT_FIFO))); + + (void) memcpy(txEvtFifo, txEvent, sizeof(CAN_TX_EVENT_FIFO)); + + if ((count + 1U) == numberOfTxEvent) + { + break; + } + txEvtFifo += sizeof(CAN_TX_EVENT_FIFO); + txefgi++; + if (txefgi == 1U) + { + txefgi = 0U; + } + } + + /* Ack the Tx Event FIFO position */ + CAN0_REGS->CAN_TXEFA = CAN_TXEFA_EFAI((uint32_t)txefgi); + + txFifo_event = true; + } + return txFifo_event; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN0_TxEventFifoFillLevelGet(void) + + Summary: + Returns Tx Event FIFO Fill Level. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Tx Event FIFO Fill Level. +*/ +uint8_t CAN0_TxEventFifoFillLevelGet(void) +{ + return (uint8_t)(CAN0_REGS->CAN_TXEFS & CAN_TXEFS_EFFL_Msk); +} + + +// ***************************************************************************** +/* Function: + bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) + + Summary: + Read messages from Rx FIFO0/FIFO1. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + rxFifoNum - Rx FIFO number + numberOfMessage - Total number of message + rxBuffer - Pointer to Rx buffer + + Returns: + Request status. + true - Request was successful. + false - Request has failed. +*/ +bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer) +{ + uint8_t rxgi = 0U; + uint8_t count = 0U; + uint8_t *rxFifo = NULL; + uint8_t *rxBuf = (uint8_t *)rxBuffer; + bool status = false; + + if (rxBuffer != NULL) + { + switch (rxFifoNum) + { + case CAN_RX_FIFO_0: + /* Read data from the Rx FIFO0 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO0Address + ((uint32_t)rxgi * CAN0_RX_FIFO0_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO0_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN0_RX_FIFO0_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF0A = CAN_RXF0A_F0AI((uint32_t)rxgi); + + status = true; + break; + case CAN_RX_FIFO_1: + /* Read data from the Rx FIFO1 */ + rxgi = (uint8_t)((CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos); + for (count = 0U; count < numberOfMessage; count++) + { + rxFifo = (uint8_t *) ((uint8_t *)can0Obj.msgRAMConfig.rxFIFO1Address + ((uint32_t)rxgi * CAN0_RX_FIFO1_ELEMENT_SIZE)); + + (void) memcpy(rxBuf, rxFifo, CAN0_RX_FIFO1_ELEMENT_SIZE); + + if ((count + 1U) == numberOfMessage) + { + break; + } + rxBuf += CAN0_RX_FIFO1_ELEMENT_SIZE; + rxgi++; + if (rxgi == 1U) + { + rxgi = 0U; + } + } + /* Ack the fifo position */ + CAN0_REGS->CAN_RXF1A = CAN_RXF1A_F1AI((uint32_t)rxgi); + + status = true; + break; + default: + /* Do nothing */ + break; + } + } + return status; +} + +// ***************************************************************************** +/* Function: + uint8_t CAN0_RxFifoFillLevelGet(CAN_RX_FIFO_NUM rxFifoNum) + + Summary: + Returns Rx FIFO0/FIFO1 Fill Level. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Rx FIFO0/FIFO1 Fill Level. +*/ +uint8_t CAN0_RxFifoFillLevelGet(CAN_RX_FIFO_NUM rxFifoNum) +{ + uint8_t fillLevel = 0U; + + if (rxFifoNum == CAN_RX_FIFO_0) + { + fillLevel = (uint8_t)(CAN0_REGS->CAN_RXF0S & CAN_RXF0S_F0FL_Msk); + } + else + { + fillLevel = (uint8_t)(CAN0_REGS->CAN_RXF1S & CAN_RXF1S_F1FL_Msk); + } + return fillLevel; +} + +// ***************************************************************************** +/* Function: + CAN_ERROR CAN0_ErrorGet(void) + + Summary: + Returns the error during transfer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + None. + + Returns: + Error during transfer. +*/ +CAN_ERROR CAN0_ErrorGet(void) +{ + CAN_ERROR error; + uint32_t errorStatus = CAN0_REGS->CAN_PSR; + + error = (CAN_ERROR) ((errorStatus & CAN_PSR_LEC_Msk) | (errorStatus & CAN_PSR_EP_Msk) | (errorStatus & CAN_PSR_EW_Msk) + | (errorStatus & CAN_PSR_BO_Msk) | (errorStatus & CAN_PSR_DLEC_Msk) | (errorStatus & CAN_PSR_PXE_Msk)); + + if ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + } + + return error; +} + +// ***************************************************************************** +/* Function: + void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) + + Summary: + Returns the transmit and receive error count during transfer. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + txErrorCount - Transmit Error Count to be received + rxErrorCount - Receive Error Count to be received + + Returns: + None. +*/ +void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount) +{ + *txErrorCount = (uint8_t)(CAN0_REGS->CAN_ECR & CAN_ECR_TEC_Msk); + *rxErrorCount = (uint8_t)((CAN0_REGS->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos); +} + +// ***************************************************************************** +/* Function: + bool CAN0_InterruptGet(CAN_INTERRUPT_MASK interruptMask) + + Summary: + Returns the Interrupt status. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + interruptMask - Interrupt source number + + Returns: + true - Requested interrupt is occurred. + false - Requested interrupt is not occurred. +*/ +bool CAN0_InterruptGet(CAN_INTERRUPT_MASK interruptMask) +{ + return ((CAN0_REGS->CAN_IR & (uint32_t)interruptMask) != 0x0U); +} + +// ***************************************************************************** +/* Function: + void CAN0_InterruptClear(CAN_INTERRUPT_MASK interruptMask) + + Summary: + Clears Interrupt status. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + interruptMask - Interrupt to be cleared + + Returns: + None +*/ +void CAN0_InterruptClear(CAN_INTERRUPT_MASK interruptMask) +{ + CAN0_REGS->CAN_IR = (uint32_t)interruptMask; +} + +// ***************************************************************************** +/* Function: + void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) + + Summary: + Set the Message RAM Configuration. + + Precondition: + CAN0_Initialize must have been called for the associated CAN instance. + + Parameters: + msgRAMConfigBaseAddress - Pointer to application allocated buffer base address. + Application must allocate buffer from non-cached + contiguous memory and buffer size must be + CAN0_MESSAGE_RAM_CONFIG_SIZE + + Returns: + None +*/ +/* MISRA C-2012 Rule 11.3 violated 4 times below. Deviation record ID - H3_MISRAC_2012_R_11_3_DR_1*/ +void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress) +{ + uint32_t offset = 0U; + uint32_t msgRAMConfigBaseAddr = (uint32_t)msgRAMConfigBaseAddress; + + (void) memset(msgRAMConfigBaseAddress, 0x00, CAN0_MESSAGE_RAM_CONFIG_SIZE); + + /* Set CAN CCCR Init for Message RAM Configuration */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + can0Obj.msgRAMConfig.rxFIFO0Address = (can_rxf0e_registers_t *)msgRAMConfigBaseAddr; + offset = CAN0_RX_FIFO0_SIZE; + /* Receive FIFO 0 Configuration Register */ + CAN0_REGS->CAN_RXF0C = CAN_RXF0C_F0S(1UL) | CAN_RXF0C_F0WM(0UL) | CAN_RXF0C_F0OM_Msk | + CAN_RXF0C_F0SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO0Address); + + can0Obj.msgRAMConfig.rxFIFO1Address = (can_rxf1e_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_RX_FIFO1_SIZE; + /* Receive FIFO 1 Configuration Register */ + CAN0_REGS->CAN_RXF1C = CAN_RXF1C_F1S(1UL) | CAN_RXF1C_F1WM(0UL) | CAN_RXF1C_F1OM_Msk | + CAN_RXF1C_F1SA((uint32_t)can0Obj.msgRAMConfig.rxFIFO1Address); + + can0Obj.msgRAMConfig.txBuffersAddress = (can_txbe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_TX_FIFO_BUFFER_SIZE; + /* Transmit Buffer/FIFO Configuration Register */ + CAN0_REGS->CAN_TXBC = CAN_TXBC_TFQS(1UL) | + CAN_TXBC_TBSA((uint32_t)can0Obj.msgRAMConfig.txBuffersAddress); + + can0Obj.msgRAMConfig.txEventFIFOAddress = (can_txefe_registers_t *)(msgRAMConfigBaseAddr + offset); + offset += CAN0_TX_EVENT_FIFO_SIZE; + /* Transmit Event FIFO Configuration Register */ + CAN0_REGS->CAN_TXEFC = CAN_TXEFC_EFWM(0UL) | CAN_TXEFC_EFS(1UL) | + CAN_TXEFC_EFSA((uint32_t)can0Obj.msgRAMConfig.txEventFIFOAddress); + + + /* Reference offset variable once to remove warning about the variable not being used after increment */ + (void)offset; + + /* Complete Message RAM Configuration by clearing CAN CCCR Init */ + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for configuration complete */ + } +} +/* MISRAC 2012 deviation block end for 11.3 */ + + + + +void CAN0_SleepModeEnter(void) +{ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CSR_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) != CAN_CCCR_CSA_Msk) + { + /* Wait for clock stop request to complete */ + } +} + +void CAN0_SleepModeExit(void) +{ + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_CSR_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_CSA_Msk) == CAN_CCCR_CSA_Msk) + { + /* Wait for no clock stop */ + } + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } +} + +bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + uint32_t numOfTimeQuanta; + uint8_t tseg1; + float temp1; + float temp2; + + if ((setup != NULL) && (bitTiming != NULL)) + { + if (setup->nominalBitTimingSet == true) + { + numOfTimeQuanta = CAN0_CLOCK_FREQUENCY / (setup->nominalBitRate * ((uint32_t)setup->nominalPrescaler + 1U)); + if ((numOfTimeQuanta >= 4U) && (numOfTimeQuanta <= 385U)) + { + if (setup->nominalSamplePoint < 50.0f) + { + setup->nominalSamplePoint = 50.0f; + } + temp1 = (float)numOfTimeQuanta; + temp2 = (temp1 * setup->nominalSamplePoint) / 100.0f; + tseg1 = (uint8_t)temp2; + bitTiming->nominalBitTiming.nominalTimeSegment2 = (uint8_t)(numOfTimeQuanta - tseg1 - 1U); + bitTiming->nominalBitTiming.nominalTimeSegment1 = tseg1 - 2U; + bitTiming->nominalBitTiming.nominalSJW = bitTiming->nominalBitTiming.nominalTimeSegment2; + bitTiming->nominalBitTiming.nominalPrescaler = setup->nominalPrescaler; + bitTiming->nominalBitTimingSet = true; + status = true; + } + else + { + bitTiming->nominalBitTimingSet = false; + } + } + } + + return status; +} + +bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming) +{ + bool status = false; + bool nominalBitTimingSet = false; + + if ((bitTiming->nominalBitTimingSet == true) + && (bitTiming->nominalBitTiming.nominalTimeSegment1 >= 0x1U) + && (bitTiming->nominalBitTiming.nominalTimeSegment2 <= 0x7FU) + && (bitTiming->nominalBitTiming.nominalPrescaler <= 0x1FFU) + && (bitTiming->nominalBitTiming.nominalSJW <= 0x7FU)) + { + nominalBitTimingSet = true; + } + + if (nominalBitTimingSet == true) + { + /* Start CAN initialization */ + CAN0_REGS->CAN_CCCR = CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) != CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + + /* Set CCE to unlock the configuration registers */ + CAN0_REGS->CAN_CCCR |= CAN_CCCR_CCE_Msk; + + /* Set Nominal Bit timing and Prescaler Register */ + CAN0_REGS->CAN_NBTP = CAN_NBTP_NTSEG2(bitTiming->nominalBitTiming.nominalTimeSegment2) | CAN_NBTP_NTSEG1(bitTiming->nominalBitTiming.nominalTimeSegment1) | CAN_NBTP_NBRP(bitTiming->nominalBitTiming.nominalPrescaler) | CAN_NBTP_NSJW(bitTiming->nominalBitTiming.nominalSJW); + + /* Set the operation mode */ + + + CAN0_REGS->CAN_CCCR &= ~CAN_CCCR_INIT_Msk; + while ((CAN0_REGS->CAN_CCCR & CAN_CCCR_INIT_Msk) == CAN_CCCR_INIT_Msk) + { + /* Wait for initialization complete */ + } + status = true; + } + return status; +} + +/******************************************************************************* + End of File +*/ diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can0.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can0.h new file mode 100644 index 00000000..0201c79b --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can0.h @@ -0,0 +1,124 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company: + Microchip Technology Inc. + + File Name: + plib_can0.h + + Summary: + CAN PLIB interface declarations. + + Description: + The CAN plib provides a simple interface to manage the CAN modules on + Microchip microcontrollers. This file defines the interface declarations + for the CAN plib. + + Remarks: + None. + +*******************************************************************************/ +//DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +//DOM-IGNORE-END + +#ifndef PLIB_CAN0_H +#define PLIB_CAN0_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +/* + * This section lists the other files that are included in this file. + */ +#include +#include + +#include "device.h" +#include "plib_can_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +#define CAN0_CLOCK_FREQUENCY 48000000U + +/* CAN0 Message RAM Configuration Size */ +#define CAN0_RX_FIFO0_ELEMENT_SIZE 16U +#define CAN0_RX_FIFO0_SIZE 16U +#define CAN0_RX_FIFO1_ELEMENT_SIZE 16U +#define CAN0_RX_FIFO1_SIZE 16U +#define CAN0_TX_FIFO_BUFFER_ELEMENT_SIZE 16U +#define CAN0_TX_FIFO_BUFFER_SIZE 16U +#define CAN0_TX_EVENT_FIFO_SIZE 8U + +/* CAN0_MESSAGE_RAM_CONFIG_SIZE to be used by application or driver + for allocating buffer from non-cached contiguous memory */ +#define CAN0_MESSAGE_RAM_CONFIG_SIZE 56U + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +void CAN0_Initialize(void); +bool CAN0_MessageTransmitFifo(uint8_t numberOfMessage, CAN_TX_BUFFER *txBuffer); +uint8_t CAN0_TxFifoFreeLevelGet(void); +bool CAN0_TxBufferIsBusy(uint8_t bufferNumber); +bool CAN0_TxEventFifoRead(uint8_t numberOfTxEvent, CAN_TX_EVENT_FIFO *txEventFifo); +uint8_t CAN0_TxEventFifoFillLevelGet(void); +bool CAN0_MessageReceiveFifo(CAN_RX_FIFO_NUM rxFifoNum, uint8_t numberOfMessage, CAN_RX_BUFFER *rxBuffer); +uint8_t CAN0_RxFifoFillLevelGet(CAN_RX_FIFO_NUM rxFifoNum); +CAN_ERROR CAN0_ErrorGet(void); +void CAN0_ErrorCountGet(uint8_t *txErrorCount, uint8_t *rxErrorCount); +bool CAN0_InterruptGet(CAN_INTERRUPT_MASK interruptMask); +void CAN0_InterruptClear(CAN_INTERRUPT_MASK interruptMask); +void CAN0_MessageRAMConfigSet(uint8_t *msgRAMConfigBaseAddress); +void CAN0_SleepModeEnter(void); +void CAN0_SleepModeExit(void); +bool CAN0_BitTimingCalculationGet(CAN_BIT_TIMING_SETUP *setup, CAN_BIT_TIMING *bitTiming); +bool CAN0_BitTimingSet(CAN_BIT_TIMING *bitTiming); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif +// DOM-IGNORE-END + +#endif // PLIB_CAN0_H + +/******************************************************************************* + End of File +*/ diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can_common.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can_common.h new file mode 100644 index 00000000..b5f9f963 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/can/plib_can_common.h @@ -0,0 +1,668 @@ +/******************************************************************************* + CAN Peripheral Library Interface Header File + + Company + Microchip Technology Inc. + + File Name + plib_can_common.h + + Summary + CAN peripheral library interface. + + Description + This file defines the interface to the CAN peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_CAN_COMMON_H +#define PLIB_CAN_COMMON_H + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + + // ***************************************************************************** +/* CAN Transfer Errors + + Summary: + CAN Transfer Error macros. + + Description: + Helper macros to identify CAN errors. + + Remarks: + None. +*/ + +#define CAN_ERROR_NONE 0x0U +#define CAN_ERROR_LEC_STUFF 0x1U +#define CAN_ERROR_LEC_FORM 0x2U +#define CAN_ERROR_LEC_ACK 0x3U +#define CAN_ERROR_LEC_BIT1 0x4U +#define CAN_ERROR_LEC_BIT0 0x5U +#define CAN_ERROR_LEC_CRC 0x6U +#define CAN_ERROR_LEC_NC 0x7U +#define CAN_ERROR_PASSIVE 0x20U +#define CAN_ERROR_WARNING_STATUS 0x40U +#define CAN_ERROR_BUS_OFF 0x80U +#define CAN_ERROR_DLEC_STUFF 0x100U +#define CAN_ERROR_DLEC_FORM 0x200U +#define CAN_ERROR_DLEC_ACK 0x300U +#define CAN_ERROR_DLEC_BIT1 0x400U +#define CAN_ERROR_DLEC_BIT0 0x500U +#define CAN_ERROR_DLEC_CRC 0x600U +#define CAN_ERROR_DLEC_NC 0x700U +#define CAN_ERROR_PROTOCOL_EXCEPTION_EVENT 0x4000U +#define CAN_ERROR_INVALID 0xFFFFFFFFU + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* CAN Rx FIFO Number + + Summary: + CAN Rx FIFO Number. + + Description: + This data type defines CAN Rx FIFO number for Rx FIFO0 and FIFO1. + + Remarks: + None. +*/ +typedef enum +{ + CAN_RX_FIFO_0 = 0U, + CAN_RX_FIFO_1 +} CAN_RX_FIFO_NUM; + +// ***************************************************************************** +/* CAN Interrupt Mask + + Summary: + CAN Interrupt Mask. + + Description: + This data type defines the CAN Interrupt sources number. + + Remarks: + None. +*/ +typedef enum +{ + CAN_INTERRUPT_RF0N_MASK = (1UL << 0U), + CAN_INTERRUPT_RF0W_MASK = (1UL << 1U), + CAN_INTERRUPT_RF0F_MASK = (1UL << 2U), + CAN_INTERRUPT_RF0L_MASK = (1UL << 3U), + CAN_INTERRUPT_RF1N_MASK = (1UL << 4U), + CAN_INTERRUPT_RF1W_MASK = (1UL << 5U), + CAN_INTERRUPT_RF1F_MASK = (1UL << 6U), + CAN_INTERRUPT_RF1L_MASK = (1UL << 7U), + CAN_INTERRUPT_HPM_MASK = (1UL << 8U), + CAN_INTERRUPT_TC_MASK = (1UL << 9U), + CAN_INTERRUPT_TCF_MASK = (1UL << 10U), + CAN_INTERRUPT_TFE_MASK = (1UL << 11U), + CAN_INTERRUPT_TEFN_MASK = (1UL << 12U), + CAN_INTERRUPT_TEFW_MASK = (1UL << 13U), + CAN_INTERRUPT_TEFF_MASK = (1UL << 14U), + CAN_INTERRUPT_TEFL_MASK = (1UL << 15U), + CAN_INTERRUPT_TSW_MASK = (1UL << 16U), + CAN_INTERRUPT_MRAF_MASK = (1UL << 17U), + CAN_INTERRUPT_TOO_MASK = (1UL << 18U), + CAN_INTERRUPT_DRX_MASK = (1UL << 19U), + CAN_INTERRUPT_ELO_MASK = (1UL << 22U), + CAN_INTERRUPT_EP_MASK = (1UL << 23U), + CAN_INTERRUPT_EW_MASK = (1UL << 24U), + CAN_INTERRUPT_BO_MASK = (1UL << 25U), + CAN_INTERRUPT_WDI_MASK = (1UL << 26U), + CAN_INTERRUPT_PEA_MASK = (1UL << 27U), + CAN_INTERRUPT_PED_MASK = (1UL << 28U), + CAN_INTERRUPT_ARA_MASK = (1UL << 29U) +}CAN_INTERRUPT_MASK; + +// ***************************************************************************** +/* CAN Transfer Error + + Summary: + CAN Transfer Error data type. + + Description: + This data type defines the CAN Transfer Error. + + Remarks: + None. +*/ +typedef uint32_t CAN_ERROR; + +// ***************************************************************************** +/* CAN Tx FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_FIFO_CALLBACK) (uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN TX/RX Buffers Callback + + Summary: + CAN Callback Function Pointer for TX/RX Buffers. + + Description: + This data type defines the CAN Callback Function Pointer for TX/RX Buffers. + + Remarks: + None. +*/ +typedef void (*CAN_TXRX_BUFFERS_CALLBACK) (uint8_t bufferNumber, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback + + Summary: + CAN Callback Function Pointer for Tx Event FIFO. + + Description: + This data type defines the CAN Callback Function Pointer for Tx Event FIFO. + + Remarks: + None. +*/ +typedef void (*CAN_TX_EVENT_FIFO_CALLBACK) (uint8_t numberOfTxEvent, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback + + Summary: + CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Description: + This data type defines the CAN Callback Function Pointer for Rx FIFO0/FIFO1. + + Remarks: + None. +*/ +typedef void (*CAN_RX_FIFO_CALLBACK) (uint8_t numberOfMessage, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Callback + + Summary: + CAN Callback Function Pointer. + + Description: + This data type defines the CAN Callback Function Pointer. + + Remarks: + None. +*/ +typedef void (*CAN_CALLBACK) (uint32_t interruptStatus, uintptr_t contextHandle); + +// ***************************************************************************** +/* CAN Message RAM Configuration + + Summary: + CAN Message RAM Configuration structure. + + Description: + This data structure defines the CAN Message RAM Base address for Rx FIFO0, + Rx FIFO1, Rx Buffers, Tx Buffers/FIFO, Tx Event FIFO, Standard Message ID Filter and + Extended Message ID Filter configuration. + + Remarks: + None. +*/ +typedef struct +{ + /* Rx FIFO0 base address */ + can_rxf0e_registers_t *rxFIFO0Address; + + /* Rx FIFO1 base address */ + can_rxf1e_registers_t *rxFIFO1Address; + + /* Rx Buffer base address */ + can_rxbe_registers_t *rxBuffersAddress; + + /* Tx Buffers/FIFO base address */ + can_txbe_registers_t *txBuffersAddress; + + /* Tx Event FIFO base address */ + can_txefe_registers_t *txEventFIFOAddress; + + /* Standard Message ID Filter base address */ + can_sidfe_registers_t *stdMsgIDFilterAddress; + + /* Extended Message ID Filter base address */ + can_xidfe_registers_t *extMsgIDFilterAddress; +} CAN_MSG_RAM_CONFIG; + +// ***************************************************************************** +/* CAN Rx Buffer and FIFO Element + + Summary: + CAN Rx Buffer and FIFO Element Structure. + + Description: + This data structure defines CAN Rx Buffer and FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Rx Timestamp */ + unsigned int rxts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :2; + /* Filter Index */ + unsigned int fidx:7; + /* Accepted Non-matching Frame */ + unsigned int anmf:1; + + /* Data field */ + uint8_t data[8]; + +} CAN_RX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Buffer Element + + Summary: + CAN Tx Buffer Element Structure. + + Description: + This data structure defines CAN Tx Buffer Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Reserved */ + unsigned int :16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switching */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Reserved */ + unsigned int :1; + /* Event FIFO Control */ + unsigned int efc:1; + /* Message Marker */ + unsigned int mm:8; + + /* Data field */ + uint8_t data[8]; + +} CAN_TX_BUFFER; + +// ***************************************************************************** +/* CAN Tx Event FIFO Element + + Summary: + CAN Tx Event FIFO Element Structure. + + Description: + This data structure defines CAN Tx Event FIFO Element. + + Remarks: + None. +*/ +typedef struct +{ + /* Identifier */ + unsigned int id:29; + /* Remote Transmission Request */ + unsigned int rtr:1; + /* Extended Identifier */ + unsigned int xtd:1; + /* Error State Indicator */ + unsigned int esi:1; + + /* Tx Timestamp */ + unsigned int txts:16; + /* Data Length Code */ + unsigned int dlc:4; + /* Bit Rate Switch */ + unsigned int brs:1; + /* FD Format */ + unsigned int fdf:1; + /* Event Type */ + unsigned int et:2; + /* Message Marker */ + unsigned int mm:8; + +} CAN_TX_EVENT_FIFO; + +// ***************************************************************************** +/* CAN Nominal Bit Timing Parameters + + Summary: + CAN Nominal Bit Timing Parameter structure. + + Description: + This data structure defines Nominal Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal Time segment after sample point */ + uint8_t nominalTimeSegment2; + + /* Nominal Time segment before sample point */ + uint8_t nominalTimeSegment1; + + /* Nominal Baud Rate Prescaler */ + uint16_t nominalPrescaler; + + /* Nominal Syncronization Jump Width */ + uint8_t nominalSJW; + +} CAN_NOMINAL_BIT_TIMING; + +// ***************************************************************************** +/* CAN Data Bit Timing Parameters + + Summary: + CAN Data Bit Timing Parameter structure. + + Description: + This data structure defines Data Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Data Time segment after sample point */ + uint8_t dataTimeSegment2; + + /* Data Time segment before sample point */ + uint8_t dataTimeSegment1; + + /* Data Baud Rate Prescaler */ + uint8_t dataPrescaler; + + /* Data Syncronization Jump Width */ + uint8_t dataSJW; + +} CAN_DATA_BIT_TIMING; + +// ***************************************************************************** +/* CAN Bit Timing Parameters + + Summary: + CAN Bit Timing Parameter structure. + + Description: + This data structure defines Bit Timing Parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal bit timing set flag */ + bool nominalBitTimingSet; + + /* Nominal bit timing parameters */ + CAN_NOMINAL_BIT_TIMING nominalBitTiming; + + /* Data bit timing set flag */ + bool dataBitTimingSet; + + /* Data bit timing parameters */ + CAN_DATA_BIT_TIMING dataBitTiming; +} CAN_BIT_TIMING; + +// ***************************************************************************** +/* CAN Bit Timing Setup + + Summary: + CAN Bit Timing Setup structure. + + Description: + This data structure defines Bit Timing Setup parameters. + + Remarks: + None. +*/ +typedef struct +{ + /* Nominal bit timing set flag */ + bool nominalBitTimingSet; + + /* Nominal bit rate */ + uint32_t nominalBitRate; + + /* Nominal Sample Point */ + float nominalSamplePoint; + + /* Nominal Baud Rate Prescaler */ + uint16_t nominalPrescaler; + + /* Data bit timing set flag */ + bool dataBitTimingSet; + + /* Data bit rate */ + uint32_t dataBitRate; + + /* Data Sample Point */ + float dataSamplePoint; + + /* Data Baud Rate Prescaler */ + uint8_t dataPrescaler; + +} CAN_BIT_TIMING_SETUP; + +// ***************************************************************************** +/* CAN Tx FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx/Rx Buffers Callback Object + + Summary: + CAN transfer event callback structure for Tx/Rx Buffers. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TXRX_BUFFERS_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TXRX_BUFFERS_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Tx Event FIFO Callback Object + + Summary: + CAN transfer event callback structure for Tx Event FIFO. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_TX_EVENT_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_TX_EVENT_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Rx FIFO0/FIFO1 Callback Object + + Summary: + CAN transfer event callback structure for Rx FIFO0/FIFO1. + + Description: + This data structure stores transfer event callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* Transfer Event Callback */ + CAN_RX_FIFO_CALLBACK callback; + + /* Transfer Event Callback Context */ + uintptr_t context; +} CAN_RX_FIFO_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN Callback Object + + Summary: + CAN interrupt status callback structure. + + Description: + This data structure stores interrupt status callback and it's context. + + Remarks: + None. +*/ +typedef struct +{ + /* CAN Interrupt Status Callback */ + CAN_CALLBACK callback; + + /* CAN Interrupt Status Callback Context */ + uintptr_t context; +} CAN_CALLBACK_OBJ; + +// ***************************************************************************** +/* CAN PLib Instance Object + + Summary: + CAN PLib Object structure. + + Description: + This data structure defines the CAN PLib Instance Object. + + Remarks: + None. +*/ +typedef struct +{ + /* Message RAM Configuration */ + CAN_MSG_RAM_CONFIG msgRAMConfig; + +} CAN_OBJ; + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif //PLIB_CAN_COMMON_H +/******************************************************************************* + End of File +*/ diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/clock/plib_clock.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/clock/plib_clock.c new file mode 100644 index 00000000..e030cfb8 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/clock/plib_clock.c @@ -0,0 +1,155 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.c + + Summary: + CLOCK PLIB Implementation File. + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_clock.h" +#include "device.h" +#include "interrupts.h" + + + + +static void OSCCTRL_Initialize(void) +{ + uint32_t calibValue = (uint32_t)(((*(uint64_t*)0x00806020UL) >> 19 ) & 0x3fffffUL); + OSCCTRL_REGS->OSCCTRL_CAL48M = calibValue; + + + /* Selection of the Division Value */ + OSCCTRL_REGS->OSCCTRL_OSC48MDIV = (uint8_t)OSCCTRL_OSC48MDIV_DIV(0UL); + + while((OSCCTRL_REGS->OSCCTRL_OSC48MSYNCBUSY & OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) == OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Msk) + { + /* Waiting for the synchronization */ + } + + while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_OSC48MRDY_Msk) != OSCCTRL_STATUS_OSC48MRDY_Msk) + { + /* Waiting for the OSC48M Ready state */ + } + OSCCTRL_REGS->OSCCTRL_OSC48MCTRL |= OSCCTRL_OSC48MCTRL_ONDEMAND_Msk; + +} + +static void OSC32KCTRL_Initialize(void) +{ + OSC32KCTRL_REGS->OSC32KCTRL_OSC32K = 0x0UL; + + OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0UL); +} + + + +static void GCLK0_Initialize(void) +{ + + GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1UL) | GCLK_GENCTRL_SRC(6UL) | GCLK_GENCTRL_GENEN_Msk; + + while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL0_Msk) == GCLK_SYNCBUSY_GENCTRL0_Msk) + { + /* wait for the Generator 0 synchronization */ + } +} + +void CLOCK_Initialize (void) +{ + /* Function to Initialize the Oscillators */ + OSCCTRL_Initialize(); + + /* Function to Initialize the 32KHz Oscillators */ + OSC32KCTRL_Initialize(); + + GCLK0_Initialize(); + + + /* Selection of the Generator and write Lock for EIC */ + GCLK_REGS->GCLK_PCHCTRL[2] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[2] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM0_CORE */ + GCLK_REGS->GCLK_PCHCTRL[19] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[19] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM1_CORE */ + GCLK_REGS->GCLK_PCHCTRL[20] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[20] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM2_CORE */ + GCLK_REGS->GCLK_PCHCTRL[21] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[21] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for SERCOM3_CORE */ + GCLK_REGS->GCLK_PCHCTRL[22] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[22] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Selection of the Generator and write Lock for CAN0 */ + GCLK_REGS->GCLK_PCHCTRL[26] = GCLK_PCHCTRL_GEN(0x0UL) | GCLK_PCHCTRL_CHEN_Msk; + + while ((GCLK_REGS->GCLK_PCHCTRL[26] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk) + { + /* Wait for synchronization */ + } + /* Configure the AHB Bridge Clocks */ + MCLK_REGS->MCLK_AHBMASK = 0x1dffU; + + + + /* Configure the APBC Bridge Clocks */ + MCLK_REGS->MCLK_APBCMASK = 0x1eU; + + +} + + + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/clock/plib_clock.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/clock/plib_clock.h new file mode 100644 index 00000000..71d6690a --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/clock/plib_clock.h @@ -0,0 +1,143 @@ +/******************************************************************************* + CLOCK PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_clock.h + + Summary: + CLOCK PLIB Header File. + + Description: + The Clock PLIB initializes all the oscillators based on the + requirements. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_CLOCK_H +#define PLIB_CLOCK_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of +this interface. +*/ + +// ***************************************************************************** +/* Function: + void CLOCK_Initialize (void); + + Summary: + Initializes all the modules related to the system clock. + + Description: + This function initializes the clock as defined by the MHC and Clock Manager + selections. The function will configure the NVM Flash Wait states based on + the configured CPU operational frequency. It will then configure the + oscillators. + + For each of the clock sources (External Oscillator, Digital Phase Locked + Loop, Internal 48MHz Oscillator, External 32KHz oscillator and the Internal + 32KHz oscillator) enabled in MHC, the function will configure the clock + settings and will then wait till the clock is ready. In case of DPLL, the + function will wait till a lock is obtained. + + The function will then configure the Generic clock generators based on MHC + configurations. If a Generic Clock is enabled in MHC, this will be enabled + in the CLOCK_Initialize() function. The function will apply the CPU clock + divider and will wait for the Main Clock module to get ready. If the Main + Clock to the Peripheral APB and AHB interfaces was enabled in MHC, these + will be enabled in the CLOCK_Initialize() function. If the Peripheral Clock + Channels were enabled in MHC, these will be enabled in the + CLOCK_Initialize() function. + + The peripheral AHB and APB main clock and peripheral channel clocks will be + enabled when the peripheral specific initialize functions are called. This + will override the setting in MHC. The Generic Clock Generator source for + desired peripheral channel must be configured in MHC. + + Precondition: + MHC GUI should be configured with the right values. Incorrect configuration + of the Clock will result in incorrect peripheral behavior or a non + functional device. + + Parameters: + None. + + Returns: + None. + + Example: + + CLOCK_Initialize(); + + + Remarks: + This function should be called before calling other Clock library functions. +*/ + +void CLOCK_Initialize (void); + + + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif + +#endif /* PLIB_CLOCK_H */ + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/eic/plib_eic.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/eic/plib_eic.c new file mode 100644 index 00000000..e87bf923 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/eic/plib_eic.c @@ -0,0 +1,114 @@ +/******************************************************************************* + External Interrupt Controller (EIC) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_eic.c + + Summary + Source for EIC peripheral library interface Implementation. + + Description + This file defines the interface to the EIC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. + +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "plib_eic.h" +#include "interrupts.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** + + + +void EIC_Initialize (void) +{ + /* Reset all registers in the EIC module to their initial state and + EIC will be disabled. */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_SWRST_Msk; + + while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_SWRST_Msk) == EIC_SYNCBUSY_SWRST_Msk) + { + /* Wait for sync */ + } + + /* EIC is by default clocked by GCLK */ + + /* NMI Control register */ + + /* Interrupt sense type and filter control for EXTINT channels 0 to 7*/ + EIC_REGS->EIC_CONFIG[0] = EIC_CONFIG_SENSE0_NONE | + EIC_CONFIG_SENSE1_NONE | + EIC_CONFIG_SENSE2_NONE | + EIC_CONFIG_SENSE3_NONE | + EIC_CONFIG_SENSE4_NONE | + EIC_CONFIG_SENSE5_NONE | + EIC_CONFIG_SENSE6_NONE | + EIC_CONFIG_SENSE7_NONE ; + + /* Interrupt sense type and filter control for EXTINT channels 8 to 15 */ + EIC_REGS->EIC_CONFIG[1] = EIC_CONFIG_SENSE0_NONE + | EIC_CONFIG_SENSE1_NONE + | EIC_CONFIG_SENSE2_NONE + | EIC_CONFIG_SENSE3_NONE + | EIC_CONFIG_SENSE4_NONE + | EIC_CONFIG_SENSE5_NONE + | EIC_CONFIG_SENSE6_NONE + | EIC_CONFIG_SENSE7_NONE ; + + + + + + + /* Enable the EIC */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_ENABLE_Msk; + + while((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_ENABLE_Msk) == EIC_SYNCBUSY_ENABLE_Msk) + { + /* Wait for sync */ + } +} diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/eic/plib_eic.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/eic/plib_eic.h new file mode 100644 index 00000000..e123682b --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/eic/plib_eic.h @@ -0,0 +1,183 @@ +/******************************************************************************* External Interrupt Controller (EIC) PLIB + + Company + Microchip Technology Inc. + + File Name + plib_eic.h + + Summary + EIC PLIB Header File. + + Description + This file defines the interface to the EIC peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +/* Guards against multiple inclusion */ +#ifndef PLIB_EIC_H +#define PLIB_EIC_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +/* This section lists the other files that are included in this file. +*/ + +#include "device.h" +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +/* The following data type definitions are used by the functions in this + interface and should be considered part of it. +*/ + +/* EIC Pin Count */ +#define EXTINT_COUNT (16U) + +// ***************************************************************************** +/* EIC Pins + + Summary: + Identifies the available EIC pins. + + Description: + This enumeration identifies all the available EIC pins. Not all pins will be + implemented in a device. The pins described here are for documentation + purposes only. The MHC will generate this enumeration with the enabled EIC + pins only. The application should not use the constant value that are + assigned to enumeration constants as this may vary between devices. + + Remarks: + None. +*/ + + +#define EIC_PIN_MAX (16U) + +typedef uint16_t EIC_PIN; + + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** +/* The following functions make up the methods (set of possible operations) of + this interface. +*/ + +// ***************************************************************************** +/* Function: + void EIC_Initialize (void); + + Summary: + Initializes given instance of EIC peripheral. + + Description: + This function initializes given instance of EIC peripheral of the device + with the values configured in MHC GUI. + + Precondition: + MHC GUI should be configured with the right values. + + Parameters: + None. + + Returns: + None. + + Example: + + EIC_Initialize(); + + + Remarks: + This function should only be called once during system initialization + before any other EIC function is called. +*/ + +void EIC_Initialize (void); + +// ***************************************************************************** +/* Function: + void EIC_InterruptEnable (EIC_PIN pin) + + Summary: + Enables interrupts on a pin. + + Description + This function enables interrupts on an external interrupt pin. + When enabled, the interrupt pin sense will be configured as per the + configuration set in MHC. + + Precondition: + EIC_Initialize() function must have been called for the + associated instance. + + Parameters: + pin - EIC Pin number + + Returns: + None + + Example: + + EIC_Initialize(); + EIC_InterruptEnable(EIC_PIN_3); + + + Remarks: + None. +*/ + + +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +#endif /* PLIB_EIC_H */ diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/evsys/plib_evsys.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/evsys/plib_evsys.c new file mode 100644 index 00000000..0876df57 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/evsys/plib_evsys.c @@ -0,0 +1,52 @@ +/******************************************************************************* + EVSYS Peripheral Library + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.c + + Summary: + EVSYS Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "plib_evsys.h" +#include "interrupts.h" + + +void EVSYS_Initialize( void ) +{ /*Event Channel User Configuration*/ + + +} + + + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/evsys/plib_evsys.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/evsys/plib_evsys.h new file mode 100644 index 00000000..9ea8b02b --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/evsys/plib_evsys.h @@ -0,0 +1,68 @@ +/******************************************************************************* + Interface definition of EVSYS PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_evsys.h + + Summary: + Interface definition of the Event System Plib (EVSYS). + + Description: + This file defines the interface for the EVSYS Plib. + It allows user to setup event generators and users. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef EVSYS_H // Guards against multiple inclusion +#define EVSYS_H + +#include "device.h" +#include +#include + +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface +// ***************************************************************************** +// ***************************************************************************** + + + +/***************************** EVSYS API *******************************/ +void EVSYS_Initialize( void ); + +#ifdef __cplusplus // Provide C++ Compatibility + } +#endif + +#endif diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvic/plib_nvic.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvic/plib_nvic.c new file mode 100644 index 00000000..a63cd19f --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvic/plib_nvic.c @@ -0,0 +1,127 @@ +/******************************************************************************* + NVIC PLIB Implementation + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.c + + Summary: + NVIC PLIB Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#include "device.h" +#include "plib_nvic.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVIC Implementation +// ***************************************************************************** +// ***************************************************************************** + +void NVIC_Initialize( void ) +{ + + /* Enable NVIC Controller */ + __DMB(); + __enable_irq(); + + /* Enable the interrupt sources and configure the priorities as configured + * from within the "Interrupt Manager" of MHC. */ + NVIC_SetPriority(RTC_IRQn, 3); + NVIC_EnableIRQ(RTC_IRQn); + NVIC_SetPriority(SERCOM0_IRQn, 3); + NVIC_EnableIRQ(SERCOM0_IRQn); + NVIC_SetPriority(SERCOM1_IRQn, 3); + NVIC_EnableIRQ(SERCOM1_IRQn); + NVIC_SetPriority(SERCOM2_IRQn, 3); + NVIC_EnableIRQ(SERCOM2_IRQn); + NVIC_SetPriority(SERCOM3_IRQn, 3); + NVIC_EnableIRQ(SERCOM3_IRQn); + + + + +} + +void NVIC_INT_Enable( void ) +{ + __DMB(); + __enable_irq(); +} + +bool NVIC_INT_Disable( void ) +{ + bool processorStatus = (__get_PRIMASK() == 0U); + + __disable_irq(); + __DMB(); + + return processorStatus; +} + +void NVIC_INT_Restore( bool state ) +{ + if( state == true ) + { + __DMB(); + __enable_irq(); + } + else + { + __disable_irq(); + __DMB(); + } +} + +bool NVIC_INT_SourceDisable( IRQn_Type source ) +{ + bool processorStatus; + bool intSrcStatus; + + processorStatus = NVIC_INT_Disable(); + intSrcStatus = (NVIC_GetEnableIRQ(source) != 0U); + NVIC_DisableIRQ( source ); + NVIC_INT_Restore( processorStatus ); + + /* return the source status */ + return intSrcStatus; +} + +void NVIC_INT_SourceRestore( IRQn_Type source, bool status ) +{ + if( status ) { + NVIC_EnableIRQ( source ); + } + + return; +} \ No newline at end of file diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvic/plib_nvic.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvic/plib_nvic.h new file mode 100644 index 00000000..6d36bd14 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvic/plib_nvic.h @@ -0,0 +1,72 @@ +/******************************************************************************* + NVIC PLIB Header + + Company: + Microchip Technology Inc. + + File Name: + plib_nvic.h + + Summary: + NVIC PLIB Header File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_NVIC_H +#define PLIB_NVIC_H + +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + + +/***************************** NVIC Inline *******************************/ + +void NVIC_Initialize( void ); +void NVIC_INT_Enable( void ); +bool NVIC_INT_Disable( void ); +void NVIC_INT_Restore( bool state ); +bool NVIC_INT_SourceDisable( IRQn_Type source ); +void NVIC_INT_SourceRestore( IRQn_Type source, bool status ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END +#endif // PLIB_NVIC_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c new file mode 100644 index 00000000..36679253 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.c @@ -0,0 +1,260 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.c + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include "interrupts.h" +#include "plib_nvmctrl.h" + + +// ***************************************************************************** +// ***************************************************************************** +// Section: NVMCTRL Implementation +// ***************************************************************************** +// ***************************************************************************** + + +void NVMCTRL_Initialize(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY | NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS | NVMCTRL_CTRLB_RWS(2UL) | NVMCTRL_CTRLB_MANW_Msk; +} + +void NVMCTRL_CacheInvalidate(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_INVALL | NVMCTRL_CTRLA_CMDEX_KEY); +} +bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t *paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* Writing 32-bit words in the given address */ + for ( i = 0U; i < (NVMCTRL_RWWEEPROM_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEWP | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_RWWEEPROM_RowErase( uint32_t address ) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_RWWEEER | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ) +{ + uint32_t *paddress = (uint32_t*)address; + (void)memcpy(data, paddress, length); + return true; +} + +bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + return true; +} + +bool NVMCTRL_PageBufferCommit( const uint32_t address) +{ + uint16_t command = NVMCTRL_CTRLA_CMD_WP_Val; + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + if (address >= NVMCTRL_RWWEEPROM_START_ADDRESS) + { + command = NVMCTRL_CTRLA_CMD_RWWEEWP; + } + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(command | NVMCTRL_CTRLA_CMDEX_KEY); + + + return true; +} + +bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_FLASH_PAGESIZE/4U); i++) + { + *paddress = *(data + i); + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_WP_Val | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_RowErase( uint32_t address ) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_ER_Val | NVMCTRL_CTRLA_CMDEX_KEY); + + return true; +} + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ) +{ + uint32_t i; + uint32_t * paddress = (uint32_t *)address; + bool pagewrite_val = false; + + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= ((NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE) - NVMCTRL_USERROW_PAGESIZE))) + { + /* writing 32-bit data into the given address */ + for (i = 0U; i < (NVMCTRL_USERROW_PAGESIZE/4U); i++) + { + *paddress = data[i]; + paddress++; + } + + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_WAP_Val | NVMCTRL_CTRLA_CMDEX_KEY; + + + pagewrite_val = true; + } + + return pagewrite_val; +} + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ) +{ + bool rowerase = false; + if ((address >= NVMCTRL_USERROW_START_ADDRESS) && (address <= (NVMCTRL_USERROW_START_ADDRESS + NVMCTRL_USERROW_SIZE))) + { + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = NVMCTRL_CTRLA_CMD_EAR_Val | NVMCTRL_CTRLA_CMDEX_KEY; + + + rowerase = true; + } + + return rowerase; +} + +NVMCTRL_ERROR NVMCTRL_ErrorGet( void ) +{ + uint16_t nvm_error; + + /* Get the error bits set */ + nvm_error = (NVMCTRL_REGS->NVMCTRL_STATUS & (NVMCTRL_STATUS_NVME_Msk | NVMCTRL_STATUS_LOCKE_Msk | NVMCTRL_STATUS_PROGE_Msk)); + + /* Clear the error bits in both STATUS and INTFLAG register */ + NVMCTRL_REGS->NVMCTRL_STATUS |= nvm_error; + + NVMCTRL_REGS->NVMCTRL_INTFLAG = NVMCTRL_INTFLAG_ERROR_Msk; + + return ((NVMCTRL_ERROR) nvm_error); +} + +bool NVMCTRL_IsBusy(void) +{ + return ((NVMCTRL_REGS->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_READY_Msk)!= NVMCTRL_INTFLAG_READY_Msk); +} + +void NVMCTRL_RegionLock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_LR_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} + +void NVMCTRL_RegionUnlock(uint32_t address) +{ + /* Set address and command */ + NVMCTRL_REGS->NVMCTRL_ADDR = address >> 1U; + + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_UR_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} + +void NVMCTRL_SecurityBitSet(void) +{ + NVMCTRL_REGS->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMD_SSB_Val | NVMCTRL_CTRLA_CMDEX_KEY); +} diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h new file mode 100644 index 00000000..365c2866 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/nvmctrl/plib_nvmctrl.h @@ -0,0 +1,137 @@ +/******************************************************************************* + Non-Volatile Memory Controller(NVMCTRL) PLIB. + + Company: + Microchip Technology Inc. + + File Name: + plib_nvmctrl.h + + Summary: + Interface definition of NVMCTRL Plib. + + Description: + This file defines the interface for the NVMCTRL Plib. + It allows user to Program, Erase and lock the on-chip Non Volatile Flash + Memory. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_NVMCTRL_H +#define PLIB_NVMCTRL_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif + +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section: Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** + +#define NVMCTRL_FLASH_START_ADDRESS (0x00000000U) +#define NVMCTRL_FLASH_PAGESIZE (64U) +#define NVMCTRL_FLASH_ROWSIZE (256U) + +#define NVMCTRL_EMULATED_EEPROM_START_ADDRESS (0x40000U) +#define NVMCTRL_EMULATED_EEPROM_PAGESIZE (64U) +#define NVMCTRL_EMULATED_EEPROM_SIZE (0U) + +#define NVMCTRL_RWWEEPROM_START_ADDRESS (0x00400000U) +#define NVMCTRL_RWWEEPROM_SIZE (0x2000U) +#define NVMCTRL_RWWEEPROM_PAGESIZE (64U) +#define NVMCTRL_RWWEEPROM_ROWSIZE (256U) + +#define NVMCTRL_USERROW_START_ADDRESS (0x00804000U) +#define NVMCTRL_USERROW_SIZE (0x100U) +#define NVMCTRL_USERROW_PAGESIZE (64U) + +#define NVMCTRL_ERROR_NONE 0x0U +#define NVMCTRL_ERROR_PROG 0x4U +#define NVMCTRL_ERROR_LOCK 0x8U +#define NVMCTRL_ERROR_NVM 0x10U + +typedef uint16_t NVMCTRL_ERROR; + + +void NVMCTRL_Initialize(void); + +bool NVMCTRL_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +bool NVMCTRL_PageWrite( uint32_t *data, const uint32_t address ); + + +bool NVMCTRL_PageBufferWrite( uint32_t *data, const uint32_t address); + +bool NVMCTRL_PageBufferCommit( const uint32_t address); + + +bool NVMCTRL_RowErase( uint32_t address ); + +bool NVMCTRL_RWWEEPROM_Read( uint32_t *data, uint32_t length, const uint32_t address ); + +bool NVMCTRL_RWWEEPROM_PageWrite ( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_RWWEEPROM_RowErase ( uint32_t address ); + +NVMCTRL_ERROR NVMCTRL_ErrorGet( void ); + +bool NVMCTRL_IsBusy( void ); + +void NVMCTRL_RegionLock (uint32_t address); + +void NVMCTRL_RegionUnlock (uint32_t address); + +void NVMCTRL_SecurityBitSet(void); + + +bool NVMCTRL_USER_ROW_PageWrite( uint32_t *data, const uint32_t address ); + +bool NVMCTRL_USER_ROW_RowErase( uint32_t address ); + +void NVMCTRL_CacheInvalidate ( void ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END +#endif // PLIB_NVMCTRL_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/port/plib_port.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/port/plib_port.c new file mode 100644 index 00000000..d220aa67 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/port/plib_port.c @@ -0,0 +1,334 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.c + + Summary: + Interface definition of PORT PLIB + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_port.h" + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT Implementation +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + + void PORT_Initialize(void) + + Summary: + Initializes the PORT Library. + + Description: + This function initializes all ports and pins as configured in the + MHC Pin Manager. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_Initialize(void) +{ + /************************** GROUP 0 Initialization *************************/ + PORT_REGS->GROUP[0].PORT_DIR = 0x4U; + PORT_REGS->GROUP[0].PORT_PINCFG[2] = 0x2U; + + PORT_REGS->GROUP[0].PORT_PMUX[1] = 0x0U; + + +} +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_IN); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value) +{ + /* Write the desired value */ + ((port_group_registers_t*)group)->PORT_OUT = (((port_group_registers_t*)group)->PORT_OUT & (~mask)) | (mask & value); +} + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Remarks: + Refer plib_port.h file for more information. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group) +{ + return (((port_group_registers_t*)group)->PORT_OUT); +} + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTCLR = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_OUTTGL = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRCLR = mask; + + for(uint32_t i = 0U; i < 32U; i++) + { + if((mask & ((uint32_t)1U << i)) != 0U) + { + ((port_group_registers_t*)group)->PORT_PINCFG[i] |= PORT_PINCFG_INEN_Msk; + } + } +} + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Remarks: + Refer plib_port.h file for more information. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) +{ + ((port_group_registers_t*)group)->PORT_DIRSET = mask; +} + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) +{ + uint32_t periph_func = (uint32_t) function; + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + uint32_t pinmux_val = (uint32_t)((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)]; + + /* For odd pins */ + if (0U != (pin_num & 0x01U)) + { + pinmux_val = (pinmux_val & ~0xF0U) | (periph_func << 4); + } + else + { + pinmux_val = (pinmux_val & ~0x0FU) | periph_func; + } + ((port_group_registers_t*)group)->PORT_PMUX[(pin_num >> 1)] = (uint8_t)pinmux_val; + + /* Enable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] |= (uint8_t)PORT_PINCFG_PMUXEN_Msk; +} + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + Refer plib_port.h file for more information. +*/ +void PORT_PinGPIOConfig(PORT_PIN pin) +{ + PORT_GROUP group = GET_PORT_GROUP(pin); + uint32_t pin_num = ((uint32_t)pin) & 0x1FU; + + /* Disable peripheral control of the pin */ + ((port_group_registers_t*)group)->PORT_PINCFG[pin_num] &= ((uint8_t)(~PORT_PINCFG_PMUXEN_Msk)); +} \ No newline at end of file diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/port/plib_port.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/port/plib_port.h new file mode 100644 index 00000000..b7c7c8de --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/port/plib_port.h @@ -0,0 +1,961 @@ +/******************************************************************************* + PORT PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_port.h + + Summary: + PORT PLIB Header File + + Description: + This file provides an interface to control and interact with PORT-I/O + Pin controller module. + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_PORT_H +#define PLIB_PORT_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + extern "C" { +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data types and constants +// ***************************************************************************** +// ***************************************************************************** + +/*** Macros for GPIO_PA02 pin ***/ +#define GPIO_PA02_Set() (PORT_REGS->GROUP[0].PORT_OUTSET = ((uint32_t)1U << 2U)) +#define GPIO_PA02_Clear() (PORT_REGS->GROUP[0].PORT_OUTCLR = ((uint32_t)1U << 2U)) +#define GPIO_PA02_Toggle() (PORT_REGS->GROUP[0].PORT_OUTTGL = ((uint32_t)1U << 2U)) +#define GPIO_PA02_OutputEnable() (PORT_REGS->GROUP[0].PORT_DIRSET = ((uint32_t)1U << 2U)) +#define GPIO_PA02_InputEnable() (PORT_REGS->GROUP[0].PORT_DIRCLR = ((uint32_t)1U << 2U)) +#define GPIO_PA02_Get() (((PORT_REGS->GROUP[0].PORT_IN >> 2U)) & 0x01U) +#define GPIO_PA02_PIN PORT_PIN_PA02 + +// ***************************************************************************** +/* PORT Group + + Summary: + Identifies the port groups available on the device. + + Description: + These macros identifies all the ports groups that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the preprocessor macros as these may vary between devices. + + Port groups shown here are the ones available on the selected device. Not + all ports groups are implemented. Refer to the device specific datasheet + for more details. The MHC will generate these macros with the port + groups that are available on the device. +*/ + +/* Group 0 */ +#define PORT_GROUP_0 (PORT_BASE_ADDRESS + (0U * 0x80U)) + + +/* Helper macros to get port information from the pin */ +#define GET_PORT_GROUP(pin) ((PORT_GROUP)(PORT_BASE_ADDRESS + (0x80U * (((uint32_t)pin) >> 5U)))) +#define GET_PIN_MASK(pin) (((uint32_t)(0x1U)) << (((uint32_t)pin) & 0x1FU)) + +/* Named type for port group */ +typedef uint32_t PORT_GROUP; + + +typedef enum +{ +PERIPHERAL_FUNCTION_A = 0x0, +PERIPHERAL_FUNCTION_B = 0x1, +PERIPHERAL_FUNCTION_C = 0x2, +PERIPHERAL_FUNCTION_D = 0x3, +PERIPHERAL_FUNCTION_E = 0x4, +PERIPHERAL_FUNCTION_F = 0x5, +PERIPHERAL_FUNCTION_G = 0x6, +PERIPHERAL_FUNCTION_H = 0x7, +PERIPHERAL_FUNCTION_I = 0x8, + +}PERIPHERAL_FUNCTION; + +// ***************************************************************************** +/* PORT Pins + + Summary: + Identifies the available Ports pins. + + Description: + This enumeration identifies all the ports pins that are available on this + device. + + Remarks: + The caller should not use the constant expressions assigned to any of + the enumeration constants as these may vary between devices. + + Port pins shown here are the ones available on the selected device. Not + all ports pins within a port group are implemented. Refer to the device + specific datasheet for more details. +*/ + +typedef enum +{ + /* PA00 pin */ + PORT_PIN_PA00 = 0U, + + /* PA01 pin */ + PORT_PIN_PA01 = 1U, + + /* PA02 pin */ + PORT_PIN_PA02 = 2U, + + /* PA03 pin */ + PORT_PIN_PA03 = 3U, + + /* PA04 pin */ + PORT_PIN_PA04 = 4U, + + /* PA05 pin */ + PORT_PIN_PA05 = 5U, + + /* PA06 pin */ + PORT_PIN_PA06 = 6U, + + /* PA07 pin */ + PORT_PIN_PA07 = 7U, + + /* PA08 pin */ + PORT_PIN_PA08 = 8U, + + /* PA09 pin */ + PORT_PIN_PA09 = 9U, + + /* PA10 pin */ + PORT_PIN_PA10 = 10U, + + /* PA11 pin */ + PORT_PIN_PA11 = 11U, + + /* PA14 pin */ + PORT_PIN_PA14 = 14U, + + /* PA15 pin */ + PORT_PIN_PA15 = 15U, + + /* PA16 pin */ + PORT_PIN_PA16 = 16U, + + /* PA17 pin */ + PORT_PIN_PA17 = 17U, + + /* PA18 pin */ + PORT_PIN_PA18 = 18U, + + /* PA19 pin */ + PORT_PIN_PA19 = 19U, + + /* PA22 pin */ + PORT_PIN_PA22 = 22U, + + /* PA23 pin */ + PORT_PIN_PA23 = 23U, + + /* PA24 pin */ + PORT_PIN_PA24 = 24U, + + /* PA25 pin */ + PORT_PIN_PA25 = 25U, + + /* PA27 pin */ + PORT_PIN_PA27 = 27U, + + /* PA28 pin */ + PORT_PIN_PA28 = 28U, + + /* PA30 pin */ + PORT_PIN_PA30 = 30U, + + /* PA31 pin */ + PORT_PIN_PA31 = 31U, + + /* This element should not be used in any of the PORT APIs. + * It will be used by other modules or application to denote that none of + * the PORT Pin is used */ + PORT_PIN_NONE = 65535U, + +} PORT_PIN; + +// ***************************************************************************** +// ***************************************************************************** +// Section: Generated API based on pin configurations done in Pin Manager +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** +/* Function: + void PORT_Initialize(void) + + Summary: + Initializes the PORT Library. + + Description: + This function initializes all ports and pins as configured in the + MHC Pin Manager. + + Precondition: + None. + + Parameters: + None. + + Returns: + None. + + Example: + + + PORT_Initialize(); + + + + Remarks: + The function should be called once before calling any other PORTS PLIB + functions. +*/ + +void PORT_Initialize(void); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on multiple pins of a group +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupRead(PORT_GROUP group) + + Summary: + Read all the I/O pins in the specified port group. + + Description: + The function reads the hardware pin state of all pins in the specified group + and returns this as a 32 bit value. Each bit in the 32 bit value represent a + pin. For example, bit 0 in group 0 will represent pin PA0. Bit 1 will + represent PA1 and so on. The application should only consider the value of + the port group pins which are implemented on the device. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the hardware state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_Read(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + uint32_t PORT_GroupLatchRead(PORT_GROUP group) + + Summary: + Read the data driven on all the I/O pins of the selected port group. + + Description: + The function will return a 32-bit value representing the logic levels being + driven on the output pins within the group. The function will not sample the + actual hardware state of the output pin. Each bit in the 32-bit return value + will represent one of the 32 port pins within the group. The application + should only consider the value of the pins which are available on the + device. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + Returns: + A 32-bit value representing the output state of of all the I/O pins in the + selected port group. + + Example: + + + uint32_t value; + value = PORT_GroupLatchRead(PORT_GROUP_C); + + + + Remarks: + None. +*/ + +uint32_t PORT_GroupLatchRead(PORT_GROUP group); + +// ***************************************************************************** +/* Function: + void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + + Summary: + Write value on the masked pins of the selected port group. + + Description: + This function writes the value contained in the value parameter to the + port group. Port group pins which are configured for output will be updated. + The mask parameter provides additional control on the bits in the group to + be affected. Setting a bit to 1 in the mask will cause the corresponding + bit in the port group to be updated. Clearing a bit in the mask will cause + that corresponding bit in the group to stay unaffected. For example, + setting a mask value 0xFFFFFFFF will cause all bits in the port group + to be updated. Setting a value 0x3 will only cause port group bit 0 and + bit 1 to be updated. + + For port pins which are not configured for output and have the pull feature + enabled, this function will affect pull value (pull up or pull down). A bit + value of 1 will enable the pull up. A bit value of 0 will enable the pull + down. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO groups from the enum PORT_GROUP. + + mask - A 32 bit value in which positions of 0s and 1s decide + which IO pins of the selected port group will be written. + 1's - Will write to corresponding IO pins. + 0's - Will remain unchanged. + + value - Value which has to be written/driven on the I/O + lines of the selected port for which mask bits are '1'. + Values for the corresponding mask bit '0' will be ignored. + Refer to the function description for effect on pins + which are not configured for output. + + Returns: + None. + + Example: + + + PORT_GroupWrite(PORT_GROUP_C, 0x0F, 0xF563D453); + + + + Remarks: + None. +*/ + +void PORT_GroupWrite(PORT_GROUP group, uint32_t mask, uint32_t value); + +// ***************************************************************************** +/* Function: + void PORT_GroupSet(PORT_GROUP group, uint32_t mask) + + Summary: + Set the selected IO pins of a group. + + Description: + This function sets (drives a logic high) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be set. A + mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 1. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupSet(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 1 on this pin will cause the pull + up to be enabled. +*/ + +void PORT_GroupSet(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupClear(PORT_GROUP group, uint32_t mask) + + Summary: + Clears the selected IO pins of a group. + + Description: + This function clears (drives a logic 0) on the selected output pins of a + group. The mask parameter control the pins to be updated. A mask bit + position with a value 1 will cause that corresponding port pin to be clear. + A mask bit position with a value 0 will cause the corresponding port pin to + stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will driven to logic 0. If + the value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupClear(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. +*/ + +void PORT_GroupClear(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupToggle(PORT_GROUP group, uint32_t mask) + + Summary: + Toggles the selected IO pins of a group. + + Description: + This function toggles the selected output pins of a group. The mask + parameter control the pins to be updated. A mask bit position with a value 1 + will cause that corresponding port pin to be toggled. A mask bit position + with a value 0 will cause the corresponding port pin to stay un-affected. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represent a pin in the group. If the + value of the bit is 1, the corresponding port pin will be toggled. If the + value of the bit is 0. the corresponding port pin will stay un-affected. + + Returns: + None. + + Example: + + + PORT_GroupToggle(PORT_GROUP_C, 0x00A0); + + + + Remarks: + If the port pin within the the group is not configured for output and has + the pull feature enabled, driving a logic 0 on this pin will cause the pull + down to be enabled. Driving a logic 1 on this pin will cause the pull up to + be enabled. +*/ + +void PORT_GroupToggle(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as input. + + Description: + This function configures the selected IO pins of a group as input. The pins + to be configured as input are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + input. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupInputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupInputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask) + + Summary: + Configures the selected IO pins of a group as output. + + Description: + This function configures the selected IO pins of a group as output. The pins + to be configured as output are selected by setting the corresponding bits in + the mask parameter to 1. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + group - One or more of the of the IO ports from the enum PORT_GROUP. + mask - A 32 bit value in which a bit represents a pin in the group. If the + value of the bit is 1, the corresponding port pin will be configured as + output. If the value of the bit is 0. the corresponding port pin will stay + un-affected. + + Returns: + None. + + Example: + + + PORT_GroupOutputEnable(PORT_GROUP_C, 0x00A0); + + + + Remarks: + None. +*/ + +void PORT_GroupOutputEnable(PORT_GROUP group, uint32_t mask); + +// ***************************************************************************** +/* Function: + void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function) + + Summary: + Configures the peripheral function on the selected port pin + + Description: + This function configures the selected peripheral function on the given port pin. + + Remarks: + None +*/ +void PORT_PinPeripheralFunctionConfig(PORT_PIN pin, PERIPHERAL_FUNCTION function); + +// ***************************************************************************** +/* Function: + void PORT_PinGPIOConfig(PORT_PIN pin) + + Summary: + Configures the selected pin as GPIO + + Description: + This function configures the given pin as GPIO. + + Remarks: + None +*/ +void PORT_PinGPIOConfig(PORT_PIN pin); + +// ***************************************************************************** +// ***************************************************************************** +// Section: PORT APIs which operates on one pin at a time +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* Function: + void PORT_PinWrite(PORT_PIN pin, bool value) + + Summary: + Writes the specified value to the selected pin. + + Description: + This function writes/drives the "value" on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called once. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + value - value to be written on the selected pin. + true = set pin to high (1). + false = clear pin to low (0). + + Returns: + None. + + Example: + + + bool value = true; + PORT_PinWrite(PORT_PIN_PB3, value); + + + + Remarks: + Calling this function with an input pin with the pull-up/pull-down feature + enabled will affect the pull-up/pull-down configuration. If the value is + false, the pull-down will be enabled. If the value is true, the pull-up will + be enabled. +*/ + +static inline void PORT_PinWrite(PORT_PIN pin, bool value) +{ + PORT_GroupWrite(GET_PORT_GROUP(pin), + GET_PIN_MASK(pin), + (value ? GET_PIN_MASK(pin) : 0U)); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinRead(PORT_PIN pin) + + Summary: + Read the selected pin value. + + Description: + This function reads the present state at the selected input pin. The + function can also be called to read the value of an output pin if input + sampling on the output pin is enabled in MHC. If input synchronization on + the pin is disabled in MHC, the function will cause a 2 PORT Clock cycles + delay. Enabling the synchronization eliminates the delay but will increase + power consumption. + + Precondition: + The PORT_Initialize() function should have been called. Input buffer + (INEN bit in the Pin Configuration register) should be enabled in MHC. + + Parameters: + pin - the port pin whose state needs to be read. + + Returns: + true - the state at the pin is a logic high. + false - the state at the pin is a logic low. + + Example: + + + bool value; + value = PORT_PinRead(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline bool PORT_PinRead(PORT_PIN pin) +{ + return ((PORT_GroupRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + bool PORT_PinLatchRead(PORT_PIN pin) + + Summary: + Read the value driven on the selected pin. + + Description: + This function reads the data driven on the selected I/O line/pin. The + function does not sample the state of the hardware pin. It only returns the + value that is written to output register. Refer to the PORT_PinRead() + function if the state of the output pin needs to be read. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + true - the present value in the output latch is a logic high. + false - the present value in the output latch is a logic low. + + Example: + + + bool value; + value = PORT_PinLatchRead(PORT_PIN_PB3); + + + + Remarks: + To read actual pin value, PIN_Read API should be used. +*/ + +static inline bool PORT_PinLatchRead(PORT_PIN pin) +{ + return ((PORT_GroupLatchRead(GET_PORT_GROUP(pin)) & GET_PIN_MASK(pin)) != 0U); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinToggle(PORT_PIN pin) + + Summary: + Toggles the selected pin. + + Description: + This function toggles/inverts the present value on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinToggle(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinToggle(PORT_PIN pin) +{ + PORT_GroupToggle(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinSet(PORT_PIN pin) + + Summary: + Sets the selected pin. + + Description: + This function drives a logic 1 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinSet(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinSet(PORT_PIN pin) +{ + PORT_GroupSet(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinClear(PORT_PIN pin) + + Summary: + Clears the selected pin. + + Description: + This function drives a logic 0 on the selected I/O line/pin. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinClear(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinClear(PORT_PIN pin) +{ + PORT_GroupClear(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinInputEnable(PORT_PIN pin) + + Summary: + Configures the selected IO pin as input. + + Description: + This function configures the selected IO pin as input. This function + override the MHC input output pin settings. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinInputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinInputEnable(PORT_PIN pin) +{ + PORT_GroupInputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + + +// ***************************************************************************** +/* Function: + void PORT_PinOutputEnable(PORT_PIN pin) + + Summary: + Enables selected IO pin as output. + + Description: + This function enables selected IO pin as output. Calling this function will + override the MHC input output pin configuration. + + Precondition: + The PORT_Initialize() function should have been called. + + Parameters: + pin - One of the IO pins from the enum PORT_PIN. + + Returns: + None. + + Example: + + + PORT_PinOutputEnable(PORT_PIN_PB3); + + + + Remarks: + None. +*/ + +static inline void PORT_PinOutputEnable(PORT_PIN pin) +{ + PORT_GroupOutputEnable(GET_PORT_GROUP(pin), GET_PIN_MASK(pin)); +} + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + +} + +#endif +// DOM-IGNORE-END +#endif // PLIB_PORT_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/rtc/plib_rtc.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/rtc/plib_rtc.h new file mode 100644 index 00000000..a68c0c25 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/rtc/plib_rtc.h @@ -0,0 +1,116 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc.h + + Summary: + RTC PLIB Header file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_RTC_H +#define PLIB_RTC_H + +#include "device.h" +#include +#include +#include + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif +// DOM-IGNORE-END +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +/* Frequency of Counter Clock for RTC */ +#define RTC_COUNTER_CLOCK_FREQUENCY (1024U / (1UL << (0x1U - 1U))) + +#define RTC_TIMER32_INT_MASK_PER0 RTC_MODE0_INTENSET_PER0_Msk +#define RTC_TIMER32_INT_MASK_PER1 RTC_MODE0_INTENSET_PER1_Msk +#define RTC_TIMER32_INT_MASK_PER2 RTC_MODE0_INTENSET_PER2_Msk +#define RTC_TIMER32_INT_MASK_PER3 RTC_MODE0_INTENSET_PER3_Msk +#define RTC_TIMER32_INT_MASK_PER4 RTC_MODE0_INTENSET_PER4_Msk +#define RTC_TIMER32_INT_MASK_PER5 RTC_MODE0_INTENSET_PER5_Msk +#define RTC_TIMER32_INT_MASK_PER6 RTC_MODE0_INTENSET_PER6_Msk +#define RTC_TIMER32_INT_MASK_PER7 RTC_MODE0_INTENSET_PER7_Msk +#define RTC_TIMER32_INT_MASK_CMP0 RTC_MODE0_INTENSET_CMP0_Msk +#define RTC_TIMER32_INT_MASK_OVF RTC_MODE0_INTENSET_OVF_Msk +#define RTC_TIMER32_INT_MASK_INVALID 0xFFFFFFFFU +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +typedef uint32_t RTC_TIMER32_INT_MASK; +typedef void (*RTC_TIMER32_CALLBACK)( RTC_TIMER32_INT_MASK intCause, uintptr_t context ); + +typedef struct +{ + /* Timer 32Bit */ + RTC_TIMER32_CALLBACK timer32BitCallback; + RTC_TIMER32_INT_MASK timer32intCause; + uintptr_t context; +} RTC_OBJECT; + +void RTC_Initialize(void); +void RTC_Timer32CountSyncEnable ( void ); +void RTC_Timer32CountSyncDisable ( void ); +void RTC_Timer32Start ( void ); +void RTC_Timer32Stop ( void ); +void RTC_Timer32CounterSet ( uint32_t count ); +uint32_t RTC_Timer32CounterGet ( void ); +uint32_t RTC_Timer32FrequencyGet ( void ); +void RTC_Timer32CompareSet ( uint32_t compareValue ); +uint32_t RTC_Timer32PeriodGet ( void ); +void RTC_Timer32InterruptEnable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32InterruptDisable( RTC_TIMER32_INT_MASK interruptMask ); +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ); + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility +} +#endif +// DOM-IGNORE-END + +#endif /* PLIB_RTC_H */ diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/rtc/plib_rtc_timer.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/rtc/plib_rtc_timer.c new file mode 100644 index 00000000..17613298 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/rtc/plib_rtc_timer.c @@ -0,0 +1,196 @@ +/******************************************************************************* + Real Time Counter (RTC) PLIB + + Company: + Microchip Technology Inc. + + File Name: + plib_rtc_timer.c + + Summary: + RTC PLIB Implementation file + + Description: + This file defines the interface to the RTC peripheral library. This + library provides access to and control of the associated peripheral + instance in timer mode. + +*******************************************************************************/ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include "interrupts.h" +#include "plib_rtc.h" +#include + +static volatile RTC_OBJECT rtcObj; + + +void RTC_Initialize(void) +{ + RTC_REGS->MODE0.RTC_CTRLA = RTC_MODE0_CTRLA_SWRST_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_SWRST_Msk) == RTC_MODE0_SYNCBUSY_SWRST_Msk) + { + /* Wait for Synchronization after Software Reset */ + } + + + RTC_REGS->MODE0.RTC_CTRLA = (uint16_t)(RTC_MODE0_CTRLA_MODE(0UL) | RTC_MODE0_CTRLA_PRESCALER(0x1UL) | RTC_MODE0_CTRLA_COUNTSYNC_Msk ); + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + RTC_REGS->MODE0.RTC_COMP = 0x0U; + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } + +} + + +void RTC_Timer32CountSyncEnable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32CountSyncDisable ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_COUNTSYNC_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } +} + +void RTC_Timer32Start ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_ENABLE_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for synchronization after Enabling RTC */ + } +} + + +void RTC_Timer32Stop ( void ) +{ + RTC_REGS->MODE0.RTC_CTRLA &= (uint16_t)(~RTC_MODE0_CTRLA_ENABLE_Msk); + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_ENABLE_Msk) == RTC_MODE0_SYNCBUSY_ENABLE_Msk) + { + /* Wait for Synchronization after Disabling RTC */ + } +} + +void RTC_Timer32CounterSet ( uint32_t count ) +{ + RTC_REGS->MODE0.RTC_COUNT = count; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization after writing value to Count Register */ + } +} + +void RTC_Timer32CompareSet ( uint32_t compareValue ) +{ + RTC_REGS->MODE0.RTC_COMP = compareValue; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COMP0_Msk) == RTC_MODE0_SYNCBUSY_COMP0_Msk) + { + /* Wait for Synchronization after writing Compare Value */ + } +} +uint32_t RTC_Timer32CounterGet ( void ) +{ + if ((RTC_REGS->MODE0.RTC_CTRLA & RTC_MODE0_CTRLA_COUNTSYNC_Msk) == 0U) + { + RTC_REGS->MODE0.RTC_CTRLA |= RTC_MODE0_CTRLA_COUNTSYNC_Msk; + + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) == RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk) + { + /* Wait for Synchronization */ + } + } + while((RTC_REGS->MODE0.RTC_SYNCBUSY & RTC_MODE0_SYNCBUSY_COUNT_Msk) == RTC_MODE0_SYNCBUSY_COUNT_Msk) + { + /* Wait for Synchronization before reading value from Count Register */ + } + return(RTC_REGS->MODE0.RTC_COUNT); +} + +uint32_t RTC_Timer32PeriodGet ( void ) +{ + /* Get 32Bit Compare Value */ + /*lint -e{9048} PC lint incorrectly reports a missing 'U' Suffix */ + return (RTC_MODE0_COUNT_COUNT_Msk); +} + +uint32_t RTC_Timer32FrequencyGet ( void ) +{ + /* Return Frequency of RTC Clock */ + return RTC_COUNTER_CLOCK_FREQUENCY; +} + +void RTC_Timer32InterruptEnable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENSET = (uint16_t)interruptMask; +} + +void RTC_Timer32InterruptDisable(RTC_TIMER32_INT_MASK interruptMask) +{ + RTC_REGS->MODE0.RTC_INTENCLR = (uint16_t)interruptMask; +} + + +void RTC_Timer32CallbackRegister ( RTC_TIMER32_CALLBACK callback, uintptr_t context ) +{ + rtcObj.timer32BitCallback = callback; + rtcObj.context = context; +} + +void __attribute__((used)) RTC_InterruptHandler( void ) +{ + rtcObj.timer32intCause = (RTC_TIMER32_INT_MASK) RTC_REGS->MODE0.RTC_INTFLAG; + RTC_REGS->MODE0.RTC_INTFLAG = (uint16_t)RTC_MODE0_INTFLAG_Msk; + (void)RTC_REGS->MODE0.RTC_INTFLAG; + + /* Invoke registered Callback function */ + if(rtcObj.timer32BitCallback != NULL) + { + RTC_TIMER32_INT_MASK timer32intCause = rtcObj.timer32intCause; + uintptr_t context = rtcObj.context; + rtcObj.timer32BitCallback( timer32intCause, context ); + } +} diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom0_usart.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom0_usart.c new file mode 100644 index 00000000..87c53c68 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom0_usart.c @@ -0,0 +1,615 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom0_usart.h" +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM0 USART baud value for 115200 Hz baud rate */ +#define SERCOM0_USART_INT_BAUD_VALUE (63019UL) + +static volatile SERCOM_USART_OBJECT sercom0USARTObj; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM0 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM0_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM0_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM0_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM0_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM0_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM0_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM0_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM0_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM0_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM0_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM0_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize instance object */ + sercom0USARTObj.rxBuffer = NULL; + sercom0USARTObj.rxSize = 0; + sercom0USARTObj.rxProcessedSize = 0; + sercom0USARTObj.rxBusyStatus = false; + sercom0USARTObj.rxCallback = NULL; + sercom0USARTObj.txBuffer = NULL; + sercom0USARTObj.txSize = 0; + sercom0USARTObj.txProcessedSize = 0; + sercom0USARTObj.txBusyStatus = false; + sercom0USARTObj.txCallback = NULL; + sercom0USARTObj.errorStatus = USART_ERROR_NONE; +} + + + + + +uint32_t SERCOM0_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM0_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + bool transferProgress = sercom0USARTObj.txBusyStatus; + transferProgress = sercom0USARTObj.rxBusyStatus || transferProgress; + if(transferProgress) + { + /* Transaction is in progress, so return without updating settings */ + return setupStatus; + } + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM0_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM0_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM0_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM0_REGS->USART_INT.SERCOM_CTRLA = (SERCOM0_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM0_REGS->USART_INT.SERCOM_CTRLB = (SERCOM0_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM0_REGS->USART_INT.SERCOM_CTRLA = (SERCOM0_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM0_REGS->USART_INT.SERCOM_CTRLB = (SERCOM0_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM0_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM0_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = sercom0USARTObj.errorStatus; + + sercom0USARTObj.errorStatus = USART_ERROR_NONE; + + return errorStatus; +} + +void SERCOM0_USART_Enable( void ) +{ + if((SERCOM0_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM0_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM0_USART_Disable( void ) +{ + if((SERCOM0_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM0_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM0_USART_TransmitterEnable( void ) +{ + SERCOM0_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM0_USART_TransmitterDisable( void ) +{ + SERCOM0_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM0_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint32_t processedSize = 0U; + + if(buffer != NULL) + { + if(sercom0USARTObj.txBusyStatus == false) + { + sercom0USARTObj.txBuffer = buffer; + sercom0USARTObj.txSize = size; + sercom0USARTObj.txBusyStatus = true; + + size_t txSize = sercom0USARTObj.txSize; + + /* Initiate the transfer by sending first byte */ + while (((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) && + (processedSize < txSize)) + { + if (((SERCOM0_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM0_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)(buffer))[processedSize]; + } + else + { + /* 9-bit mode */ + SERCOM0_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)(buffer))[processedSize]; + } + processedSize += 1U; + } + sercom0USARTObj.txProcessedSize = processedSize; + SERCOM0_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk; + + writeStatus = true; + } + } + + return writeStatus; +} + + +bool SERCOM0_USART_WriteIsBusy( void ) +{ + return sercom0USARTObj.txBusyStatus; +} + +size_t SERCOM0_USART_WriteCountGet( void ) +{ + return sercom0USARTObj.txProcessedSize; +} + +void SERCOM0_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom0USARTObj.txCallback = callback; + + sercom0USARTObj.txContext = context; +} + + +bool SERCOM0_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM0_USART_ReceiverEnable( void ) +{ + SERCOM0_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM0_USART_ReceiverDisable( void ) +{ + SERCOM0_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM0_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM0_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + + if(buffer != NULL) + { + if(sercom0USARTObj.rxBusyStatus == false) + { + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM0_USART_ErrorClear(); + + sercom0USARTObj.rxBuffer = buffer; + sercom0USARTObj.rxSize = size; + sercom0USARTObj.rxProcessedSize = 0U; + sercom0USARTObj.rxBusyStatus = true; + sercom0USARTObj.errorStatus = USART_ERROR_NONE; + + readStatus = true; + + /* Enable receive and error interrupt */ + SERCOM0_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)(SERCOM_USART_INT_INTENSET_ERROR_Msk | SERCOM_USART_INT_INTENSET_RXC_Msk); + } + } + + return readStatus; +} + +bool SERCOM0_USART_ReadIsBusy( void ) +{ + return sercom0USARTObj.rxBusyStatus; +} + +size_t SERCOM0_USART_ReadCountGet( void ) +{ + return sercom0USARTObj.rxProcessedSize; +} + +bool SERCOM0_USART_ReadAbort(void) +{ + if (sercom0USARTObj.rxBusyStatus == true) + { + /* Disable receive and error interrupt */ + SERCOM0_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + sercom0USARTObj.rxBusyStatus = false; + + /* If required application should read the num bytes processed prior to calling the read abort API */ + sercom0USARTObj.rxSize = 0U; + sercom0USARTObj.rxProcessedSize = 0U; + } + + return true; +} + +void SERCOM0_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom0USARTObj.rxCallback = callback; + + sercom0USARTObj.rxContext = context; +} + + +static void __attribute__((used)) SERCOM0_USART_ISR_ERR_Handler( void ) +{ + USART_ERROR errorStatus; + + errorStatus = (USART_ERROR) (SERCOM0_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + /* Save the error to be reported later */ + sercom0USARTObj.errorStatus = errorStatus; + + /* Clear the error flags and flush out the error bytes */ + SERCOM0_USART_ErrorClear(); + + /* Disable error and receive interrupt to abort on-going transfer */ + SERCOM0_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + /* Clear the RX busy flag */ + sercom0USARTObj.rxBusyStatus = false; + + if(sercom0USARTObj.rxCallback != NULL) + { + uintptr_t rxContext = sercom0USARTObj.rxContext; + + sercom0USARTObj.rxCallback(rxContext); + } + } +} + +static void __attribute__((used)) SERCOM0_USART_ISR_RX_Handler( void ) +{ + uint16_t temp; + + + if(sercom0USARTObj.rxBusyStatus == true) + { + size_t rxSize = sercom0USARTObj.rxSize; + + if(sercom0USARTObj.rxProcessedSize < rxSize) + { + uintptr_t rxContext = sercom0USARTObj.rxContext; + + temp = (uint16_t)SERCOM0_REGS->USART_INT.SERCOM_DATA; + size_t rxProcessedSize = sercom0USARTObj.rxProcessedSize; + + if (((SERCOM0_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + ((uint8_t*)sercom0USARTObj.rxBuffer)[rxProcessedSize] = (uint8_t) (temp); + } + else + { + /* 9-bit mode */ + ((uint16_t*)sercom0USARTObj.rxBuffer)[rxProcessedSize] = temp; + } + + /* Increment processed size */ + rxProcessedSize++; + sercom0USARTObj.rxProcessedSize = rxProcessedSize; + + if(rxProcessedSize == sercom0USARTObj.rxSize) + { + sercom0USARTObj.rxBusyStatus = false; + sercom0USARTObj.rxSize = 0U; + SERCOM0_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_RXC_Msk | SERCOM_USART_INT_INTENCLR_ERROR_Msk); + + if(sercom0USARTObj.rxCallback != NULL) + { + sercom0USARTObj.rxCallback(rxContext); + } + } + + } + } +} + +static void __attribute__((used)) SERCOM0_USART_ISR_TX_Handler( void ) +{ + bool dataRegisterEmpty; + bool dataAvailable; + if(sercom0USARTObj.txBusyStatus == true) + { + size_t txProcessedSize = sercom0USARTObj.txProcessedSize; + + dataAvailable = (txProcessedSize < sercom0USARTObj.txSize); + dataRegisterEmpty = ((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + + while(dataRegisterEmpty && dataAvailable) + { + if (((SERCOM0_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM0_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)sercom0USARTObj.txBuffer)[txProcessedSize]; + } + else + { + /* 9-bit mode */ + SERCOM0_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)sercom0USARTObj.txBuffer)[txProcessedSize]; + } + /* Increment processed size */ + txProcessedSize++; + + dataAvailable = (txProcessedSize < sercom0USARTObj.txSize); + dataRegisterEmpty = ((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + } + + sercom0USARTObj.txProcessedSize = txProcessedSize; + + if(txProcessedSize >= sercom0USARTObj.txSize) + { + sercom0USARTObj.txBusyStatus = false; + sercom0USARTObj.txSize = 0U; + SERCOM0_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)SERCOM_USART_INT_INTENCLR_DRE_Msk; + + if(sercom0USARTObj.txCallback != NULL) + { + uintptr_t txContext = sercom0USARTObj.txContext; + sercom0USARTObj.txCallback(txContext); + } + } + } +} + +void __attribute__((used)) SERCOM0_USART_InterruptHandler( void ) +{ + bool testCondition; + if(SERCOM0_REGS->USART_INT.SERCOM_INTENSET != 0U) + { + /* Checks for error flag */ + testCondition = ((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_ERROR_Msk) == SERCOM_USART_INT_INTFLAG_ERROR_Msk); + testCondition = ((SERCOM0_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_ERROR_Msk) == SERCOM_USART_INT_INTENSET_ERROR_Msk) && testCondition; + if(testCondition) + { + SERCOM0_USART_ISR_ERR_Handler(); + } + + testCondition = ((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + testCondition = ((SERCOM0_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_DRE_Msk) == SERCOM_USART_INT_INTENSET_DRE_Msk) && testCondition; + /* Checks for data register empty flag */ + if(testCondition) + { + SERCOM0_USART_ISR_TX_Handler(); + } + + testCondition = ((SERCOM0_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk); + testCondition = ((SERCOM0_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_RXC_Msk) == SERCOM_USART_INT_INTENSET_RXC_Msk) && testCondition; + /* Checks for receive complete empty flag */ + if(testCondition) + { + SERCOM0_USART_ISR_RX_Handler(); + } + } +} + + + + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom0_usart.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom0_usart.h new file mode 100644 index 00000000..14b44d40 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom0_usart.h @@ -0,0 +1,121 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom0_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM0_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM0_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM0_USART_Initialize( void ); + +bool SERCOM0_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM0_USART_Enable( void ); + +void SERCOM0_USART_Disable( void ); + +void SERCOM0_USART_TransmitterEnable( void ); + +void SERCOM0_USART_TransmitterDisable( void ); + +bool SERCOM0_USART_Write( void *buffer, const size_t size ); + +bool SERCOM0_USART_TransmitComplete( void ); + + +bool SERCOM0_USART_WriteIsBusy( void ); + +size_t SERCOM0_USART_WriteCountGet( void ); + +void SERCOM0_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + + +void SERCOM0_USART_ReceiverEnable( void ); + +void SERCOM0_USART_ReceiverDisable( void ); + +bool SERCOM0_USART_Read( void *buffer, const size_t size ); + +bool SERCOM0_USART_ReadIsBusy( void ); + +size_t SERCOM0_USART_ReadCountGet( void ); + +bool SERCOM0_USART_ReadAbort(void); + +void SERCOM0_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + +USART_ERROR SERCOM0_USART_ErrorGet( void ); + +uint32_t SERCOM0_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM0_USART_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom1_usart.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom1_usart.c new file mode 100644 index 00000000..86782649 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom1_usart.c @@ -0,0 +1,615 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom1_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom1_usart.h" +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM1 USART baud value for 115200 Hz baud rate */ +#define SERCOM1_USART_INT_BAUD_VALUE (63019UL) + +static volatile SERCOM_USART_OBJECT sercom1USARTObj; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM1 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM1_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM1_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM1_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM1_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM1_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM1_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM1_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM1_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM1_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM1_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM1_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize instance object */ + sercom1USARTObj.rxBuffer = NULL; + sercom1USARTObj.rxSize = 0; + sercom1USARTObj.rxProcessedSize = 0; + sercom1USARTObj.rxBusyStatus = false; + sercom1USARTObj.rxCallback = NULL; + sercom1USARTObj.txBuffer = NULL; + sercom1USARTObj.txSize = 0; + sercom1USARTObj.txProcessedSize = 0; + sercom1USARTObj.txBusyStatus = false; + sercom1USARTObj.txCallback = NULL; + sercom1USARTObj.errorStatus = USART_ERROR_NONE; +} + + + + + +uint32_t SERCOM1_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM1_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + bool transferProgress = sercom1USARTObj.txBusyStatus; + transferProgress = sercom1USARTObj.rxBusyStatus || transferProgress; + if(transferProgress) + { + /* Transaction is in progress, so return without updating settings */ + return setupStatus; + } + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM1_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM1_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM1_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM1_REGS->USART_INT.SERCOM_CTRLA = (SERCOM1_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM1_REGS->USART_INT.SERCOM_CTRLB = (SERCOM1_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM1_REGS->USART_INT.SERCOM_CTRLA = (SERCOM1_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM1_REGS->USART_INT.SERCOM_CTRLB = (SERCOM1_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM1_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM1_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = sercom1USARTObj.errorStatus; + + sercom1USARTObj.errorStatus = USART_ERROR_NONE; + + return errorStatus; +} + +void SERCOM1_USART_Enable( void ) +{ + if((SERCOM1_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM1_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM1_USART_Disable( void ) +{ + if((SERCOM1_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM1_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM1_USART_TransmitterEnable( void ) +{ + SERCOM1_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM1_USART_TransmitterDisable( void ) +{ + SERCOM1_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM1_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint32_t processedSize = 0U; + + if(buffer != NULL) + { + if(sercom1USARTObj.txBusyStatus == false) + { + sercom1USARTObj.txBuffer = buffer; + sercom1USARTObj.txSize = size; + sercom1USARTObj.txBusyStatus = true; + + size_t txSize = sercom1USARTObj.txSize; + + /* Initiate the transfer by sending first byte */ + while (((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) && + (processedSize < txSize)) + { + if (((SERCOM1_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM1_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)(buffer))[processedSize]; + } + else + { + /* 9-bit mode */ + SERCOM1_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)(buffer))[processedSize]; + } + processedSize += 1U; + } + sercom1USARTObj.txProcessedSize = processedSize; + SERCOM1_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk; + + writeStatus = true; + } + } + + return writeStatus; +} + + +bool SERCOM1_USART_WriteIsBusy( void ) +{ + return sercom1USARTObj.txBusyStatus; +} + +size_t SERCOM1_USART_WriteCountGet( void ) +{ + return sercom1USARTObj.txProcessedSize; +} + +void SERCOM1_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom1USARTObj.txCallback = callback; + + sercom1USARTObj.txContext = context; +} + + +bool SERCOM1_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM1_USART_ReceiverEnable( void ) +{ + SERCOM1_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM1_USART_ReceiverDisable( void ) +{ + SERCOM1_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM1_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM1_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + + if(buffer != NULL) + { + if(sercom1USARTObj.rxBusyStatus == false) + { + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM1_USART_ErrorClear(); + + sercom1USARTObj.rxBuffer = buffer; + sercom1USARTObj.rxSize = size; + sercom1USARTObj.rxProcessedSize = 0U; + sercom1USARTObj.rxBusyStatus = true; + sercom1USARTObj.errorStatus = USART_ERROR_NONE; + + readStatus = true; + + /* Enable receive and error interrupt */ + SERCOM1_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)(SERCOM_USART_INT_INTENSET_ERROR_Msk | SERCOM_USART_INT_INTENSET_RXC_Msk); + } + } + + return readStatus; +} + +bool SERCOM1_USART_ReadIsBusy( void ) +{ + return sercom1USARTObj.rxBusyStatus; +} + +size_t SERCOM1_USART_ReadCountGet( void ) +{ + return sercom1USARTObj.rxProcessedSize; +} + +bool SERCOM1_USART_ReadAbort(void) +{ + if (sercom1USARTObj.rxBusyStatus == true) + { + /* Disable receive and error interrupt */ + SERCOM1_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + sercom1USARTObj.rxBusyStatus = false; + + /* If required application should read the num bytes processed prior to calling the read abort API */ + sercom1USARTObj.rxSize = 0U; + sercom1USARTObj.rxProcessedSize = 0U; + } + + return true; +} + +void SERCOM1_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom1USARTObj.rxCallback = callback; + + sercom1USARTObj.rxContext = context; +} + + +static void __attribute__((used)) SERCOM1_USART_ISR_ERR_Handler( void ) +{ + USART_ERROR errorStatus; + + errorStatus = (USART_ERROR) (SERCOM1_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + /* Save the error to be reported later */ + sercom1USARTObj.errorStatus = errorStatus; + + /* Clear the error flags and flush out the error bytes */ + SERCOM1_USART_ErrorClear(); + + /* Disable error and receive interrupt to abort on-going transfer */ + SERCOM1_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + /* Clear the RX busy flag */ + sercom1USARTObj.rxBusyStatus = false; + + if(sercom1USARTObj.rxCallback != NULL) + { + uintptr_t rxContext = sercom1USARTObj.rxContext; + + sercom1USARTObj.rxCallback(rxContext); + } + } +} + +static void __attribute__((used)) SERCOM1_USART_ISR_RX_Handler( void ) +{ + uint16_t temp; + + + if(sercom1USARTObj.rxBusyStatus == true) + { + size_t rxSize = sercom1USARTObj.rxSize; + + if(sercom1USARTObj.rxProcessedSize < rxSize) + { + uintptr_t rxContext = sercom1USARTObj.rxContext; + + temp = (uint16_t)SERCOM1_REGS->USART_INT.SERCOM_DATA; + size_t rxProcessedSize = sercom1USARTObj.rxProcessedSize; + + if (((SERCOM1_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + ((uint8_t*)sercom1USARTObj.rxBuffer)[rxProcessedSize] = (uint8_t) (temp); + } + else + { + /* 9-bit mode */ + ((uint16_t*)sercom1USARTObj.rxBuffer)[rxProcessedSize] = temp; + } + + /* Increment processed size */ + rxProcessedSize++; + sercom1USARTObj.rxProcessedSize = rxProcessedSize; + + if(rxProcessedSize == sercom1USARTObj.rxSize) + { + sercom1USARTObj.rxBusyStatus = false; + sercom1USARTObj.rxSize = 0U; + SERCOM1_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_RXC_Msk | SERCOM_USART_INT_INTENCLR_ERROR_Msk); + + if(sercom1USARTObj.rxCallback != NULL) + { + sercom1USARTObj.rxCallback(rxContext); + } + } + + } + } +} + +static void __attribute__((used)) SERCOM1_USART_ISR_TX_Handler( void ) +{ + bool dataRegisterEmpty; + bool dataAvailable; + if(sercom1USARTObj.txBusyStatus == true) + { + size_t txProcessedSize = sercom1USARTObj.txProcessedSize; + + dataAvailable = (txProcessedSize < sercom1USARTObj.txSize); + dataRegisterEmpty = ((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + + while(dataRegisterEmpty && dataAvailable) + { + if (((SERCOM1_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM1_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)sercom1USARTObj.txBuffer)[txProcessedSize]; + } + else + { + /* 9-bit mode */ + SERCOM1_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)sercom1USARTObj.txBuffer)[txProcessedSize]; + } + /* Increment processed size */ + txProcessedSize++; + + dataAvailable = (txProcessedSize < sercom1USARTObj.txSize); + dataRegisterEmpty = ((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + } + + sercom1USARTObj.txProcessedSize = txProcessedSize; + + if(txProcessedSize >= sercom1USARTObj.txSize) + { + sercom1USARTObj.txBusyStatus = false; + sercom1USARTObj.txSize = 0U; + SERCOM1_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)SERCOM_USART_INT_INTENCLR_DRE_Msk; + + if(sercom1USARTObj.txCallback != NULL) + { + uintptr_t txContext = sercom1USARTObj.txContext; + sercom1USARTObj.txCallback(txContext); + } + } + } +} + +void __attribute__((used)) SERCOM1_USART_InterruptHandler( void ) +{ + bool testCondition; + if(SERCOM1_REGS->USART_INT.SERCOM_INTENSET != 0U) + { + /* Checks for error flag */ + testCondition = ((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_ERROR_Msk) == SERCOM_USART_INT_INTFLAG_ERROR_Msk); + testCondition = ((SERCOM1_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_ERROR_Msk) == SERCOM_USART_INT_INTENSET_ERROR_Msk) && testCondition; + if(testCondition) + { + SERCOM1_USART_ISR_ERR_Handler(); + } + + testCondition = ((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + testCondition = ((SERCOM1_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_DRE_Msk) == SERCOM_USART_INT_INTENSET_DRE_Msk) && testCondition; + /* Checks for data register empty flag */ + if(testCondition) + { + SERCOM1_USART_ISR_TX_Handler(); + } + + testCondition = ((SERCOM1_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk); + testCondition = ((SERCOM1_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_RXC_Msk) == SERCOM_USART_INT_INTENSET_RXC_Msk) && testCondition; + /* Checks for receive complete empty flag */ + if(testCondition) + { + SERCOM1_USART_ISR_RX_Handler(); + } + } +} + + + + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom1_usart.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom1_usart.h new file mode 100644 index 00000000..f36b59ac --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom1_usart.h @@ -0,0 +1,121 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom1_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM1_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM1_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM1_USART_Initialize( void ); + +bool SERCOM1_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM1_USART_Enable( void ); + +void SERCOM1_USART_Disable( void ); + +void SERCOM1_USART_TransmitterEnable( void ); + +void SERCOM1_USART_TransmitterDisable( void ); + +bool SERCOM1_USART_Write( void *buffer, const size_t size ); + +bool SERCOM1_USART_TransmitComplete( void ); + + +bool SERCOM1_USART_WriteIsBusy( void ); + +size_t SERCOM1_USART_WriteCountGet( void ); + +void SERCOM1_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + + +void SERCOM1_USART_ReceiverEnable( void ); + +void SERCOM1_USART_ReceiverDisable( void ); + +bool SERCOM1_USART_Read( void *buffer, const size_t size ); + +bool SERCOM1_USART_ReadIsBusy( void ); + +size_t SERCOM1_USART_ReadCountGet( void ); + +bool SERCOM1_USART_ReadAbort(void); + +void SERCOM1_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + +USART_ERROR SERCOM1_USART_ErrorGet( void ); + +uint32_t SERCOM1_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM1_USART_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom2_usart.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom2_usart.c new file mode 100644 index 00000000..8c45ab16 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom2_usart.c @@ -0,0 +1,615 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom2_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom2_usart.h" +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM2 USART baud value for 115200 Hz baud rate */ +#define SERCOM2_USART_INT_BAUD_VALUE (63019UL) + +static volatile SERCOM_USART_OBJECT sercom2USARTObj; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM2 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM2_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM2_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM2_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM2_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM2_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM2_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM2_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM2_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM2_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM2_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM2_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize instance object */ + sercom2USARTObj.rxBuffer = NULL; + sercom2USARTObj.rxSize = 0; + sercom2USARTObj.rxProcessedSize = 0; + sercom2USARTObj.rxBusyStatus = false; + sercom2USARTObj.rxCallback = NULL; + sercom2USARTObj.txBuffer = NULL; + sercom2USARTObj.txSize = 0; + sercom2USARTObj.txProcessedSize = 0; + sercom2USARTObj.txBusyStatus = false; + sercom2USARTObj.txCallback = NULL; + sercom2USARTObj.errorStatus = USART_ERROR_NONE; +} + + + + + +uint32_t SERCOM2_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM2_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + bool transferProgress = sercom2USARTObj.txBusyStatus; + transferProgress = sercom2USARTObj.rxBusyStatus || transferProgress; + if(transferProgress) + { + /* Transaction is in progress, so return without updating settings */ + return setupStatus; + } + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM2_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM2_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM2_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM2_REGS->USART_INT.SERCOM_CTRLA = (SERCOM2_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM2_REGS->USART_INT.SERCOM_CTRLB = (SERCOM2_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM2_REGS->USART_INT.SERCOM_CTRLA = (SERCOM2_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM2_REGS->USART_INT.SERCOM_CTRLB = (SERCOM2_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM2_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM2_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = sercom2USARTObj.errorStatus; + + sercom2USARTObj.errorStatus = USART_ERROR_NONE; + + return errorStatus; +} + +void SERCOM2_USART_Enable( void ) +{ + if((SERCOM2_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM2_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM2_USART_Disable( void ) +{ + if((SERCOM2_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM2_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM2_USART_TransmitterEnable( void ) +{ + SERCOM2_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM2_USART_TransmitterDisable( void ) +{ + SERCOM2_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM2_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint32_t processedSize = 0U; + + if(buffer != NULL) + { + if(sercom2USARTObj.txBusyStatus == false) + { + sercom2USARTObj.txBuffer = buffer; + sercom2USARTObj.txSize = size; + sercom2USARTObj.txBusyStatus = true; + + size_t txSize = sercom2USARTObj.txSize; + + /* Initiate the transfer by sending first byte */ + while (((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) && + (processedSize < txSize)) + { + if (((SERCOM2_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM2_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)(buffer))[processedSize]; + } + else + { + /* 9-bit mode */ + SERCOM2_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)(buffer))[processedSize]; + } + processedSize += 1U; + } + sercom2USARTObj.txProcessedSize = processedSize; + SERCOM2_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk; + + writeStatus = true; + } + } + + return writeStatus; +} + + +bool SERCOM2_USART_WriteIsBusy( void ) +{ + return sercom2USARTObj.txBusyStatus; +} + +size_t SERCOM2_USART_WriteCountGet( void ) +{ + return sercom2USARTObj.txProcessedSize; +} + +void SERCOM2_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom2USARTObj.txCallback = callback; + + sercom2USARTObj.txContext = context; +} + + +bool SERCOM2_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM2_USART_ReceiverEnable( void ) +{ + SERCOM2_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM2_USART_ReceiverDisable( void ) +{ + SERCOM2_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM2_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + + if(buffer != NULL) + { + if(sercom2USARTObj.rxBusyStatus == false) + { + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM2_USART_ErrorClear(); + + sercom2USARTObj.rxBuffer = buffer; + sercom2USARTObj.rxSize = size; + sercom2USARTObj.rxProcessedSize = 0U; + sercom2USARTObj.rxBusyStatus = true; + sercom2USARTObj.errorStatus = USART_ERROR_NONE; + + readStatus = true; + + /* Enable receive and error interrupt */ + SERCOM2_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)(SERCOM_USART_INT_INTENSET_ERROR_Msk | SERCOM_USART_INT_INTENSET_RXC_Msk); + } + } + + return readStatus; +} + +bool SERCOM2_USART_ReadIsBusy( void ) +{ + return sercom2USARTObj.rxBusyStatus; +} + +size_t SERCOM2_USART_ReadCountGet( void ) +{ + return sercom2USARTObj.rxProcessedSize; +} + +bool SERCOM2_USART_ReadAbort(void) +{ + if (sercom2USARTObj.rxBusyStatus == true) + { + /* Disable receive and error interrupt */ + SERCOM2_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + sercom2USARTObj.rxBusyStatus = false; + + /* If required application should read the num bytes processed prior to calling the read abort API */ + sercom2USARTObj.rxSize = 0U; + sercom2USARTObj.rxProcessedSize = 0U; + } + + return true; +} + +void SERCOM2_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom2USARTObj.rxCallback = callback; + + sercom2USARTObj.rxContext = context; +} + + +static void __attribute__((used)) SERCOM2_USART_ISR_ERR_Handler( void ) +{ + USART_ERROR errorStatus; + + errorStatus = (USART_ERROR) (SERCOM2_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + /* Save the error to be reported later */ + sercom2USARTObj.errorStatus = errorStatus; + + /* Clear the error flags and flush out the error bytes */ + SERCOM2_USART_ErrorClear(); + + /* Disable error and receive interrupt to abort on-going transfer */ + SERCOM2_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + /* Clear the RX busy flag */ + sercom2USARTObj.rxBusyStatus = false; + + if(sercom2USARTObj.rxCallback != NULL) + { + uintptr_t rxContext = sercom2USARTObj.rxContext; + + sercom2USARTObj.rxCallback(rxContext); + } + } +} + +static void __attribute__((used)) SERCOM2_USART_ISR_RX_Handler( void ) +{ + uint16_t temp; + + + if(sercom2USARTObj.rxBusyStatus == true) + { + size_t rxSize = sercom2USARTObj.rxSize; + + if(sercom2USARTObj.rxProcessedSize < rxSize) + { + uintptr_t rxContext = sercom2USARTObj.rxContext; + + temp = (uint16_t)SERCOM2_REGS->USART_INT.SERCOM_DATA; + size_t rxProcessedSize = sercom2USARTObj.rxProcessedSize; + + if (((SERCOM2_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + ((uint8_t*)sercom2USARTObj.rxBuffer)[rxProcessedSize] = (uint8_t) (temp); + } + else + { + /* 9-bit mode */ + ((uint16_t*)sercom2USARTObj.rxBuffer)[rxProcessedSize] = temp; + } + + /* Increment processed size */ + rxProcessedSize++; + sercom2USARTObj.rxProcessedSize = rxProcessedSize; + + if(rxProcessedSize == sercom2USARTObj.rxSize) + { + sercom2USARTObj.rxBusyStatus = false; + sercom2USARTObj.rxSize = 0U; + SERCOM2_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_RXC_Msk | SERCOM_USART_INT_INTENCLR_ERROR_Msk); + + if(sercom2USARTObj.rxCallback != NULL) + { + sercom2USARTObj.rxCallback(rxContext); + } + } + + } + } +} + +static void __attribute__((used)) SERCOM2_USART_ISR_TX_Handler( void ) +{ + bool dataRegisterEmpty; + bool dataAvailable; + if(sercom2USARTObj.txBusyStatus == true) + { + size_t txProcessedSize = sercom2USARTObj.txProcessedSize; + + dataAvailable = (txProcessedSize < sercom2USARTObj.txSize); + dataRegisterEmpty = ((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + + while(dataRegisterEmpty && dataAvailable) + { + if (((SERCOM2_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM2_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)sercom2USARTObj.txBuffer)[txProcessedSize]; + } + else + { + /* 9-bit mode */ + SERCOM2_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)sercom2USARTObj.txBuffer)[txProcessedSize]; + } + /* Increment processed size */ + txProcessedSize++; + + dataAvailable = (txProcessedSize < sercom2USARTObj.txSize); + dataRegisterEmpty = ((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + } + + sercom2USARTObj.txProcessedSize = txProcessedSize; + + if(txProcessedSize >= sercom2USARTObj.txSize) + { + sercom2USARTObj.txBusyStatus = false; + sercom2USARTObj.txSize = 0U; + SERCOM2_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)SERCOM_USART_INT_INTENCLR_DRE_Msk; + + if(sercom2USARTObj.txCallback != NULL) + { + uintptr_t txContext = sercom2USARTObj.txContext; + sercom2USARTObj.txCallback(txContext); + } + } + } +} + +void __attribute__((used)) SERCOM2_USART_InterruptHandler( void ) +{ + bool testCondition; + if(SERCOM2_REGS->USART_INT.SERCOM_INTENSET != 0U) + { + /* Checks for error flag */ + testCondition = ((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_ERROR_Msk) == SERCOM_USART_INT_INTFLAG_ERROR_Msk); + testCondition = ((SERCOM2_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_ERROR_Msk) == SERCOM_USART_INT_INTENSET_ERROR_Msk) && testCondition; + if(testCondition) + { + SERCOM2_USART_ISR_ERR_Handler(); + } + + testCondition = ((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + testCondition = ((SERCOM2_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_DRE_Msk) == SERCOM_USART_INT_INTENSET_DRE_Msk) && testCondition; + /* Checks for data register empty flag */ + if(testCondition) + { + SERCOM2_USART_ISR_TX_Handler(); + } + + testCondition = ((SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk); + testCondition = ((SERCOM2_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_RXC_Msk) == SERCOM_USART_INT_INTENSET_RXC_Msk) && testCondition; + /* Checks for receive complete empty flag */ + if(testCondition) + { + SERCOM2_USART_ISR_RX_Handler(); + } + } +} + + + + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom2_usart.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom2_usart.h new file mode 100644 index 00000000..4d4ee2ad --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom2_usart.h @@ -0,0 +1,121 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom2_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM2_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM2_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM2_USART_Initialize( void ); + +bool SERCOM2_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM2_USART_Enable( void ); + +void SERCOM2_USART_Disable( void ); + +void SERCOM2_USART_TransmitterEnable( void ); + +void SERCOM2_USART_TransmitterDisable( void ); + +bool SERCOM2_USART_Write( void *buffer, const size_t size ); + +bool SERCOM2_USART_TransmitComplete( void ); + + +bool SERCOM2_USART_WriteIsBusy( void ); + +size_t SERCOM2_USART_WriteCountGet( void ); + +void SERCOM2_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + + +void SERCOM2_USART_ReceiverEnable( void ); + +void SERCOM2_USART_ReceiverDisable( void ); + +bool SERCOM2_USART_Read( void *buffer, const size_t size ); + +bool SERCOM2_USART_ReadIsBusy( void ); + +size_t SERCOM2_USART_ReadCountGet( void ); + +bool SERCOM2_USART_ReadAbort(void); + +void SERCOM2_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + +USART_ERROR SERCOM2_USART_ErrorGet( void ); + +uint32_t SERCOM2_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM2_USART_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c new file mode 100644 index 00000000..ca5c9b13 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.c @@ -0,0 +1,615 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom3_usart.c + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** +#include "interrupts.h" +#include "plib_sercom3_usart.h" +// ***************************************************************************** +// ***************************************************************************** +// Section: Global Data +// ***************************************************************************** +// ***************************************************************************** +/* SERCOM3 USART baud value for 115200 Hz baud rate */ +#define SERCOM3_USART_INT_BAUD_VALUE (63019UL) + +static volatile SERCOM_USART_OBJECT sercom3USARTObj; + + +// ***************************************************************************** +// ***************************************************************************** +// Section: SERCOM3 USART Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +static void SERCOM3_USART_ErrorClear( void ) +{ + uint8_t u8dummyData = 0U; + USART_ERROR errorStatus = (USART_ERROR) (SERCOM3_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk )); + + if(errorStatus != USART_ERROR_NONE) + { + /* Clear error flag */ + SERCOM3_REGS->USART_INT.SERCOM_INTFLAG = (uint8_t)SERCOM_USART_INT_INTFLAG_ERROR_Msk; + /* Clear all errors */ + SERCOM3_REGS->USART_INT.SERCOM_STATUS = (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk); + + /* Flush existing error bytes from the RX FIFO */ + while((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) == (uint8_t)SERCOM_USART_INT_INTFLAG_RXC_Msk) + { + u8dummyData = (uint8_t)SERCOM3_REGS->USART_INT.SERCOM_DATA; + } + } + + /* Ignore the warning */ + (void)u8dummyData; +} + +void SERCOM3_USART_Initialize( void ) +{ + /* + * Configures USART Clock Mode + * Configures TXPO and RXPO + * Configures Data Order + * Configures Standby Mode + * Configures Sampling rate + * Configures IBON + */ + + SERCOM3_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x0UL) | SERCOM_USART_INT_CTRLA_TXPO(0x0UL) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR(0UL) ; + + /* Configure Baud Rate */ + SERCOM3_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(SERCOM3_USART_INT_BAUD_VALUE); + + /* + * Configures RXEN + * Configures TXEN + * Configures CHSIZE + * Configures Parity + * Configures Stop bits + */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + + /* Enable the UART after the configurations */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Initialize instance object */ + sercom3USARTObj.rxBuffer = NULL; + sercom3USARTObj.rxSize = 0; + sercom3USARTObj.rxProcessedSize = 0; + sercom3USARTObj.rxBusyStatus = false; + sercom3USARTObj.rxCallback = NULL; + sercom3USARTObj.txBuffer = NULL; + sercom3USARTObj.txSize = 0; + sercom3USARTObj.txProcessedSize = 0; + sercom3USARTObj.txBusyStatus = false; + sercom3USARTObj.txCallback = NULL; + sercom3USARTObj.errorStatus = USART_ERROR_NONE; +} + + + + + +uint32_t SERCOM3_USART_FrequencyGet( void ) +{ + return 48000000UL; +} + +bool SERCOM3_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ) +{ + bool setupStatus = false; + uint32_t baudValue = 0U; + uint32_t sampleRate = 0U; + uint32_t sampleCount = 0U; + + bool transferProgress = sercom3USARTObj.txBusyStatus; + transferProgress = sercom3USARTObj.rxBusyStatus || transferProgress; + if(transferProgress) + { + /* Transaction is in progress, so return without updating settings */ + return setupStatus; + } + + if((serialSetup != NULL) && (serialSetup->baudRate != 0U)) + { + if(clkFrequency == 0U) + { + clkFrequency = SERCOM3_USART_FrequencyGet(); + } + + if(clkFrequency >= (16U * serialSetup->baudRate)) + { + sampleRate = 0U; + sampleCount = 16U; + } + else if(clkFrequency >= (8U * serialSetup->baudRate)) + { + sampleRate = 2U; + sampleCount = 8U; + } + else if(clkFrequency >= (3U * serialSetup->baudRate)) + { + sampleRate = 4U; + sampleCount = 3U; + } + else + { + /* Do nothing */ + } + baudValue = 65536U - (uint32_t)(((uint64_t)65536U * sampleCount * serialSetup->baudRate) / clkFrequency); + /* Disable the USART before configurations */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Configure Baud Rate */ + SERCOM3_REGS->USART_INT.SERCOM_BAUD = (uint16_t)SERCOM_USART_INT_BAUD_BAUD(baudValue); + + /* Configure Parity Options */ + if(serialSetup->parity == USART_PARITY_NONE) + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA = (SERCOM3_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x0UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM3_REGS->USART_INT.SERCOM_CTRLB = (SERCOM3_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk)) | ((uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits); + } + else + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA = (SERCOM3_REGS->USART_INT.SERCOM_CTRLA & ~(SERCOM_USART_INT_CTRLA_SAMPR_Msk | SERCOM_USART_INT_CTRLA_FORM_Msk)) | SERCOM_USART_INT_CTRLA_FORM(0x1UL) | SERCOM_USART_INT_CTRLA_SAMPR((uint32_t)sampleRate); + SERCOM3_REGS->USART_INT.SERCOM_CTRLB = (SERCOM3_REGS->USART_INT.SERCOM_CTRLB & ~(SERCOM_USART_INT_CTRLB_CHSIZE_Msk | SERCOM_USART_INT_CTRLB_SBMODE_Msk | SERCOM_USART_INT_CTRLB_PMODE_Msk)) | (uint32_t) serialSetup->dataWidth | (uint32_t) serialSetup->stopBits | (uint32_t) serialSetup->parity ; + } + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + /* Enable the USART after the configurations */ + SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + + setupStatus = true; + } + + return setupStatus; +} + +USART_ERROR SERCOM3_USART_ErrorGet( void ) +{ + USART_ERROR errorStatus = sercom3USARTObj.errorStatus; + + sercom3USARTObj.errorStatus = USART_ERROR_NONE; + + return errorStatus; +} + +void SERCOM3_USART_Enable( void ) +{ + if((SERCOM3_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) == 0U) + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + +void SERCOM3_USART_Disable( void ) +{ + if((SERCOM3_REGS->USART_INT.SERCOM_CTRLA & SERCOM_USART_INT_CTRLA_ENABLE_Msk) != 0U) + { + SERCOM3_REGS->USART_INT.SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } + } +} + + +void SERCOM3_USART_TransmitterEnable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM3_USART_TransmitterDisable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_TXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM3_USART_Write( void *buffer, const size_t size ) +{ + bool writeStatus = false; + uint32_t processedSize = 0U; + + if(buffer != NULL) + { + if(sercom3USARTObj.txBusyStatus == false) + { + sercom3USARTObj.txBuffer = buffer; + sercom3USARTObj.txSize = size; + sercom3USARTObj.txBusyStatus = true; + + size_t txSize = sercom3USARTObj.txSize; + + /* Initiate the transfer by sending first byte */ + while (((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk) && + (processedSize < txSize)) + { + if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)(buffer))[processedSize]; + } + else + { + /* 9-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)(buffer))[processedSize]; + } + processedSize += 1U; + } + sercom3USARTObj.txProcessedSize = processedSize; + SERCOM3_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)SERCOM_USART_INT_INTFLAG_DRE_Msk; + + writeStatus = true; + } + } + + return writeStatus; +} + + +bool SERCOM3_USART_WriteIsBusy( void ) +{ + return sercom3USARTObj.txBusyStatus; +} + +size_t SERCOM3_USART_WriteCountGet( void ) +{ + return sercom3USARTObj.txProcessedSize; +} + +void SERCOM3_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom3USARTObj.txCallback = callback; + + sercom3USARTObj.txContext = context; +} + + +bool SERCOM3_USART_TransmitComplete( void ) +{ + bool transmitComplete = false; + + if ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == SERCOM_USART_INT_INTFLAG_TXC_Msk) + { + transmitComplete = true; + } + + return transmitComplete; +} + +void SERCOM3_USART_ReceiverEnable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB |= SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +void SERCOM3_USART_ReceiverDisable( void ) +{ + SERCOM3_REGS->USART_INT.SERCOM_CTRLB &= ~SERCOM_USART_INT_CTRLB_RXEN_Msk; + + /* Wait for sync */ + while((SERCOM3_REGS->USART_INT.SERCOM_SYNCBUSY) != 0U) + { + /* Do nothing */ + } +} + +bool SERCOM3_USART_Read( void *buffer, const size_t size ) +{ + bool readStatus = false; + + if(buffer != NULL) + { + if(sercom3USARTObj.rxBusyStatus == false) + { + /* Clear error flags and flush out error data that may have been received when no active request was pending */ + SERCOM3_USART_ErrorClear(); + + sercom3USARTObj.rxBuffer = buffer; + sercom3USARTObj.rxSize = size; + sercom3USARTObj.rxProcessedSize = 0U; + sercom3USARTObj.rxBusyStatus = true; + sercom3USARTObj.errorStatus = USART_ERROR_NONE; + + readStatus = true; + + /* Enable receive and error interrupt */ + SERCOM3_REGS->USART_INT.SERCOM_INTENSET = (uint8_t)(SERCOM_USART_INT_INTENSET_ERROR_Msk | SERCOM_USART_INT_INTENSET_RXC_Msk); + } + } + + return readStatus; +} + +bool SERCOM3_USART_ReadIsBusy( void ) +{ + return sercom3USARTObj.rxBusyStatus; +} + +size_t SERCOM3_USART_ReadCountGet( void ) +{ + return sercom3USARTObj.rxProcessedSize; +} + +bool SERCOM3_USART_ReadAbort(void) +{ + if (sercom3USARTObj.rxBusyStatus == true) + { + /* Disable receive and error interrupt */ + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + sercom3USARTObj.rxBusyStatus = false; + + /* If required application should read the num bytes processed prior to calling the read abort API */ + sercom3USARTObj.rxSize = 0U; + sercom3USARTObj.rxProcessedSize = 0U; + } + + return true; +} + +void SERCOM3_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ) +{ + sercom3USARTObj.rxCallback = callback; + + sercom3USARTObj.rxContext = context; +} + + +static void __attribute__((used)) SERCOM3_USART_ISR_ERR_Handler( void ) +{ + USART_ERROR errorStatus; + + errorStatus = (USART_ERROR) (SERCOM3_REGS->USART_INT.SERCOM_STATUS & (uint16_t)(SERCOM_USART_INT_STATUS_PERR_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_BUFOVF_Msk)); + + if(errorStatus != USART_ERROR_NONE) + { + /* Save the error to be reported later */ + sercom3USARTObj.errorStatus = errorStatus; + + /* Clear the error flags and flush out the error bytes */ + SERCOM3_USART_ErrorClear(); + + /* Disable error and receive interrupt to abort on-going transfer */ + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXC_Msk); + + /* Clear the RX busy flag */ + sercom3USARTObj.rxBusyStatus = false; + + if(sercom3USARTObj.rxCallback != NULL) + { + uintptr_t rxContext = sercom3USARTObj.rxContext; + + sercom3USARTObj.rxCallback(rxContext); + } + } +} + +static void __attribute__((used)) SERCOM3_USART_ISR_RX_Handler( void ) +{ + uint16_t temp; + + + if(sercom3USARTObj.rxBusyStatus == true) + { + size_t rxSize = sercom3USARTObj.rxSize; + + if(sercom3USARTObj.rxProcessedSize < rxSize) + { + uintptr_t rxContext = sercom3USARTObj.rxContext; + + temp = (uint16_t)SERCOM3_REGS->USART_INT.SERCOM_DATA; + size_t rxProcessedSize = sercom3USARTObj.rxProcessedSize; + + if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + ((uint8_t*)sercom3USARTObj.rxBuffer)[rxProcessedSize] = (uint8_t) (temp); + } + else + { + /* 9-bit mode */ + ((uint16_t*)sercom3USARTObj.rxBuffer)[rxProcessedSize] = temp; + } + + /* Increment processed size */ + rxProcessedSize++; + sercom3USARTObj.rxProcessedSize = rxProcessedSize; + + if(rxProcessedSize == sercom3USARTObj.rxSize) + { + sercom3USARTObj.rxBusyStatus = false; + sercom3USARTObj.rxSize = 0U; + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)(SERCOM_USART_INT_INTENCLR_RXC_Msk | SERCOM_USART_INT_INTENCLR_ERROR_Msk); + + if(sercom3USARTObj.rxCallback != NULL) + { + sercom3USARTObj.rxCallback(rxContext); + } + } + + } + } +} + +static void __attribute__((used)) SERCOM3_USART_ISR_TX_Handler( void ) +{ + bool dataRegisterEmpty; + bool dataAvailable; + if(sercom3USARTObj.txBusyStatus == true) + { + size_t txProcessedSize = sercom3USARTObj.txProcessedSize; + + dataAvailable = (txProcessedSize < sercom3USARTObj.txSize); + dataRegisterEmpty = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + + while(dataRegisterEmpty && dataAvailable) + { + if (((SERCOM3_REGS->USART_INT.SERCOM_CTRLB & SERCOM_USART_INT_CTRLB_CHSIZE_Msk) >> SERCOM_USART_INT_CTRLB_CHSIZE_Pos) != 0x01U) + { + /* 8-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint8_t*)sercom3USARTObj.txBuffer)[txProcessedSize]; + } + else + { + /* 9-bit mode */ + SERCOM3_REGS->USART_INT.SERCOM_DATA = ((uint16_t*)sercom3USARTObj.txBuffer)[txProcessedSize]; + } + /* Increment processed size */ + txProcessedSize++; + + dataAvailable = (txProcessedSize < sercom3USARTObj.txSize); + dataRegisterEmpty = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + } + + sercom3USARTObj.txProcessedSize = txProcessedSize; + + if(txProcessedSize >= sercom3USARTObj.txSize) + { + sercom3USARTObj.txBusyStatus = false; + sercom3USARTObj.txSize = 0U; + SERCOM3_REGS->USART_INT.SERCOM_INTENCLR = (uint8_t)SERCOM_USART_INT_INTENCLR_DRE_Msk; + + if(sercom3USARTObj.txCallback != NULL) + { + uintptr_t txContext = sercom3USARTObj.txContext; + sercom3USARTObj.txCallback(txContext); + } + } + } +} + +void __attribute__((used)) SERCOM3_USART_InterruptHandler( void ) +{ + bool testCondition; + if(SERCOM3_REGS->USART_INT.SERCOM_INTENSET != 0U) + { + /* Checks for error flag */ + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_ERROR_Msk) == SERCOM_USART_INT_INTFLAG_ERROR_Msk); + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_ERROR_Msk) == SERCOM_USART_INT_INTENSET_ERROR_Msk) && testCondition; + if(testCondition) + { + SERCOM3_USART_ISR_ERR_Handler(); + } + + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == SERCOM_USART_INT_INTFLAG_DRE_Msk); + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_DRE_Msk) == SERCOM_USART_INT_INTENSET_DRE_Msk) && testCondition; + /* Checks for data register empty flag */ + if(testCondition) + { + SERCOM3_USART_ISR_TX_Handler(); + } + + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == SERCOM_USART_INT_INTFLAG_RXC_Msk); + testCondition = ((SERCOM3_REGS->USART_INT.SERCOM_INTENSET & SERCOM_USART_INT_INTENSET_RXC_Msk) == SERCOM_USART_INT_INTENSET_RXC_Msk) && testCondition; + /* Checks for receive complete empty flag */ + if(testCondition) + { + SERCOM3_USART_ISR_RX_Handler(); + } + } +} + + + + diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h new file mode 100644 index 00000000..22cbca64 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom3_usart.h @@ -0,0 +1,121 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchrnous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom3_usart.h + + Summary + USART peripheral library interface. + + Description + This file defines the interface to the USART peripheral library. This + library provides access to and control of the associated peripheral + instance. + + Remarks: + None. +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef PLIB_SERCOM3_USART_H // Guards against multiple inclusion +#define PLIB_SERCOM3_USART_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include "plib_sercom_usart_common.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section: Interface Routines +// ***************************************************************************** +// ***************************************************************************** + +void SERCOM3_USART_Initialize( void ); + +bool SERCOM3_USART_SerialSetup( USART_SERIAL_SETUP * serialSetup, uint32_t clkFrequency ); + +void SERCOM3_USART_Enable( void ); + +void SERCOM3_USART_Disable( void ); + +void SERCOM3_USART_TransmitterEnable( void ); + +void SERCOM3_USART_TransmitterDisable( void ); + +bool SERCOM3_USART_Write( void *buffer, const size_t size ); + +bool SERCOM3_USART_TransmitComplete( void ); + + +bool SERCOM3_USART_WriteIsBusy( void ); + +size_t SERCOM3_USART_WriteCountGet( void ); + +void SERCOM3_USART_WriteCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + + +void SERCOM3_USART_ReceiverEnable( void ); + +void SERCOM3_USART_ReceiverDisable( void ); + +bool SERCOM3_USART_Read( void *buffer, const size_t size ); + +bool SERCOM3_USART_ReadIsBusy( void ); + +size_t SERCOM3_USART_ReadCountGet( void ); + +bool SERCOM3_USART_ReadAbort(void); + +void SERCOM3_USART_ReadCallbackRegister( SERCOM_USART_CALLBACK callback, uintptr_t context ); + +USART_ERROR SERCOM3_USART_ErrorGet( void ); + +uint32_t SERCOM3_USART_FrequencyGet( void ); + + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM3_USART_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h new file mode 100644 index 00000000..ab6321c6 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/peripheral/sercom/usart/plib_sercom_usart_common.h @@ -0,0 +1,405 @@ +/******************************************************************************* + SERCOM Universal Synchronous/Asynchronous Receiver/Transmitter PLIB + + Company + Microchip Technology Inc. + + File Name + plib_sercom_usart_common.h + + Summary + Data Type definition of the USART Peripheral Interface Plib. + + Description + This file defines the Data Types for the USART Plib. + + Remarks: + None. +*******************************************************************************/ + +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#ifndef PLIB_SERCOM_USART_COMMON_H // Guards against multiple inclusion +#define PLIB_SERCOM_USART_COMMON_H + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include +#include +#include +#include "device.h" + +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + extern "C" { + +#endif +// DOM-IGNORE-END + +// ***************************************************************************** +// ***************************************************************************** +// Section:Preprocessor macros +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* USART Error convenience macros */ +// ***************************************************************************** +// ***************************************************************************** + /* Error status when no error has occurred */ +#define USART_ERROR_NONE 0U + + /* Error status when parity error has occurred */ +#define USART_ERROR_PARITY SERCOM_USART_INT_STATUS_PERR_Msk + + /* Error status when framing error has occurred */ +#define USART_ERROR_FRAMING SERCOM_USART_INT_STATUS_FERR_Msk + + /* Error status when overrun error has occurred */ +#define USART_ERROR_OVERRUN SERCOM_USART_INT_STATUS_BUFOVF_Msk + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Data Types +// ***************************************************************************** +// ***************************************************************************** +// ***************************************************************************** + +// ***************************************************************************** +/* USART Errors + + Summary: + Defines the data type for the USART peripheral errors. + + Description: + This may be used to check the type of error occurred with the USART + peripheral during error status. + + Remarks: + None. +*/ + +typedef uint16_t USART_ERROR; + +// ***************************************************************************** +/* USART DATA + + Summary: + Defines the data type for the USART peripheral data. + + Description: + This may be used to check the type of data with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_DATA_5_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT, + USART_DATA_6_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT, + USART_DATA_7_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT, + USART_DATA_8_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT, + USART_DATA_9_BIT = SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT, + + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_DATA_INVALID = 0xFFFFFFFFU + +} USART_DATA; + +// ***************************************************************************** +/* USART PARITY + + Summary: + Defines the data type for the USART peripheral parity. + + Description: + This may be used to check the type of parity with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_PARITY_EVEN = SERCOM_USART_INT_CTRLB_PMODE_EVEN, + + USART_PARITY_ODD = SERCOM_USART_INT_CTRLB_PMODE_ODD, + + /* This enum is defined to set frame format only + * This value won't be written to register + */ + USART_PARITY_NONE = 0x2, + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_PARITY_INVALID = 0xFFFFFFFFU + +} USART_PARITY; + +// ***************************************************************************** +/* USART STOP + + Summary: + Defines the data type for the USART peripheral stop bits. + + Description: + This may be used to check the type of stop bits with the USART + peripheral during serial setup. + + Remarks: + None. +*/ + +typedef enum +{ + USART_STOP_0_BIT = SERCOM_USART_INT_CTRLB_SBMODE_1_BIT, + USART_STOP_1_BIT = SERCOM_USART_INT_CTRLB_SBMODE_2_BIT, + + + /* Force the compiler to reserve 32-bit memory for each enum */ + USART_STOP_INVALID = 0xFFFFFFFFU + +} USART_STOP; + +// ***************************************************************************** +/* USART LIN Command + + Summary: + Defines the data type for the USART peripheral LIN Command. + + Description: + This may be used to set the USART LIN Master mode command. + + Remarks: + None. +*/ + +typedef enum +{ + USART_LIN_MASTER_CMD_NONE = SERCOM_USART_INT_CTRLB_LINCMD_NONE, + + USART_LIN_MASTER_CMD_SOFTWARE_CONTROLLED = SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD, + + USART_LIN_MASTER_CMD_AUTO_TRANSMIT = SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD + +} USART_LIN_MASTER_CMD; + +// ***************************************************************************** +/* USART Serial Configuration + + Summary: + Defines the data type for the USART serial configurations. + + Description: + This may be used to set the serial configurations for USART. + + Remarks: + None. +*/ + +typedef struct +{ + uint32_t baudRate; + + USART_PARITY parity; + + USART_DATA dataWidth; + + USART_STOP stopBits; + +} USART_SERIAL_SETUP; + +// ***************************************************************************** +/* Callback Function Pointer + + Summary: + Defines the data type and function signature for the USART peripheral + callback function. + + Description: + This data type defines the function signature for the USART peripheral + callback function. The USART peripheral will call back the client's + function with this signature when the USART buffer event has occurred. + + Remarks: + None. +*/ + +typedef void (*SERCOM_USART_CALLBACK)( uintptr_t context ); + +// ***************************************************************************** +/* SERCOM USART Object + + Summary: + Defines the data type for the data structures used for + peripheral operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + void * txBuffer; + + size_t txSize; + + size_t txProcessedSize; + + SERCOM_USART_CALLBACK txCallback; + + uintptr_t txContext; + + bool txBusyStatus; + + void * rxBuffer; + + size_t rxSize; + + size_t rxProcessedSize; + + SERCOM_USART_CALLBACK rxCallback; + + uintptr_t rxContext; + + bool rxBusyStatus; + + USART_ERROR errorStatus; + +} SERCOM_USART_OBJECT; + + +typedef enum +{ + /* Threshold number of bytes are available in the receive ring buffer */ + SERCOM_USART_EVENT_READ_THRESHOLD_REACHED = 0, + + /* Receive ring buffer is full. Application must read the data out to avoid missing data on the next RX interrupt. */ + SERCOM_USART_EVENT_READ_BUFFER_FULL, + + /* USART error. Application must call the SERCOMx_USART_ErrorGet API to get the type of error and clear the error. */ + SERCOM_USART_EVENT_READ_ERROR, + + /* Threshold number of free space is available in the transmit ring buffer */ + SERCOM_USART_EVENT_WRITE_THRESHOLD_REACHED, + + /* Recevie break signal is detected */ + SERCOM_USART_EVENT_BREAK_SIGNAL_DETECTED, +}SERCOM_USART_EVENT; + +// ***************************************************************************** +/* Callback Function Pointer + + Summary: + Defines the data type and function signature for the USART peripheral + callback function. + + Description: + This data type defines the function signature for the USART peripheral + callback function. The USART peripheral will call back the client's + function with this signature when the USART buffer event has occurred. + + Remarks: + None. +*/ + +typedef void (*SERCOM_USART_RING_BUFFER_CALLBACK)(SERCOM_USART_EVENT event, uintptr_t context ); + +// ***************************************************************************** +/* SERCOM USART Ring Buffer Object + + Summary: + Defines the data type for the data structures used for + peripheral operations. + + Description: + This may be for used for peripheral operations. + + Remarks: + None. +*/ + +typedef struct +{ + SERCOM_USART_RING_BUFFER_CALLBACK wrCallback; + + uintptr_t wrContext; + + uint32_t wrInIndex; + + uint32_t wrOutIndex; + + uint32_t wrBufferSize; + + bool isWrNotificationEnabled; + + uint32_t wrThreshold; + + bool isWrNotifyPersistently; + + SERCOM_USART_RING_BUFFER_CALLBACK rdCallback; + + uintptr_t rdContext; + + uint32_t rdInIndex; + + uint32_t rdOutIndex; + + uint32_t rdBufferSize; + + bool isRdNotificationEnabled; + + uint32_t rdThreshold; + + bool isRdNotifyPersistently; + + USART_ERROR errorStatus; + +} SERCOM_USART_RING_BUFFER_OBJECT; + +// ***************************************************************************** +// DOM-IGNORE-BEGIN +#ifdef __cplusplus // Provide C++ Compatibility + + } + +#endif +// DOM-IGNORE-END + +#endif //PLIB_SERCOM_USART_COMMON_H diff --git a/bms_e18a/bms_e18a_config/src/config/default/startup_xc32.c b/bms_e18a/bms_e18a_config/src/config/default/startup_xc32.c new file mode 100644 index 00000000..d9430dd5 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/startup_xc32.c @@ -0,0 +1,145 @@ +// DOM-IGNORE-BEGIN +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +// DOM-IGNORE-END + +#include +#include +#include +#include "device.h" +#include "interrupts.h" + +/* + * The MPLAB X Simulator does not yet support simulation of programming the + * GPNVM bits yet. We can remove this once it supports the FRDY bit. + */ + /* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.1 deviated 1 time. Deviation record ID - H3_MISRAC_2012_R_21_1_DR_1 */ +#ifdef __MPLAB_DEBUGGER_SIMULATOR +#define __XC32_SKIP_STARTUP_GPNVM_WAIT +#endif +/* MISRAC 2012 deviation block end */ + +/* + * This startup code relies on features that are specific to the MPLAB XC32 + * toolchain. Do not use it with other toolchains. + */ +#ifndef __XC32 +#warning This startup code is intended for use with the MPLAB XC32 Compiler only. +#endif + +/* MISRAC 2012 deviation block start */ +/* MISRA C-2012 Rule 21.2 deviated 5 times. Deviation record ID - H3_MISRAC_2012_R_21_2_DR_1 */ +/* MISRA C-2012 Rule 8.6 deviated 6 times. Deviation record ID - H3_MISRAC_2012_R_8_6_DR_1 */ + +/* array initialization function */ +extern void __attribute__((long_call)) __libc_init_array(void); + +/* Optional application-provided functions */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) _on_bootstrap(void); + +/* Reserved for use by the MPLAB XC32 Compiler */ +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_reset(void); +extern void __attribute__((weak,long_call, alias("Dummy_App_Func"))) __xc32_on_bootstrap(void); + +/* Linker defined variables */ +extern uint32_t __svectors; +#if defined (__REINIT_STACK_POINTER) +extern uint32_t _stack; +#endif + +/* MISRAC 2012 deviation block end */ + + +extern int main(void); + + + +/* Brief default application function used as a weak reference */ +extern void Dummy_App_Func(void); +void __attribute__((optimize("-O1"),long_call))Dummy_App_Func(void) +{ + /* Do nothing */ + return; +} + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void __attribute__((optimize("-O1"), section(".text.Reset_Handler"), long_call, noreturn)) Reset_Handler(void) +{ +#ifdef SCB_VTOR_TBLOFF_Msk + uint32_t *pSrc; +#endif + +#if defined (__REINIT_STACK_POINTER) + /* Initialize SP from linker-defined _stack symbol. */ + __set_MSP((uint32_t)&_stack); + +#ifdef SCB_VTOR_TBLOFF_Msk + /* Buy stack for locals */ + __asm__ volatile ("sub sp, sp, #8" : : : "sp"); +#endif + __asm__ volatile ("add r7, sp, #0" : : : "r7"); +#endif + + /* Call the optional application-provided _on_reset() function. */ + _on_reset(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_reset(); + + /* Initialize data after TCM is enabled. + * Data initialization from the XC32 .dinit template */ + __pic32c_data_initialization(); + + +# ifdef SCB_VTOR_TBLOFF_Msk + /* Set the vector-table base address in FLASH */ + pSrc = (uint32_t *) & __svectors; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); +# endif /* SCB_VTOR_TBLOFF_Msk */ + + /* Initialize the C library */ + __libc_init_array(); + + /* Call the optional application-provided _on_bootstrap() function. */ + _on_bootstrap(); + + /* Reserved for use by MPLAB XC32. */ + __xc32_on_bootstrap(); + + /* Branch to application's main function */ + (void)main(); + +#if (defined(__DEBUG) || defined(__DEBUG_D)) && defined(__XC32) + __builtin_software_breakpoint(); +#endif + + while (true) + { + /* Infinite loop */ + } +} diff --git a/bms_e18a/bms_e18a_config/src/config/default/stdio/xc32_monitor.c b/bms_e18a/bms_e18a_config/src/config/default/stdio/xc32_monitor.c new file mode 100644 index 00000000..8d9df630 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/stdio/xc32_monitor.c @@ -0,0 +1,54 @@ +/******************************************************************************* + Debug Console Source file + + Company: + Microchip Technology Inc. + + File Name: + xc32_monitor.c + + Summary: + debug console Source File + + Description: + None + +*******************************************************************************/ + +/******************************************************************************* +* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ +#include + +extern int read(int handle, void *buffer, unsigned int len); +extern int write(int handle, void * buffer, size_t count); + + +int read(int handle, void *buffer, unsigned int len) +{ + return -1; +} + +int write(int handle, void * buffer, size_t count) +{ + return -1; +} \ No newline at end of file diff --git a/bms_e18a/bms_e18a_config/src/config/default/toolchain_specifics.h b/bms_e18a/bms_e18a_config/src/config/default/toolchain_specifics.h new file mode 100644 index 00000000..96407a4e --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/config/default/toolchain_specifics.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries. +* +* Subject to your compliance with these terms, you may use Microchip software +* and any derivatives exclusively with Microchip products. It is your +* responsibility to comply with third party license terms applicable to your +* use of third party software (including open source software) that may +* accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER +* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED +* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A +* PARTICULAR PURPOSE. +* +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE +* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN +* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +*******************************************************************************/ + +#ifndef TOOLCHAIN_SPECIFICS_H +#define TOOLCHAIN_SPECIFICS_H + +#ifdef __cplusplus // Provide C++ Compatibility +extern "C" { +#endif + +#pragma GCC diagnostic push +#ifndef __cplusplus + #pragma GCC diagnostic ignored "-Wnested-externs" +#endif +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wattributes" +#pragma GCC diagnostic ignored "-Wundef" +#include "cmsis_compiler.h" +#pragma GCC diagnostic pop + +#include + +#define NO_INIT __attribute__((section(".no_init"))) +#define SECTION(a) __attribute__((__section__(a))) + +#define CACHE_LINE_SIZE (4u) +#define CACHE_ALIGN + +#define CACHE_ALIGNED_SIZE_GET(size) ((size) + ((((size) % (CACHE_LINE_SIZE))!= 0U)? ((CACHE_LINE_SIZE) - ((size) % (CACHE_LINE_SIZE))) : (0U))) + +#ifndef FORMAT_ATTRIBUTE + #define FORMAT_ATTRIBUTE(archetype, string_index, first_to_check) __attribute__ ((format (archetype, string_index, first_to_check))) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // end of header + diff --git a/bms_e18a/bms_e18a_config/src/main.c b/bms_e18a/bms_e18a_config/src/main.c new file mode 100644 index 00000000..fca5cf22 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/main.c @@ -0,0 +1,57 @@ +/******************************************************************************* + Main Source File + + Company: + Microchip Technology Inc. + + File Name: + main.c + + Summary: + This file contains the "main" function for a project. + + Description: + This file contains the "main" function for a project. The + "main" function calls the "SYS_Initialize" function to initialize the state + machines of all modules in the system + *******************************************************************************/ + +// ***************************************************************************** +// ***************************************************************************** +// Section: Included Files +// ***************************************************************************** +// ***************************************************************************** + +#include // Defines NULL +#include // Defines true +#include // Defines EXIT_FAILURE +#include "config/default/definitions.h" // SYS function prototypes + + +// ***************************************************************************** +// ***************************************************************************** +// Section: Main Entry Point +// ***************************************************************************** +// ***************************************************************************** + +int main ( void ) +{ + /* Initialize all modules */ + SYS_Initialize ( NULL ); + + while ( true ) + { + /* Maintain state machines of all polled MPLAB Harmony modules. */ + SYS_Tasks ( ); + } + + /* Execution should not come here during normal operation */ + + return ( EXIT_FAILURE ); +} + + +/******************************************************************************* + End of File +*/ + diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/ac.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/ac.h new file mode 100644 index 00000000..1f81f59a --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/ac.h @@ -0,0 +1,490 @@ +/* + * Component description for AC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_AC_COMPONENT_H_ +#define _SAMC21_AC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _UINT8_(0x00) /* (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _UINT8_(0) /* (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_UINT8_(0x1) << AC_CTRLA_SWRST_Pos) /* (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & (_UINT8_(value) << AC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AC_CTRLA register */ +#define AC_CTRLA_ENABLE_Pos _UINT8_(1) /* (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << AC_CTRLA_ENABLE_Pos) /* (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & (_UINT8_(value) << AC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_CTRLA register */ +#define AC_CTRLA_Msk _UINT8_(0x03) /* (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _UINT8_(0x00) /* (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _UINT8_(0) /* (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_UINT8_(0x1) << AC_CTRLB_START0_Pos) /* (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & (_UINT8_(value) << AC_CTRLB_START0_Pos)) /* Assigment of value for START0 in the AC_CTRLB register */ +#define AC_CTRLB_START1_Pos _UINT8_(1) /* (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_UINT8_(0x1) << AC_CTRLB_START1_Pos) /* (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & (_UINT8_(value) << AC_CTRLB_START1_Pos)) /* Assigment of value for START1 in the AC_CTRLB register */ +#define AC_CTRLB_START2_Pos _UINT8_(2) /* (AC_CTRLB) Comparator 2 Start Comparison Position */ +#define AC_CTRLB_START2_Msk (_UINT8_(0x1) << AC_CTRLB_START2_Pos) /* (AC_CTRLB) Comparator 2 Start Comparison Mask */ +#define AC_CTRLB_START2(value) (AC_CTRLB_START2_Msk & (_UINT8_(value) << AC_CTRLB_START2_Pos)) /* Assigment of value for START2 in the AC_CTRLB register */ +#define AC_CTRLB_START3_Pos _UINT8_(3) /* (AC_CTRLB) Comparator 3 Start Comparison Position */ +#define AC_CTRLB_START3_Msk (_UINT8_(0x1) << AC_CTRLB_START3_Pos) /* (AC_CTRLB) Comparator 3 Start Comparison Mask */ +#define AC_CTRLB_START3(value) (AC_CTRLB_START3_Msk & (_UINT8_(value) << AC_CTRLB_START3_Pos)) /* Assigment of value for START3 in the AC_CTRLB register */ +#define AC_CTRLB_Msk _UINT8_(0x0F) /* (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _UINT8_(0) /* (AC_CTRLB Position) Comparator 3 Start Comparison */ +#define AC_CTRLB_START_Msk (_UINT8_(0xF) << AC_CTRLB_START_Pos) /* (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & (_UINT8_(value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _UINT16_(0) /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO0_Pos) /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assigment of value for COMPEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO1_Pos _UINT16_(1) /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO1_Pos) /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assigment of value for COMPEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO2_Pos _UINT16_(2) /* (AC_EVCTRL) Comparator 2 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO2_Pos) /* (AC_EVCTRL) Comparator 2 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO2(value) (AC_EVCTRL_COMPEO2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO2_Pos)) /* Assigment of value for COMPEO2 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO3_Pos _UINT16_(3) /* (AC_EVCTRL) Comparator 3 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO3_Pos) /* (AC_EVCTRL) Comparator 3 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO3(value) (AC_EVCTRL_COMPEO3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO3_Pos)) /* Assigment of value for COMPEO3 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO0_Pos _UINT16_(4) /* (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO0_Pos) /* (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assigment of value for WINEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO1_Pos _UINT16_(5) /* (AC_EVCTRL) Window 1 Event Output Enable Position */ +#define AC_EVCTRL_WINEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO1_Pos) /* (AC_EVCTRL) Window 1 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO1(value) (AC_EVCTRL_WINEO1_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO1_Pos)) /* Assigment of value for WINEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI0_Pos _UINT16_(8) /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI0_Pos) /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assigment of value for COMPEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI1_Pos _UINT16_(9) /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI1_Pos) /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assigment of value for COMPEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI2_Pos _UINT16_(10) /* (AC_EVCTRL) Comparator 2 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI2_Pos) /* (AC_EVCTRL) Comparator 2 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI2(value) (AC_EVCTRL_COMPEI2_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI2_Pos)) /* Assigment of value for COMPEI2 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI3_Pos _UINT16_(11) /* (AC_EVCTRL) Comparator 3 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI3_Pos) /* (AC_EVCTRL) Comparator 3 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI3(value) (AC_EVCTRL_COMPEI3_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI3_Pos)) /* Assigment of value for COMPEI3 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI0_Pos _UINT16_(12) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI0_Pos) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assigment of value for INVEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI1_Pos _UINT16_(13) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI1_Pos) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assigment of value for INVEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI2_Pos _UINT16_(14) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI2_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI2_Pos) /* (AC_EVCTRL) Comparator 2 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI2(value) (AC_EVCTRL_INVEI2_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI2_Pos)) /* Assigment of value for INVEI2 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI3_Pos _UINT16_(15) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI3_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI3_Pos) /* (AC_EVCTRL) Comparator 3 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI3(value) (AC_EVCTRL_INVEI3_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI3_Pos)) /* Assigment of value for INVEI3 in the AC_EVCTRL register */ +#define AC_EVCTRL_Msk _UINT16_(0xFF3F) /* (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _UINT16_(0) /* (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEO_Pos) /* (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _UINT16_(4) /* (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_UINT16_(0x3) << AC_EVCTRL_WINEO_Pos) /* (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _UINT16_(8) /* (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_UINT16_(0xF) << AC_EVCTRL_COMPEI_Pos) /* (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _UINT16_(12) /* (AC_EVCTRL Position) Comparator 3 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_UINT16_(0xF) << AC_EVCTRL_INVEI_Pos) /* (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _UINT8_(0) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP0_Pos) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & (_UINT8_(value) << AC_INTENCLR_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP1_Pos _UINT8_(1) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP1_Pos) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & (_UINT8_(value) << AC_INTENCLR_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP2_Pos _UINT8_(2) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Position */ +#define AC_INTENCLR_COMP2_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP2_Pos) /* (AC_INTENCLR) Comparator 2 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP2(value) (AC_INTENCLR_COMP2_Msk & (_UINT8_(value) << AC_INTENCLR_COMP2_Pos)) /* Assigment of value for COMP2 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP3_Pos _UINT8_(3) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Position */ +#define AC_INTENCLR_COMP3_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP3_Pos) /* (AC_INTENCLR) Comparator 3 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP3(value) (AC_INTENCLR_COMP3_Msk & (_UINT8_(value) << AC_INTENCLR_COMP3_Pos)) /* Assigment of value for COMP3 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN0_Pos _UINT8_(4) /* (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN0_Pos) /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & (_UINT8_(value) << AC_INTENCLR_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN1_Pos _UINT8_(5) /* (AC_INTENCLR) Window 1 Interrupt Enable Position */ +#define AC_INTENCLR_WIN1_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN1_Pos) /* (AC_INTENCLR) Window 1 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN1(value) (AC_INTENCLR_WIN1_Msk & (_UINT8_(value) << AC_INTENCLR_WIN1_Pos)) /* Assigment of value for WIN1 in the AC_INTENCLR register */ +#define AC_INTENCLR_Msk _UINT8_(0x3F) /* (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _UINT8_(0) /* (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_UINT8_(0xF) << AC_INTENCLR_COMP_Pos) /* (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & (_UINT8_(value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _UINT8_(4) /* (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_UINT8_(0x3) << AC_INTENCLR_WIN_Pos) /* (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & (_UINT8_(value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _UINT8_(0x00) /* (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _UINT8_(0) /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_UINT8_(0x1) << AC_INTENSET_COMP0_Pos) /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & (_UINT8_(value) << AC_INTENSET_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENSET register */ +#define AC_INTENSET_COMP1_Pos _UINT8_(1) /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_UINT8_(0x1) << AC_INTENSET_COMP1_Pos) /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & (_UINT8_(value) << AC_INTENSET_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENSET register */ +#define AC_INTENSET_COMP2_Pos _UINT8_(2) /* (AC_INTENSET) Comparator 2 Interrupt Enable Position */ +#define AC_INTENSET_COMP2_Msk (_UINT8_(0x1) << AC_INTENSET_COMP2_Pos) /* (AC_INTENSET) Comparator 2 Interrupt Enable Mask */ +#define AC_INTENSET_COMP2(value) (AC_INTENSET_COMP2_Msk & (_UINT8_(value) << AC_INTENSET_COMP2_Pos)) /* Assigment of value for COMP2 in the AC_INTENSET register */ +#define AC_INTENSET_COMP3_Pos _UINT8_(3) /* (AC_INTENSET) Comparator 3 Interrupt Enable Position */ +#define AC_INTENSET_COMP3_Msk (_UINT8_(0x1) << AC_INTENSET_COMP3_Pos) /* (AC_INTENSET) Comparator 3 Interrupt Enable Mask */ +#define AC_INTENSET_COMP3(value) (AC_INTENSET_COMP3_Msk & (_UINT8_(value) << AC_INTENSET_COMP3_Pos)) /* Assigment of value for COMP3 in the AC_INTENSET register */ +#define AC_INTENSET_WIN0_Pos _UINT8_(4) /* (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_UINT8_(0x1) << AC_INTENSET_WIN0_Pos) /* (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & (_UINT8_(value) << AC_INTENSET_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENSET register */ +#define AC_INTENSET_WIN1_Pos _UINT8_(5) /* (AC_INTENSET) Window 1 Interrupt Enable Position */ +#define AC_INTENSET_WIN1_Msk (_UINT8_(0x1) << AC_INTENSET_WIN1_Pos) /* (AC_INTENSET) Window 1 Interrupt Enable Mask */ +#define AC_INTENSET_WIN1(value) (AC_INTENSET_WIN1_Msk & (_UINT8_(value) << AC_INTENSET_WIN1_Pos)) /* Assigment of value for WIN1 in the AC_INTENSET register */ +#define AC_INTENSET_Msk _UINT8_(0x3F) /* (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _UINT8_(0) /* (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_UINT8_(0xF) << AC_INTENSET_COMP_Pos) /* (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & (_UINT8_(value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _UINT8_(4) /* (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_UINT8_(0x3) << AC_INTENSET_WIN_Pos) /* (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & (_UINT8_(value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _UINT8_(0) /* (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP0_Pos) /* (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & (_UINT8_(value) << AC_INTFLAG_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP1_Pos _UINT8_(1) /* (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP1_Pos) /* (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & (_UINT8_(value) << AC_INTFLAG_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP2_Pos _UINT8_(2) /* (AC_INTFLAG) Comparator 2 Position */ +#define AC_INTFLAG_COMP2_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP2_Pos) /* (AC_INTFLAG) Comparator 2 Mask */ +#define AC_INTFLAG_COMP2(value) (AC_INTFLAG_COMP2_Msk & (_UINT8_(value) << AC_INTFLAG_COMP2_Pos)) /* Assigment of value for COMP2 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP3_Pos _UINT8_(3) /* (AC_INTFLAG) Comparator 3 Position */ +#define AC_INTFLAG_COMP3_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP3_Pos) /* (AC_INTFLAG) Comparator 3 Mask */ +#define AC_INTFLAG_COMP3(value) (AC_INTFLAG_COMP3_Msk & (_UINT8_(value) << AC_INTFLAG_COMP3_Pos)) /* Assigment of value for COMP3 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN0_Pos _UINT8_(4) /* (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN0_Pos) /* (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & (_UINT8_(value) << AC_INTFLAG_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN1_Pos _UINT8_(5) /* (AC_INTFLAG) Window 1 Position */ +#define AC_INTFLAG_WIN1_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN1_Pos) /* (AC_INTFLAG) Window 1 Mask */ +#define AC_INTFLAG_WIN1(value) (AC_INTFLAG_WIN1_Msk & (_UINT8_(value) << AC_INTFLAG_WIN1_Pos)) /* Assigment of value for WIN1 in the AC_INTFLAG register */ +#define AC_INTFLAG_Msk _UINT8_(0x3F) /* (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _UINT8_(0) /* (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_UINT8_(0xF) << AC_INTFLAG_COMP_Pos) /* (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & (_UINT8_(value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _UINT8_(4) /* (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_UINT8_(0x3) << AC_INTFLAG_WIN_Pos) /* (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & (_UINT8_(value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _UINT8_(0x00) /* (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _UINT8_(0) /* (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_UINT8_(0x1) << AC_STATUSA_STATE0_Pos) /* (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & (_UINT8_(value) << AC_STATUSA_STATE0_Pos)) /* Assigment of value for STATE0 in the AC_STATUSA register */ +#define AC_STATUSA_STATE1_Pos _UINT8_(1) /* (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_UINT8_(0x1) << AC_STATUSA_STATE1_Pos) /* (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & (_UINT8_(value) << AC_STATUSA_STATE1_Pos)) /* Assigment of value for STATE1 in the AC_STATUSA register */ +#define AC_STATUSA_STATE2_Pos _UINT8_(2) /* (AC_STATUSA) Comparator 2 Current State Position */ +#define AC_STATUSA_STATE2_Msk (_UINT8_(0x1) << AC_STATUSA_STATE2_Pos) /* (AC_STATUSA) Comparator 2 Current State Mask */ +#define AC_STATUSA_STATE2(value) (AC_STATUSA_STATE2_Msk & (_UINT8_(value) << AC_STATUSA_STATE2_Pos)) /* Assigment of value for STATE2 in the AC_STATUSA register */ +#define AC_STATUSA_STATE3_Pos _UINT8_(3) /* (AC_STATUSA) Comparator 3 Current State Position */ +#define AC_STATUSA_STATE3_Msk (_UINT8_(0x1) << AC_STATUSA_STATE3_Pos) /* (AC_STATUSA) Comparator 3 Current State Mask */ +#define AC_STATUSA_STATE3(value) (AC_STATUSA_STATE3_Msk & (_UINT8_(value) << AC_STATUSA_STATE3_Pos)) /* Assigment of value for STATE3 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_Pos _UINT8_(4) /* (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assigment of value for WSTATE0 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_WSTATE1_Pos _UINT8_(6) /* (AC_STATUSA) Window 1 Current State Position */ +#define AC_STATUSA_WSTATE1_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Window 1 Current State Mask */ +#define AC_STATUSA_WSTATE1(value) (AC_STATUSA_WSTATE1_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE1_Pos)) /* Assigment of value for WSTATE1 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE1_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE1_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE1_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE1_ABOVE (AC_STATUSA_WSTATE1_ABOVE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE1_INSIDE (AC_STATUSA_WSTATE1_INSIDE_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE1_BELOW (AC_STATUSA_WSTATE1_BELOW_Val << AC_STATUSA_WSTATE1_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _UINT8_(0xFF) /* (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _UINT8_(0) /* (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_UINT8_(0xF) << AC_STATUSA_STATE_Pos) /* (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & (_UINT8_(value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _UINT8_(0x00) /* (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _UINT8_(0) /* (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_UINT8_(0x1) << AC_STATUSB_READY0_Pos) /* (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & (_UINT8_(value) << AC_STATUSB_READY0_Pos)) /* Assigment of value for READY0 in the AC_STATUSB register */ +#define AC_STATUSB_READY1_Pos _UINT8_(1) /* (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_UINT8_(0x1) << AC_STATUSB_READY1_Pos) /* (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & (_UINT8_(value) << AC_STATUSB_READY1_Pos)) /* Assigment of value for READY1 in the AC_STATUSB register */ +#define AC_STATUSB_READY2_Pos _UINT8_(2) /* (AC_STATUSB) Comparator 2 Ready Position */ +#define AC_STATUSB_READY2_Msk (_UINT8_(0x1) << AC_STATUSB_READY2_Pos) /* (AC_STATUSB) Comparator 2 Ready Mask */ +#define AC_STATUSB_READY2(value) (AC_STATUSB_READY2_Msk & (_UINT8_(value) << AC_STATUSB_READY2_Pos)) /* Assigment of value for READY2 in the AC_STATUSB register */ +#define AC_STATUSB_READY3_Pos _UINT8_(3) /* (AC_STATUSB) Comparator 3 Ready Position */ +#define AC_STATUSB_READY3_Msk (_UINT8_(0x1) << AC_STATUSB_READY3_Pos) /* (AC_STATUSB) Comparator 3 Ready Mask */ +#define AC_STATUSB_READY3(value) (AC_STATUSB_READY3_Msk & (_UINT8_(value) << AC_STATUSB_READY3_Pos)) /* Assigment of value for READY3 in the AC_STATUSB register */ +#define AC_STATUSB_Msk _UINT8_(0x0F) /* (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _UINT8_(0) /* (AC_STATUSB Position) Comparator 3 Ready */ +#define AC_STATUSB_READY_Msk (_UINT8_(0xF) << AC_STATUSB_READY_Pos) /* (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & (_UINT8_(value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /* (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AC_DBGCTRL register */ +#define AC_DBGCTRL_Msk _UINT8_(0x01) /* (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _UINT8_(0x00) /* (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _UINT8_(0) /* (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN0_Pos) /* (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & (_UINT8_(value) << AC_WINCTRL_WEN0_Pos)) /* Assigment of value for WEN0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_Pos _UINT8_(1) /* (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL0_Pos)) /* Assigment of value for WINTSEL0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_WEN1_Pos _UINT8_(4) /* (AC_WINCTRL) Window 1 Mode Enable Position */ +#define AC_WINCTRL_WEN1_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN1_Pos) /* (AC_WINCTRL) Window 1 Mode Enable Mask */ +#define AC_WINCTRL_WEN1(value) (AC_WINCTRL_WEN1_Msk & (_UINT8_(value) << AC_WINCTRL_WEN1_Pos)) /* Assigment of value for WEN1 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL1_Pos _UINT8_(5) /* (AC_WINCTRL) Window 1 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL1_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Window 1 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL1(value) (AC_WINCTRL_WINTSEL1_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL1_Pos)) /* Assigment of value for WINTSEL1 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL1_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL1_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL1_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL1_ABOVE (AC_WINCTRL_WINTSEL1_ABOVE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL1_INSIDE (AC_WINCTRL_WINTSEL1_INSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL1_BELOW (AC_WINCTRL_WINTSEL1_BELOW_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE (AC_WINCTRL_WINTSEL1_OUTSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _UINT8_(0x77) /* (AC_WINCTRL) Register Mask */ + + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _UINT8_(0x00) /* (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _UINT8_(0) /* (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_UINT8_(0x3F) << AC_SCALER_VALUE_Pos) /* (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & (_UINT8_(value) << AC_SCALER_VALUE_Pos)) /* Assigment of value for VALUE in the AC_SCALER register */ +#define AC_SCALER_Msk _UINT8_(0x3F) /* (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _UINT32_(0x00) /* (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _UINT32_(1) /* (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos) /* (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SINGLE_Pos _UINT32_(2) /* (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos) /* (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assigment of value for SINGLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_Pos _UINT32_(3) /* (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assigment of value for INTSEL in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _UINT32_(0x0) /* (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _UINT32_(0x1) /* (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _UINT32_(0x2) /* (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _UINT32_(0x3) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _UINT32_(6) /* (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /* (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_Pos _UINT32_(8) /* (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _UINT32_(0x4) /* (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _UINT32_(0x5) /* (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _UINT32_(0x6) /* (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _UINT32_(0x7) /* (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _UINT32_(12) /* (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXPOS_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _UINT32_(0x4) /* (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _UINT32_(15) /* (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos) /* (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assigment of value for SWAP in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_Pos _UINT32_(16) /* (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_UINT32_(0x3) << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assigment of value for SPEED in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_LOW_Val _UINT32_(0x0) /* (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _UINT32_(0x3) /* (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Low speed Position */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _UINT32_(19) /* (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_UINT32_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /* (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & (_UINT32_(value) << AC_COMPCTRL_HYSTEN_Pos)) /* Assigment of value for HYSTEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_Pos _UINT32_(24) /* (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assigment of value for FLEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _UINT32_(0x1) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _UINT32_(0x2) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _UINT32_(28) /* (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assigment of value for OUT in the AC_COMPCTRL register */ +#define AC_COMPCTRL_OUT_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _UINT32_(0x1) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _UINT32_(0x2) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _UINT32_(0x370BF75E) /* (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_WINCTRL_Pos _UINT32_(2) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) /* Assigment of value for WINCTRL in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL0_Pos _UINT32_(3) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assigment of value for COMPCTRL0 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL1_Pos _UINT32_(4) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assigment of value for COMPCTRL1 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL2_Pos _UINT32_(5) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL2_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL2_Pos) /* (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL2(value) (AC_SYNCBUSY_COMPCTRL2_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL2_Pos)) /* Assigment of value for COMPCTRL2 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL3_Pos _UINT32_(6) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL3_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL3_Pos) /* (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL3(value) (AC_SYNCBUSY_COMPCTRL3_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL3_Pos)) /* Assigment of value for COMPCTRL3 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_Msk _UINT32_(0x0000007F) /* (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _UINT32_(3) /* (AC_SYNCBUSY Position) COMPCTRL 3 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_UINT32_(0xF) << AC_SYNCBUSY_COMPCTRL_Pos) /* (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/** \brief AC register offsets definitions */ +#define AC_CTRLA_REG_OFST _UINT32_(0x00) /* (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST _UINT32_(0x01) /* (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST _UINT32_(0x02) /* (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST _UINT32_(0x04) /* (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST _UINT32_(0x05) /* (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST _UINT32_(0x06) /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST _UINT32_(0x07) /* (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST _UINT32_(0x08) /* (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST _UINT32_(0x0A) /* (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST _UINT32_(0x0C) /* (AC_SCALER) Scaler n Offset */ +#define AC_SCALER0_REG_OFST _UINT32_(0x0C) /* (AC_SCALER0) Scaler n Offset */ +#define AC_SCALER1_REG_OFST _UINT32_(0x0D) /* (AC_SCALER1) Scaler n Offset */ +#define AC_SCALER2_REG_OFST _UINT32_(0x0E) /* (AC_SCALER2) Scaler n Offset */ +#define AC_SCALER3_REG_OFST _UINT32_(0x0F) /* (AC_SCALER3) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_COMPCTRL0_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL0) Comparator Control n Offset */ +#define AC_COMPCTRL1_REG_OFST _UINT32_(0x14) /* (AC_COMPCTRL1) Comparator Control n Offset */ +#define AC_COMPCTRL2_REG_OFST _UINT32_(0x18) /* (AC_COMPCTRL2) Comparator Control n Offset */ +#define AC_COMPCTRL3_REG_OFST _UINT32_(0x1C) /* (AC_COMPCTRL3) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (AC_SYNCBUSY) Synchronization Busy Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[4]; /**< Offset: 0x0C (R/W 8) Scaler n */ + __IO uint32_t AC_COMPCTRL[4]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_AC_COMPONENT_H_ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/adc.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/adc.h new file mode 100644 index 00000000..418bc316 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/adc.h @@ -0,0 +1,523 @@ +/* + * Component description for ADC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_ADC_COMPONENT_H_ +#define _SAMC21_ADC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _UINT8_(0) /* (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_UINT8_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT8_(value) << ADC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_CTRLA register */ +#define ADC_CTRLA_ENABLE_Pos _UINT8_(1) /* (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT8_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_CTRLA register */ +#define ADC_CTRLA_SLAVEEN_Pos _UINT8_(5) /* (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_UINT8_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT8_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assigment of value for SLAVEEN in the ADC_CTRLA register */ +#define ADC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (ADC_CTRLA) Run During Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run During Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the ADC_CTRLA register */ +#define ADC_CTRLA_ONDEMAND_Pos _UINT8_(7) /* (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_UINT8_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT8_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the ADC_CTRLA register */ +#define ADC_CTRLA_Msk _UINT8_(0xE3) /* (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _UINT8_(0x00) /* (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_PRESCALER_Pos _UINT8_(0) /* (ADC_CTRLB) Prescaler Configuration Position */ +#define ADC_CTRLB_PRESCALER_Msk (_UINT8_(0x7) << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Prescaler Configuration Mask */ +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & (_UINT8_(value) << ADC_CTRLB_PRESCALER_Pos)) /* Assigment of value for PRESCALER in the ADC_CTRLB register */ +#define ADC_CTRLB_PRESCALER_DIV2_Val _UINT8_(0x0) /* (ADC_CTRLB) Peripheral clock / 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _UINT8_(0x1) /* (ADC_CTRLB) Peripheral clock / 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _UINT8_(0x2) /* (ADC_CTRLB) Peripheral clock / 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _UINT8_(0x3) /* (ADC_CTRLB) Peripheral clock / 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _UINT8_(0x4) /* (ADC_CTRLB) Peripheral clock / 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _UINT8_(0x5) /* (ADC_CTRLB) Peripheral clock / 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _UINT8_(0x6) /* (ADC_CTRLB) Peripheral clock / 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _UINT8_(0x7) /* (ADC_CTRLB) Peripheral clock / 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 2 Position */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 4 Position */ +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 8 Position */ +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 16 Position */ +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 32 Position */ +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 64 Position */ +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 128 Position */ +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) /* (ADC_CTRLB) Peripheral clock / 256 Position */ +#define ADC_CTRLB_Msk _UINT8_(0x07) /* (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assigment of value for REFSEL in the ADC_REFCTRL register */ +#define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x1) /* (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x3) /* (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_DAC_Val _UINT8_(0x4) /* (ADC_REFCTRL) DAC */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _UINT8_(0x5) /* (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/1.6 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference Position */ +#define ADC_REFCTRL_REFSEL_DAC (ADC_REFCTRL_REFSEL_DAC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) DAC Position */ +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assigment of value for REFCOMP in the ADC_REFCTRL register */ +#define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assigment of value for FLUSHEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assigment of value for STARTEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assigment of value for FLUSHINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assigment of value for STARTINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assigment of value for RESRDYEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assigment of value for WINMONEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENCLR register */ +#define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENCLR register */ +#define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENCLR register */ +#define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENSET register */ +#define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENSET register */ +#define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENSET register */ +#define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTFLAG register */ +#define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTFLAG register */ +#define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTFLAG register */ +#define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) ( R/ 8) Sequence Status -------- */ +#define ADC_SEQSTATUS_RESETVALUE _UINT8_(0x00) /* (ADC_SEQSTATUS) Sequence Status Reset Value */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos _UINT8_(0) /* (ADC_SEQSTATUS) Sequence State Position */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_UINT8_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) /* (ADC_SEQSTATUS) Sequence State Mask */ +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQSTATE_Pos)) /* Assigment of value for SEQSTATE in the ADC_SEQSTATUS register */ +#define ADC_SEQSTATUS_SEQBUSY_Pos _UINT8_(7) /* (ADC_SEQSTATUS) Sequence Busy Position */ +#define ADC_SEQSTATUS_SEQBUSY_Msk (_UINT8_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) /* (ADC_SEQSTATUS) Sequence Busy Mask */ +#define ADC_SEQSTATUS_SEQBUSY(value) (ADC_SEQSTATUS_SEQBUSY_Msk & (_UINT8_(value) << ADC_SEQSTATUS_SEQBUSY_Pos)) /* Assigment of value for SEQBUSY in the ADC_SEQSTATUS register */ +#define ADC_SEQSTATUS_Msk _UINT8_(0x9F) /* (ADC_SEQSTATUS) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _UINT16_(0x1C) /* (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_Msk _UINT16_(0x1F1F) /* (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#define ADC_CTRLC_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLC) Control C Reset Value */ + +#define ADC_CTRLC_DIFFMODE_Pos _UINT16_(0) /* (ADC_CTRLC) Differential Mode Position */ +#define ADC_CTRLC_DIFFMODE_Msk (_UINT16_(0x1) << ADC_CTRLC_DIFFMODE_Pos) /* (ADC_CTRLC) Differential Mode Mask */ +#define ADC_CTRLC_DIFFMODE(value) (ADC_CTRLC_DIFFMODE_Msk & (_UINT16_(value) << ADC_CTRLC_DIFFMODE_Pos)) /* Assigment of value for DIFFMODE in the ADC_CTRLC register */ +#define ADC_CTRLC_LEFTADJ_Pos _UINT16_(1) /* (ADC_CTRLC) Left-Adjusted Result Position */ +#define ADC_CTRLC_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLC_LEFTADJ_Pos) /* (ADC_CTRLC) Left-Adjusted Result Mask */ +#define ADC_CTRLC_LEFTADJ(value) (ADC_CTRLC_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLC_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the ADC_CTRLC register */ +#define ADC_CTRLC_FREERUN_Pos _UINT16_(2) /* (ADC_CTRLC) Free Running Mode Position */ +#define ADC_CTRLC_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLC_FREERUN_Pos) /* (ADC_CTRLC) Free Running Mode Mask */ +#define ADC_CTRLC_FREERUN(value) (ADC_CTRLC_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLC_FREERUN_Pos)) /* Assigment of value for FREERUN in the ADC_CTRLC register */ +#define ADC_CTRLC_CORREN_Pos _UINT16_(3) /* (ADC_CTRLC) Digital Correction Logic Enable Position */ +#define ADC_CTRLC_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLC_CORREN_Pos) /* (ADC_CTRLC) Digital Correction Logic Enable Mask */ +#define ADC_CTRLC_CORREN(value) (ADC_CTRLC_CORREN_Msk & (_UINT16_(value) << ADC_CTRLC_CORREN_Pos)) /* Assigment of value for CORREN in the ADC_CTRLC register */ +#define ADC_CTRLC_RESSEL_Pos _UINT16_(4) /* (ADC_CTRLC) Conversion Result Resolution Position */ +#define ADC_CTRLC_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) Conversion Result Resolution Mask */ +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLC_RESSEL_Pos)) /* Assigment of value for RESSEL in the ADC_CTRLC register */ +#define ADC_CTRLC_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLC) 12-bit */ +#define ADC_CTRLC_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLC) 16-bit averaging mode */ +#define ADC_CTRLC_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLC) 10-bit */ +#define ADC_CTRLC_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLC) 8-bit */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 12-bit Position */ +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 16-bit averaging mode Position */ +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 10-bit Position */ +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) /* (ADC_CTRLC) 8-bit Position */ +#define ADC_CTRLC_R2R_Pos _UINT16_(7) /* (ADC_CTRLC) Rail-to-Rail mode enable Position */ +#define ADC_CTRLC_R2R_Msk (_UINT16_(0x1) << ADC_CTRLC_R2R_Pos) /* (ADC_CTRLC) Rail-to-Rail mode enable Mask */ +#define ADC_CTRLC_R2R(value) (ADC_CTRLC_R2R_Msk & (_UINT16_(value) << ADC_CTRLC_R2R_Pos)) /* Assigment of value for R2R in the ADC_CTRLC register */ +#define ADC_CTRLC_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLC) Window Monitor Mode Position */ +#define ADC_CTRLC_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) Window Monitor Mode Mask */ +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLC_WINMODE_Pos)) /* Assigment of value for WINMODE in the ADC_CTRLC register */ +#define ADC_CTRLC_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) No window mode (default) Position */ +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT > WINLT Position */ +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) RESULT < WINUT Position */ +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) /* (ADC_CTRLC) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLC_DUALSEL_Pos _UINT16_(12) /* (ADC_CTRLC) Dual Mode Trigger Selection Position */ +#define ADC_CTRLC_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLC_DUALSEL_Pos)) /* Assigment of value for DUALSEL in the ADC_CTRLC register */ +#define ADC_CTRLC_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) /* (ADC_CTRLC) START event or software trigger will alternately start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLC_Msk _UINT16_(0x37BF) /* (ADC_CTRLC) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assigment of value for SAMPLENUM in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assigment of value for ADJRES in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assigment of value for SAMPLEN in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assigment of value for OFFCOMP in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_WINLT register */ +#define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_WINUT register */ +#define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_GAINCORR register */ +#define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_OFFSETCORR register */ +#define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assigment of value for FLUSH in the ADC_SWTRIG register */ +#define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assigment of value for START in the ADC_SWTRIG register */ +#define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the ADC_DBGCTRL register */ +#define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) ( R/ 16) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _UINT16_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _UINT16_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_ENABLE_Pos _UINT16_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT16_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT16_(2) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_CTRLC_Pos _UINT16_(3) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLC_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) /* (ADC_SYNCBUSY) CTRLC Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLC(value) (ADC_SYNCBUSY_CTRLC_Msk & (_UINT16_(value) << ADC_SYNCBUSY_CTRLC_Pos)) /* Assigment of value for CTRLC in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_AVGCTRL_Pos _UINT16_(4) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) AVGCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT16_(5) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINLT_Pos _UINT16_(6) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) WINLT Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINUT_Pos _UINT16_(7) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) WINUT Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT16_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_GAINCORR_Pos _UINT16_(8) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) GAINCORR Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT16_(9) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT16_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SWTRIG_Pos _UINT16_(10) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_UINT16_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) SWTRG Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT16_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assigment of value for SWTRIG in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_Msk _UINT16_(0x07FF) /* (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x24) ( R/ 16) Result -------- */ +#define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Reset Value */ + +#define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Value Position */ +#define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the ADC_RESULT register */ +#define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ + + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#define ADC_SEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_SEQCTRL) Sequence Control Reset Value */ + +#define ADC_SEQCTRL_SEQEN_Pos _UINT32_(0) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Position */ +#define ADC_SEQCTRL_SEQEN_Msk (_UINT32_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) /* (ADC_SEQCTRL) Enable Positive Input in the Sequence Mask */ +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & (_UINT32_(value) << ADC_SEQCTRL_SEQEN_Pos)) /* Assigment of value for SEQEN in the ADC_SEQCTRL register */ +#define ADC_SEQCTRL_Msk _UINT32_(0xFFFFFFFF) /* (ADC_SEQCTRL) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assigment of value for BIASCOMP in the ADC_CALIB register */ +#define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assigment of value for BIASREFBUF in the ADC_CALIB register */ +#define ADC_CALIB_Msk _UINT16_(0x0707) /* (ADC_CALIB) Register Mask */ + + +/** \brief ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ +#define ADC_CTRLB_REG_OFST _UINT32_(0x01) /* (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST _UINT32_(0x02) /* (ADC_REFCTRL) Reference Control Offset */ +#define ADC_EVCTRL_REG_OFST _UINT32_(0x03) /* (ADC_EVCTRL) Event Control Offset */ +#define ADC_INTENCLR_REG_OFST _UINT32_(0x04) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST _UINT32_(0x05) /* (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST _UINT32_(0x06) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_SEQSTATUS_REG_OFST _UINT32_(0x07) /* (ADC_SEQSTATUS) Sequence Status Offset */ +#define ADC_INPUTCTRL_REG_OFST _UINT32_(0x08) /* (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLC_REG_OFST _UINT32_(0x0A) /* (ADC_CTRLC) Control C Offset */ +#define ADC_AVGCTRL_REG_OFST _UINT32_(0x0C) /* (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0D) /* (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST _UINT32_(0x0E) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST _UINT32_(0x10) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST _UINT32_(0x12) /* (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST _UINT32_(0x14) /* (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST _UINT32_(0x18) /* (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_DBGCTRL_REG_OFST _UINT32_(0x1C) /* (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_RESULT_REG_OFST _UINT32_(0x24) /* (ADC_RESULT) Result Offset */ +#define ADC_SEQCTRL_REG_OFST _UINT32_(0x28) /* (ADC_SEQCTRL) Sequence Control Offset */ +#define ADC_CALIB_REG_OFST _UINT32_(0x2C) /* (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint8_t ADC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t ADC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t ADC_REFCTRL; /**< Offset: 0x02 (R/W 8) Reference Control */ + __IO uint8_t ADC_EVCTRL; /**< Offset: 0x03 (R/W 8) Event Control */ + __IO uint8_t ADC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_SEQSTATUS; /**< Offset: 0x07 (R/ 8) Sequence Status */ + __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x08 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLC; /**< Offset: 0x0A (R/W 16) Control C */ + __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0C (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0D (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /**< Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /**< Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /**< Offset: 0x12 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x14 (R/W 16) Offset Correction */ + __I uint8_t Reserved1[0x02]; + __IO uint8_t ADC_SWTRIG; /**< Offset: 0x18 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x03]; + __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x1C (R/W 8) Debug Control */ + __I uint8_t Reserved3[0x03]; + __I uint16_t ADC_SYNCBUSY; /**< Offset: 0x20 (R/ 16) Synchronization Busy */ + __I uint8_t Reserved4[0x02]; + __I uint16_t ADC_RESULT; /**< Offset: 0x24 (R/ 16) Result */ + __I uint8_t Reserved5[0x02]; + __IO uint32_t ADC_SEQCTRL; /**< Offset: 0x28 (R/W 32) Sequence Control */ + __IO uint16_t ADC_CALIB; /**< Offset: 0x2C (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_ADC_COMPONENT_H_ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/can.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/can.h new file mode 100644 index 00000000..b95505e8 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/can.h @@ -0,0 +1,2527 @@ +/* + * Component description for CAN + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_CAN_COMPONENT_H_ +#define _SAMC21_CAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CAN */ +/* ************************************************************************** */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ +#define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ +#define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ +#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ +#define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ +#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ +#define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ +#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ + + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ +#define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ +#define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ +#define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ +#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ +#define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ +#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ +#define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ +#define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ + + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ +#define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ +#define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ +#define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ +#define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ + + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ +#define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ +#define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ +#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ +#define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ +#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ +#define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ +#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ + + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ +#define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ +#define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ +#define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ +#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ +#define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ +#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ +#define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ + + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ +#define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ +#define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ +#define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ +#define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ + + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ +#define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ +#define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ +#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ +#define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ +#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ +#define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ +#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ + + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ +#define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ +#define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ +#define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ +#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ +#define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ +#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ +#define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ + + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ +#define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ +#define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ +#define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ +#define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ + + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ +#define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ +#define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ +#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ +#define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ +#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ +#define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ +#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ + + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ +#define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ +#define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ +#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ +#define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ +#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ +#define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ +#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assigment of value for EFC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ +#define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ + + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ +#define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ +#define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ +#define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ +#define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ + + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ +#define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ +#define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ +#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ +#define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ +#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ +#define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ +#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ + + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ +#define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assigment of value for TXTS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ +#define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ +#define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ +#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ +#define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ +#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ +#define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assigment of value for ET in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ +#define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ + + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ +#define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assigment of value for SFID2 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ +#define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assigment of value for SFID1 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assigment of value for SFEC in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ +#define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ +#define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assigment of value for SFT in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ +#define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ +#define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assigment of value for EFID1 in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assigment of value for EFEC in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ +#define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ +#define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assigment of value for EFID2 in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ +#define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assigment of value for EFT in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ + + +/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ +#define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ + +#define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ +#define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assigment of value for SUBSTEP in the CAN_CREL register */ +#define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ +#define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assigment of value for STEP in the CAN_CREL register */ +#define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ +#define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assigment of value for REL in the CAN_CREL register */ +#define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ + + +/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ +#define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ + +#define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ +#define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assigment of value for ETV in the CAN_ENDN register */ +#define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ + + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ + +#define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ +#define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assigment of value for QOS in the CAN_MRCFG register */ +#define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ +#define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ + + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ + +#define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ +#define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assigment of value for DSJW in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ +#define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assigment of value for DTSEG2 in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ +#define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assigment of value for DTSEG1 in the CAN_DBTP register */ +#define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ +#define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assigment of value for DBRP in the CAN_DBTP register */ +#define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ +#define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ +#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assigment of value for TDC in the CAN_DBTP register */ +#define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ + + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ + +#define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ +#define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ +#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assigment of value for LBCK in the CAN_TEST register */ +#define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ +#define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assigment of value for TX in the CAN_TEST register */ +#define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ +#define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ +#define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ +#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assigment of value for RX in the CAN_TEST register */ +#define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ + + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ + +#define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ +#define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assigment of value for WDC in the CAN_RWD register */ +#define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ +#define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assigment of value for WDV in the CAN_RWD register */ +#define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ + + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ + +#define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ +#define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ +#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assigment of value for INIT in the CAN_CCCR register */ +#define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ +#define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ +#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assigment of value for CCE in the CAN_CCCR register */ +#define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ +#define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ +#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assigment of value for ASM in the CAN_CCCR register */ +#define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ +#define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ +#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assigment of value for CSA in the CAN_CCCR register */ +#define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ +#define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ +#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assigment of value for CSR in the CAN_CCCR register */ +#define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ +#define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ +#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assigment of value for MON in the CAN_CCCR register */ +#define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ +#define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ +#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assigment of value for DAR in the CAN_CCCR register */ +#define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ +#define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ +#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assigment of value for TEST in the CAN_CCCR register */ +#define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ +#define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ +#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assigment of value for FDOE in the CAN_CCCR register */ +#define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ +#define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ +#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assigment of value for BRSE in the CAN_CCCR register */ +#define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ +#define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ +#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assigment of value for PXHD in the CAN_CCCR register */ +#define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ +#define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ +#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assigment of value for EFBI in the CAN_CCCR register */ +#define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ +#define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ +#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assigment of value for TXP in the CAN_CCCR register */ +#define CAN_CCCR_NISO_Pos _UINT32_(15) /* (CAN_CCCR) Non ISO Operation Position */ +#define CAN_CCCR_NISO_Msk (_UINT32_(0x1) << CAN_CCCR_NISO_Pos) /* (CAN_CCCR) Non ISO Operation Mask */ +#define CAN_CCCR_NISO(value) (CAN_CCCR_NISO_Msk & (_UINT32_(value) << CAN_CCCR_NISO_Pos)) /* Assigment of value for NISO in the CAN_CCCR register */ +#define CAN_CCCR_Msk _UINT32_(0x0000F3FF) /* (CAN_CCCR) Register Mask */ + + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ + +#define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ +#define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assigment of value for NTSEG2 in the CAN_NBTP register */ +#define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ +#define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assigment of value for NTSEG1 in the CAN_NBTP register */ +#define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ +#define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assigment of value for NBRP in the CAN_NBTP register */ +#define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ +#define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assigment of value for NSJW in the CAN_NBTP register */ +#define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ + + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ + +#define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ +#define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assigment of value for TSS in the CAN_TSCC register */ +#define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _UINT32_(0x2) /* (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) External timestamp counter value used Position */ +#define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ +#define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assigment of value for TCP in the CAN_TSCC register */ +#define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ + + +/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ +#define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ + +#define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ +#define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assigment of value for TSC in the CAN_TSCV register */ +#define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ + + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ + +#define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ +#define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ +#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assigment of value for ETOC in the CAN_TOCC register */ +#define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ +#define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assigment of value for TOS in the CAN_TOCC register */ +#define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ +#define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ +#define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assigment of value for TOP in the CAN_TOCC register */ +#define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ + + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ + +#define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ +#define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assigment of value for TOC in the CAN_TOCV register */ +#define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ + + +/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ +#define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ + +#define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ +#define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assigment of value for TEC in the CAN_ECR register */ +#define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ +#define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assigment of value for REC in the CAN_ECR register */ +#define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ +#define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ +#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assigment of value for RP in the CAN_ECR register */ +#define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ +#define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assigment of value for CEL in the CAN_ECR register */ +#define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ + + +/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ +#define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ + +#define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ +#define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assigment of value for LEC in the CAN_PSR register */ +#define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ +#define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assigment of value for ACT in the CAN_PSR register */ +#define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ +#define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ +#define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ +#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assigment of value for EP in the CAN_PSR register */ +#define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ +#define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ +#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assigment of value for EW in the CAN_PSR register */ +#define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ +#define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ +#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assigment of value for BO in the CAN_PSR register */ +#define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ +#define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assigment of value for DLEC in the CAN_PSR register */ +#define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ +#define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ +#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assigment of value for RESI in the CAN_PSR register */ +#define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ +#define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ +#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assigment of value for RBRS in the CAN_PSR register */ +#define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ +#define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ +#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assigment of value for RFDF in the CAN_PSR register */ +#define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ +#define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ +#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assigment of value for PXE in the CAN_PSR register */ +#define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ +#define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assigment of value for TDCV in the CAN_PSR register */ +#define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ + + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ + +#define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ +#define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assigment of value for TDCF in the CAN_TDCR register */ +#define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assigment of value for TDCO in the CAN_TDCR register */ +#define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ + + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ + +#define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ +#define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ +#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assigment of value for RF0N in the CAN_IR register */ +#define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ +#define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ +#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assigment of value for RF0W in the CAN_IR register */ +#define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ +#define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ +#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assigment of value for RF0F in the CAN_IR register */ +#define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ +#define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ +#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_IR register */ +#define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ +#define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ +#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assigment of value for RF1N in the CAN_IR register */ +#define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ +#define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ +#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assigment of value for RF1W in the CAN_IR register */ +#define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ +#define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ +#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assigment of value for RF1F in the CAN_IR register */ +#define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ +#define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ +#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_IR register */ +#define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ +#define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ +#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assigment of value for HPM in the CAN_IR register */ +#define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ +#define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ +#define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assigment of value for TC in the CAN_IR register */ +#define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ +#define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ +#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assigment of value for TCF in the CAN_IR register */ +#define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ +#define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ +#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assigment of value for TFE in the CAN_IR register */ +#define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ +#define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ +#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assigment of value for TEFN in the CAN_IR register */ +#define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ +#define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assigment of value for TEFW in the CAN_IR register */ +#define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ +#define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ +#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assigment of value for TEFF in the CAN_IR register */ +#define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ +#define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ +#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_IR register */ +#define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ +#define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ +#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assigment of value for TSW in the CAN_IR register */ +#define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ +#define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ +#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assigment of value for MRAF in the CAN_IR register */ +#define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ +#define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ +#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assigment of value for TOO in the CAN_IR register */ +#define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ +#define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ +#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assigment of value for DRX in the CAN_IR register */ +#define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ +#define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ +#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assigment of value for BEC in the CAN_IR register */ +#define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ +#define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ +#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assigment of value for BEU in the CAN_IR register */ +#define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ +#define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ +#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assigment of value for ELO in the CAN_IR register */ +#define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ +#define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ +#define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assigment of value for EP in the CAN_IR register */ +#define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ +#define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ +#define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assigment of value for EW in the CAN_IR register */ +#define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ +#define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ +#define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assigment of value for BO in the CAN_IR register */ +#define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ +#define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ +#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assigment of value for WDI in the CAN_IR register */ +#define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ +#define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ +#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assigment of value for PEA in the CAN_IR register */ +#define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ +#define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ +#define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assigment of value for PED in the CAN_IR register */ +#define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ +#define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ +#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assigment of value for ARA in the CAN_IR register */ +#define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ + + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ + +#define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ +#define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ +#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assigment of value for RF0NE in the CAN_IE register */ +#define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assigment of value for RF0WE in the CAN_IE register */ +#define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ +#define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ +#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assigment of value for RF0FE in the CAN_IE register */ +#define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assigment of value for RF0LE in the CAN_IE register */ +#define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ +#define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ +#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assigment of value for RF1NE in the CAN_IE register */ +#define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assigment of value for RF1WE in the CAN_IE register */ +#define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ +#define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ +#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assigment of value for RF1FE in the CAN_IE register */ +#define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assigment of value for RF1LE in the CAN_IE register */ +#define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ +#define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ +#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assigment of value for HPME in the CAN_IE register */ +#define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ +#define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ +#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assigment of value for TCE in the CAN_IE register */ +#define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assigment of value for TCFE in the CAN_IE register */ +#define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assigment of value for TFEE in the CAN_IE register */ +#define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assigment of value for TEFNE in the CAN_IE register */ +#define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assigment of value for TEFWE in the CAN_IE register */ +#define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assigment of value for TEFFE in the CAN_IE register */ +#define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ +#define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ +#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assigment of value for TEFLE in the CAN_IE register */ +#define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assigment of value for TSWE in the CAN_IE register */ +#define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assigment of value for MRAFE in the CAN_IE register */ +#define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ +#define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assigment of value for TOOE in the CAN_IE register */ +#define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ +#define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ +#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assigment of value for DRXE in the CAN_IE register */ +#define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ +#define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ +#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assigment of value for BECE in the CAN_IE register */ +#define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ +#define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ +#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assigment of value for BEUE in the CAN_IE register */ +#define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assigment of value for ELOE in the CAN_IE register */ +#define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ +#define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ +#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assigment of value for EPE in the CAN_IE register */ +#define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ +#define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ +#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assigment of value for EWE in the CAN_IE register */ +#define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ +#define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assigment of value for BOE in the CAN_IE register */ +#define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ +#define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ +#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assigment of value for WDIE in the CAN_IE register */ +#define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assigment of value for PEAE in the CAN_IE register */ +#define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ +#define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ +#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assigment of value for PEDE in the CAN_IE register */ +#define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ +#define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ +#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assigment of value for ARAE in the CAN_IE register */ +#define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ + + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ + +#define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ +#define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ +#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assigment of value for RF0NL in the CAN_ILS register */ +#define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assigment of value for RF0WL in the CAN_ILS register */ +#define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ +#define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ +#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assigment of value for RF0FL in the CAN_ILS register */ +#define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assigment of value for RF0LL in the CAN_ILS register */ +#define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ +#define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ +#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assigment of value for RF1NL in the CAN_ILS register */ +#define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assigment of value for RF1WL in the CAN_ILS register */ +#define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ +#define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ +#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assigment of value for RF1FL in the CAN_ILS register */ +#define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assigment of value for RF1LL in the CAN_ILS register */ +#define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ +#define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ +#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assigment of value for HPML in the CAN_ILS register */ +#define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ +#define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ +#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assigment of value for TCL in the CAN_ILS register */ +#define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assigment of value for TCFL in the CAN_ILS register */ +#define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assigment of value for TFEL in the CAN_ILS register */ +#define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assigment of value for TEFNL in the CAN_ILS register */ +#define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assigment of value for TEFWL in the CAN_ILS register */ +#define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assigment of value for TEFFL in the CAN_ILS register */ +#define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ +#define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ +#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assigment of value for TEFLL in the CAN_ILS register */ +#define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assigment of value for TSWL in the CAN_ILS register */ +#define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assigment of value for MRAFL in the CAN_ILS register */ +#define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ +#define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assigment of value for TOOL in the CAN_ILS register */ +#define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ +#define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ +#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assigment of value for DRXL in the CAN_ILS register */ +#define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ +#define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ +#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assigment of value for BECL in the CAN_ILS register */ +#define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ +#define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ +#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assigment of value for BEUL in the CAN_ILS register */ +#define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assigment of value for ELOL in the CAN_ILS register */ +#define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ +#define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ +#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assigment of value for EPL in the CAN_ILS register */ +#define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ +#define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ +#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assigment of value for EWL in the CAN_ILS register */ +#define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ +#define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assigment of value for BOL in the CAN_ILS register */ +#define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ +#define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ +#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assigment of value for WDIL in the CAN_ILS register */ +#define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assigment of value for PEAL in the CAN_ILS register */ +#define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ +#define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ +#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assigment of value for PEDL in the CAN_ILS register */ +#define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ +#define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ +#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assigment of value for ARAL in the CAN_ILS register */ +#define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ + + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ + +#define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ +#define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ +#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assigment of value for EINT0 in the CAN_ILE register */ +#define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ +#define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ +#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assigment of value for EINT1 in the CAN_ILE register */ +#define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ + +#define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ +#define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ +#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ + +#define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ +#define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ +#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assigment of value for RRFE in the CAN_GFC register */ +#define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ +#define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ +#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assigment of value for RRFS in the CAN_GFC register */ +#define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ +#define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assigment of value for ANFE in the CAN_GFC register */ +#define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ +#define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assigment of value for ANFS in the CAN_GFC register */ +#define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ + + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ + +#define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ +#define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assigment of value for FLSSA in the CAN_SIDFC register */ +#define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ +#define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assigment of value for LSS in the CAN_SIDFC register */ +#define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ + + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ + +#define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ +#define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assigment of value for FLESA in the CAN_XIDFC register */ +#define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ +#define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assigment of value for LSE in the CAN_XIDFC register */ +#define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ + + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ + +#define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ +#define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assigment of value for EIDM in the CAN_XIDAM register */ +#define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ + + +/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ +#define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ + +#define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ +#define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assigment of value for BIDX in the CAN_HPMS register */ +#define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ +#define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assigment of value for MSI in the CAN_HPMS register */ +#define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ +#define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ +#define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_HPMS register */ +#define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ +#define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ +#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assigment of value for FLST in the CAN_HPMS register */ +#define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ + + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ + +#define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ +#define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ +#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assigment of value for ND0 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ +#define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ +#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assigment of value for ND1 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ +#define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ +#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assigment of value for ND2 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ +#define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ +#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assigment of value for ND3 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ +#define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ +#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assigment of value for ND4 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ +#define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ +#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assigment of value for ND5 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ +#define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ +#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assigment of value for ND6 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ +#define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ +#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assigment of value for ND7 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ +#define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ +#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assigment of value for ND8 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ +#define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ +#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assigment of value for ND9 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ +#define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ +#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assigment of value for ND10 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ +#define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ +#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assigment of value for ND11 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ +#define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ +#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assigment of value for ND12 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ +#define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ +#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assigment of value for ND13 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ +#define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ +#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assigment of value for ND14 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ +#define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ +#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assigment of value for ND15 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ +#define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ +#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assigment of value for ND16 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ +#define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ +#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assigment of value for ND17 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ +#define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ +#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assigment of value for ND18 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ +#define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ +#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assigment of value for ND19 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ +#define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ +#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assigment of value for ND20 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ +#define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ +#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assigment of value for ND21 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ +#define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ +#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assigment of value for ND22 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ +#define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ +#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assigment of value for ND23 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ +#define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ +#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assigment of value for ND24 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ +#define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ +#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assigment of value for ND25 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ +#define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ +#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assigment of value for ND26 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ +#define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ +#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assigment of value for ND27 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ +#define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ +#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assigment of value for ND28 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ +#define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ +#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assigment of value for ND29 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ +#define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ +#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assigment of value for ND30 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ +#define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ +#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assigment of value for ND31 in the CAN_NDAT1 register */ +#define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ + +#define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ +#define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ +#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ + +#define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ +#define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ +#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assigment of value for ND32 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ +#define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ +#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assigment of value for ND33 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ +#define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ +#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assigment of value for ND34 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ +#define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ +#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assigment of value for ND35 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ +#define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ +#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assigment of value for ND36 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ +#define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ +#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assigment of value for ND37 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ +#define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ +#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assigment of value for ND38 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ +#define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ +#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assigment of value for ND39 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ +#define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ +#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assigment of value for ND40 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ +#define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ +#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assigment of value for ND41 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ +#define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ +#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assigment of value for ND42 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ +#define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ +#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assigment of value for ND43 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ +#define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ +#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assigment of value for ND44 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ +#define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ +#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assigment of value for ND45 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ +#define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ +#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assigment of value for ND46 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ +#define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ +#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assigment of value for ND47 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ +#define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ +#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assigment of value for ND48 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ +#define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ +#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assigment of value for ND49 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ +#define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ +#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assigment of value for ND50 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ +#define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ +#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assigment of value for ND51 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ +#define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ +#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assigment of value for ND52 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ +#define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ +#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assigment of value for ND53 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ +#define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ +#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assigment of value for ND54 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ +#define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ +#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assigment of value for ND55 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ +#define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ +#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assigment of value for ND56 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ +#define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ +#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assigment of value for ND57 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ +#define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ +#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assigment of value for ND58 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ +#define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ +#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assigment of value for ND59 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ +#define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ +#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assigment of value for ND60 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ +#define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ +#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assigment of value for ND61 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ +#define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ +#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assigment of value for ND62 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ +#define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ +#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assigment of value for ND63 in the CAN_NDAT2 register */ +#define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ + +#define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ +#define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ +#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ + +#define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ +#define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assigment of value for F0SA in the CAN_RXF0C register */ +#define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ +#define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assigment of value for F0S in the CAN_RXF0C register */ +#define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ +#define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assigment of value for F0WM in the CAN_RXF0C register */ +#define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ +#define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assigment of value for F0OM in the CAN_RXF0C register */ +#define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ + + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ +#define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ + +#define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ +#define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assigment of value for F0FL in the CAN_RXF0S register */ +#define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ +#define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assigment of value for F0GI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ +#define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assigment of value for F0PI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ +#define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ +#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assigment of value for F0F in the CAN_RXF0S register */ +#define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ +#define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ +#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_RXF0S register */ +#define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ + + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ + +#define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ +#define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assigment of value for F0AI in the CAN_RXF0A register */ +#define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ + + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ + +#define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ +#define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assigment of value for RBSA in the CAN_RXBC register */ +#define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ + + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ + +#define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ +#define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assigment of value for F1SA in the CAN_RXF1C register */ +#define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ +#define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assigment of value for F1S in the CAN_RXF1C register */ +#define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ +#define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assigment of value for F1WM in the CAN_RXF1C register */ +#define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ +#define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assigment of value for F1OM in the CAN_RXF1C register */ +#define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ + + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ +#define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ + +#define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ +#define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assigment of value for F1FL in the CAN_RXF1S register */ +#define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ +#define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assigment of value for F1GI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ +#define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assigment of value for F1PI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ +#define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ +#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assigment of value for F1F in the CAN_RXF1S register */ +#define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ +#define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ +#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ +#define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assigment of value for DMS in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ +#define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ + + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ + +#define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ +#define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assigment of value for F1AI in the CAN_RXF1A register */ +#define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ + + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ + +#define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ +#define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assigment of value for F0DS in the CAN_RXESC register */ +#define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ +#define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assigment of value for F1DS in the CAN_RXESC register */ +#define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ +#define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assigment of value for RBDS in the CAN_RXESC register */ +#define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ + + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ + +#define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ +#define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assigment of value for TBSA in the CAN_TXBC register */ +#define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assigment of value for NDTB in the CAN_TXBC register */ +#define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ +#define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assigment of value for TFQS in the CAN_TXBC register */ +#define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ +#define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assigment of value for TFQM in the CAN_TXBC register */ +#define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ + + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ +#define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ + +#define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ +#define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assigment of value for TFFL in the CAN_TXFQS register */ +#define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ +#define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assigment of value for TFGI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assigment of value for TFQPI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ +#define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assigment of value for TFQF in the CAN_TXFQS register */ +#define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ + + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ + +#define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ +#define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assigment of value for TBDS in the CAN_TXESC register */ +#define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ +#define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ + + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ +#define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ + +#define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ +#define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ +#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assigment of value for TRP0 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ +#define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ +#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assigment of value for TRP1 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ +#define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ +#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assigment of value for TRP2 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ +#define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ +#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assigment of value for TRP3 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ +#define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ +#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assigment of value for TRP4 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ +#define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ +#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assigment of value for TRP5 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ +#define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ +#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assigment of value for TRP6 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ +#define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ +#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assigment of value for TRP7 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ +#define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ +#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assigment of value for TRP8 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ +#define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ +#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assigment of value for TRP9 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ +#define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ +#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assigment of value for TRP10 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ +#define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ +#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assigment of value for TRP11 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ +#define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ +#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assigment of value for TRP12 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ +#define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ +#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assigment of value for TRP13 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ +#define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ +#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assigment of value for TRP14 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ +#define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ +#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assigment of value for TRP15 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ +#define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ +#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assigment of value for TRP16 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ +#define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ +#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assigment of value for TRP17 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ +#define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ +#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assigment of value for TRP18 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ +#define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ +#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assigment of value for TRP19 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ +#define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ +#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assigment of value for TRP20 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ +#define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ +#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assigment of value for TRP21 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ +#define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ +#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assigment of value for TRP22 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ +#define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ +#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assigment of value for TRP23 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ +#define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ +#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assigment of value for TRP24 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ +#define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ +#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assigment of value for TRP25 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ +#define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ +#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assigment of value for TRP26 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ +#define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ +#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assigment of value for TRP27 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ +#define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ +#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assigment of value for TRP28 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ +#define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ +#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assigment of value for TRP29 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ +#define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ +#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assigment of value for TRP30 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ +#define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ +#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assigment of value for TRP31 in the CAN_TXBRP register */ +#define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ + +#define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ +#define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ +#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ + +#define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ +#define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ +#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assigment of value for AR0 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ +#define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ +#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assigment of value for AR1 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ +#define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ +#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assigment of value for AR2 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ +#define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ +#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assigment of value for AR3 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ +#define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ +#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assigment of value for AR4 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ +#define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ +#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assigment of value for AR5 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ +#define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ +#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assigment of value for AR6 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ +#define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ +#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assigment of value for AR7 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ +#define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ +#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assigment of value for AR8 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ +#define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ +#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assigment of value for AR9 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ +#define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ +#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assigment of value for AR10 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ +#define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ +#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assigment of value for AR11 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ +#define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ +#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assigment of value for AR12 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ +#define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ +#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assigment of value for AR13 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ +#define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ +#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assigment of value for AR14 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ +#define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ +#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assigment of value for AR15 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ +#define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ +#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assigment of value for AR16 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ +#define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ +#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assigment of value for AR17 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ +#define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ +#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assigment of value for AR18 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ +#define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ +#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assigment of value for AR19 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ +#define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ +#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assigment of value for AR20 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ +#define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ +#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assigment of value for AR21 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ +#define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ +#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assigment of value for AR22 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ +#define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ +#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assigment of value for AR23 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ +#define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ +#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assigment of value for AR24 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ +#define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ +#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assigment of value for AR25 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ +#define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ +#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assigment of value for AR26 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ +#define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ +#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assigment of value for AR27 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ +#define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ +#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assigment of value for AR28 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ +#define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ +#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assigment of value for AR29 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ +#define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ +#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assigment of value for AR30 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ +#define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ +#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assigment of value for AR31 in the CAN_TXBAR register */ +#define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ + +#define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ +#define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ +#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ + +#define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ +#define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ +#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assigment of value for CR0 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ +#define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ +#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assigment of value for CR1 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ +#define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ +#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assigment of value for CR2 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ +#define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ +#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assigment of value for CR3 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ +#define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ +#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assigment of value for CR4 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ +#define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ +#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assigment of value for CR5 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ +#define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ +#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assigment of value for CR6 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ +#define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ +#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assigment of value for CR7 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ +#define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ +#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assigment of value for CR8 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ +#define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ +#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assigment of value for CR9 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ +#define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ +#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assigment of value for CR10 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ +#define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ +#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assigment of value for CR11 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ +#define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ +#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assigment of value for CR12 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ +#define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ +#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assigment of value for CR13 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ +#define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ +#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assigment of value for CR14 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ +#define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ +#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assigment of value for CR15 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ +#define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ +#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assigment of value for CR16 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ +#define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ +#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assigment of value for CR17 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ +#define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ +#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assigment of value for CR18 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ +#define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ +#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assigment of value for CR19 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ +#define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ +#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assigment of value for CR20 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ +#define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ +#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assigment of value for CR21 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ +#define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ +#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assigment of value for CR22 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ +#define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ +#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assigment of value for CR23 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ +#define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ +#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assigment of value for CR24 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ +#define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ +#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assigment of value for CR25 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ +#define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ +#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assigment of value for CR26 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ +#define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ +#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assigment of value for CR27 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ +#define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ +#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assigment of value for CR28 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ +#define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ +#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assigment of value for CR29 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ +#define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ +#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assigment of value for CR30 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ +#define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ +#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assigment of value for CR31 in the CAN_TXBCR register */ +#define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ + +#define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ +#define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ +#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ +#define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ + +#define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ +#define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ +#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assigment of value for TO0 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ +#define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ +#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assigment of value for TO1 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ +#define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ +#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assigment of value for TO2 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ +#define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ +#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assigment of value for TO3 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ +#define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ +#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assigment of value for TO4 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ +#define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ +#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assigment of value for TO5 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ +#define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ +#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assigment of value for TO6 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ +#define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ +#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assigment of value for TO7 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ +#define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ +#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assigment of value for TO8 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ +#define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ +#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assigment of value for TO9 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ +#define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ +#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assigment of value for TO10 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ +#define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ +#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assigment of value for TO11 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ +#define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ +#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assigment of value for TO12 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ +#define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ +#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assigment of value for TO13 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ +#define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ +#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assigment of value for TO14 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ +#define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ +#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assigment of value for TO15 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ +#define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ +#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assigment of value for TO16 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ +#define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ +#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assigment of value for TO17 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ +#define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ +#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assigment of value for TO18 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ +#define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ +#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assigment of value for TO19 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ +#define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ +#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assigment of value for TO20 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ +#define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ +#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assigment of value for TO21 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ +#define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ +#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assigment of value for TO22 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ +#define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ +#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assigment of value for TO23 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ +#define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ +#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assigment of value for TO24 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ +#define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ +#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assigment of value for TO25 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ +#define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ +#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assigment of value for TO26 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ +#define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ +#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assigment of value for TO27 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ +#define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ +#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assigment of value for TO28 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ +#define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ +#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assigment of value for TO29 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ +#define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ +#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assigment of value for TO30 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ +#define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ +#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assigment of value for TO31 in the CAN_TXBTO register */ +#define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ + +#define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ +#define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ +#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ +#define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ + +#define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ +#define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ +#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assigment of value for CF0 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ +#define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ +#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assigment of value for CF1 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ +#define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ +#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assigment of value for CF2 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ +#define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ +#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assigment of value for CF3 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ +#define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ +#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assigment of value for CF4 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ +#define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ +#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assigment of value for CF5 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ +#define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ +#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assigment of value for CF6 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ +#define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ +#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assigment of value for CF7 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ +#define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ +#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assigment of value for CF8 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ +#define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ +#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assigment of value for CF9 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ +#define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ +#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assigment of value for CF10 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ +#define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ +#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assigment of value for CF11 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ +#define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ +#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assigment of value for CF12 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ +#define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ +#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assigment of value for CF13 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ +#define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ +#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assigment of value for CF14 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ +#define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ +#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assigment of value for CF15 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ +#define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ +#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assigment of value for CF16 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ +#define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ +#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assigment of value for CF17 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ +#define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ +#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assigment of value for CF18 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ +#define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ +#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assigment of value for CF19 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ +#define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ +#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assigment of value for CF20 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ +#define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ +#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assigment of value for CF21 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ +#define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ +#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assigment of value for CF22 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ +#define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ +#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assigment of value for CF23 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ +#define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ +#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assigment of value for CF24 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ +#define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ +#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assigment of value for CF25 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ +#define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ +#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assigment of value for CF26 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ +#define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ +#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assigment of value for CF27 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ +#define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ +#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assigment of value for CF28 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ +#define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ +#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assigment of value for CF29 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ +#define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ +#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assigment of value for CF30 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ +#define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ +#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assigment of value for CF31 in the CAN_TXBCF register */ +#define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ + +#define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ +#define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ +#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ + +#define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ +#define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ +#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assigment of value for TIE0 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ +#define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ +#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assigment of value for TIE1 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ +#define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ +#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assigment of value for TIE2 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ +#define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ +#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assigment of value for TIE3 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ +#define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ +#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assigment of value for TIE4 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ +#define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ +#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assigment of value for TIE5 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ +#define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ +#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assigment of value for TIE6 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ +#define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ +#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assigment of value for TIE7 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ +#define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ +#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assigment of value for TIE8 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ +#define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ +#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assigment of value for TIE9 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ +#define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ +#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assigment of value for TIE10 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ +#define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ +#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assigment of value for TIE11 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ +#define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ +#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assigment of value for TIE12 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ +#define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ +#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assigment of value for TIE13 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ +#define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ +#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assigment of value for TIE14 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ +#define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ +#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assigment of value for TIE15 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ +#define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ +#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assigment of value for TIE16 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ +#define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ +#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assigment of value for TIE17 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ +#define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ +#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assigment of value for TIE18 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ +#define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ +#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assigment of value for TIE19 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ +#define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ +#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assigment of value for TIE20 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ +#define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ +#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assigment of value for TIE21 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ +#define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ +#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assigment of value for TIE22 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ +#define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ +#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assigment of value for TIE23 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ +#define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ +#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assigment of value for TIE24 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ +#define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ +#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assigment of value for TIE25 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ +#define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ +#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assigment of value for TIE26 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ +#define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ +#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assigment of value for TIE27 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ +#define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ +#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assigment of value for TIE28 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ +#define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ +#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assigment of value for TIE29 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ +#define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ +#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assigment of value for TIE30 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ +#define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ +#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assigment of value for TIE31 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ + +#define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ +#define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ +#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ + +#define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ +#define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ +#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assigment of value for CFIE0 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ +#define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ +#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assigment of value for CFIE1 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ +#define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ +#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assigment of value for CFIE2 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ +#define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ +#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assigment of value for CFIE3 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ +#define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ +#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assigment of value for CFIE4 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ +#define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ +#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assigment of value for CFIE5 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ +#define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ +#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assigment of value for CFIE6 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ +#define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ +#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assigment of value for CFIE7 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ +#define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ +#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assigment of value for CFIE8 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ +#define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ +#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assigment of value for CFIE9 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ +#define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ +#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assigment of value for CFIE10 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ +#define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ +#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assigment of value for CFIE11 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ +#define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ +#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assigment of value for CFIE12 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ +#define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ +#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assigment of value for CFIE13 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ +#define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ +#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assigment of value for CFIE14 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ +#define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ +#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assigment of value for CFIE15 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ +#define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ +#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assigment of value for CFIE16 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ +#define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ +#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assigment of value for CFIE17 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ +#define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ +#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assigment of value for CFIE18 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ +#define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ +#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assigment of value for CFIE19 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ +#define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ +#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assigment of value for CFIE20 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ +#define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ +#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assigment of value for CFIE21 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ +#define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ +#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assigment of value for CFIE22 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ +#define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ +#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assigment of value for CFIE23 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ +#define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ +#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assigment of value for CFIE24 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ +#define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ +#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assigment of value for CFIE25 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ +#define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ +#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assigment of value for CFIE26 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ +#define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ +#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assigment of value for CFIE27 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ +#define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ +#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assigment of value for CFIE28 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ +#define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ +#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assigment of value for CFIE29 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ +#define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ +#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assigment of value for CFIE30 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ +#define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ +#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assigment of value for CFIE31 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ + +#define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ +#define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ +#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ + +#define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ +#define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assigment of value for EFSA in the CAN_TXEFC register */ +#define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ +#define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assigment of value for EFS in the CAN_TXEFC register */ +#define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ +#define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assigment of value for EFWM in the CAN_TXEFC register */ +#define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ + + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ +#define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ + +#define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ +#define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assigment of value for EFFL in the CAN_TXEFS register */ +#define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ +#define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assigment of value for EFGI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ +#define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assigment of value for EFPI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ +#define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ +#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assigment of value for EFF in the CAN_TXEFS register */ +#define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_TXEFS register */ +#define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ + + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ + +#define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assigment of value for EFAI in the CAN_TXEFA register */ +#define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ + + +/** \brief CAN register offsets definitions */ +#define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ +#define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ +#define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ +#define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ +#define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ +#define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ +#define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ +#define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ +#define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ +#define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ +#define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ +#define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ +#define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ +#define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ +#define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ +#define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ +#define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ +#define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ +#define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ +#define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ +#define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ +#define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ +#define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ +#define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ +#define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ +#define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ +#define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ +#define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ +#define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ +#define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ +#define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ +#define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ +#define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ +#define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ +#define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ +#define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ +#define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ +#define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ +#define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ +#define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ +#define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ +#define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ +#define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ +#define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ +#define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ +#define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ +#define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t CAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t CAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t CAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} can_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t CAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t CAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t CAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} can_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t CAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t CAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t CAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} can_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t CAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t CAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t CAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} can_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t CAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t CAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} can_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t CAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} can_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t CAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t CAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} can_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN register API structure */ +typedef struct +{ /* Control Area Network */ + __I uint32_t CAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release */ + __I uint32_t CAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian */ + __IO uint32_t CAN_MRCFG; /**< Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO uint32_t CAN_DBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO uint32_t CAN_TEST; /**< Offset: 0x10 (R/W 32) Test */ + __IO uint32_t CAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO uint32_t CAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control */ + __IO uint32_t CAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO uint32_t CAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I uint32_t CAN_TSCV; /**< Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO uint32_t CAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO uint32_t CAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value */ + __I uint8_t Reserved1[0x10]; + __I uint32_t CAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter */ + __I uint32_t CAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status */ + __IO uint32_t CAN_TDCR; /**< Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t CAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt */ + __IO uint32_t CAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO uint32_t CAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO uint32_t CAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t CAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO uint32_t CAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO uint32_t CAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t CAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I uint32_t CAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO uint32_t CAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 */ + __IO uint32_t CAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 */ + __IO uint32_t CAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I uint32_t CAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO uint32_t CAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO uint32_t CAN_RXBC; /**< Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO uint32_t CAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I uint32_t CAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO uint32_t CAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO uint32_t CAN_RXESC; /**< Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t CAN_TXBC; /**< Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I uint32_t CAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO uint32_t CAN_TXESC; /**< Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I uint32_t CAN_TXBRP; /**< Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO uint32_t CAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO uint32_t CAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I uint32_t CAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I uint32_t CAN_TXBCF; /**< Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO uint32_t CAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t CAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t CAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I uint32_t CAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO uint32_t CAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} can_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_CAN_COMPONENT_H_ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/ccl.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/ccl.h new file mode 100644 index 00000000..74bf2c33 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/ccl.h @@ -0,0 +1,217 @@ +/* + * Component description for CCL + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_CCL_COMPONENT_H_ +#define _SAMC21_CCL_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CCL_CTRL register */ +#define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_CTRL register */ +#define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the CCL_CTRL register */ +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assigment of value for SEQSEL in the CCL_SEQCTRL register */ +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assigment of value for FILTSEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assigment of value for EDGESEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assigment of value for INSEL0 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assigment of value for INSEL1 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assigment of value for INSEL2 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assigment of value for LUTEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assigment of value for LUTEO in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assigment of value for TRUTH in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ + + +/** \brief CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ +#define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ +#define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ +#define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ +#define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ +#define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_CCL_COMPONENT_H_ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/dac.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/dac.h new file mode 100644 index 00000000..49599db0 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/dac.h @@ -0,0 +1,216 @@ +/* + * Component description for DAC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_DAC_COMPONENT_H_ +#define _SAMC21_DAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_CTRLA register */ +#define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable Position */ +#define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_CTRLA register */ +#define DAC_CTRLA_RUNSTDBY_Pos _UINT8_(6) /* (DAC_CTRLA) Run in Standby Position */ +#define DAC_CTRLA_RUNSTDBY_Msk (_UINT8_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) /* (DAC_CTRLA) Run in Standby Mask */ +#define DAC_CTRLA_RUNSTDBY(value) (DAC_CTRLA_RUNSTDBY_Msk & (_UINT8_(value) << DAC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the DAC_CTRLA register */ +#define DAC_CTRLA_Msk _UINT8_(0x43) /* (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_EOEN_Pos _UINT8_(0) /* (DAC_CTRLB) External Output Enable Position */ +#define DAC_CTRLB_EOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_EOEN_Pos) /* (DAC_CTRLB) External Output Enable Mask */ +#define DAC_CTRLB_EOEN(value) (DAC_CTRLB_EOEN_Msk & (_UINT8_(value) << DAC_CTRLB_EOEN_Pos)) /* Assigment of value for EOEN in the DAC_CTRLB register */ +#define DAC_CTRLB_IOEN_Pos _UINT8_(1) /* (DAC_CTRLB) Internal Output Enable Position */ +#define DAC_CTRLB_IOEN_Msk (_UINT8_(0x1) << DAC_CTRLB_IOEN_Pos) /* (DAC_CTRLB) Internal Output Enable Mask */ +#define DAC_CTRLB_IOEN(value) (DAC_CTRLB_IOEN_Msk & (_UINT8_(value) << DAC_CTRLB_IOEN_Pos)) /* Assigment of value for IOEN in the DAC_CTRLB register */ +#define DAC_CTRLB_LEFTADJ_Pos _UINT8_(2) /* (DAC_CTRLB) Left Adjusted Data Position */ +#define DAC_CTRLB_LEFTADJ_Msk (_UINT8_(0x1) << DAC_CTRLB_LEFTADJ_Pos) /* (DAC_CTRLB) Left Adjusted Data Mask */ +#define DAC_CTRLB_LEFTADJ(value) (DAC_CTRLB_LEFTADJ_Msk & (_UINT8_(value) << DAC_CTRLB_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the DAC_CTRLB register */ +#define DAC_CTRLB_VPD_Pos _UINT8_(3) /* (DAC_CTRLB) Voltage Pump Disable Position */ +#define DAC_CTRLB_VPD_Msk (_UINT8_(0x1) << DAC_CTRLB_VPD_Pos) /* (DAC_CTRLB) Voltage Pump Disable Mask */ +#define DAC_CTRLB_VPD(value) (DAC_CTRLB_VPD_Msk & (_UINT8_(value) << DAC_CTRLB_VPD_Pos)) /* Assigment of value for VPD in the DAC_CTRLB register */ +#define DAC_CTRLB_DITHER_Pos _UINT8_(5) /* (DAC_CTRLB) Dither Enable Position */ +#define DAC_CTRLB_DITHER_Msk (_UINT8_(0x1) << DAC_CTRLB_DITHER_Pos) /* (DAC_CTRLB) Dither Enable Mask */ +#define DAC_CTRLB_DITHER(value) (DAC_CTRLB_DITHER_Msk & (_UINT8_(value) << DAC_CTRLB_DITHER_Pos)) /* Assigment of value for DITHER in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_Pos _UINT8_(6) /* (DAC_CTRLB) Reference Selection Position */ +#define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assigment of value for REFSEL in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_INT1V_Val _UINT8_(0x0) /* (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _UINT8_(0x1) /* (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal 1.0V reference Position */ +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) AVCC Position */ +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference Position */ +#define DAC_CTRLB_Msk _UINT8_(0xEF) /* (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input Position */ +#define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL) Start Conversion Event Input Mask */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) /* Assigment of value for STARTEI in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(1) /* (DAC_EVCTRL) Data Buffer Empty Event Output Position */ +#define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output Mask */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) /* Assigment of value for EMPTYEO in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI_Pos _UINT8_(2) /* (DAC_EVCTRL) Invert Event Input Position */ +#define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL) Invert Event Input Mask */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the DAC_EVCTRL register */ +#define DAC_EVCTRL_Msk _UINT8_(0x07) /* (DAC_EVCTRL) Register Mask */ + + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR) Underrun Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) /* Assigment of value for UNDERRUN in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY_Pos _UINT8_(1) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR) Data Buffer Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) /* Assigment of value for EMPTY in the DAC_INTENCLR register */ +#define DAC_INTENCLR_Msk _UINT8_(0x03) /* (DAC_INTENCLR) Register Mask */ + + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET) Underrun Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) /* Assigment of value for UNDERRUN in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY_Pos _UINT8_(1) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET) Data Buffer Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) /* Assigment of value for EMPTY in the DAC_INTENSET register */ +#define DAC_INTENSET_Msk _UINT8_(0x03) /* (DAC_INTENSET) Register Mask */ + + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG) Underrun Position */ +#define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG) Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) /* Assigment of value for UNDERRUN in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY_Pos _UINT8_(1) /* (DAC_INTFLAG) Data Buffer Empty Position */ +#define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG) Data Buffer Empty Mask */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) /* Assigment of value for EMPTY in the DAC_INTFLAG register */ +#define DAC_INTFLAG_Msk _UINT8_(0x03) /* (DAC_INTFLAG) Register Mask */ + + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS) Ready Position */ +#define DAC_STATUS_READY_Msk (_UINT8_(0x1) << DAC_STATUS_READY_Pos) /* (DAC_STATUS) Ready Mask */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) /* Assigment of value for READY in the DAC_STATUS register */ +#define DAC_STATUS_Msk _UINT8_(0x01) /* (DAC_STATUS) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */ +#define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) Data Reset Value */ + +#define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) Data value to be converted Position */ +#define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) Data value to be converted Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assigment of value for DATA in the DAC_DATA register */ +#define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assigment of value for DATABUF in the DAC_DATABUF register */ +#define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) Enable Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) Enable Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data Position */ +#define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY) Data Mask */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) /* Assigment of value for DATA in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data Buffer Position */ +#define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY) Data Buffer Mask */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) /* Assigment of value for DATABUF in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_Msk _UINT32_(0x0000000F) /* (DAC_SYNCBUSY) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the DAC_DBGCTRL register */ +#define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ + + +/** \brief DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ +#define DAC_DATA_REG_OFST _UINT32_(0x08) /* (DAC_DATA) Data Offset */ +#define DAC_DATABUF_REG_OFST _UINT32_(0x0C) /* (DAC_DATABUF) Data Buffer Offset */ +#define DAC_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DBGCTRL_REG_OFST _UINT32_(0x14) /* (DAC_DBGCTRL) Debug Control Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DAC register API structure */ +typedef struct +{ /* Digital Analog Converter */ + __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ + __O uint16_t DAC_DATA; /**< Offset: 0x08 ( /W 16) Data */ + __I uint8_t Reserved2[0x02]; + __O uint16_t DAC_DATABUF; /**< Offset: 0x0C ( /W 16) Data Buffer */ + __I uint8_t Reserved3[0x02]; + __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Busy */ + __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x14 (R/W 8) Debug Control */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_DAC_COMPONENT_H_ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/divas.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/divas.h new file mode 100644 index 00000000..84bf6983 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/divas.h @@ -0,0 +1,126 @@ +/* + * Component description for DIVAS + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_DIVAS_COMPONENT_H_ +#define _SAMC21_DIVAS_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DIVAS */ +/* ************************************************************************** */ + +/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */ +#define DIVAS_CTRLA_RESETVALUE _UINT8_(0x00) /* (DIVAS_CTRLA) Control Reset Value */ + +#define DIVAS_CTRLA_SIGNED_Pos _UINT8_(0) /* (DIVAS_CTRLA) Signed Position */ +#define DIVAS_CTRLA_SIGNED_Msk (_UINT8_(0x1) << DIVAS_CTRLA_SIGNED_Pos) /* (DIVAS_CTRLA) Signed Mask */ +#define DIVAS_CTRLA_SIGNED(value) (DIVAS_CTRLA_SIGNED_Msk & (_UINT8_(value) << DIVAS_CTRLA_SIGNED_Pos)) /* Assigment of value for SIGNED in the DIVAS_CTRLA register */ +#define DIVAS_CTRLA_DLZ_Pos _UINT8_(1) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Position */ +#define DIVAS_CTRLA_DLZ_Msk (_UINT8_(0x1) << DIVAS_CTRLA_DLZ_Pos) /* (DIVAS_CTRLA) Disable Leading Zero Optimization Mask */ +#define DIVAS_CTRLA_DLZ(value) (DIVAS_CTRLA_DLZ_Msk & (_UINT8_(value) << DIVAS_CTRLA_DLZ_Pos)) /* Assigment of value for DLZ in the DIVAS_CTRLA register */ +#define DIVAS_CTRLA_Msk _UINT8_(0x03) /* (DIVAS_CTRLA) Register Mask */ + + +/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */ +#define DIVAS_STATUS_RESETVALUE _UINT8_(0x00) /* (DIVAS_STATUS) Status Reset Value */ + +#define DIVAS_STATUS_BUSY_Pos _UINT8_(0) /* (DIVAS_STATUS) DIVAS Accelerator Busy Position */ +#define DIVAS_STATUS_BUSY_Msk (_UINT8_(0x1) << DIVAS_STATUS_BUSY_Pos) /* (DIVAS_STATUS) DIVAS Accelerator Busy Mask */ +#define DIVAS_STATUS_BUSY(value) (DIVAS_STATUS_BUSY_Msk & (_UINT8_(value) << DIVAS_STATUS_BUSY_Pos)) /* Assigment of value for BUSY in the DIVAS_STATUS register */ +#define DIVAS_STATUS_DBZ_Pos _UINT8_(1) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Position */ +#define DIVAS_STATUS_DBZ_Msk (_UINT8_(0x1) << DIVAS_STATUS_DBZ_Pos) /* (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero Mask */ +#define DIVAS_STATUS_DBZ(value) (DIVAS_STATUS_DBZ_Msk & (_UINT8_(value) << DIVAS_STATUS_DBZ_Pos)) /* Assigment of value for DBZ in the DIVAS_STATUS register */ +#define DIVAS_STATUS_Msk _UINT8_(0x03) /* (DIVAS_STATUS) Register Mask */ + + +/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */ +#define DIVAS_DIVIDEND_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVIDEND) Dividend Reset Value */ + +#define DIVAS_DIVIDEND_DIVIDEND_Pos _UINT32_(0) /* (DIVAS_DIVIDEND) DIVIDEND Position */ +#define DIVAS_DIVIDEND_DIVIDEND_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos) /* (DIVAS_DIVIDEND) DIVIDEND Mask */ +#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & (_UINT32_(value) << DIVAS_DIVIDEND_DIVIDEND_Pos)) /* Assigment of value for DIVIDEND in the DIVAS_DIVIDEND register */ +#define DIVAS_DIVIDEND_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVIDEND) Register Mask */ + + +/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */ +#define DIVAS_DIVISOR_RESETVALUE _UINT32_(0x00) /* (DIVAS_DIVISOR) Divisor Reset Value */ + +#define DIVAS_DIVISOR_DIVISOR_Pos _UINT32_(0) /* (DIVAS_DIVISOR) DIVISOR Position */ +#define DIVAS_DIVISOR_DIVISOR_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos) /* (DIVAS_DIVISOR) DIVISOR Mask */ +#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & (_UINT32_(value) << DIVAS_DIVISOR_DIVISOR_Pos)) /* Assigment of value for DIVISOR in the DIVAS_DIVISOR register */ +#define DIVAS_DIVISOR_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_DIVISOR) Register Mask */ + + +/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) ( R/ 32) Result -------- */ +#define DIVAS_RESULT_RESETVALUE _UINT32_(0x00) /* (DIVAS_RESULT) Result Reset Value */ + +#define DIVAS_RESULT_RESULT_Pos _UINT32_(0) /* (DIVAS_RESULT) RESULT Position */ +#define DIVAS_RESULT_RESULT_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos) /* (DIVAS_RESULT) RESULT Mask */ +#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & (_UINT32_(value) << DIVAS_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the DIVAS_RESULT register */ +#define DIVAS_RESULT_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_RESULT) Register Mask */ + + +/* -------- DIVAS_REM : (DIVAS Offset: 0x14) ( R/ 32) Remainder -------- */ +#define DIVAS_REM_RESETVALUE _UINT32_(0x00) /* (DIVAS_REM) Remainder Reset Value */ + +#define DIVAS_REM_REM_Pos _UINT32_(0) /* (DIVAS_REM) REM Position */ +#define DIVAS_REM_REM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_REM_REM_Pos) /* (DIVAS_REM) REM Mask */ +#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & (_UINT32_(value) << DIVAS_REM_REM_Pos)) /* Assigment of value for REM in the DIVAS_REM register */ +#define DIVAS_REM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_REM) Register Mask */ + + +/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */ +#define DIVAS_SQRNUM_RESETVALUE _UINT32_(0x00) /* (DIVAS_SQRNUM) Square Root Input Reset Value */ + +#define DIVAS_SQRNUM_SQRNUM_Pos _UINT32_(0) /* (DIVAS_SQRNUM) Square Root Input Position */ +#define DIVAS_SQRNUM_SQRNUM_Msk (_UINT32_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos) /* (DIVAS_SQRNUM) Square Root Input Mask */ +#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & (_UINT32_(value) << DIVAS_SQRNUM_SQRNUM_Pos)) /* Assigment of value for SQRNUM in the DIVAS_SQRNUM register */ +#define DIVAS_SQRNUM_Msk _UINT32_(0xFFFFFFFF) /* (DIVAS_SQRNUM) Register Mask */ + + +/** \brief DIVAS register offsets definitions */ +#define DIVAS_CTRLA_REG_OFST _UINT32_(0x00) /* (DIVAS_CTRLA) Control Offset */ +#define DIVAS_STATUS_REG_OFST _UINT32_(0x04) /* (DIVAS_STATUS) Status Offset */ +#define DIVAS_DIVIDEND_REG_OFST _UINT32_(0x08) /* (DIVAS_DIVIDEND) Dividend Offset */ +#define DIVAS_DIVISOR_REG_OFST _UINT32_(0x0C) /* (DIVAS_DIVISOR) Divisor Offset */ +#define DIVAS_RESULT_REG_OFST _UINT32_(0x10) /* (DIVAS_RESULT) Result Offset */ +#define DIVAS_REM_REG_OFST _UINT32_(0x14) /* (DIVAS_REM) Remainder Offset */ +#define DIVAS_SQRNUM_REG_OFST _UINT32_(0x18) /* (DIVAS_SQRNUM) Square Root Input Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DIVAS register API structure */ +typedef struct +{ /* Divide and Square Root Accelerator */ + __IO uint8_t DIVAS_CTRLA; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t DIVAS_STATUS; /**< Offset: 0x04 (R/W 8) Status */ + __I uint8_t Reserved2[0x03]; + __IO uint32_t DIVAS_DIVIDEND; /**< Offset: 0x08 (R/W 32) Dividend */ + __IO uint32_t DIVAS_DIVISOR; /**< Offset: 0x0C (R/W 32) Divisor */ + __I uint32_t DIVAS_RESULT; /**< Offset: 0x10 (R/ 32) Result */ + __I uint32_t DIVAS_REM; /**< Offset: 0x14 (R/ 32) Remainder */ + __IO uint32_t DIVAS_SQRNUM; /**< Offset: 0x18 (R/W 32) Square Root Input */ +} divas_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAMC21_DIVAS_COMPONENT_H_ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/dmac.h b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/dmac.h new file mode 100644 index 00000000..924dc654 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/ATSAMC21E18A_DFP/component/dmac.h @@ -0,0 +1,882 @@ +/* + * Component description for DMAC + * + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2022-03-14T06:33:44Z */ +#ifndef _SAMC21_DMAC_COMPONENT_H_ +#define _SAMC21_DMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _UINT16_(0x00) /* (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _UINT16_(0) /* (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos) /* (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assigment of value for VALID in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_Pos _UINT16_(1) /* (DMAC_BTCTRL) Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assigment of value for EVOSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when block transfer complete Position */ +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event strobe when beat transfer complete Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _UINT16_(3) /* (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assigment of value for BLOCKACT in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _UINT16_(0x2) /* (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _UINT16_(8) /* (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assigment of value for BEATSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _UINT16_(0x1) /* (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _UINT16_(0x2) /* (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _UINT16_(10) /* (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /* (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assigment of value for SRCINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_DSTINC_Pos _UINT16_(11) /* (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assigment of value for DSTINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_Pos _UINT16_(12) /* (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assigment of value for STEPSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_DST_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _UINT16_(13) /* (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assigment of value for STEPSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSIZE_X1_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M0PLUS Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAMC21E18A specific Interrupt Numbers ***********************************/ + MCLK_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (MCLK) */ + OSCCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (OSC32KCTRL) */ + PAC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (PAC) */ + SUPC_IRQn = 0, /* 0 Shared between MCLK OSCCTRL OSC32KCTRL PAC SUPC (SUPC) */ + WDT_IRQn = 1, /* 1 Watchdog Timer (WDT) */ + RTC_IRQn = 2, /* 2 Real-Time Counter (RTC) */ + EIC_IRQn = 3, /* 3 External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /* 4 Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /* 5 Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /* 6 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /* 7 Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /* 8 Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /* 9 Serial Communication Interface (SERCOM0) */ + SERCOM1_IRQn = 10, /* 10 Serial Communication Interface (SERCOM1) */ + SERCOM2_IRQn = 11, /* 11 Serial Communication Interface (SERCOM2) */ + SERCOM3_IRQn = 12, /* 12 Serial Communication Interface (SERCOM3) */ + CAN0_IRQn = 15, /* 15 Control Area Network (CAN0) */ + TCC0_IRQn = 17, /* 17 Timer Counter Control (TCC0) */ + TCC1_IRQn = 18, /* 18 Timer Counter Control (TCC1) */ + TCC2_IRQn = 19, /* 19 Timer Counter Control (TCC2) */ + TC0_IRQn = 20, /* 20 Basic Timer Counter (TC0) */ + TC1_IRQn = 21, /* 21 Basic Timer Counter (TC1) */ + TC2_IRQn = 22, /* 22 Basic Timer Counter (TC2) */ + TC3_IRQn = 23, /* 23 Basic Timer Counter (TC3) */ + TC4_IRQn = 24, /* 24 Basic Timer Counter (TC4) */ + ADC0_IRQn = 25, /* 25 Analog Digital Converter (ADC0) */ + ADC1_IRQn = 26, /* 26 Analog Digital Converter (ADC1) */ + AC_IRQn = 27, /* 27 Analog Comparators (AC) */ + DAC_IRQn = 28, /* 28 Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /* 30 Peripheral Touch Controller (PTC) */ + + PERIPH_MAX_IRQn = 30 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M0PLUS handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pvReservedC12; + void* pvReservedC11; + void* pvReservedC10; + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pvReservedC4; + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 System peripherals shared interrupt (MCLK OSCCTRL OSC32KCTRL PAC SUPC) */ + void* pfnWDT_Handler; /* 1 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 2 Real-Time Counter (RTC) */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 4 Frequency Meter (FREQM) */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor (TSENS) */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_Handler; /* 8 Event System Interface (EVSYS) */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface (SERCOM3) */ + void* pvReserved13; + void* pvReserved14; + void* pfnCAN0_Handler; /* 15 Control Area Network (CAN0) */ + void* pvReserved16; + void* pfnTCC0_Handler; /* 17 Timer Counter Control (TCC0) */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control (TCC1) */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control (TCC2) */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter (TC4) */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter (ADC0) */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 27 Analog Comparators (AC) */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter (DAC) */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter (SDADC) */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller (PTC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M0PLUS exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void CAN0_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M0PLUS Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001 /* Cortex-M0+ Core Revision */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm0plus.h" +#if defined USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E18A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/ptc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Peripheral Access Controller (PAC) */ +#define ID_PM ( 1) /* Power Manager (PM) */ +#define ID_MCLK ( 2) /* Main Clock (MCLK) */ +#define ID_RSTC ( 3) /* Reset Controller (RSTC) */ +#define ID_OSCCTRL ( 4) /* Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Supply Controller (SUPC) */ +#define ID_GCLK ( 7) /* Generic Clock Generator (GCLK) */ +#define ID_WDT ( 8) /* Watchdog Timer (WDT) */ +#define ID_RTC ( 9) /* Real-Time Counter (RTC) */ +#define ID_EIC ( 10) /* External Interrupt Controller (EIC) */ +#define ID_FREQM ( 11) /* Frequency Meter (FREQM) */ +#define ID_TSENS ( 12) /* Temperature Sensor (TSENS) */ +#define ID_PORT ( 32) /* Port Module (PORT) */ +#define ID_DSU ( 33) /* Device Service Unit (DSU) */ +#define ID_NVMCTRL ( 34) /* Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC ( 35) /* Direct Memory Access Controller (DMAC) */ +#define ID_MTB ( 36) /* Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS ( 37) /* HSB Matrix (HMATRIXHS) */ +#define ID_EVSYS ( 64) /* Event System Interface (EVSYS) */ +#define ID_SERCOM0 ( 65) /* Serial Communication Interface (SERCOM0) */ +#define ID_SERCOM1 ( 66) /* Serial Communication Interface (SERCOM1) */ +#define ID_SERCOM2 ( 67) /* Serial Communication Interface (SERCOM2) */ +#define ID_SERCOM3 ( 68) /* Serial Communication Interface (SERCOM3) */ +#define ID_CAN0 ( 71) /* Control Area Network (CAN0) */ +#define ID_TCC0 ( 73) /* Timer Counter Control (TCC0) */ +#define ID_TCC1 ( 74) /* Timer Counter Control (TCC1) */ +#define ID_TCC2 ( 75) /* Timer Counter Control (TCC2) */ +#define ID_TC0 ( 76) /* Basic Timer Counter (TC0) */ +#define ID_TC1 ( 77) /* Basic Timer Counter (TC1) */ +#define ID_TC2 ( 78) /* Basic Timer Counter (TC2) */ +#define ID_TC3 ( 79) /* Basic Timer Counter (TC3) */ +#define ID_TC4 ( 80) /* Basic Timer Counter (TC4) */ +#define ID_ADC0 ( 81) /* Analog Digital Converter (ADC0) */ +#define ID_ADC1 ( 82) /* Analog Digital Converter (ADC1) */ +#define ID_SDADC ( 83) /* Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC ( 84) /* Analog Comparators (AC) */ +#define ID_DAC ( 85) /* Digital Analog Converter (DAC) */ +#define ID_PTC ( 86) /* Peripheral Touch Controller (PTC) */ +#define ID_CCL ( 87) /* Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_MAX ( 87) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42005000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x42004400) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x42004800) /* ADC1 Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42001c00) /* CAN0 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42005c00) /* CCL Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x42005400) /* DAC Registers Address */ +#define DIVAS_REGS ((divas_registers_t*)0x48000000) /* DIVAS Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x41006000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x42000000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define HMATRIXHS_REGS ((hmatrixb_registers_t*)0x4100a000) /* HMATRIXHS Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define MTB_REGS ((mtb_registers_t*)0x41008000) /* MTB Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define OTP5_FUSES_REGS ((fuses_otp5_fuses_registers_t*)0x00806020) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00806030) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41000000) /* PORT Registers Address */ +#define PORT_IOBUS_REGS ((port_registers_t*)0x60000000) /* PORT Registers Address */ +#define PTC_REGS ((ptc_registers_t*)0x42005800) /* PTC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDADC_REGS ((sdadc_registers_t*)0x42004c00) /* SDADC Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x42000400) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x42000800) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x42000c00) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x42001000) /* SERCOM3 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x42003000) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x42003400) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x42003800) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x42003c00) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42004000) /* TC4 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x42002400) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x42002800) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42002c00) /* TCC2 Registers Address */ +#define TSENS_REGS ((tsens_registers_t*)0x40003000) /* TSENS Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42005000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x42004400) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x42004800) /* ADC1 Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42001c00) /* CAN0 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42005c00) /* CCL Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x42005400) /* DAC Base Address */ +#define DIVAS_BASE_ADDRESS _UINT32_(0x48000000) /* DIVAS Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x41006000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x42000000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define HMATRIXHS_BASE_ADDRESS _UINT32_(0x4100a000) /* HMATRIXHS Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define MTB_BASE_ADDRESS _UINT32_(0x41008000) /* MTB Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define OTP5_FUSES_BASE_ADDRESS _UINT32_(0x00806020) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00806030) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41000000) /* PORT Base Address */ +#define PORT_IOBUS_BASE_ADDRESS _UINT32_(0x60000000) /* PORT Base Address */ +#define PTC_BASE_ADDRESS _UINT32_(0x42005800) /* PTC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDADC_BASE_ADDRESS _UINT32_(0x42004c00) /* SDADC Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x42000400) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x42000800) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x42000c00) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x42001000) /* SERCOM3 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x42003000) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x42003400) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x42003800) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x42003c00) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42004000) /* TC4 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x42002400) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x42002800) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42002c00) /* TCC2 Base Address */ +#define TSENS_BASE_ADDRESS _UINT32_(0x40003000) /* TSENS Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#include "pio/samc21e18a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 64) +#define FLASH_NB_OF_PAGES _UINT32_( 4096) + +#define OTP5_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000008) /* 0kB Memory segment type: fuses */ +#define USER_PAGE_SIZE _UINT32_(0x00000100) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 64) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 4) + +#define RWW_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: flash */ +#define RWW_PAGE_SIZE _UINT32_( 64) +#define RWW_NB_OF_PAGES _UINT32_( 128) + +#define HSRAM_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004000) /* 16kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00010000) /* 64kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: io */ +#define DIVAS_SIZE _UINT32_(0x00000020) /* 0kB Memory segment type: io */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define PERIPHERALS_SIZE _UINT32_(0x20000000) /* 524288kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define OTP5_ADDR _UINT32_(0x00806020) /* OTP5 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00806030) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define RWW_ADDR _UINT32_(0x00400000) /* RWW base address (type: flash)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define DIVAS_ADDR _UINT32_(0x48000000) /* DIVAS base address (type: io)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ +#define PERIPHERALS_ADDR _UINT32_(0x40000000) /* PERIPHERALS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAMC21E18A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X1101050A) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAMC21E18A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL 1 /* ID for OSCCTRL event generator XOSC_FAIL */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_CMP_0 3 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 4 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_OVF 5 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_RTC_PER_0 6 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 7 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 8 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 9 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 10 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 11 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 12 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 13 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_0 14 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 15 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 16 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 17 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 18 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 19 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 20 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 21 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 22 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 23 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 24 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 25 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 26 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 27 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 28 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 29 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_TSENS_WINMON 30 /* ID for TSENS event generator WINMON */ +#define EVENT_ID_GEN_DMAC_CH_0 31 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 32 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 33 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 34 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_TCC0_OVF 35 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 36 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 37 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 38 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 39 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 40 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 41 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC1_OVF 42 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 43 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 44 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 45 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 46 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_OVF 47 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 48 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 49 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 50 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 51 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 52 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 53 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 54 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 55 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 56 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 57 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 58 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 59 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 60 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 61 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 62 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 63 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 64 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 65 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 66 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 67 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 68 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 69 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 70 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_SDADC_RESRDY 71 /* ID for SDADC event generator RESRDY */ +#define EVENT_ID_GEN_SDADC_WINMON 72 /* ID for SDADC event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 73 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 74 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_COMP_2 75 /* ID for AC event generator COMP_2 */ +#define EVENT_ID_GEN_AC_COMP_3 76 /* ID for AC event generator COMP_3 */ +#define EVENT_ID_GEN_AC_WIN_0 77 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_AC_WIN_1 78 /* ID for AC event generator WIN_1 */ +#define EVENT_ID_GEN_DAC_EMPTY 79 /* ID for DAC event generator EMPTY */ +#define EVENT_ID_GEN_PTC_EOC 80 /* ID for PTC event generator EOC */ +#define EVENT_ID_GEN_PTC_WIN_COMP 81 /* ID for PTC event generator WIN_COMP */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 82 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 83 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 84 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 85 /* ID for CCL event generator LUTOUT_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 86 /* ID for PAC event generator ACCERR */ + +/* ************************************************************************** */ +/* Event User IDs for SAMC21E18A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_TSENS_START 0 /* ID for TSENS event user START */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_TCC0_EV_0 9 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 10 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 11 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 12 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 13 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 14 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC1_EV_0 15 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 16 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 17 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 18 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC2_EV_0 19 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 20 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 21 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 22 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 23 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 24 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 25 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 26 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 27 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_ADC0_START 28 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 29 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 30 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 31 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_SDADC_START 32 /* ID for SDADC event user START */ +#define EVENT_ID_USER_SDADC_FLUSH 33 /* ID for SDADC event user FLUSH */ +#define EVENT_ID_USER_AC_SOC_0 34 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 35 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_AC_SOC_2 36 /* ID for AC event user SOC_2 */ +#define EVENT_ID_USER_AC_SOC_3 37 /* ID for AC event user SOC_3 */ +#define EVENT_ID_USER_DAC_START 38 /* ID for DAC event user START */ +#define EVENT_ID_USER_CCL_LUTIN_0 40 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 41 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 42 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 43 /* ID for CCL event user LUTIN_3 */ +#define EVENT_ID_USER_MTB_START 45 /* ID for MTB event user START */ +#define EVENT_ID_USER_MTB_STOP 46 /* ID for MTB event user STOP */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAMC21E18A_H_ */ + diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000..9f4c4d77 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000..a2ad65fb --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000..74bc4a2d --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..6edd5096 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000..21a2c711 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000..045aaf19 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000..407b94ba --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000..6addcbb7 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000..ed961aa4 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000..3b268177 --- /dev/null +++ b/bms_e18a/bms_e18a_config/src/packs/CMSIS/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bms_e18a/cmake/bms_e18a/default/CMakeLists.txt b/bms_e18a/cmake/bms_e18a/default/CMakeLists.txt new file mode 100644 index 00000000..4e9eca87 --- /dev/null +++ b/bms_e18a/cmake/bms_e18a/default/CMakeLists.txt @@ -0,0 +1,23 @@ + +# This CMakeLists.txt is generated. +# Do not modify directly. +# If you want to customize cmake behavior create a user.cmake in this +# directory and add it to your version control system. + +# format v1.00 +# { + +cmake_minimum_required(VERSION 3.24.0) +set(CMAKE_SYSTEM_NAME "Generic") + +project(bms_e18a_default_project LANGUAGES C CXX ASM) + +include("${CMAKE_CURRENT_LIST_DIR}/.generated/main.cmake") + +if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/user.cmake) + include(user.cmake) +endif() + + +# } + diff --git a/bms_e18a/cmake/bms_e18a/default/CMakePresets.json b/bms_e18a/cmake/bms_e18a/default/CMakePresets.json new file mode 100644 index 00000000..152f0a6b --- /dev/null +++ b/bms_e18a/cmake/bms_e18a/default/CMakePresets.json @@ -0,0 +1,21 @@ +{ + "version": 6, + "configurePresets": [ + { + "name": "bms_e18a_default_conf", + "binaryDir": "${fileDir}/../../../_build/bms_e18a/default", + "generator": "Ninja", + "toolchainFile": "${fileDir}/.generated/toolchain.cmake", + "cacheVariables": { + "CMAKE_USER_MAKE_RULES_OVERRIDE": { + "type": "FILEPATH", + "value": "${fileDir}/.generated/overrides.cmake" + }, + "CMAKE_EXPORT_COMPILE_COMMANDS": { + "type": "BOOL", + "value": "ON" + } + } + } + ] +} \ No newline at end of file