Fixes for T2080 CW VPX3 TLB. Removes test workarounds and implements peer review feedback.

Author: dgarske

.github/workflows/test-configs.yml

@@ -207,8 +207,11 @@ jobs:
 
   nxp_t2080_test:
     uses: ./.github/workflows/test-build-powerpc.yml
-  # T2080 RDB DDR register values are not yet populated (placeholders in
-  # nxp_t2080.h), so CI must select a board with complete DDR config.
+    with:
+      arch: ppc
+      config-file: ./config/examples/nxp-t2080.config
+
+  # Additional T2080 board-specific compile tests for alternate board macros.
   nxp_t2080_test_naii_68ppc2:
     uses: ./.github/workflows/test-build-powerpc.yml
     with:

config/examples/nxp-t2080.config

@@ -1,13 +1,17 @@
 # NXP T2080 wolfBoot Configuration
 # Default board: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
 #
-# Board selection: uncomment exactly one line to override the default.
-#   Default (no define): T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
-#   BOARD_CW_VPX3152:   CW VPX3-152 (66.667 MHz oscillator, DDR3L)
-#   BOARD_NAII_68PPC2:  NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
+# Board selection:
+#   Default (no define):  T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
+#   BOARD_NAII_68PPC2:    NAII 68PPC2 (100 MHz oscillator, 8 GB DDR3)
+#   BOARD_CW_VPX3152:     CW VPX3-152 (66.667 MHz oscillator, 4 GB DDR3L)
 #
-#CFLAGS_EXTRA+=-DBOARD_CW_VPX3152
+# For NAII 68PPC2, uncomment the line below (addresses are the same as RDB):
 #CFLAGS_EXTRA+=-DBOARD_NAII_68PPC2
+#
+# For CW VPX3-152 (256 MB NOR flash at 0xF0000000), uncomment the BOARD
+# define AND the address override block at the bottom of this file.
+#CFLAGS_EXTRA+=-DBOARD_CW_VPX3152
 
 ARCH=PPC
 TARGET=nxp_t2080
@@ -35,50 +39,57 @@ DUALBANK_SWAP?=0
 WOLFTPM?=0
 OPTIMIZATION_LEVEL?=1
 
-# NOR Base Address
-# T2080 RDB:   128MB flash at 0xE8000000, wolfBoot at top (0xEFFE0000)
-# CW VPX3-152: 256MB flash at 0xF0000000, wolfBoot at top (0xFFFE0000)
+# -----------------------------------------------------------------------------
+# Default addresses: T2080 RDB / NAII 68PPC2 (128 MB NOR flash @ 0xE8000000)
+# -----------------------------------------------------------------------------
+
+# NOR Base Address: wolfBoot at top of flash
 ARCH_FLASH_OFFSET?=0xEFFE0000
-#ARCH_FLASH_OFFSET?=0xFFFE0000  # CW VPX3-152
 
 # CPC SRAM address (must match L2SRAM_ADDR in nxp_ppc.h)
-# CW VPX3-152: relocated to 0xEE900000 to avoid 256MB flash TLB overlap
 L2SRAM_ADDR?=0xF8F00000
-#L2SRAM_ADDR?=0xEE900000  # CW VPX3-152
 
 # Flash Sector Size
 WOLFBOOT_SECTOR_SIZE?=0x10000
 
 # wolfBoot start address
 WOLFBOOT_ORIGIN?=0xEFFE0000
-#WOLFBOOT_ORIGIN?=0xFFFE0000  # CW VPX3-152
 # wolfBoot partition size (custom)
 BOOTLOADER_PARTITION_SIZE=0x20000
 
 # Application Partition Size
 WOLFBOOT_PARTITION_SIZE?=0x100000
 # Location in Flash for Application Partition
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFEE0000
-#WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xFFEE0000  # CW VPX3-152
 # Load Partition to RAM Address
 WOLFBOOT_LOAD_ADDRESS?=0x19000
 
 # Location in Flash for Update Partition
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFDE0000
-#WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xFFDE0000  # CW VPX3-152
 
 # Location of temporary sector used during updates
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFDD0000
-#WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFDD0000  # CW VPX3-152
 
 # DTS (Device Tree)
 WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
-#WOLFBOOT_DTS_BOOT_ADDRESS?=0xF0040000  # CW VPX3-152
 WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
-#WOLFBOOT_DTS_UPDATE_ADDRESS?=0xF0050000  # CW VPX3-152
 # DTS Load to RAM Address
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
 
+# -----------------------------------------------------------------------------
+# CW VPX3-152 address overrides (256 MB NOR flash @ 0xF0000000)
+# Uncomment ALL lines below when building for VPX3-152.
+# Also uncomment CFLAGS_EXTRA+=-DBOARD_CW_VPX3152 at the top of this file.
+# -----------------------------------------------------------------------------
+#ARCH_FLASH_OFFSET=0xFFFE0000
+#L2SRAM_ADDR=0xEE900000
+#WOLFBOOT_ORIGIN=0xFFFE0000
+#WOLFBOOT_PARTITION_BOOT_ADDRESS=0xFFEE0000
+#WOLFBOOT_PARTITION_UPDATE_ADDRESS=0xFFDE0000
+#WOLFBOOT_PARTITION_SWAP_ADDRESS=0xFFDD0000
+#WOLFBOOT_DTS_BOOT_ADDRESS=0xF0040000
+#WOLFBOOT_DTS_UPDATE_ADDRESS=0xF0050000
+
 # Flash erase/write/read test at update partition address
 #TEST_FLASH?=1
 

docs/Targets.md

@@ -4018,10 +4018,10 @@ variants are supported:
 | Curtiss-Wright VPX3-152 | `BOARD_CW_VPX3152` | 66.667 MHz | 4 GB DDR3L | 256 MB @ `0xF0000000` |
 | NAII 68PPC2 | `BOARD_NAII_68PPC2` | 100 MHz | 8 GB DDR3 | 128 MB @ `0xE8000000` |
 
-> **Note:** The T2080 RDB DDR register values are placeholder stubs (all zeros
-> with TODO comments in `hal/nxp_t2080.h`). DDR initialization will not succeed
-> until you populate them from a U-Boot register dump. The NAII 68PPC2 and
-> CW VPX3-152 DDR configs are populated and tested.
+> **Note:** The T2080 RDB DDR register values in `hal/nxp_t2080.h` are
+> populated from a U-Boot register dump but have not been validated on
+> hardware. The NAII 68PPC2 and CW VPX3-152 DDR configs are populated
+> and tested.
 
 Example configuration: [/config/examples/nxp-t2080.config](/config/examples/nxp-t2080.config).
 See [Board Selection](#board-selection) below for per-board setup.
@@ -4359,11 +4359,27 @@ md.l 0xef008b28 2
 md.l 0xef008e40 3; md.l 0xef008e58 1
 ```
 
-**Automated test script:** `tools/scripts/nxp_t2080/cw_vpx3152_pabs_test.sh`
+**Flashing wolfBoot via PABS U-Boot:**
 
-Uses Pi4 GPIO control (GPIO 16 = PABS/JB1, GPIO 19 = Reset) and UART monitoring
-to automate the full flash-and-verify cycle. See script for usage and options
-including `--dump-ddr` mode.
+The PABS U-Boot maps main NOR flash starting at `0x80000000`. To convert wolfBoot
+flash addresses to PABS addresses, replace the `0xF` prefix with `0x8` (e.g.
+`0xFFFE0000` becomes `0x8FFE0000`). After configuring the network, use:
+
+```
+# Flash wolfBoot (128 KB at top of flash)
+tftp 0x1000000 wolfboot.bin
+erase 0x8FFE0000 +0x20000
+cp.b 0x1000000 0x8FFE0000 $filesize
+cmp.b 0x1000000 0x8FFE0000 $filesize
+
+# Flash signed application (1 MB boot partition)
+tftp 0x1000000 image_v1_signed.bin
+erase 0x8FEE0000 +0x100000
+cp.b 0x1000000 0x8FEE0000 $filesize
+cmp.b 0x1000000 0x8FEE0000 $filesize
+```
+
+Remove the JB1 jumper and power cycle to boot from main flash with wolfBoot.
 
 ### Debugging NXP T2080 PPC
 

hal/nxp_t2080.c

@@ -31,16 +31,8 @@
 /* #define DEBUG_FLASH */
 
 #ifndef BUILD_LOADER_STAGE1
-#ifndef BOARD_CW_VPX3152
-    /* CW VPX3-152: hal_mp_init() calls disable_tlb1(0) which invalidates the
-     * 16 MB boot TLB Entry 0 (which contains wolfBoot code). Without a separate
-     * flash TLB entry covering wolfBoot's code, the next instruction fetch
-     * faults. NAII works because its 256 KB boot TLB doesn't cover wolfBoot
-     * code (which is in flash TLB Entry 2 at 0xE8000000-0xEFFFFFFF).
-     * For VPX3-152, secondary cores remain disabled. */
     #define ENABLE_MP   /* multi-core support */
 #endif
-#endif
 
 /* generic shared NXP QorIQ driver code */
 #include "nxp_ppc.c"
@@ -80,6 +72,12 @@ static void hal_mp_init(void);
 #define FLASH_UNLOCK_ADDR2 0x555
 #endif
 
+/* FLASH_CMD_SECTOR: sector used for flash command sequences that don't target
+ * a specific sector (reset, unlock, PPB entry/exit). AMD flash command decode
+ * only looks at the low address bits, so sector 0 works for all boards with
+ * a properly mapped full-flash TLB entry. */
+#define FLASH_CMD_SECTOR 0
+
 /* Flash IO Helpers */
 #if FLASH_CFI_WIDTH == 16
 #define FLASH_IO8_WRITE(sec, n, val)      *((volatile uint16_t*)(FLASH_BASE_ADDR + (FLASH_SECTOR_SIZE * (sec)) + ((n) * 2))) = (((val) << 8) | (val))
@@ -375,15 +373,9 @@ static void hal_reconfigure_cpc_as_cache(void)
 
 /* Make flash TLB cacheable for XIP code performance.
  * Changes TLB Entry 2 (flash) from MAS2_I|MAS2_G to MAS2_M.
- * This enables L1 I-cache + L2 + CPC to cache flash instructions.
- *
- * For BOARD_CW_VPX3152: TLB1 Entry 2 is NOT used (256 MB flash TLB would
- * overlap with the 16 MB boot ROM TLB at the top of flash, causing e6500
- * multi-hit). The boot TLB covers wolfBoot + partitions cache-inhibited;
- * skip the caching update — flash runs uncached (slower but correct). */
+ * This enables L1 I-cache + L2 + CPC to cache flash instructions. */
 static void hal_flash_enable_caching(void)
 {
-#ifndef BOARD_CW_VPX3152
     /* Rewrite flash TLB entry with cacheable attributes.
      * MAS2_M = memory coherent, enables caching */
     set_tlb(1, 2,
@@ -393,7 +385,6 @@ static void hal_flash_enable_caching(void)
 
     /* Invalidate L1 I-cache so new TLB attributes take effect */
     invalidate_icache();
-#endif
 
 #ifdef DEBUG_UART
     wolfBoot_printf("Flash: caching enabled (L1+L2+CPC)\n");
@@ -481,21 +472,17 @@ void hal_init(void)
  * returns a bus error (DSI). */
 static void RAMFUNCTION hal_flash_cache_disable(void)
 {
-#ifndef BOARD_CW_VPX3152
     set_tlb(1, 2, FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, FLASH_TLB_PAGESZ, 1);
-#endif
 }
 
 /* Restore flash TLB to cacheable mode after flash operation.
  * Flash must be back in read-array mode before calling (AMD_CMD_RESET sent).
  * Invalidate caches afterward so stale pre-erase data is not served. */
 static void RAMFUNCTION hal_flash_cache_enable(void)
 {
-#ifndef BOARD_CW_VPX3152
     set_tlb(1, 2, FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, FLASH_TLB_PAGESZ, 1);
-#endif
     invalidate_dcache();
     invalidate_icache();
 }
@@ -539,9 +526,9 @@ static int RAMFUNCTION hal_flash_ppb_unlock(uint32_t sector)
     uint32_t timeout;
 
     /* Enter PPB ASO (Address Space Overlay) */
-    FLASH_IO8_WRITE(0, FLASH_UNLOCK_ADDR1, AMD_CMD_UNLOCK_START);
-    FLASH_IO8_WRITE(0, FLASH_UNLOCK_ADDR2, AMD_CMD_UNLOCK_ACK);
-    FLASH_IO8_WRITE(0, FLASH_UNLOCK_ADDR1, AMD_CMD_SET_PPB_ENTRY);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, FLASH_UNLOCK_ADDR1, AMD_CMD_UNLOCK_START);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, FLASH_UNLOCK_ADDR2, AMD_CMD_UNLOCK_ACK);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, FLASH_UNLOCK_ADDR1, AMD_CMD_SET_PPB_ENTRY);
 
     /* Read PPB status for target sector: DQ0=0 means protected.
      * On 16-bit bus, must read both chip lanes to check both devices. */
@@ -553,16 +540,16 @@ static int RAMFUNCTION hal_flash_ppb_unlock(uint32_t sector)
     if ((ppb_status & 0x01) == 0x01) {
 #endif
         /* Both chips report unprotected — exit PPB mode and return */
-        FLASH_IO8_WRITE(0, 0, AMD_CMD_SET_PPB_EXIT_BC1);
-        FLASH_IO8_WRITE(0, 0, AMD_CMD_SET_PPB_EXIT_BC2);
+        FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_SET_PPB_EXIT_BC1);
+        FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_SET_PPB_EXIT_BC2);
         return 0;
     }
 
     /* Exit PPB ASO before calling printf (flash must be in read-array
      * mode for I-cache misses to fetch valid instructions) */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_SET_PPB_EXIT_BC1);
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_SET_PPB_EXIT_BC2);
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_RESET);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_SET_PPB_EXIT_BC1);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_SET_PPB_EXIT_BC2);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_RESET);
     udelay(50);
 
 #ifdef DEBUG_FLASH
@@ -571,36 +558,36 @@ static int RAMFUNCTION hal_flash_ppb_unlock(uint32_t sector)
 #endif
 
     /* Re-enter PPB ASO for erase */
-    FLASH_IO8_WRITE(0, FLASH_UNLOCK_ADDR1, AMD_CMD_UNLOCK_START);
-    FLASH_IO8_WRITE(0, FLASH_UNLOCK_ADDR2, AMD_CMD_UNLOCK_ACK);
-    FLASH_IO8_WRITE(0, FLASH_UNLOCK_ADDR1, AMD_CMD_SET_PPB_ENTRY);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, FLASH_UNLOCK_ADDR1, AMD_CMD_UNLOCK_START);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, FLASH_UNLOCK_ADDR2, AMD_CMD_UNLOCK_ACK);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, FLASH_UNLOCK_ADDR1, AMD_CMD_SET_PPB_ENTRY);
 
     /* PPB Erase All (clears all sectors' PPBs) */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_PPB_UNLOCK_BC1);  /* 0x80 */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_PPB_UNLOCK_BC2);  /* 0x30 */
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_PPB_UNLOCK_BC1);  /* 0x80 */
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_PPB_UNLOCK_BC2);  /* 0x30 */
 
     /* Wait for PPB erase completion — poll for toggle stop.
      * On 16-bit bus, read both chip lanes to ensure both complete. */
     timeout = 0;
     do {
 #if FLASH_CFI_WIDTH == 16
-        read1 = FLASH_IO16_READ(0, 0);
-        read2 = FLASH_IO16_READ(0, 0);
+        read1 = FLASH_IO16_READ(FLASH_CMD_SECTOR, 0);
+        read2 = FLASH_IO16_READ(FLASH_CMD_SECTOR, 0);
 #else
-        read1 = FLASH_IO8_READ(0, 0);
-        read2 = FLASH_IO8_READ(0, 0);
+        read1 = FLASH_IO8_READ(FLASH_CMD_SECTOR, 0);
+        read2 = FLASH_IO8_READ(FLASH_CMD_SECTOR, 0);
 #endif
         if (read1 == read2)
             break;
         udelay(10);
     } while (timeout++ < 100000); /* 1 second */
 
     /* Exit PPB ASO */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_SET_PPB_EXIT_BC1);
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_SET_PPB_EXIT_BC2);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_SET_PPB_EXIT_BC1);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_SET_PPB_EXIT_BC2);
 
     /* Reset to read-array mode */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_RESET);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_RESET);
     udelay(50);
 
     if (timeout >= 100000) {
@@ -717,7 +704,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
 
     /* Reset flash to read-array mode in case previous operation left it
      * in command mode (e.g. after a timeout or incomplete operation) */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_RESET);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_RESET);
     udelay(50);
 
     /* Program one word at a time using AMD single-word program (0xA0).
@@ -788,7 +775,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 
     /* Reset flash to read-array mode in case previous operation left it
      * in command mode (e.g. after a timeout or incomplete operation) */
-    FLASH_IO8_WRITE(0, 0, AMD_CMD_RESET);
+    FLASH_IO8_WRITE(FLASH_CMD_SECTOR, 0, AMD_CMD_RESET);
     udelay(50);
 
     while (len > 0) {
@@ -1033,14 +1020,7 @@ void hal_prepare_boot(void)
 #ifdef MMU
 void* hal_get_dts_address(void)
 {
-#ifdef BOARD_CW_VPX3152
-    /* DTS is at 0xF0040000 which is below the 16 MB boot TLB
-     * (covers 0xFF000000-0xFFFFFFFF). Return NULL to skip DTS loading
-     * until a separate flash TLB is added for the DTS region. */
-    return NULL;
-#else
     return (void*)WOLFBOOT_DTS_BOOT_ADDRESS;
-#endif
 }
 
 int hal_dts_fixup(void* dts_addr)