Peer review fixes

Author: dgarske

arch.mk

@@ -563,7 +563,10 @@ endif
 ## RISCV (32-bit)
 ifeq ($(ARCH),RISCV)
   CROSS_COMPILE?=riscv32-unknown-elf-
-  ARCH_FLAGS=-march=rv32imac -mabi=ilp32 -mcmodel=medany
+  # GCC 12+ requires explicit zicsr/zifencei extensions
+  RISCV32_ZICSR := $(shell echo "" | $(CC) -march=rv32imac_zicsr -x c -c - -o /dev/null 2>/dev/null && echo _zicsr)
+  RISCV32_ZIFENCEI := $(shell echo "" | $(CC) -march=rv32imac_zifencei -x c -c - -o /dev/null 2>/dev/null && echo _zifencei)
+  ARCH_FLAGS=-march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) -mabi=ilp32 -mcmodel=medany
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV
   CFLAGS+=$(ARCH_FLAGS)
   LDFLAGS+=$(ARCH_FLAGS)
@@ -605,12 +608,17 @@ ifeq ($(ARCH),RISCV64)
     UPDATE_OBJS?=src/update_ram.o
   endif
 
+  # GCC 12+ / binutils 2.38+ split CSR and fence.i instructions into
+  # separate extensions (zicsr, zifencei). Detect and add if supported.
+  RISCV64_ZICSR := $(shell echo "" | $(CC) -march=rv64imac_zicsr -x c -c - -o /dev/null 2>/dev/null && echo _zicsr)
+  RISCV64_ZIFENCEI := $(shell echo "" | $(CC) -march=rv64imac_zifencei -x c -c - -o /dev/null 2>/dev/null && echo _zifencei)
+
   ifeq ($(RISCV_MMODE),1)
     # E51 core: rv64imac (no FPU, no crypto extensions)
-    ARCH_FLAGS=-march=rv64imac -mabi=lp64 -mcmodel=medany
+    ARCH_FLAGS=-march=rv64imac$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64 -mcmodel=medany
   else
     # U54 cores: rv64gc (with FPU)
-    ARCH_FLAGS=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+    ARCH_FLAGS=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
 
     # FDT support required
     CFLAGS+=-DWOLFBOOT_FDT

hal/riscv.h

@@ -83,8 +83,6 @@
 #define MODE_PREFIX(__suffix)    s##__suffix
 #endif
 
-
-
 /* ============================================================================
  * CSR Access Macros
  * ============================================================================ */

src/boot_riscv.c

@@ -419,7 +419,7 @@ void do_boot(const uint32_t *app_offset)
 #endif
 #ifdef MMU
     unsigned long dts_addr;
-#else
+#elif __riscv_xlen == 64
     unsigned long dts_addr = 0;
 #endif
 

src/boot_riscv_start.S

@@ -63,11 +63,12 @@ _reset:
      * 5. Handle multi-hart (E51 runs, U54s park in WFI)
      * ======================================================================== */
 
-#if 0 //def TARGET_mpfs250
+    /* Early UART initialization for M-mode boot on MPFS.
+     * Intentionally disabled: only needed for low-level bring-up debug
+     * to enable serial output before C runtime is available.
+     * To re-enable, change the guard to `#ifdef TARGET_mpfs250`. */
+#if 0
     /*
-     * Early UART initialization for M-mode boot on MPFS.
-     * This enables debug output during the boot sequence.
-     */
     li    t0, 0x20000000           /* UART0 base */
     li    t1, 0x20002000           /* SYSREG_BASE */
     /* Enable UART0 clock */