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Commit 1c18481

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dgarskedanielinux
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Peer review fixes
1 parent 88a32de commit 1c18481

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3 files changed

+26
-19
lines changed

3 files changed

+26
-19
lines changed

hal/zynq.c

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1602,18 +1602,17 @@ void hal_prepare_boot(void)
16021602
* fetch instructions via I-cache from main memory. We must:
16031603
* 1. Clean D-cache (flush dirty data to memory)
16041604
* 2. Invalidate I-cache (ensure fresh instruction fetch) */
1605-
__asm__ volatile("dsb sy");
16061605
{
16071606
uintptr_t addr;
16081607
uintptr_t end = WOLFBOOT_LOAD_ADDRESS + APP_CACHE_FLUSH_SIZE;
16091608
for (addr = WOLFBOOT_LOAD_ADDRESS; addr < end; addr += CACHE_LINE_SIZE) {
1610-
__asm__ volatile("dc civac, %0" : : "r"(addr));
1609+
__asm__ volatile("dc civac, %0" : : "r"(addr) : "memory");
16111610
}
16121611
}
1613-
__asm__ volatile("dsb sy");
1614-
__asm__ volatile("ic iallu");
1615-
__asm__ volatile("dsb sy");
1616-
__asm__ volatile("isb");
1612+
__asm__ volatile("dsb sy" : : : "memory");
1613+
__asm__ volatile("ic iallu" : : : "memory");
1614+
__asm__ volatile("dsb sy" : : : "memory");
1615+
__asm__ volatile("isb" : : : "memory");
16171616
}
16181617

16191618
/* Flash functions must be relocated to RAM for execution */
@@ -2084,15 +2083,15 @@ void sdhci_platform_init(void)
20842083
* This feeds into the SDHCI Capabilities register bits 31:30 and makes
20852084
* the controller report card as always present, bypassing the physical
20862085
* CD pin that is not connected to the SDHCI controller on ZCU102. */
2087-
if (ZYNQMP_SDHCI_BASE == ZYNQMP_SD0_BASE) {
2088-
slot_mask = SD_CONFIG_REG2_SD0_SLOTTYPE_MASK;
2089-
slot_shift = SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT;
2090-
reset_bit = RST_LPD_IOU2_SDIO0;
2091-
} else {
2092-
slot_mask = SD_CONFIG_REG2_SD1_SLOTTYPE_MASK;
2093-
slot_shift = SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT;
2094-
reset_bit = RST_LPD_IOU2_SDIO1;
2095-
}
2086+
#if ZYNQMP_SDHCI_BASE == ZYNQMP_SD0_BASE
2087+
slot_mask = SD_CONFIG_REG2_SD0_SLOTTYPE_MASK;
2088+
slot_shift = SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT;
2089+
reset_bit = RST_LPD_IOU2_SDIO0;
2090+
#else
2091+
slot_mask = SD_CONFIG_REG2_SD1_SLOTTYPE_MASK;
2092+
slot_shift = SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT;
2093+
reset_bit = RST_LPD_IOU2_SDIO1;
2094+
#endif
20962095

20972096
reg = IOU_SLCR_SD_CONFIG_REG2;
20982097
reg &= ~slot_mask;
@@ -2113,7 +2112,11 @@ void sdhci_platform_init(void)
21132112
uint32_t val;
21142113

21152114
wolfBoot_printf("sdhci_platform_init: SD%d at 0x%x\n",
2116-
(ZYNQMP_SDHCI_BASE == ZYNQMP_SD0_BASE) ? 0 : 1,
2115+
#if ZYNQMP_SDHCI_BASE == ZYNQMP_SD0_BASE
2116+
0,
2117+
#else
2118+
1,
2119+
#endif
21172120
(unsigned int)ZYNQMP_SDHCI_BASE);
21182121

21192122
wolfBoot_printf(" SD_CONFIG_REG2: 0x%x\n",
@@ -2157,7 +2160,8 @@ void sdhci_platform_dma_prepare(void *buf, uint32_t sz, int is_write)
21572160
{
21582161
uintptr_t addr;
21592162
uintptr_t start = (uintptr_t)buf & ~(CACHE_LINE_SIZE - 1);
2160-
uintptr_t end = (uintptr_t)buf + sz;
2163+
uintptr_t end = ((uintptr_t)buf + sz + CACHE_LINE_SIZE - 1) &
2164+
~(CACHE_LINE_SIZE - 1);
21612165

21622166
if (is_write) {
21632167
/* Clean D-cache: flush dirty lines to memory for DMA to read */
@@ -2180,7 +2184,8 @@ void sdhci_platform_dma_complete(void *buf, uint32_t sz, int is_write)
21802184
* new data for the CPU to see and invalidation could discard dirty lines. */
21812185
uintptr_t addr;
21822186
uintptr_t start = (uintptr_t)buf & ~(CACHE_LINE_SIZE - 1);
2183-
uintptr_t end = (uintptr_t)buf + sz;
2187+
uintptr_t end = ((uintptr_t)buf + sz + CACHE_LINE_SIZE - 1) &
2188+
~(CACHE_LINE_SIZE - 1);
21842189

21852190
if (!is_write) {
21862191
for (addr = start; addr < end; addr += CACHE_LINE_SIZE) {

src/sdhci.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1253,8 +1253,10 @@ static int sdhci_transfer(int dir, uint32_t cmd_index, uint32_t block_addr,
12531253
}
12541254
sdhci_disable_sdma_interrupts();
12551255

1256+
#ifndef SDHCI_SDMA_DISABLED
12561257
/* Platform DMA cache maintenance after transfer */
12571258
sdhci_platform_dma_complete(buf, sz, dir == SDHCI_DIR_WRITE);
1259+
#endif /* !SDHCI_SDMA_DISABLED */
12581260
}
12591261
else {
12601262
/* Blocking mode - buffer ready flag differs for read vs write */

test-app/app_zynq.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
#ifdef TARGET_zynq
3030

3131
/* Provide current_el() for hal/zynq.o (normally in boot_aarch64.c) */
32-
unsigned int current_el(void)
32+
__attribute__((weak)) unsigned int current_el(void)
3333
{
3434
unsigned long el;
3535
__asm__ volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");

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