PolarFire SoC M-Mode, QSPI and L2-LIM support

Adds support for running wolfBoot in **Machine Mode (M-mode)** on the PolarFire SoC MPFS250T, booting from eNVM and loading a signed application from **SC QSPI flash** into on-chip LIM (Loosely Integrated Memory). No HSS (Hart Software Services) or DDR is required. It also extends the existing PolarFire HAL with multi-hart support, L2 cache configuration, per-hart UART, and refactors shared code (SDHCI, SCB mailbox, linker/test-app) for both S-mode and M-mode builds.

Author: dgarske

.gdbinit

@@ -4,4 +4,3 @@ add-symbol-file test-app/image.elf
 set pagination off
 foc c
 
-

.github/workflows/test-build-riscv.yml

@@ -19,7 +19,6 @@ jobs:
   build:
     runs-on: ubuntu-24.04
     timeout-minutes: 30
-
     steps:
       - uses: actions/checkout@v4
         with:
@@ -80,26 +79,28 @@ jobs:
       - name: Update repository
         run: sudo apt-get update -o Acquire::Retries=3
 
-      - name: Download and install RISC-V toolchains
+      # ============================================================
+      # Prebuilt RISC-V toolchains from riscv-collab
+      # https://github.com/riscv-collab/riscv-gnu-toolchain/releases
+      # Extracts to: riscv/bin/riscv{32,64}-unknown-elf-*
+      # ============================================================
+      - name: Download and install RISC-V toolchain (riscv32)
         if: ${{ inputs.arch == 'riscv' }}
         run: |
-          # Download SiFive prebuilt toolchain with newlib
-          wget -q https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-          tar xzf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-          echo "$GITHUB_WORKSPACE/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_PATH
-
-          # Download latest prebuilt RISC-V toolchains
-          #wget -q https://github.com/RISCV-Tools/riscv-gnu-toolchain/releases/latest/download/riscv32-elf-ubuntu-24.04-gcc.tar.xz
-          #tar -xf riscv32-elf-ubuntu-24.04-gcc.tar.xz
-          #echo "$GITHUB_WORKSPACE/riscv/bin" >> $GITHUB_PATH
+          wget -q https://github.com/riscv-collab/riscv-gnu-toolchain/releases/latest/download/riscv32-elf-ubuntu-24.04-gcc.tar.xz
+          tar -xf riscv32-elf-ubuntu-24.04-gcc.tar.xz
+          echo "$GITHUB_WORKSPACE/riscv/bin" >> $GITHUB_PATH
+          $GITHUB_WORKSPACE/riscv/bin/riscv32-unknown-elf-gcc --version
 
-      - name: Download and install RISC-V toolchains
+      - name: Install RISC-V toolchain (riscv64)
         if: ${{ inputs.arch == 'riscv64' }}
         run: |
-          wget -q https://github.com/RISCV-Tools/riscv-gnu-toolchain/releases/latest/download/riscv64-elf-ubuntu-24.04-gcc.tar.xz
-          tar -xf riscv64-elf-ubuntu-24.04-gcc.tar.xz
-          echo "$GITHUB_WORKSPACE/riscv/bin" >> $GITHUB_PATH
+          sudo apt-get install -y gcc-riscv64-unknown-elf binutils-riscv64-unknown-elf
+          riscv64-unknown-elf-gcc --version
 
+      # ============================================================
+      # Build wolfboot
+      # ============================================================
       - name: make clean
         run: |
           make distclean
@@ -115,10 +116,9 @@ jobs:
       - name: Build wolfboot (riscv32)
         if: ${{ inputs.arch == 'riscv' }}
         run: |
-          # using riscv64 for now since riscv32-unknown-elf- is missing "zicsr" extension
-          make CROSS_COMPILE=riscv64-unknown-elf- FREEDOM_E_SDK=$GITHUB_WORKSPACE/freedom-e-sdk ${{inputs.make-args}}
+          make CROSS_COMPILE=riscv32-unknown-elf- FREEDOM_E_SDK=$GITHUB_WORKSPACE/freedom-e-sdk ${{inputs.make-args}}
 
-      - name: Build wolfboot (riscv64))
+      - name: Build wolfboot (riscv64)
         if: ${{ inputs.arch == 'riscv64' }}
         run: |
           make CROSS_COMPILE=riscv64-unknown-elf- ${{inputs.make-args}}

.github/workflows/test-configs.yml

@@ -19,9 +19,6 @@ jobs:
     with:
       arch: riscv
       config-file: ./config/examples/hifive1.config
-      # Only building wolfBoot - not test app for now (cross compiler cannot find suitable multilib set for '-march=rv32imafdc_zicsr_zmmul_zaamo_zalrsc_zca_zcd_zcf'/'-mabi=ilp32d')
-      # Consider building cached RISCV64 toolchain for this target
-      make-args: wolfboot.bin
 
   sama5d3_test:
     uses: ./.github/workflows/test-build.yml
@@ -266,9 +263,16 @@ jobs:
     with:
       arch: riscv64
       config-file: ./config/examples/polarfire_mpfs250.config
-      # Only building wolfBoot - not test app for now (cross compiler cannot find suitable multilib set for '-march=rv64imafd_zicsr_zmmul_zaamo_zalrsc'/'-mabi=lp64d')
-      # Consider building cached RISCV64 toolchain for this target
-      make-args: wolfboot.bin
+  microchip_mpfs250_qspi_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_qspi.config
+  microchip_mpfs250_m_qspi_test:
+    uses: ./.github/workflows/test-build-riscv.yml
+    with:
+      arch: riscv64
+      config-file: ./config/examples/polarfire_mpfs250_m_qspi.config
 
   raspi3_test:
     uses: ./.github/workflows/test-build.yml

.gitignore

@@ -327,6 +327,7 @@ language.settings.xml
 
 # PolarFire SoC Device Tree Binary
 hal/mpfs.dtb
+bootmode1/
 
 # Emulator test: generated linker scripts
 test-app/emu-test-apps/*/target.ld

Makefile

@@ -521,7 +521,8 @@ $(LSCRIPT): $(LSCRIPT_IN) FORCE
 		sed -e "s/@WOLFBOOT_LOAD_BASE@/$(WOLFBOOT_LOAD_BASE)/g" | \
 		sed -e "s/@BOOTLOADER_START@/$(BOOTLOADER_START)/g" | \
 		sed -e "s/@IMAGE_HEADER_SIZE@/$(IMAGE_HEADER_SIZE)/g" | \
-		sed -e "s/@FSP_S_LOAD_BASE@/$(FSP_S_LOAD_BASE)/g" \
+		sed -e "s/@FSP_S_LOAD_BASE@/$(FSP_S_LOAD_BASE)/g" | \
+		sed -e "s/@WOLFBOOT_L2LIM_SIZE@/$(WOLFBOOT_L2LIM_SIZE)/g" \
 		> $@
 
 hex: wolfboot.hex

arch.mk

@@ -564,10 +564,24 @@ endif
 ## RISCV (32-bit)
 ifeq ($(ARCH),RISCV)
   CROSS_COMPILE?=riscv32-unknown-elf-
-  ARCH_FLAGS=-march=rv32imac -mabi=ilp32 -mcmodel=medany
+  # GCC 12+ separated _zicsr (CSR instructions) and _zifencei (fence.i)
+  # from the base "I" extension, requiring them to be listed explicitly in
+  # the -march string.  Detect with compile-only tests (-c).
+  #
+  # IMPORTANT: these extensions are added to CFLAGS only (compilation).
+  # They must NOT appear in LDFLAGS because GCC 15 decomposes the ISA
+  # string (m→zmmul, a→zaamo+zalrsc, c→zca) producing an expanded
+  # -march that has no matching multilib, causing a fatal error at
+  # link time.  The base march is multilib-safe for all GCC versions.
+  RISCV32_ZICSR := $(shell echo "void _start(void){}" | \
+    $(CROSS_COMPILE)gcc -march=rv32imac_zicsr -mabi=ilp32 -c -x c - -o /dev/null 2>/dev/null && echo _zicsr)
+  RISCV32_ZIFENCEI := $(shell echo "void _start(void){}" | \
+    $(CROSS_COMPILE)gcc -march=rv32imac_zifencei -mabi=ilp32 -c -x c - -o /dev/null 2>/dev/null && echo _zifencei)
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV
-  CFLAGS+=$(ARCH_FLAGS)
-  LDFLAGS+=$(ARCH_FLAGS)
+  # Compilation: extended march so assembler accepts CSR/fence.i
+  CFLAGS+=-march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) -mabi=ilp32 -mcmodel=medany
+  # Linking: base march (no extension suffixes) for multilib lookup
+  LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
   MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c32.o
 
   # Prune unused functions and data
@@ -582,7 +596,24 @@ endif
 ## RISCV64 (64-bit)
 ifeq ($(ARCH),RISCV64)
   CROSS_COMPILE?=riscv64-unknown-elf-
-  CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+
+  # M-mode vs S-mode configuration
+  ifeq ($(RISCV_MMODE),1)
+    # Machine Mode: Running directly from eNVM/L2 SRAM
+    CFLAGS+=-DWOLFBOOT_RISCV_MMODE -DWOLFBOOT_DUALBOOT
+    # Use M-mode specific linker script
+    LSCRIPT_IN:=hal/$(TARGET)-m.ld
+  else
+    # Supervisor Mode: Running under HSS
+    CFLAGS+=-DWOLFBOOT_DUALBOOT
+    ifeq ($(MPFS_L2LIM),1)
+      # L2-LIM mode: wolfBoot in on-chip SRAM, loaded by HSS (no DDR)
+      LSCRIPT_IN:=hal/$(TARGET)-hss.ld
+    else
+      # DDR mode (default): full MMU and FDT support
+      CFLAGS+=-DMMU
+    endif
+  endif
 
   # If SD card or eMMC is enabled use update_disk loader with GPT support
   ifneq ($(filter 1,$(DISK_SDCARD) $(DISK_EMMC)),)
@@ -596,10 +627,30 @@ ifeq ($(ARCH),RISCV64)
     UPDATE_OBJS?=src/update_ram.o
   endif
 
-  ARCH_FLAGS=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+  # GCC 12+ extension detection (see RISCV 32-bit section above).
+  # Extensions go in CFLAGS only; LDFLAGS uses the base march to avoid
+  # GCC 15 multilib lookup failures from ISA string decomposition.
+  RISCV64_ZICSR := $(shell echo "void _start(void){}" | \
+    $(CROSS_COMPILE)gcc -march=rv64imafd_zicsr -mabi=lp64d -c -x c - -o /dev/null 2>/dev/null && echo _zicsr)
+  RISCV64_ZIFENCEI := $(shell echo "void _start(void){}" | \
+    $(CROSS_COMPILE)gcc -march=rv64imafd_zifencei -mabi=lp64d -c -x c - -o /dev/null 2>/dev/null && echo _zifencei)
+
+  ifeq ($(RISCV_MMODE),1)
+    # E51 core: rv64imac (no FPU, no crypto extensions)
+    CFLAGS+=-march=rv64imac$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64 -mcmodel=medany
+    LDFLAGS+=-march=rv64imac -mabi=lp64 -mcmodel=medany
+  else
+    # U54 cores: rv64gc (with FPU)
+    CFLAGS+=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
+    LDFLAGS+=-march=rv64imafd -mabi=lp64d -mcmodel=medany
+
+    # FDT support for DDR S-mode (not needed for L2-LIM bare-metal boot)
+    ifneq ($(MPFS_L2LIM),1)
+      CFLAGS+=-DWOLFBOOT_FDT
+      OBJS+=src/fdt.o
+    endif
+  endif
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV -DARCH_RISCV64
-  CFLAGS+=$(ARCH_FLAGS)
-  LDFLAGS+=$(ARCH_FLAGS)
 
   # Prune unused functions and data
   CFLAGS +=-ffunction-sections -fdata-sections
@@ -608,9 +659,6 @@ ifeq ($(ARCH),RISCV64)
   # Unified RISC-V boot code (32/64-bit via __riscv_xlen)
   OBJS+=src/boot_riscv_start.o src/boot_riscv.o src/vector_riscv.o
 
-  CFLAGS+=-DWOLFBOOT_FDT
-  OBJS+=src/fdt.o
-
   ifeq ($(SPMATH),1)
     MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c64.o
   endif
@@ -1632,6 +1680,13 @@ ifeq ($(DEBUG_UART),1)
   endif
 endif
 
+# UART QSPI programmer (PolarFire SoC MPFS): receive binary over UART and
+# write it directly to QSPI flash. Requires EXT_FLASH=1 and DEBUG_UART=1.
+# Use tools/scripts/mpfs_qspi_prog.py on the host side.
+ifeq ($(UART_QSPI_PROGRAM),1)
+  CFLAGS+=-DUART_QSPI_PROGRAM
+endif
+
 ifeq ($(NXP_CUSTOM_DCD),1)
   CFLAGS+=-DNXP_CUSTOM_DCD
   OBJS+=$(NXP_CUSTOM_DCD_OBJS)

config/examples/polarfire_mpfs250.config

@@ -68,7 +68,7 @@ CFLAGS_EXTRA+=-DBOOT_PART_B=2
 # Speed up disk partition read (512KB chunks - max DMA size)
 CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
 
-# DTS (Device Tree)
+# DTS (Device Tree) load address
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x8A000000
 
 # Optional Encryption
@@ -78,7 +78,7 @@ WOLFBOOT_LOAD_DTS_ADDRESS?=0x8A000000
 #OBJS_EXTRA=src/my_custom_encrypt_key.o
 
 # Optional EMMC_SD debugging logs
-#CFLAGS_EXTRA+=-DDEBUG_MMC
+#CFLAGS_EXTRA+=-DDEBUG_SDHCI
 # Optional disk debugging logs
 #CFLAGS_EXTRA+=-DDEBUG_DISK
 #CFLAGS_EXTRA+=-DDISK_TEST

config/examples/polarfire_mpfs250_hss_l2lim.config

@@ -0,0 +1,92 @@
+ARCH?=RISCV64
+TARGET?=mpfs250
+
+# ECC P384 + SHA384
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE=512
+
+WOLFBOOT_VERSION?=1
+ARMORED?=0
+DEBUG?=0
+DEBUG_SYMBOLS?=1
+DEBUG_UART?=1
+VTOR?=1
+
+NO_XIP?=1
+
+NVM_FLASH_WRITEONCE?=0
+UART_FLASH?=0
+V?=0
+NO_MPU?=1
+RAM_CODE?=0
+SPMATH?=1
+DUALBANK_SWAP?=0
+PKA?=0
+ENCRYPT=0
+WOLFTPM?=0
+ELF?=0
+
+# U54 cores lack RISC-V crypto extensions (Zknh); use portable C implementations
+NO_ASM?=1
+
+# QSPI Flash Configuration
+# Using Micron MT25QL01GBBB (128MB, 64KB sectors)
+EXT_FLASH?=1
+SPI_FLASH?=0
+
+# SPI Flash Controller Selection:
+# MPFS_SC_SPI: Use SC QSPI Controller (0x37020100) for fabric-connected flash.
+#              Direct register access to System Controller's QSPI instance.
+# DEFAULT:     Use MSS QSPI Controller (0x21000000) for external flash
+#              on MSS QSPI pins.
+CFLAGS_EXTRA+=-DMPFS_SC_SPI
+
+# L2-LIM mode: wolfBoot loaded by HSS to L2-LIM (no DDR)
+# HSS runs on E51 from eNVM, loads wolfBoot to L2-LIM on U54 (S-mode)
+# wolfBoot loads application from SC ext SPI flash to L2-LIM
+MPFS_L2LIM?=1
+
+# wolfBoot origin in L2-LIM (above HSS resident region)
+# NOTE: Adjust based on HSS L2-LIM footprint. HSS typically uses ~200-400KB
+# from 0x08000000. Check HSS linker map for actual end address.
+WOLFBOOT_ORIGIN?=0x08040000
+
+# Application loaded from QSPI to L2-LIM (above wolfBoot, 128KB offset)
+WOLFBOOT_LOAD_ADDRESS?=0x08060000
+
+# Stack at top of 1.5MB L2-LIM (grows downward)
+WOLFBOOT_STACK_TOP?=0x08180000
+
+# L2-LIM size available for wolfBoot (STACK_TOP - ORIGIN)
+WOLFBOOT_L2LIM_SIZE?=0x140000
+
+# Flash geometry (64 KB sector)
+WOLFBOOT_SECTOR_SIZE?=0x10000
+
+# Partition layout for 128MB QSPI flash
+# Boot partition:     0x00020000 - 0x01FFFFFF (~32MB)
+# Update partition:   0x02000000 - 0x03FFFFFF (~32MB)
+# Swap partition:     0x04000000 - 0x0400FFFF (64KB)
+# Remaining:          0x04010000 - 0x07FFFFFF (~64MB available)
+WOLFBOOT_PARTITION_SIZE?=0x1FE0000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x20000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x2000000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x4000000
+
+# Speed up reads from flash by using larger blocks
+CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
+
+# Optional Encryption
+#CUSTOM_ENCRYPT_KEY=1
+#ENCRYPT=1
+#ENCRYPT_WITH_AES256=1
+#OBJS_EXTRA=src/my_custom_encrypt_key.o
+
+# Optional QSPI debugging
+# Uncomment for verbose QSPI debug output
+#CFLAGS_EXTRA+=-DDEBUG_QSPI
+
+# Optional QSPI flash test (erase/write/read on update partition)
+# Uncomment to run test during hal_init()
+#CFLAGS_EXTRA+=-DTEST_EXT_FLASH