|
| 1 | +# PolarFire SoC MPFS250T M-Mode (Machine Mode) with LPDDR4 + SD card |
| 2 | +# |
| 3 | +# Standalone wolfBoot replacing HSS: |
| 4 | +# 1. eNVM (0x20220100) -> L2_SCRATCH (0x0A000000) - wolfBoot starts |
| 5 | +# 2. M-mode init: PLLs, DDR controller, LPDDR4 training (Video Kit) |
| 6 | +# 3. Load signed Linux kernel/DTB from SD card to DDR (0x8E000000 / 0x8A000000) |
| 7 | +# 4. Verify ECC384/SHA384 signature |
| 8 | +# 5. Drop to S-mode and jump to kernel |
| 9 | +# |
| 10 | +# Flash via mpfsBootmodeProgrammer (bootmode 1): |
| 11 | +# java -jar mpfsBootmodeProgrammer.jar --bootmode 1 --die MPFS250T \ |
| 12 | +# --package FCG1152 --workdir $PWD wolfboot.elf |
| 13 | + |
| 14 | +ARCH?=RISCV64 |
| 15 | +TARGET?=mpfs250 |
| 16 | +SIGN?=ECC384 |
| 17 | +HASH?=SHA384 |
| 18 | +IMAGE_HEADER_SIZE=512 |
| 19 | +WOLFBOOT_VERSION?=1 |
| 20 | +ARMORED?=0 |
| 21 | +DEBUG?=0 |
| 22 | +DEBUG_SYMBOLS?=1 |
| 23 | +DEBUG_UART?=1 |
| 24 | +VTOR?=1 |
| 25 | +EXT_FLASH?=0 |
| 26 | +SPI_FLASH?=0 |
| 27 | +NO_XIP?=1 |
| 28 | +NVM_FLASH_WRITEONCE?=0 |
| 29 | +UART_FLASH?=0 |
| 30 | +V?=0 |
| 31 | +NO_MPU?=1 |
| 32 | +RAM_CODE?=0 |
| 33 | +SPMATH?=0 |
| 34 | +SPMATHALL?=1 |
| 35 | +DUALBANK_SWAP?=0 |
| 36 | +PKA?=0 |
| 37 | +ENCRYPT=0 |
| 38 | +WOLFTPM?=0 |
| 39 | +ELF?=1 |
| 40 | +#DEBUG_ELF?=1 |
| 41 | + |
| 42 | +OPTIMIZATION_LEVEL=1 |
| 43 | + |
| 44 | +# M-Mode configuration: runs on E51 from L2 SRAM |
| 45 | +RISCV_MMODE?=1 |
| 46 | + |
| 47 | +# Stack size per hart (L2 SRAM constraints) |
| 48 | +CFLAGS_EXTRA+=-DSTACK_SIZE_PER_HART=8192 |
| 49 | + |
| 50 | +# E51 core lacks RISC-V crypto extensions (Zknh), use portable C |
| 51 | +NO_ASM?=1 |
| 52 | + |
| 53 | +# Enable LPDDR4 init in hal_init() by pointing at the Libero/HSS-generated |
| 54 | +# fpga_design_config directory for this board. The directory must contain |
| 55 | +# fpga_design_config.h and its sub-headers (memory_map/, ddr/, clocks/, ...). |
| 56 | +# Typical sources: |
| 57 | +# - HSS Video Kit build: |
| 58 | +# <hss>/build/boards/mpfs-video-kit/fpga_design_config |
| 59 | +# - Libero MSS Configurator export for the design. |
| 60 | +# The -I path is added and -DMPFS_DDR_INIT is set automatically when this is |
| 61 | +# non-empty (see arch.mk). Override on the command line for one-off builds: |
| 62 | +# make LIBERO_FPGA_CONFIG_DIR=/path/to/fpga_design_config |
| 63 | +LIBERO_FPGA_CONFIG_DIR?= |
| 64 | + |
| 65 | +# Boot Linux: drop to S-mode after wolfBoot verifies kernel |
| 66 | +CFLAGS_EXTRA+=-DWOLFBOOT_MMODE_SMODE_BOOT |
| 67 | + |
| 68 | +# SD card storage for kernel image (no QSPI flash) |
| 69 | +DISK_SDCARD?=1 |
| 70 | +DISK_EMMC?=0 |
| 71 | + |
| 72 | +# wolfBoot in L2 SRAM (256KB available) |
| 73 | +WOLFBOOT_ORIGIN?=0x0A000000 |
| 74 | + |
| 75 | +# 4KB sector size (SD card flow is partition-based, not flash-erase-based) |
| 76 | +WOLFBOOT_SECTOR_SIZE?=0x1000 |
| 77 | + |
| 78 | +# Scratch address where the signed FIT image is staged before signature |
| 79 | +# verification + FIT parse. Placed early in DDR (32 MB into 2 GB) so we |
| 80 | +# stay within the fully-trained region near 0x80000000 - the LPDDR4 TIP |
| 81 | +# completes BCLK_SCLK only (train_stat=0x1) on this Video Kit and higher |
| 82 | +# DDR addresses (e.g. 0x8E000000) have shown intermittent write |
| 83 | +# corruption during long disk loads. |
| 84 | +# After the FIT is parsed: |
| 85 | +# kernel is copied to 0x80200000 (FIT-internal "load") |
| 86 | +# DTB is copied to WOLFBOOT_LOAD_DTS_ADDRESS (0x8A000000) |
| 87 | +# Layout: |
| 88 | +# 0x80200000 - 0x814FFFFF : kernel (~19 MB after parse) |
| 89 | +# 0x82000000 - 0x832FFFFF : FIT scratch (~19 MB - overwritten on next boot) |
| 90 | +# 0x8A000000 - 0x8A004FFF : DTB |
| 91 | +WOLFBOOT_LOAD_ADDRESS?=0x82000000 |
| 92 | + |
| 93 | +# DTB load address in DDR |
| 94 | +WOLFBOOT_LOAD_DTS_ADDRESS?=0x8A000000 |
| 95 | + |
| 96 | +# Use update_disk loader (partition A/B numbering instead of flash addresses). |
| 97 | +# BOOT_PART_A / BOOT_PART_B are 0-indexed GPT entry numbers. GPT partitions |
| 98 | +# in our SD card layout (see tools/scripts/program-sdcard.sh): |
| 99 | +# index 0 (parted "boot" 1 MiB - 33 MiB) -> active boot FIT |
| 100 | +# index 1 (parted "update" 33 MiB - 65 MiB) -> inactive/update slot |
| 101 | +# index 2 (parted "rootfs" 65 MiB - end) -> Linux rootfs |
| 102 | +WOLFBOOT_NO_PARTITIONS=1 |
| 103 | +CFLAGS_EXTRA+=-DBOOT_PART_A=0 |
| 104 | +CFLAGS_EXTRA+=-DBOOT_PART_B=1 |
| 105 | + |
| 106 | +# Speed up disk partition read (512KB chunks - max DMA size) |
| 107 | +CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000 |
| 108 | + |
| 109 | +# Disable SDMA on the Cadence SD4HC. SDMA hangs silently at first |
| 110 | +# multi-block read on the Video Kit (Cadence boundary-cross bug). |
| 111 | +# Use PIO single-block reads instead. |
| 112 | +CFLAGS_EXTRA+=-DSDHCI_SDMA_DISABLED |
| 113 | + |
| 114 | +# Force single-block (CMD17) reads. Multi-block PIO suffers a BRR |
| 115 | +# race on Arasan/Cadence-family controllers; single-block avoids it. |
| 116 | +CFLAGS_EXTRA+=-DSDHCI_FORCE_SINGLE_BLOCK_READ |
| 117 | + |
| 118 | +# Video Kit routes the SD slot's Card Detect (CD#) signal through the FPGA |
| 119 | +# fabric rather than MSSIO, so the SDHCI controller's hardware CI/CDPL |
| 120 | +# detection always reads 'no card' in M-mode (no fabric configuration). |
| 121 | +# Force the SD bring-up code to assume a card is present. |
| 122 | +CFLAGS_EXTRA+=-DSDHCI_FORCE_CARD_DETECT |
| 123 | + |
| 124 | +# Optional encryption (kernel signed+encrypted with AES-256) |
| 125 | +#CUSTOM_ENCRYPT_KEY=1 |
| 126 | +#ENCRYPT=1 |
| 127 | +#ENCRYPT_WITH_AES256=1 |
| 128 | +#OBJS_EXTRA=src/my_custom_encrypt_key.o |
| 129 | + |
| 130 | +# Used by test-application/ELF wrapper |
| 131 | +WOLFBOOT_PARTITION_BOOT_ADDRESS=0x80200000 |
| 132 | +WOLFBOOT_PARTITION_SIZE=0x4000000 |
| 133 | + |
| 134 | +# Debug options (useful for initial M-mode + DDR bring-up) |
| 135 | +CFLAGS_EXTRA+=-DDEBUG_BOOT |
| 136 | +#CFLAGS_EXTRA+=-DDEBUG_SDHCI |
| 137 | +#CFLAGS_EXTRA+=-DDEBUG_DISK |
| 138 | +#CFLAGS_EXTRA+=-DDISK_TEST |
| 139 | +# DDR pattern test at 0x82000000 (256 KB triple-write). This MUST |
| 140 | +# stay enabled -- without it the post-training MTC sanity check |
| 141 | +# times out and the non-cached probe hangs (the cached pattern test |
| 142 | +# acts as a "warm-up" that exercises the L2->DDR writeback path |
| 143 | +# enough to stabilize controller state). The test halts the boot |
| 144 | +# after running, which is fine while disk-load is still under |
| 145 | +# investigation; remove the while(1) at the end of the block when |
| 146 | +# disk-load reliably completes. |
| 147 | +CFLAGS_EXTRA+=-DMPFS_DDR_PATTERN_TEST |
| 148 | +# Verbose register-level DDR tracing. KEEP ENABLED until the timing |
| 149 | +# sensitivity in run_training is fixed -- the DBG_DDR printf delays |
| 150 | +# during the post-ZQ-cal phase appear to be required for TIP to |
| 151 | +# reach train_stat=0x1D consistently. Removing -DDEBUG_DDR causes |
| 152 | +# train_stat to stick at 0x1. |
| 153 | +CFLAGS_EXTRA+=-DDEBUG_DDR |
| 154 | +# Phase 3.9 ruled out: kicking PHY_TRAINING_START=1 does not advance |
| 155 | +# TIP past BCLK_SCLK. Macro left for posterity, off by default. |
| 156 | +#CFLAGS_EXTRA+=-DMPFS_DDR_KICK_TRAINING_START |
0 commit comments