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lines changed Original file line number Diff line number Diff line change 118118 #define ENABLE_L1_CACHE
119119 #define ENABLE_L2_CACHE
120120
121- /* T2080 CPC SRAM config - 1MB for ECC P384 stack requirements */
121+ /* L1 locked dcache as initial stack (16KB).
122+ * CPC SRAM (via CoreNet) is unreliable on cold power cycle —
123+ * store buffer drains cause bus errors. L1 locked cache is
124+ * core-local and works reliably from first instruction.
125+ * Address chosen below CPC SRAM range, no backing memory needed. */
126+ #define L1_CACHE_ADDR (0xF8E00000UL)
127+
128+ /* T2080 CPC SRAM config - 1MB for ECC P384 stack requirements.
129+ * CPC hardware is configured in early ASM but NOT used for stack.
130+ * CPC SRAM becomes usable after cache hierarchy is initialized in C. */
122131 #define L2SRAM_ADDR (0xF8F00000UL) /* CPC as SRAM (1MB) */
123132 #define L2SRAM_SIZE (1024UL * 1024UL)
124133
Original file line number Diff line number Diff line change @@ -934,7 +934,14 @@ cache_sram_init:
934934setup_stack:
935935 /* Build top of stack address */
936936 /* Reserve 64 bytes of initial data (must be 16 byte aligned) */
937+ #ifdef L1_CACHE_ADDR
938+ /* Use L1 locked dcache as initial stack (16KB).
939+ * L1_CACHE_ADDR + 4*4KB = top of locked region.
940+ * CPC SRAM is unreliable on cold power cycle (bus errors via CoreNet). */
941+ LOAD_ADDR32(r1, L1_CACHE_ADDR + 0x4000 - 64 )
942+ #else
937943 LOAD_ADDR32(r1, _end_stack-64 )
944+ #endif
938945
939946 /* PowerPC e500 Application Binary Interface User's Guide
940947 * 2.3.5.1.1 Minimal Stack Frame: No Local Variables or Saved Parameters
@@ -948,12 +955,12 @@ setup_stack:
948955 stwu r1, -8 (r1) /* Save back chain and move SP */
949956 stw r0, +12 (r1) /* Save return addr (underflow vect) */
950957
958+ uart_putc_debug 'D' /* checkpoint D: stack ready */
951959 /* switch back to AS/TS=0, enable recoverable interrupts */
952960 lis r3, (MSR_CE | MSR_ME | MSR_DE | MSR_RI)@h
953961 ori r3, r3, (MSR_CE | MSR_ME | MSR_DE | MSR_RI)@l
954962 mtmsr r3
955963 isync
956- uart_putc_debug 'D' /* checkpoint D: stack ready, entering C */
957964
958965#ifdef USE_GOT
959966 GET_GOT
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