Progress with SDHC-I testing on ZCU102

Author: dgarske

config/examples/zynqmp_sdcard.config

@@ -26,6 +26,9 @@ CFLAGS_EXTRA+=-DDEBUG_ZYNQ=1
 # SD card support - use SDHCI driver
 DISK_SDCARD?=1
 DISK_EMMC?=0
+# ZynqMP Arasan SDHCI does not support CDSS/CDTL card detect test level.
+# Since FSBL booted from the same SD card, we know it is present.
+CFLAGS_EXTRA+=-DSDHCI_FORCE_CARD_DETECT
 
 # Disable QSPI flash when using SD card
 EXT_FLASH?=0

hal/zynq.c

@@ -1869,6 +1869,8 @@ static int test_ext_flash(QspiDev_t* dev)
 /* Standard SDHCI Software Reset is in the Clock/Timeout/Reset register */
 #define STD_SDHCI_RESET_REG     0x2C  /* Clock Control / Timeout / SW Reset */
 #define STD_SDHCI_SRA           (1U << 24) /* Software Reset for All */
+#define STD_SDHCI_SRCMD         (1U << 25) /* Software Reset for CMD Line */
+#define STD_SDHCI_SRDAT         (1U << 26) /* Software Reset for DAT Line */
 
 /* Handle reads from Cadence HRS registers (0x000-0x1FF) */
 static uint32_t zynqmp_sdhci_hrs_read(uint32_t hrs_offset)
@@ -1878,7 +1880,10 @@ static uint32_t zynqmp_sdhci_hrs_read(uint32_t hrs_offset)
     switch (hrs_offset) {
     case 0x000: /* HRS00 - Software Reset */
     {
-        /* Map standard SRA (bit 24 of 0x2C) to Cadence SWR (bit 0) */
+        /* Map standard SRA (bit 24 of 0x2C) to Cadence SWR (bit 0).
+         * SRA is safe because sdhci_platform_init() sets the slot type
+         * to "Embedded", so the controller accepts BP/SDCE writes after
+         * reset. */
         uint32_t val = *((volatile uint32_t *)(base + STD_SDHCI_RESET_REG));
         return (val & STD_SDHCI_SRA) ? 1U : 0U;
     }
@@ -1898,7 +1903,12 @@ static void zynqmp_sdhci_hrs_write(uint32_t hrs_offset, uint32_t val)
 
     switch (hrs_offset) {
     case 0x000: /* HRS00 - Software Reset */
-        if (val & 1U) { /* SWR bit -> standard SRA */
+        if (val & 1U) {
+            /* Issue SRA (Software Reset for All).
+             * This is safe because sdhci_platform_init() configures the
+             * IOU_SLCR slot type to "Embedded" before this reset, so the
+             * controller will accept Bus Power and SD Clock Enable writes
+             * during the subsequent initialization. */
             uint32_t reg = *((volatile uint32_t *)(base + STD_SDHCI_RESET_REG));
             reg |= STD_SDHCI_SRA;
             *((volatile uint32_t *)(base + STD_SDHCI_RESET_REG)) = reg;
@@ -1940,26 +1950,51 @@ void sdhci_reg_write(uint32_t offset, uint32_t val)
 /* Platform initialization - called from sdhci_init()
  * FSBL already initializes the SD controller on ZynqMP when booting from SD,
  * so we don't need to configure clocks/reset (CRL_APB registers).
- * We verify the SDHCI controller is accessible via standard register reads. */
+ *
+ * However, the FSBL uses GPIO-based card detect (polling MIO45 as GPIO)
+ * rather than the SDHCI controller's built-in CD mechanism. The default
+ * IOU_SLCR SD_CONFIG_REG2 slot type is "Removable" (00), but MIO45 is not
+ * routed to the SDHCI controller as a CD function. This causes the Arasan
+ * SDHCI to report Card Inserted=0 and gate writes to Bus Power and SD Clock
+ * Enable registers.
+ *
+ * Fix: Set SD1 slot type to "Embedded" (01) in IOU_SLCR SD_CONFIG_REG2.
+ * This makes the controller always assert Card Inserted and Card State
+ * Stable, allowing normal SDHCI register access. */
 void sdhci_platform_init(void)
 {
+    uint32_t reg;
+
+    /* Set SD1 slot type to "Embedded Slot for One Device" (01).
+     * This feeds into the SDHCI Capabilities register bits 31:30 and makes
+     * the controller report card as always present, bypassing the physical
+     * CD pin that is not connected to the SDHCI controller on ZCU102. */
+    reg = IOU_SLCR_SD_CONFIG_REG2;
+    reg &= ~SD_CONFIG_REG2_SD1_SLOTTYPE_MASK;
+    reg |= (1UL << SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT); /* 01 = Embedded */
+    IOU_SLCR_SD_CONFIG_REG2 = reg;
+
 #ifdef DEBUG_SDHCI
-    volatile uint8_t *base = (volatile uint8_t *)ZYNQMP_SDHCI_BASE;
-    uint32_t val;
+    {
+        volatile uint8_t *base = (volatile uint8_t *)ZYNQMP_SDHCI_BASE;
+        uint32_t val;
 
-    wolfBoot_printf("sdhci_platform_init: SD%d at 0x%x\n",
-        (ZYNQMP_SDHCI_BASE == ZYNQMP_SD0_BASE) ? 0 : 1,
-        (unsigned int)ZYNQMP_SDHCI_BASE);
+        wolfBoot_printf("sdhci_platform_init: SD%d at 0x%x\n",
+            (ZYNQMP_SDHCI_BASE == ZYNQMP_SD0_BASE) ? 0 : 1,
+            (unsigned int)ZYNQMP_SDHCI_BASE);
 
-    /* Read standard SDHCI registers to verify controller access */
-    val = *((volatile uint32_t *)(base + 0x24));  /* Present State */
-    wolfBoot_printf("  Present State: 0x%x\n", (unsigned int)val);
+        wolfBoot_printf("  SD_CONFIG_REG2: 0x%x\n",
+            (unsigned int)IOU_SLCR_SD_CONFIG_REG2);
 
-    val = *((volatile uint32_t *)(base + 0x40));  /* Capabilities */
-    wolfBoot_printf("  Capabilities:  0x%x\n", (unsigned int)val);
-    (void)val;
+        /* Read standard SDHCI registers to verify controller access */
+        val = *((volatile uint32_t *)(base + 0x24));  /* Present State */
+        wolfBoot_printf("  Present State: 0x%x\n", (unsigned int)val);
+
+        val = *((volatile uint32_t *)(base + 0x40));  /* Capabilities */
+        wolfBoot_printf("  Capabilities:  0x%x\n", (unsigned int)val);
+        (void)val;
+    }
 #endif
-    /* FSBL already configured SD1 - no clock/reset setup needed */
 }
 
 /* Platform interrupt setup - called from sdhci_init()
@@ -1971,7 +2006,7 @@ void sdhci_platform_irq_init(void)
 #endif
 }
 
-/* Platform bus mode selection - called from sdhci_init() */
+/* Platform bus mode selection - called from sdhci_init() after software reset */
 void sdhci_platform_set_bus_mode(int is_emmc)
 {
     (void)is_emmc;

hal/zynq.h

@@ -413,6 +413,15 @@
 #define RST_LPD_IOU2_SDIO0  (1UL << 5)
 #define RST_LPD_IOU2_SDIO1  (1UL << 6)
 
+/* IOU_SLCR SD Configuration (feeds into SDHCI Capabilities register) */
+#define IOU_SLCR_SD_CONFIG_REG2  (*((volatile uint32_t*)(IOU_SLCR_BASSE + 0x320)))
+/* SD1 Slot Type: 00=Removable, 01=Embedded, 10=Shared Bus */
+#define SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT  28
+#define SD_CONFIG_REG2_SD1_SLOTTYPE_MASK   0x30000000UL
+/* SD0 Slot Type */
+#define SD_CONFIG_REG2_SD0_SLOTTYPE_SHIFT  12
+#define SD_CONFIG_REG2_SD0_SLOTTYPE_MASK   0x00003000UL
+
 
 /* Configuration Security Unit (CSU) */
 /* Triple-Dedundant MicroBlaze processor */

include/sdhci.h

@@ -212,6 +212,8 @@
 /* SRS10 - Host Control 1 / Power / Block Gap / Wakeup */
 #define SDHCI_SRS10_DTW         (1U << 1)   /* Data transfer width (4-bit) */
 #define SDHCI_SRS10_EDTW        (1U << 5)   /* Extended data transfer width (8-bit) */
+#define SDHCI_SRS10_CDTL        (1U << 6)   /* Card Detect Test Level */
+#define SDHCI_SRS10_CDSS        (1U << 7)   /* Card Detect Signal Selection */
 #define SDHCI_SRS10_HSE         (1U << 2)   /* High speed enable */
 #define SDHCI_SRS10_BP          (1U << 8)   /* Bus power */
 #define SDHCI_SRS10_BVS_MASK    (0x7U << 9)

src/sdhci.c

@@ -560,6 +560,13 @@ static int sdcard_power_init_seq(uint32_t voltage)
 {
     /* Set power to specified voltage */
     int status = sdhci_set_power(voltage);
+#ifdef DEBUG_SDHCI
+    wolfBoot_printf("sdcard_power_init: power status=%d, SRS09=0x%x, "
+        "SRS10=0x%x, SRS11=0x%x, SRS12=0x%x\n",
+        status,
+        SDHCI_REG(SDHCI_SRS09), SDHCI_REG(SDHCI_SRS10),
+        SDHCI_REG(SDHCI_SRS11), SDHCI_REG(SDHCI_SRS12));
+#endif
     if (status == 0) {
         /* send CMD0 (go idle) to reset card */
         status = sdhci_cmd(MMC_CMD0_GO_IDLE, 0, SDHCI_RESP_NONE);
@@ -1407,6 +1414,7 @@ int sdhci_init(void)
 
     /* check if card inserted and stable */
     reg = SDHCI_REG(SDHCI_SRS09);
+#ifndef SDHCI_FORCE_CARD_DETECT
     if ((reg & SDHCI_SRS09_CSS) == 0) {
         /* card not inserted or not stable */
         return -1;
@@ -1419,6 +1427,7 @@ int sdhci_init(void)
         return -1;
     }
 #endif
+#endif /* !SDHCI_FORCE_CARD_DETECT */
 
     /* Start in 1-bit bus mode */
     reg = SDHCI_REG(SDHCI_SRS10);