Attempt to resolve the CI build errors. Add missing .yaml file.

Author: dgarske

.github/workflows/test-build-riscv.yml

@@ -19,6 +19,10 @@ jobs:
   build:
     runs-on: ubuntu-24.04
     timeout-minutes: 30
+    env:
+      # Pin toolchain release to avoid GCC 15+ multilib breakage.
+      # https://github.com/riscv-collab/riscv-gnu-toolchain/releases
+      RISCV_TOOLCHAIN_TAG: '2024.09.03'
 
     steps:
       - uses: actions/checkout@v4
@@ -88,16 +92,16 @@ jobs:
       - name: Download and install RISC-V toolchain (riscv32)
         if: ${{ inputs.arch == 'riscv' }}
         run: |
-          wget -q https://github.com/riscv-collab/riscv-gnu-toolchain/releases/latest/download/riscv32-elf-ubuntu-24.04-gcc.tar.xz
-          tar -xf riscv32-elf-ubuntu-24.04-gcc.tar.xz
+          wget -q https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/${RISCV_TOOLCHAIN_TAG}/riscv32-elf-ubuntu-24.04-gcc-nightly-${RISCV_TOOLCHAIN_TAG}-nightly.tar.gz
+          tar -xf riscv32-elf-ubuntu-24.04-gcc-nightly-${RISCV_TOOLCHAIN_TAG}-nightly.tar.gz
           echo "$GITHUB_WORKSPACE/riscv/bin" >> $GITHUB_PATH
           $GITHUB_WORKSPACE/riscv/bin/riscv32-unknown-elf-gcc --version
 
       - name: Download and install RISC-V toolchain (riscv64)
         if: ${{ inputs.arch == 'riscv64' }}
         run: |
-          wget -q https://github.com/riscv-collab/riscv-gnu-toolchain/releases/latest/download/riscv64-elf-ubuntu-24.04-gcc.tar.xz
-          tar -xf riscv64-elf-ubuntu-24.04-gcc.tar.xz
+          wget -q https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/${RISCV_TOOLCHAIN_TAG}/riscv64-elf-ubuntu-24.04-gcc-nightly-${RISCV_TOOLCHAIN_TAG}-nightly.tar.gz
+          tar -xf riscv64-elf-ubuntu-24.04-gcc-nightly-${RISCV_TOOLCHAIN_TAG}-nightly.tar.gz
           echo "$GITHUB_WORKSPACE/riscv/bin" >> $GITHUB_PATH
           $GITHUB_WORKSPACE/riscv/bin/riscv64-unknown-elf-gcc --version
 

arch.mk

@@ -572,7 +572,10 @@ ifeq ($(ARCH),RISCV)
   RISCV32_ZIFENCEI := $(shell echo "void _start(void){}" | \
     $(CROSS_COMPILE)gcc -march=rv32imac_zifencei -mabi=ilp32 -c -x c - -o /dev/null 2>/dev/null && echo _zifencei)
   ifneq ($(RISCV32_ZICSR)$(RISCV32_ZIFENCEI),)
-    RISCV32_EXT_LINK_OK := $(shell echo "void _start(void){}" | \
+    # Link test using 64-bit integer division to force libgcc resolution.
+    # A trivial void _start(){} never references libgcc, hiding ABI
+    # mismatches (e.g., GCC 15 falling back to double-float libgcc).
+    RISCV32_EXT_LINK_OK := $(shell echo 'long long _d(long long a,long long b){return a/b;}void _start(void){_d(0,1);}' | \
       $(CROSS_COMPILE)gcc -march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) \
       -mabi=ilp32 -nostartfiles -x c - -o /dev/null 2>/dev/null && echo ok)
     ifneq ($(RISCV32_EXT_LINK_OK),ok)
@@ -635,7 +638,10 @@ ifeq ($(ARCH),RISCV64)
   RISCV64_ZIFENCEI := $(shell echo "void _start(void){}" | \
     $(CROSS_COMPILE)gcc -march=rv64imafd_zifencei -mabi=lp64d -c -x c - -o /dev/null 2>/dev/null && echo _zifencei)
   ifneq ($(RISCV64_ZICSR)$(RISCV64_ZIFENCEI),)
-    RISCV64_EXT_LINK_OK := $(shell echo "void _start(void){}" | \
+    # Link test using 128-bit integer division to force libgcc resolution.
+    # A trivial void _start(){} never references libgcc, hiding multilib
+    # mismatches (e.g., GCC 15 arch decomposition breaking multilib lookup).
+    RISCV64_EXT_LINK_OK := $(shell echo '__int128 _d(__int128 a,__int128 b){return a/b;}void _start(void){_d(0,1);}' | \
       $(CROSS_COMPILE)gcc -march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) \
       -mabi=lp64d -nostartfiles -x c - -o /dev/null 2>/dev/null && echo ok)
     ifneq ($(RISCV64_EXT_LINK_OK),ok)

hal/mpfs-l2lim.yaml

@@ -0,0 +1,21 @@
+#
+# HSS Payload Generator - configuration file for wolfBoot on PolarFire SoC
+# Boot target: L2-LIM (no DDR) via sNVM or QSPI HSS payload
+#
+# wolfBoot is loaded by HSS to L2-LIM at WOLFBOOT_ORIGIN (0x08040000).
+# HSS remains resident in lower L2-LIM for SBI services (timer, IPI, etc.).
+# wolfBoot runs on U54_1 in S-mode, loads application from SC QSPI flash.
+#
+
+set-name: 'PolarFire-SoC-HSS::wolfBoot-L2LIM'
+hart-entry-points: {
+  u54_1: '0x08040000',
+  u54_2: '0x08040000',
+  u54_3: '0x08040000',
+  u54_4: '0x08040000'
+}
+payloads:
+  wolfboot.elf: {
+    owner-hart: u54_1,
+    priv-mode: prv_s
+  }